summaryrefslogtreecommitdiff
path: root/arch/arm64/boot/dts/nvidia/tegra194.dtsi
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm64/boot/dts/nvidia/tegra194.dtsi')
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra194.dtsi538
1 files changed, 537 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index 9fc14bb9a0af..6dfa1ca0b851 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -4,6 +4,8 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/tegra186-hsp.h>
#include <dt-bindings/reset/tegra194-reset.h>
+#include <dt-bindings/power/tegra194-powergate.h>
+#include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
/ {
compatible = "nvidia,tegra194";
@@ -209,6 +211,90 @@
status = "disabled";
};
+ pwm1: pwm@3280000 {
+ compatible = "nvidia,tegra194-pwm",
+ "nvidia,tegra186-pwm";
+ reg = <0x3280000 0x10000>;
+ clocks = <&bpmp TEGRA194_CLK_PWM1>;
+ clock-names = "pwm";
+ resets = <&bpmp TEGRA194_RESET_PWM1>;
+ reset-names = "pwm";
+ status = "disabled";
+ #pwm-cells = <2>;
+ };
+
+ pwm2: pwm@3290000 {
+ compatible = "nvidia,tegra194-pwm",
+ "nvidia,tegra186-pwm";
+ reg = <0x3290000 0x10000>;
+ clocks = <&bpmp TEGRA194_CLK_PWM2>;
+ clock-names = "pwm";
+ resets = <&bpmp TEGRA194_RESET_PWM2>;
+ reset-names = "pwm";
+ status = "disabled";
+ #pwm-cells = <2>;
+ };
+
+ pwm3: pwm@32a0000 {
+ compatible = "nvidia,tegra194-pwm",
+ "nvidia,tegra186-pwm";
+ reg = <0x32a0000 0x10000>;
+ clocks = <&bpmp TEGRA194_CLK_PWM3>;
+ clock-names = "pwm";
+ resets = <&bpmp TEGRA194_RESET_PWM3>;
+ reset-names = "pwm";
+ status = "disabled";
+ #pwm-cells = <2>;
+ };
+
+ pwm5: pwm@32c0000 {
+ compatible = "nvidia,tegra194-pwm",
+ "nvidia,tegra186-pwm";
+ reg = <0x32c0000 0x10000>;
+ clocks = <&bpmp TEGRA194_CLK_PWM5>;
+ clock-names = "pwm";
+ resets = <&bpmp TEGRA194_RESET_PWM5>;
+ reset-names = "pwm";
+ status = "disabled";
+ #pwm-cells = <2>;
+ };
+
+ pwm6: pwm@32d0000 {
+ compatible = "nvidia,tegra194-pwm",
+ "nvidia,tegra186-pwm";
+ reg = <0x32d0000 0x10000>;
+ clocks = <&bpmp TEGRA194_CLK_PWM6>;
+ clock-names = "pwm";
+ resets = <&bpmp TEGRA194_RESET_PWM6>;
+ reset-names = "pwm";
+ status = "disabled";
+ #pwm-cells = <2>;
+ };
+
+ pwm7: pwm@32e0000 {
+ compatible = "nvidia,tegra194-pwm",
+ "nvidia,tegra186-pwm";
+ reg = <0x32e0000 0x10000>;
+ clocks = <&bpmp TEGRA194_CLK_PWM7>;
+ clock-names = "pwm";
+ resets = <&bpmp TEGRA194_RESET_PWM7>;
+ reset-names = "pwm";
+ status = "disabled";
+ #pwm-cells = <2>;
+ };
+
+ pwm8: pwm@32f0000 {
+ compatible = "nvidia,tegra194-pwm",
+ "nvidia,tegra186-pwm";
+ reg = <0x32f0000 0x10000>;
+ clocks = <&bpmp TEGRA194_CLK_PWM8>;
+ clock-names = "pwm";
+ resets = <&bpmp TEGRA194_RESET_PWM8>;
+ reset-names = "pwm";
+ status = "disabled";
+ #pwm-cells = <2>;
+ };
+
sdmmc1: sdhci@3400000 {
compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci";
reg = <0x03400000 0x10000>;
@@ -242,6 +328,22 @@
status = "disabled";
};
+ hda@3510000 {
+ compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda";
+ reg = <0x3510000 0x10000>;
+ interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA194_CLK_HDA>,
+ <&bpmp TEGRA194_CLK_HDA2CODEC_2X>,
+ <&bpmp TEGRA194_CLK_HDA2HDMICODEC>;
+ clock-names = "hda", "hda2codec_2x", "hda2hdmi";
+ resets = <&bpmp TEGRA194_RESET_HDA>,
+ <&bpmp TEGRA194_RESET_HDA2CODEC_2X>,
+ <&bpmp TEGRA194_RESET_HDA2HDMICODEC>;
+ reset-names = "hda", "hda2codec_2x", "hda2hdmi";
+ power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
+ status = "disabled";
+ };
+
gic: interrupt-controller@3881000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
@@ -255,6 +357,15 @@
interrupt-parent = <&gic>;
};
+ cec@3960000 {
+ compatible = "nvidia,tegra194-cec";
+ reg = <0x03960000 0x10000>;
+ interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA194_CLK_CEC>;
+ clock-names = "cec";
+ status = "disabled";
+ };
+
hsp_top0: hsp@3c00000 {
compatible = "nvidia,tegra186-hsp";
reg = <0x03c00000 0xa0000>;
@@ -313,7 +424,44 @@
status = "disabled";
};
- pmc@c360000 {
+ rtc: rtc@c2a0000 {
+ compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc";
+ reg = <0x0c2a0000 0x10000>;
+ interrupt-parent = <&pmc>;
+ interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA194_CLK_CLK_32K>;
+ clock-names = "rtc";
+ status = "disabled";
+ };
+
+ gpio_aon: gpio@c2f0000 {
+ compatible = "nvidia,tegra194-gpio-aon";
+ reg-names = "security", "gpio";
+ reg = <0xc2f0000 0x1000>,
+ <0xc2f1000 0x1000>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ pwm4: pwm@c340000 {
+ compatible = "nvidia,tegra194-pwm",
+ "nvidia,tegra186-pwm";
+ reg = <0xc340000 0x10000>;
+ clocks = <&bpmp TEGRA194_CLK_PWM4>;
+ clock-names = "pwm";
+ resets = <&bpmp TEGRA194_RESET_PWM4>;
+ reset-names = "pwm";
+ status = "disabled";
+ #pwm-cells = <2>;
+ };
+
+ pmc: pmc@c360000 {
compatible = "nvidia,tegra194-pmc";
reg = <0x0c360000 0x10000>,
<0x0c370000 0x10000>,
@@ -321,6 +469,356 @@
<0x0c390000 0x10000>,
<0x0c3a0000 0x10000>;
reg-names = "pmc", "wake", "aotag", "scratch", "misc";
+
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ };
+
+ host1x@13e00000 {
+ compatible = "nvidia,tegra194-host1x", "simple-bus";
+ reg = <0x13e00000 0x10000>,
+ <0x13e10000 0x10000>;
+ reg-names = "hypervisor", "vm";
+ interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA194_CLK_HOST1X>;
+ clock-names = "host1x";
+ resets = <&bpmp TEGRA194_RESET_HOST1X>;
+ reset-names = "host1x";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ranges = <0x15000000 0x15000000 0x01000000>;
+
+ display-hub@15200000 {
+ compatible = "nvidia,tegra194-display", "simple-bus";
+ reg = <0x15200000 0x00040000>;
+ resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>,
+ <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>,
+ <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>,
+ <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>,
+ <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>,
+ <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>,
+ <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>;
+ reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
+ "wgrp3", "wgrp4", "wgrp5";
+ clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>,
+ <&bpmp TEGRA194_CLK_NVDISPLAYHUB>;
+ clock-names = "disp", "hub";
+ status = "disabled";
+
+ power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ranges = <0x15200000 0x15200000 0x40000>;
+
+ display@15200000 {
+ compatible = "nvidia,tegra194-dc";
+ reg = <0x15200000 0x10000>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>;
+ clock-names = "dc";
+ resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>;
+ reset-names = "dc";
+
+ power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
+
+ nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
+ nvidia,head = <0>;
+ };
+
+ display@15210000 {
+ compatible = "nvidia,tegra194-dc";
+ reg = <0x15210000 0x10000>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>;
+ clock-names = "dc";
+ resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>;
+ reset-names = "dc";
+
+ power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>;
+
+ nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
+ nvidia,head = <1>;
+ };
+
+ display@15220000 {
+ compatible = "nvidia,tegra194-dc";
+ reg = <0x15220000 0x10000>;
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>;
+ clock-names = "dc";
+ resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>;
+ reset-names = "dc";
+
+ power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
+
+ nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
+ nvidia,head = <2>;
+ };
+
+ display@15230000 {
+ compatible = "nvidia,tegra194-dc";
+ reg = <0x15230000 0x10000>;
+ interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>;
+ clock-names = "dc";
+ resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>;
+ reset-names = "dc";
+
+ power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
+
+ nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
+ nvidia,head = <3>;
+ };
+ };
+
+ vic@15340000 {
+ compatible = "nvidia,tegra194-vic";
+ reg = <0x15340000 0x00040000>;
+ interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA194_CLK_VIC>;
+ clock-names = "vic";
+ resets = <&bpmp TEGRA194_RESET_VIC>;
+ reset-names = "vic";
+
+ power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>;
+ };
+
+ dpaux0: dpaux@155c0000 {
+ compatible = "nvidia,tegra194-dpaux";
+ reg = <0x155c0000 0x10000>;
+ interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA194_CLK_DPAUX>,
+ <&bpmp TEGRA194_CLK_PLLDP>;
+ clock-names = "dpaux", "parent";
+ resets = <&bpmp TEGRA194_RESET_DPAUX>;
+ reset-names = "dpaux";
+ status = "disabled";
+
+ power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
+
+ state_dpaux0_aux: pinmux-aux {
+ groups = "dpaux-io";
+ function = "aux";
+ };
+
+ state_dpaux0_i2c: pinmux-i2c {
+ groups = "dpaux-io";
+ function = "i2c";
+ };
+
+ state_dpaux0_off: pinmux-off {
+ groups = "dpaux-io";
+ function = "off";
+ };
+
+ i2c-bus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ dpaux1: dpaux@155d0000 {
+ compatible = "nvidia,tegra194-dpaux";
+ reg = <0x155d0000 0x10000>;
+ interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA194_CLK_DPAUX1>,
+ <&bpmp TEGRA194_CLK_PLLDP>;
+ clock-names = "dpaux", "parent";
+ resets = <&bpmp TEGRA194_RESET_DPAUX1>;
+ reset-names = "dpaux";
+ status = "disabled";
+
+ power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
+
+ state_dpaux1_aux: pinmux-aux {
+ groups = "dpaux-io";
+ function = "aux";
+ };
+
+ state_dpaux1_i2c: pinmux-i2c {
+ groups = "dpaux-io";
+ function = "i2c";
+ };
+
+ state_dpaux1_off: pinmux-off {
+ groups = "dpaux-io";
+ function = "off";
+ };
+
+ i2c-bus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ dpaux2: dpaux@155e0000 {
+ compatible = "nvidia,tegra194-dpaux";
+ reg = <0x155e0000 0x10000>;
+ interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA194_CLK_DPAUX2>,
+ <&bpmp TEGRA194_CLK_PLLDP>;
+ clock-names = "dpaux", "parent";
+ resets = <&bpmp TEGRA194_RESET_DPAUX2>;
+ reset-names = "dpaux";
+ status = "disabled";
+
+ power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
+
+ state_dpaux2_aux: pinmux-aux {
+ groups = "dpaux-io";
+ function = "aux";
+ };
+
+ state_dpaux2_i2c: pinmux-i2c {
+ groups = "dpaux-io";
+ function = "i2c";
+ };
+
+ state_dpaux2_off: pinmux-off {
+ groups = "dpaux-io";
+ function = "off";
+ };
+
+ i2c-bus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ dpaux3: dpaux@155f0000 {
+ compatible = "nvidia,tegra194-dpaux";
+ reg = <0x155f0000 0x10000>;
+ interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA194_CLK_DPAUX3>,
+ <&bpmp TEGRA194_CLK_PLLDP>;
+ clock-names = "dpaux", "parent";
+ resets = <&bpmp TEGRA194_RESET_DPAUX3>;
+ reset-names = "dpaux";
+ status = "disabled";
+
+ power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
+
+ state_dpaux3_aux: pinmux-aux {
+ groups = "dpaux-io";
+ function = "aux";
+ };
+
+ state_dpaux3_i2c: pinmux-i2c {
+ groups = "dpaux-io";
+ function = "i2c";
+ };
+
+ state_dpaux3_off: pinmux-off {
+ groups = "dpaux-io";
+ function = "off";
+ };
+
+ i2c-bus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ sor0: sor@15b00000 {
+ compatible = "nvidia,tegra194-sor";
+ reg = <0x15b00000 0x40000>;
+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA194_CLK_SOR0_REF>,
+ <&bpmp TEGRA194_CLK_SOR0_OUT>,
+ <&bpmp TEGRA194_CLK_PLLD>,
+ <&bpmp TEGRA194_CLK_PLLDP>,
+ <&bpmp TEGRA194_CLK_SOR_SAFE>,
+ <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>;
+ clock-names = "sor", "out", "parent", "dp", "safe",
+ "pad";
+ resets = <&bpmp TEGRA194_RESET_SOR0>;
+ reset-names = "sor";
+ pinctrl-0 = <&state_dpaux0_aux>;
+ pinctrl-1 = <&state_dpaux0_i2c>;
+ pinctrl-2 = <&state_dpaux0_off>;
+ pinctrl-names = "aux", "i2c", "off";
+ status = "disabled";
+
+ power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
+ nvidia,interface = <0>;
+ };
+
+ sor1: sor@15b40000 {
+ compatible = "nvidia,tegra194-sor";
+ reg = <0x155c0000 0x40000>;
+ interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA194_CLK_SOR1_REF>,
+ <&bpmp TEGRA194_CLK_SOR1_OUT>,
+ <&bpmp TEGRA194_CLK_PLLD2>,
+ <&bpmp TEGRA194_CLK_PLLDP>,
+ <&bpmp TEGRA194_CLK_SOR_SAFE>,
+ <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>;
+ clock-names = "sor", "out", "parent", "dp", "safe",
+ "pad";
+ resets = <&bpmp TEGRA194_RESET_SOR1>;
+ reset-names = "sor";
+ pinctrl-0 = <&state_dpaux1_aux>;
+ pinctrl-1 = <&state_dpaux1_i2c>;
+ pinctrl-2 = <&state_dpaux1_off>;
+ pinctrl-names = "aux", "i2c", "off";
+ status = "disabled";
+
+ power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
+ nvidia,interface = <1>;
+ };
+
+ sor2: sor@15b80000 {
+ compatible = "nvidia,tegra194-sor";
+ reg = <0x15b80000 0x40000>;
+ interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA194_CLK_SOR2_REF>,
+ <&bpmp TEGRA194_CLK_SOR2_OUT>,
+ <&bpmp TEGRA194_CLK_PLLD3>,
+ <&bpmp TEGRA194_CLK_PLLDP>,
+ <&bpmp TEGRA194_CLK_SOR_SAFE>,
+ <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>;
+ clock-names = "sor", "out", "parent", "dp", "safe",
+ "pad";
+ resets = <&bpmp TEGRA194_RESET_SOR2>;
+ reset-names = "sor";
+ pinctrl-0 = <&state_dpaux2_aux>;
+ pinctrl-1 = <&state_dpaux2_i2c>;
+ pinctrl-2 = <&state_dpaux2_off>;
+ pinctrl-names = "aux", "i2c", "off";
+ status = "disabled";
+
+ power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
+ nvidia,interface = <2>;
+ };
+
+ sor3: sor@15bc0000 {
+ compatible = "nvidia,tegra194-sor";
+ reg = <0x15bc0000 0x40000>;
+ interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA194_CLK_SOR3_REF>,
+ <&bpmp TEGRA194_CLK_SOR3_OUT>,
+ <&bpmp TEGRA194_CLK_PLLD4>,
+ <&bpmp TEGRA194_CLK_PLLDP>,
+ <&bpmp TEGRA194_CLK_SOR_SAFE>,
+ <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>;
+ clock-names = "sor", "out", "parent", "dp", "safe",
+ "pad";
+ resets = <&bpmp TEGRA194_RESET_SOR3>;
+ reset-names = "sor";
+ pinctrl-0 = <&state_dpaux3_aux>;
+ pinctrl-1 = <&state_dpaux3_i2c>;
+ pinctrl-2 = <&state_dpaux3_off>;
+ pinctrl-names = "aux", "i2c", "off";
+ status = "disabled";
+
+ power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
+ nvidia,interface = <3>;
+ };
};
};
@@ -435,6 +933,44 @@
method = "smc";
};
+ thermal-zones {
+ cpu {
+ thermal-sensors = <&{/bpmp/thermal}
+ TEGRA194_BPMP_THERMAL_ZONE_CPU>;
+ status = "disabled";
+ };
+
+ gpu {
+ thermal-sensors = <&{/bpmp/thermal}
+ TEGRA194_BPMP_THERMAL_ZONE_GPU>;
+ status = "disabled";
+ };
+
+ aux {
+ thermal-sensors = <&{/bpmp/thermal}
+ TEGRA194_BPMP_THERMAL_ZONE_AUX>;
+ status = "disabled";
+ };
+
+ pllx {
+ thermal-sensors = <&{/bpmp/thermal}
+ TEGRA194_BPMP_THERMAL_ZONE_PLLX>;
+ status = "disabled";
+ };
+
+ ao {
+ thermal-sensors = <&{/bpmp/thermal}
+ TEGRA194_BPMP_THERMAL_ZONE_AO>;
+ status = "disabled";
+ };
+
+ tj {
+ thermal-sensors = <&{/bpmp/thermal}
+ TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>;
+ status = "disabled";
+ };
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13
generated by cgit v1.2.3 (git 2.39.0) at 2024-11-25 07:42:57 +0300