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-rw-r--r--arch/arm64/boot/dts/mediatek/Makefile1
-rw-r--r--arch/arm64/boot/dts/mediatek/mt6779.dtsi17
-rw-r--r--arch/arm64/boot/dts/mediatek/mt7622.dtsi2
-rw-r--r--arch/arm64/boot/dts/mediatek/mt8183-evb.dts12
-rw-r--r--arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku0.dts23
-rw-r--r--arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts5
-rw-r--r--arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi46
-rw-r--r--arch/arm64/boot/dts/mediatek/mt8183.dtsi26
-rw-r--r--arch/arm64/boot/dts/mediatek/mt8192.dtsi57
-rw-r--r--arch/arm64/boot/dts/mediatek/mt8516.dtsi30
10 files changed, 213 insertions, 6 deletions
diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
index 18f7b46c4095..deba27ab7657 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -13,6 +13,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana-rev7.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-evb.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku0.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb
diff --git a/arch/arm64/boot/dts/mediatek/mt6779.dtsi b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
index 370f309d32de..9bdf5145966c 100644
--- a/arch/arm64/boot/dts/mediatek/mt6779.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
@@ -189,6 +189,23 @@
#clock-cells = <1>;
};
+ pwrap: pwrap@1000d000 {
+ compatible = "mediatek,mt6779-pwrap";
+ reg = <0 0x1000d000 0 0x1000>;
+ reg-names = "pwrap";
+ interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_PMIC_AP>;
+ clock-names = "spi", "wrap";
+ };
+
+ devapc: devapc@10207000 {
+ compatible = "mediatek,mt6779-devapc";
+ reg = <0 0x10207000 0 0x1000>;
+ interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&infracfg_ao CLK_INFRA_DEVICE_APC>;
+ clock-names = "devapc-infra-clock";
+ };
+
uart0: serial@11002000 {
compatible = "mediatek,mt6779-uart",
"mediatek,mt6577-uart";
diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
index 5b9ec032ce8d..7c6d871538a6 100644
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
@@ -698,6 +698,8 @@
clocks = <&pericfg CLK_PERI_MSDC30_1_PD>,
<&topckgen CLK_TOP_AXI_SEL>;
clock-names = "source", "hclk";
+ resets = <&pericfg MT7622_PERI_MSDC1_SW_RST>;
+ reset-names = "hrst";
status = "disabled";
};
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
index cba2d8933e79..3249c959f76f 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
@@ -344,6 +344,12 @@
bias-disable;
};
};
+
+ pwm_pins_1: pwm1 {
+ pins_pwm {
+ pinmux = <PINMUX_GPIO90__FUNC_PWM_A>;
+ };
+ };
};
&spi0 {
@@ -392,3 +398,9 @@
&uart0 {
status = "okay";
};
+
+&pwm1 {
+ status = "okay";
+ pinctrl-0 = <&pwm_pins_1>;
+ pinctrl-names = "default";
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku0.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku0.dts
new file mode 100644
index 000000000000..fb5ee91b6fe0
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku0.dts
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2019 Google LLC
+ *
+ * Device-tree for Krane sku0.
+ *
+ * SKU is a 8-bit value (0x00 == 0):
+ * - Bits 7..4: Panel ID: 0x0 (AUO)
+ * - Bits 3..0: SKU ID: 0x0 (default)
+ */
+
+/dts-v1/;
+#include "mt8183-kukui-krane.dtsi"
+
+/ {
+ model = "MediaTek krane sku0 board";
+ compatible = "google,krane-sku0", "google,krane", "mediatek,mt8183";
+};
+
+&panel {
+ status = "okay";
+ compatible = "auo,kd101n80-45na";
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts
index 47113e275cb5..721d16f9c3b4 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts
@@ -16,3 +16,8 @@
model = "MediaTek krane sku176 board";
compatible = "google,krane-sku176", "google,krane", "mediatek,mt8183";
};
+
+&panel {
+ status = "okay";
+ compatible = "boe,tv101wum-nl6";
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
index bf2ad1294dd3..ff56bcfa3370 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
@@ -249,6 +249,36 @@
proc-supply = <&mt6358_vproc11_reg>;
};
+&dsi0 {
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ panel: panel@0 {
+ /* compatible will be set in board dts */
+ reg = <0>;
+ enable-gpios = <&pio 45 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&panel_pins_default>;
+ avdd-supply = <&ppvarn_lcd>;
+ avee-supply = <&ppvarp_lcd>;
+ pp1800-supply = <&pp1800_lcd>;
+ backlight = <&backlight_lcd0>;
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&dsi_out>;
+ };
+ };
+ };
+
+ ports {
+ port {
+ dsi_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+};
+
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
@@ -290,6 +320,10 @@
clock-frequency = <100000>;
};
+&mipi_tx0 {
+ status = "okay";
+};
+
&mmc0 {
status = "okay";
pinctrl-names = "default", "state_uhs";
@@ -547,6 +581,14 @@
};
};
+ panel_pins_default: panel_pins_default {
+ panel_reset {
+ pinmux = <PINMUX_GPIO45__FUNC_GPIO45>;
+ output-low;
+ bias-pull-up;
+ };
+ };
+
pwm0_pin_default: pwm0_pin_default {
pins1 {
pinmux = <PINMUX_GPIO176__FUNC_GPIO176>;
@@ -709,6 +751,10 @@
};
};
+&mfg {
+ domain-supply = <&mt6358_vgpu_reg>;
+};
+
&soc_data {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 5b782a4769e7..80519a145f13 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -6,7 +6,7 @@
*/
#include <dt-bindings/clock/mt8183-clk.h>
-#include <dt-bindings/gce/mt8173-gce.h>
+#include <dt-bindings/gce/mt8183-gce.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/memory/mt8183-larb-port.h>
@@ -360,7 +360,7 @@
#size-cells = <0>;
#power-domain-cells = <1>;
- power-domain@MT8183_POWER_DOMAIN_MFG {
+ mfg: power-domain@MT8183_POWER_DOMAIN_MFG {
reg = <MT8183_POWER_DOMAIN_MFG>;
#address-cells = <1>;
#size-cells = <0>;
@@ -661,12 +661,27 @@
compatible = "mediatek,mt8183-disp-pwm";
reg = <0 0x1100e000 0 0x1000>;
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
#pwm-cells = <2>;
clocks = <&topckgen CLK_TOP_MUX_DISP_PWM>,
<&infracfg CLK_INFRA_DISP_PWM>;
clock-names = "main", "mm";
};
+ pwm1: pwm@11006000 {
+ compatible = "mediatek,mt8183-pwm";
+ reg = <0 0x11006000 0 0x1000>;
+ #pwm-cells = <2>;
+ clocks = <&infracfg CLK_INFRA_PWM>,
+ <&infracfg CLK_INFRA_PWM_HCLK>,
+ <&infracfg CLK_INFRA_PWM1>,
+ <&infracfg CLK_INFRA_PWM2>,
+ <&infracfg CLK_INFRA_PWM3>,
+ <&infracfg CLK_INFRA_PWM4>;
+ clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
+ "pwm4";
+ };
+
i2c3: i2c@1100f000 {
compatible = "mediatek,mt8183-i2c";
reg = <0 0x1100f000 0 0x1000>,
@@ -1011,7 +1026,7 @@
clocks = <&mmsys CLK_MM_DISP_RDMA0>;
iommus = <&iommu M4U_PORT_DISP_RDMA0>;
mediatek,larb = <&larb0>;
- mediatek,rdma_fifo_size = <5120>;
+ mediatek,rdma-fifo-size = <5120>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
};
@@ -1023,7 +1038,7 @@
clocks = <&mmsys CLK_MM_DISP_RDMA1>;
iommus = <&iommu M4U_PORT_DISP_RDMA1>;
mediatek,larb = <&larb0>;
- mediatek,rdma_fifo_size = <2048>;
+ mediatek,rdma-fifo-size = <2048>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
};
@@ -1055,8 +1070,7 @@
};
gamma0: gamma@14011000 {
- compatible = "mediatek,mt8183-disp-gamma",
- "mediatek,mt8173-disp-gamma";
+ compatible = "mediatek,mt8183-disp-gamma";
reg = <0 0x14011000 0 0x1000>;
interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index e12e024de122..9757138a8bbd 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -39,6 +39,7 @@
reg = <0x000>;
enable-method = "psci";
clock-frequency = <1701000000>;
+ cpu-idle-states = <&cpuoff_l &clusteroff_l>;
next-level-cache = <&l2_0>;
capacity-dmips-mhz = <530>;
};
@@ -49,6 +50,7 @@
reg = <0x100>;
enable-method = "psci";
clock-frequency = <1701000000>;
+ cpu-idle-states = <&cpuoff_l &clusteroff_l>;
next-level-cache = <&l2_0>;
capacity-dmips-mhz = <530>;
};
@@ -59,6 +61,7 @@
reg = <0x200>;
enable-method = "psci";
clock-frequency = <1701000000>;
+ cpu-idle-states = <&cpuoff_l &clusteroff_l>;
next-level-cache = <&l2_0>;
capacity-dmips-mhz = <530>;
};
@@ -69,6 +72,7 @@
reg = <0x300>;
enable-method = "psci";
clock-frequency = <1701000000>;
+ cpu-idle-states = <&cpuoff_l &clusteroff_l>;
next-level-cache = <&l2_0>;
capacity-dmips-mhz = <530>;
};
@@ -79,6 +83,7 @@
reg = <0x400>;
enable-method = "psci";
clock-frequency = <2171000000>;
+ cpu-idle-states = <&cpuoff_b &clusteroff_b>;
next-level-cache = <&l2_1>;
capacity-dmips-mhz = <1024>;
};
@@ -89,6 +94,7 @@
reg = <0x500>;
enable-method = "psci";
clock-frequency = <2171000000>;
+ cpu-idle-states = <&cpuoff_b &clusteroff_b>;
next-level-cache = <&l2_1>;
capacity-dmips-mhz = <1024>;
};
@@ -99,6 +105,7 @@
reg = <0x600>;
enable-method = "psci";
clock-frequency = <2171000000>;
+ cpu-idle-states = <&cpuoff_b &clusteroff_b>;
next-level-cache = <&l2_1>;
capacity-dmips-mhz = <1024>;
};
@@ -109,6 +116,7 @@
reg = <0x700>;
enable-method = "psci";
clock-frequency = <2171000000>;
+ cpu-idle-states = <&cpuoff_b &clusteroff_b>;
next-level-cache = <&l2_1>;
capacity-dmips-mhz = <1024>;
};
@@ -158,6 +166,42 @@
l3_0: l3-cache {
compatible = "cache";
};
+
+ idle-states {
+ entry-method = "arm,psci";
+ cpuoff_l: cpuoff_l {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x00010001>;
+ local-timer-stop;
+ entry-latency-us = <55>;
+ exit-latency-us = <140>;
+ min-residency-us = <780>;
+ };
+ cpuoff_b: cpuoff_b {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x00010001>;
+ local-timer-stop;
+ entry-latency-us = <35>;
+ exit-latency-us = <145>;
+ min-residency-us = <720>;
+ };
+ clusteroff_l: clusteroff_l {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x01010002>;
+ local-timer-stop;
+ entry-latency-us = <60>;
+ exit-latency-us = <155>;
+ min-residency-us = <860>;
+ };
+ clusteroff_b: clusteroff_b {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x01010002>;
+ local-timer-stop;
+ entry-latency-us = <40>;
+ exit-latency-us = <155>;
+ min-residency-us = <780>;
+ };
+ };
};
pmu-a55 {
@@ -379,6 +423,19 @@
status = "disabled";
};
+ nor_flash: spi@11234000 {
+ compatible = "mediatek,mt8192-nor";
+ reg = <0 0x11234000 0 0xe0>;
+ interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&clk26m>,
+ <&clk26m>,
+ <&clk26m>;
+ clock-names = "spi", "sf", "axi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disable";
+ };
+
i2c3: i2c3@11cb0000 {
compatible = "mediatek,mt8192-i2c";
reg = <0 0x11cb0000 0 0x1000>,
diff --git a/arch/arm64/boot/dts/mediatek/mt8516.dtsi b/arch/arm64/boot/dts/mediatek/mt8516.dtsi
index e6e4d9d60094..b80e95574bef 100644
--- a/arch/arm64/boot/dts/mediatek/mt8516.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8516.dtsi
@@ -276,6 +276,27 @@
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
+ apdma: dma-controller@11000480 {
+ compatible = "mediatek,mt8516-uart-dma",
+ "mediatek,mt6577-uart-dma";
+ reg = <0 0x11000480 0 0x80>,
+ <0 0x11000500 0 0x80>,
+ <0 0x11000580 0 0x80>,
+ <0 0x11000600 0 0x80>,
+ <0 0x11000980 0 0x80>,
+ <0 0x11000a00 0 0x80>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_LOW>;
+ dma-requests = <6>;
+ clocks = <&topckgen CLK_TOP_APDMA>;
+ clock-names = "apdma";
+ #dma-cells = <1>;
+ };
+
uart0: serial@11005000 {
compatible = "mediatek,mt8516-uart",
"mediatek,mt6577-uart";
@@ -284,6 +305,9 @@
clocks = <&topckgen CLK_TOP_UART0_SEL>,
<&topckgen CLK_TOP_UART0>;
clock-names = "baud", "bus";
+ dmas = <&apdma 0
+ &apdma 1>;
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -295,6 +319,9 @@
clocks = <&topckgen CLK_TOP_UART1_SEL>,
<&topckgen CLK_TOP_UART1>;
clock-names = "baud", "bus";
+ dmas = <&apdma 2
+ &apdma 3>;
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -306,6 +333,9 @@
clocks = <&topckgen CLK_TOP_UART2_SEL>,
<&topckgen CLK_TOP_UART2>;
clock-names = "baud", "bus";
+ dmas = <&apdma 4
+ &apdma 5>;
+ dma-names = "tx", "rx";
status = "disabled";
};
generated by cgit v1.2.3 (git 2.39.0) at 2025-01-12 11:41:46 +0300