diff options
Diffstat (limited to 'arch/arm64/boot/dts/hisilicon/hi3660.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 706 |
1 files changed, 699 insertions, 7 deletions
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index 3983086bd67b..c6a1961e8d55 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -5,6 +5,7 @@ */ #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/hi3660-clock.h> / { compatible = "hisilicon,hi3660"; @@ -141,19 +142,710 @@ #size-cells = <2>; ranges; - fixed_uart5: fixed_19_2M { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <19200000>; - clock-output-names = "fixed:uart5"; + crg_ctrl: crg_ctrl@fff35000 { + compatible = "hisilicon,hi3660-crgctrl", "syscon"; + reg = <0x0 0xfff35000 0x0 0x1000>; + #clock-cells = <1>; }; - uart5: uart@fdf05000 { + crg_rst: crg_rst_controller { + compatible = "hisilicon,hi3660-reset"; + #reset-cells = <2>; + hisi,rst-syscon = <&crg_ctrl>; + }; + + + pctrl: pctrl@e8a09000 { + compatible = "hisilicon,hi3660-pctrl", "syscon"; + reg = <0x0 0xe8a09000 0x0 0x2000>; + #clock-cells = <1>; + }; + + pmuctrl: crg_ctrl@fff34000 { + compatible = "hisilicon,hi3660-pmuctrl", "syscon"; + reg = <0x0 0xfff34000 0x0 0x1000>; + #clock-cells = <1>; + }; + + sctrl: sctrl@fff0a000 { + compatible = "hisilicon,hi3660-sctrl", "syscon"; + reg = <0x0 0xfff0a000 0x0 0x1000>; + #clock-cells = <1>; + }; + + iomcu: iomcu@ffd7e000 { + compatible = "hisilicon,hi3660-iomcu", "syscon"; + reg = <0x0 0xffd7e000 0x0 0x1000>; + #clock-cells = <1>; + + }; + + iomcu_rst: reset { + compatible = "hisilicon,hi3660-reset"; + hisi,rst-syscon = <&iomcu>; + #reset-cells = <2>; + }; + + dual_timer0: timer@fff14000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x0 0xfff14000 0x0 0x1000>; + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg_ctrl HI3660_OSC32K>, + <&crg_ctrl HI3660_OSC32K>, + <&crg_ctrl HI3660_OSC32K>; + clock-names = "timer1", "timer2", "apb_pclk"; + }; + + i2c0: i2c@ffd71000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0xffd71000 0x0 0x1000>; + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>; + resets = <&iomcu_rst 0x20 3>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>; + status = "disabled"; + }; + + i2c1: i2c@ffd72000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0xffd72000 0x0 0x1000>; + interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + clocks = <&crg_ctrl HI3660_CLK_GATE_I2C1>; + resets = <&iomcu_rst 0x20 4>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>; + status = "disabled"; + }; + + i2c3: i2c@fdf0c000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0xfdf0c000 0x0 0x1000>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + clocks = <&crg_ctrl HI3660_CLK_GATE_I2C3>; + resets = <&crg_rst 0x78 7>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pmx_func &i2c3_cfg_func>; + status = "disabled"; + }; + + i2c7: i2c@fdf0b000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0xfdf0b000 0x0 0x1000>; + interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + clocks = <&crg_ctrl HI3660_CLK_GATE_I2C7>; + resets = <&crg_rst 0x60 14>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7_pmx_func &i2c7_cfg_func>; + status = "disabled"; + }; + + uart0: serial@fdf02000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xfdf02000 0x0 0x1000>; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>, + <&crg_ctrl HI3660_PCLK>; + clock-names = "uartclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>; + status = "disabled"; + }; + + uart1: serial@fdf00000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xfdf00000 0x0 0x1000>; + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg_ctrl HI3660_CLK_GATE_UART1>, + <&crg_ctrl HI3660_CLK_GATE_UART1>; + clock-names = "uartclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>; + status = "disabled"; + }; + + uart2: serial@fdf03000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xfdf03000 0x0 0x1000>; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg_ctrl HI3660_CLK_GATE_UART2>, + <&crg_ctrl HI3660_PCLK>; + clock-names = "uartclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>; + status = "disabled"; + }; + + uart3: serial@ffd74000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xffd74000 0x0 0x1000>; + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg_ctrl HI3660_FACTOR_UART3>, + <&crg_ctrl HI3660_PCLK>; + clock-names = "uartclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>; + status = "disabled"; + }; + + uart4: serial@fdf01000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xfdf01000 0x0 0x1000>; + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg_ctrl HI3660_CLK_GATE_UART4>, + <&crg_ctrl HI3660_CLK_GATE_UART4>; + clock-names = "uartclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>; + status = "disabled"; + }; + + uart5: serial@fdf05000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0xfdf05000 0x0 0x1000>; interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&fixed_uart5 &fixed_uart5>; + clocks = <&crg_ctrl HI3660_CLK_GATE_UART5>, + <&crg_ctrl HI3660_CLK_GATE_UART5>; + clock-names = "uartclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart5_pmx_func &uart5_cfg_func>; + status = "disabled"; + }; + + uart6: serial@fff32000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xfff32000 0x0 0x1000>; + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg_ctrl HI3660_CLK_UART6>, + <&crg_ctrl HI3660_PCLK>; clock-names = "uartclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart6_pmx_func &uart6_cfg_func>; + status = "disabled"; + }; + + rtc0: rtc@fff04000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0x0 0Xfff04000 0x0 0x1000>; + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg_ctrl HI3660_PCLK>; + clock-names = "apb_pclk"; + }; + + gpio0: gpio@e8a0b000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a0b000 0 0x1000>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 1 0 7>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO0>; + clock-names = "apb_pclk"; + }; + + gpio1: gpio@e8a0c000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a0c000 0 0x1000>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 1 7 7>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO1>; + clock-names = "apb_pclk"; + }; + + gpio2: gpio@e8a0d000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a0d000 0 0x1000>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 14 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO2>; + clock-names = "apb_pclk"; + }; + + gpio3: gpio@e8a0e000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a0e000 0 0x1000>; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 22 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO3>; + clock-names = "apb_pclk"; + }; + + gpio4: gpio@e8a0f000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a0f000 0 0x1000>; + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 30 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO4>; + clock-names = "apb_pclk"; + }; + + gpio5: gpio@e8a10000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a10000 0 0x1000>; + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 38 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO5>; + clock-names = "apb_pclk"; + }; + + gpio6: gpio@e8a11000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a11000 0 0x1000>; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 46 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO6>; + clock-names = "apb_pclk"; + }; + + gpio7: gpio@e8a12000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a12000 0 0x1000>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 54 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO7>; + clock-names = "apb_pclk"; + }; + + gpio8: gpio@e8a13000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a13000 0 0x1000>; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 62 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO8>; + clock-names = "apb_pclk"; + }; + + gpio9: gpio@e8a14000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a14000 0 0x1000>; + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 70 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO9>; + clock-names = "apb_pclk"; + }; + + gpio10: gpio@e8a15000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a15000 0 0x1000>; + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 78 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO10>; + clock-names = "apb_pclk"; + }; + + gpio11: gpio@e8a16000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a16000 0 0x1000>; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 86 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO11>; + clock-names = "apb_pclk"; + }; + + gpio12: gpio@e8a17000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a17000 0 0x1000>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 94 3 &pmx0 7 101 1>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO12>; + clock-names = "apb_pclk"; + }; + + gpio13: gpio@e8a18000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a18000 0 0x1000>; + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 102 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO13>; + clock-names = "apb_pclk"; + }; + + gpio14: gpio@e8a19000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a19000 0 0x1000>; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 110 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO14>; + clock-names = "apb_pclk"; + }; + + gpio15: gpio@e8a1a000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a1a000 0 0x1000>; + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 118 6>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO15>; + clock-names = "apb_pclk"; + }; + + gpio16: gpio@e8a1b000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a1b000 0 0x1000>; + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO16>; + clock-names = "apb_pclk"; + }; + + gpio17: gpio@e8a1c000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a1c000 0 0x1000>; + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO17>; + clock-names = "apb_pclk"; + }; + + gpio18: gpio@ff3b4000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xff3b4000 0 0x1000>; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx2 0 0 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO18>; + clock-names = "apb_pclk"; + }; + + gpio19: gpio@ff3b5000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xff3b5000 0 0x1000>; + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx2 0 8 4>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO19>; + clock-names = "apb_pclk"; + }; + + gpio20: gpio@e8a1f000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a1f000 0 0x1000>; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx1 0 0 6>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO20>; + clock-names = "apb_pclk"; + }; + + gpio21: gpio@e8a20000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a20000 0 0x1000>; + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&pmx3 0 0 6>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO21>; + clock-names = "apb_pclk"; + }; + + gpio22: gpio@fff0b000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xfff0b000 0 0x1000>; + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + /* GPIO176 */ + gpio-ranges = <&pmx4 2 0 6>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&sctrl HI3660_PCLK_AO_GPIO0>; + clock-names = "apb_pclk"; + }; + + gpio23: gpio@fff0c000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xfff0c000 0 0x1000>; + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + /* GPIO184 */ + gpio-ranges = <&pmx4 0 6 7>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&sctrl HI3660_PCLK_AO_GPIO1>; + clock-names = "apb_pclk"; + }; + + gpio24: gpio@fff0d000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xfff0d000 0 0x1000>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + /* GPIO192 */ + gpio-ranges = <&pmx4 0 13 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&sctrl HI3660_PCLK_AO_GPIO2>; + clock-names = "apb_pclk"; + }; + + gpio25: gpio@fff0e000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xfff0e000 0 0x1000>; + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + /* GPIO200 */ + gpio-ranges = <&pmx4 0 21 4 &pmx4 5 25 3>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&sctrl HI3660_PCLK_AO_GPIO3>; + clock-names = "apb_pclk"; + }; + + gpio26: gpio@fff0f000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xfff0f000 0 0x1000>; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + /* GPIO208 */ + gpio-ranges = <&pmx4 0 28 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&sctrl HI3660_PCLK_AO_GPIO4>; + clock-names = "apb_pclk"; + }; + + gpio27: gpio@fff10000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xfff10000 0 0x1000>; + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + /* GPIO216 */ + gpio-ranges = <&pmx4 0 36 6>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&sctrl HI3660_PCLK_AO_GPIO5>; + clock-names = "apb_pclk"; + }; + + gpio28: gpio@fff1d000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xfff1d000 0 0x1000>; + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&sctrl HI3660_PCLK_AO_GPIO6>; + clock-names = "apb_pclk"; + }; + + spi2: spi@ffd68000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x0 0xffd68000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>; + clock-names = "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pmx_func>; + num-cs = <1>; + cs-gpios = <&gpio27 2 0>; + status = "disabled"; + }; + + spi3: spi@ff3b3000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x0 0xff3b3000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>; + clock-names = "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&spi3_pmx_func>; + num-cs = <1>; + cs-gpios = <&gpio18 5 0>; + status = "disabled"; + }; + + pcie@f4000000 { + compatible = "hisilicon,kirin960-pcie"; + reg = <0x0 0xf4000000 0x0 0x1000>, + <0x0 0xff3fe000 0x0 0x1000>, + <0x0 0xf3f20000 0x0 0x40000>, + <0x0 0xf5000000 0x0 0x2000>; + reg-names = "dbi", "apb", "phy", "config"; + bus-range = <0x0 0x1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x02000000 0x0 0x00000000 + 0x0 0xf6000000 + 0x0 0x02000000>; + num-lanes = <1>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = <0x0 0 0 1 + &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 2 + &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 3 + &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 4 + &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, + <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, + <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, + <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, + <&crg_ctrl HI3660_ACLK_GATE_PCIE>; + clock-names = "pcie_phy_ref", "pcie_aux", + "pcie_apb_phy", "pcie_apb_sys", + "pcie_aclk"; + reset-gpios = <&gpio11 1 0 >; + }; + + /* SD */ + dwmmc1: dwmmc1@ff37f000 { + #address-cells = <1>; + #size-cells = <0>; + cd-inverted; + compatible = "hisilicon,hi3660-dw-mshc"; + num-slots = <1>; + bus-width = <0x4>; + disable-wp; + cap-sd-highspeed; + supports-highspeed; + card-detect-delay = <200>; + reg = <0x0 0xff37f000 0x0 0x1000>; + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg_ctrl HI3660_CLK_GATE_SD>, + <&crg_ctrl HI3660_HCLK_GATE_SD>; + clock-names = "ciu", "biu"; + clock-frequency = <3200000>; + resets = <&crg_rst 0x94 18>; + cd-gpios = <&gpio25 3 0>; + hisilicon,peripheral-syscon = <&sctrl>; + pinctrl-names = "default"; + pinctrl-0 = <&sd_pmx_func + &sd_clk_cfg_func + &sd_cfg_func>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "disabled"; + + slot@0 { + reg = <0x0>; + bus-width = <4>; + disable-wp; + }; + }; + + /* SDIO */ + dwmmc2: dwmmc2@ff3ff000 { + compatible = "hisilicon,hi3660-dw-mshc"; + reg = <0x0 0xff3ff000 0x0 0x1000>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; + num-slots = <1>; + clocks = <&crg_ctrl HI3660_CLK_GATE_SDIO0>, + <&crg_ctrl HI3660_HCLK_GATE_SDIO0>; + clock-names = "ciu", "biu"; + resets = <&crg_rst 0x94 20>; + card-detect-delay = <200>; + supports-highspeed; + keep-power-in-suspend; + pinctrl-names = "default"; + pinctrl-0 = <&sdio_pmx_func + &sdio_clk_cfg_func + &sdio_cfg_func>; status = "disabled"; }; }; |