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Diffstat (limited to 'arch/arm64/boot/dts/exynos')
-rw-r--r--arch/arm64/boot/dts/exynos/exynos5433.dtsi9
-rw-r--r--arch/arm64/boot/dts/exynos/exynos7.dtsi4
-rw-r--r--arch/arm64/boot/dts/exynos/exynos850-e850-96.dts5
-rw-r--r--arch/arm64/boot/dts/exynos/exynos850.dtsi19
-rw-r--r--arch/arm64/boot/dts/exynos/exynosautov9-sadk.dts4
-rw-r--r--arch/arm64/boot/dts/exynos/exynosautov9.dtsi116
6 files changed, 103 insertions, 54 deletions
diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index 661567d2dd7a..75b548e495a0 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -806,7 +806,8 @@
};
timer@101c0000 {
- compatible = "samsung,exynos4210-mct";
+ compatible = "samsung,exynos5433-mct",
+ "samsung,exynos4210-mct";
reg = <0x101c0000 0x800>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
@@ -1865,8 +1866,6 @@
clocks = <&cmu_fsys CLK_PDMA0>;
clock-names = "apb_pclk";
#dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <32>;
};
pdma1: dma-controller@15600000 {
@@ -1876,8 +1875,6 @@
clocks = <&cmu_fsys CLK_PDMA1>;
clock-names = "apb_pclk";
#dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <32>;
};
audio-subsystem@11400000 {
@@ -1897,8 +1894,6 @@
clocks = <&cmu_aud CLK_ACLK_DMAC>;
clock-names = "apb_pclk";
#dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <32>;
power-domains = <&pd_aud>;
};
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index e38bb02a2152..1cd771c90b47 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -149,8 +149,6 @@
clocks = <&clock_fsys0 ACLK_PDMA0>;
clock-names = "apb_pclk";
#dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <32>;
};
pdma1: dma-controller@10eb0000 {
@@ -160,8 +158,6 @@
clocks = <&clock_fsys0 ACLK_PDMA1>;
clock-names = "apb_pclk";
#dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <32>;
};
clock_topc: clock-controller@10570000 {
diff --git a/arch/arm64/boot/dts/exynos/exynos850-e850-96.dts b/arch/arm64/boot/dts/exynos/exynos850-e850-96.dts
index 7b5a61d22cc5..f52a55f644f7 100644
--- a/arch/arm64/boot/dts/exynos/exynos850-e850-96.dts
+++ b/arch/arm64/boot/dts/exynos/exynos850-e850-96.dts
@@ -20,6 +20,11 @@
model = "WinLink E850-96 board";
compatible = "winlink,e850-96", "samsung,exynos850";
+ aliases {
+ mmc0 = &mmc_0;
+ serial0 = &serial_0;
+ };
+
chosen {
stdout-path = &serial_0;
};
diff --git a/arch/arm64/boot/dts/exynos/exynos850.dtsi b/arch/arm64/boot/dts/exynos/exynos850.dtsi
index d1700e96fee2..9076afd4bb3e 100644
--- a/arch/arm64/boot/dts/exynos/exynos850.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos850.dtsi
@@ -29,22 +29,6 @@
pinctrl3 = &pinctrl_hsi;
pinctrl4 = &pinctrl_core;
pinctrl5 = &pinctrl_peri;
- mmc0 = &mmc_0;
- serial0 = &serial_0;
- serial1 = &serial_1;
- serial2 = &serial_2;
- i2c0 = &i2c_0;
- i2c1 = &i2c_1;
- i2c2 = &i2c_2;
- i2c3 = &i2c_3;
- i2c4 = &i2c_4;
- i2c5 = &i2c_5;
- i2c6 = &i2c_6;
- i2c7 = &hsi2c_0;
- i2c8 = &hsi2c_1;
- i2c9 = &hsi2c_2;
- i2c10 = &hsi2c_3;
- i2c11 = &hsi2c_4;
};
arm-pmu {
@@ -181,7 +165,8 @@
};
timer@10040000 {
- compatible = "samsung,exynos4210-mct";
+ compatible = "samsung,exynos850-mct",
+ "samsung,exynos4210-mct";
reg = <0x10040000 0x800>;
interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
diff --git a/arch/arm64/boot/dts/exynos/exynosautov9-sadk.dts b/arch/arm64/boot/dts/exynos/exynosautov9-sadk.dts
index 57518cb5e8c4..17e568853eb6 100644
--- a/arch/arm64/boot/dts/exynos/exynosautov9-sadk.dts
+++ b/arch/arm64/boot/dts/exynos/exynosautov9-sadk.dts
@@ -58,3 +58,7 @@
&usi_0 {
status = "okay";
};
+
+&xtcxo {
+ clock-frequency = <26000000>;
+};
diff --git a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi
index 807d500d6022..0ce46ec5cdc3 100644
--- a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi
@@ -6,6 +6,7 @@
*
*/
+#include <dt-bindings/clock/samsung,exynosautov9.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/samsung,exynos-usi.h>
@@ -153,30 +154,8 @@
xtcxo: clock {
compatible = "fixed-clock";
#clock-cells = <0>;
- clock-frequency = <26000000>;
clock-output-names = "oscclk";
};
-
- /*
- * Keep the stub clock for serial driver, until proper clock
- * driver is implemented.
- */
- uart_clock: uart-clock {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <133250000>;
- clock-output-names = "uart";
- };
-
- /*
- * Keep the stub clock for ufs driver, until proper clock
- * driver is implemented.
- */
- ufs_core_clock: ufs-core-clock {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <166562500>;
- };
};
soc: soc@0 {
@@ -190,6 +169,89 @@
reg = <0x10000000 0x24>;
};
+ cmu_peris: clock-controller@10020000 {
+ compatible = "samsung,exynosautov9-cmu-peris";
+ reg = <0x10020000 0x8000>;
+ #clock-cells = <1>;
+
+ clocks = <&xtcxo>,
+ <&cmu_top DOUT_CLKCMU_PERIS_BUS>;
+ clock-names = "oscclk",
+ "dout_clkcmu_peris_bus";
+ };
+
+ cmu_peric0: clock-controller@10200000 {
+ compatible = "samsung,exynosautov9-cmu-peric0";
+ reg = <0x10200000 0x8000>;
+ #clock-cells = <1>;
+
+ clocks = <&xtcxo>,
+ <&cmu_top DOUT_CLKCMU_PERIC0_BUS>,
+ <&cmu_top DOUT_CLKCMU_PERIC0_IP>;
+ clock-names = "oscclk",
+ "dout_clkcmu_peric0_bus",
+ "dout_clkcmu_peric0_ip";
+ };
+
+ cmu_peric1: clock-controller@10800000 {
+ compatible = "samsung,exynosautov9-cmu-peric1";
+ reg = <0x10800000 0x8000>;
+ #clock-cells = <1>;
+
+ clocks = <&xtcxo>,
+ <&cmu_top DOUT_CLKCMU_PERIC1_BUS>,
+ <&cmu_top DOUT_CLKCMU_PERIC1_IP>;
+ clock-names = "oscclk",
+ "dout_clkcmu_peric1_bus",
+ "dout_clkcmu_peric1_ip";
+ };
+
+ cmu_fsys2: clock-controller@17c00000 {
+ compatible = "samsung,exynosautov9-cmu-fsys2";
+ reg = <0x17c00000 0x8000>;
+ #clock-cells = <1>;
+
+ clocks = <&xtcxo>,
+ <&cmu_top DOUT_CLKCMU_FSYS2_BUS>,
+ <&cmu_top DOUT_CLKCMU_FSYS2_UFS_EMBD>,
+ <&cmu_top DOUT_CLKCMU_FSYS2_ETHERNET>;
+ clock-names = "oscclk",
+ "dout_clkcmu_fsys2_bus",
+ "dout_fsys2_clkcmu_ufs_embd",
+ "dout_fsys2_clkcmu_ethernet";
+ };
+
+ cmu_core: clock-controller@1b030000 {
+ compatible = "samsung,exynosautov9-cmu-core";
+ reg = <0x1b030000 0x8000>;
+ #clock-cells = <1>;
+
+ clocks = <&xtcxo>,
+ <&cmu_top DOUT_CLKCMU_CORE_BUS>;
+ clock-names = "oscclk",
+ "dout_clkcmu_core_bus";
+ };
+
+ cmu_busmc: clock-controller@1b200000 {
+ compatible = "samsung,exynosautov9-cmu-busmc";
+ reg = <0x1b200000 0x8000>;
+ #clock-cells = <1>;
+
+ clocks = <&xtcxo>,
+ <&cmu_top DOUT_CLKCMU_BUSMC_BUS>;
+ clock-names = "oscclk",
+ "dout_clkcmu_busmc_bus";
+ };
+
+ cmu_top: clock-controller@1b240000 {
+ compatible = "samsung,exynosautov9-cmu-top";
+ reg = <0x1b240000 0x8000>;
+ #clock-cells = <1>;
+
+ clocks = <&xtcxo>;
+ clock-names = "oscclk";
+ };
+
gic: interrupt-controller@10101000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
@@ -271,7 +333,8 @@
#address-cells = <1>;
#size-cells = <1>;
ranges;
- clocks = <&uart_clock>, <&uart_clock>;
+ clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_0>,
+ <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_0>;
clock-names = "pclk", "ipclk";
status = "disabled";
@@ -282,7 +345,8 @@
interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&uart0_bus_dual>;
- clocks = <&uart_clock>, <&uart_clock>;
+ clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_0>,
+ <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_0>;
clock-names = "uart", "clk_uart_baud0";
status = "disabled";
};
@@ -308,8 +372,8 @@
<0x17dc0000 0x2200>; /* 3: UFS protector */
reg-names = "hci", "vs_hci", "unipro", "ufsp";
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ufs_core_clock>,
- <&ufs_core_clock>;
+ clocks = <&cmu_fsys2 CLK_GOUT_FSYS2_UFS_EMBD0_ACLK>,
+ <&cmu_fsys2 CLK_GOUT_FSYS2_UFS_EMBD0_UNIPRO>;
clock-names = "core_clk", "sclk_unipro_main";
freq-table-hz = <0 0>, <0 0>;
pinctrl-names = "default";
generated by cgit v1.2.3 (git 2.39.0) at 2025-01-28 21:56:43 +0300