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Diffstat (limited to 'arch/arm64/boot/dts/apple/t8103.dtsi')
-rw-r--r--arch/arm64/boot/dts/apple/t8103.dtsi48
1 files changed, 43 insertions, 5 deletions
diff --git a/arch/arm64/boot/dts/apple/t8103.dtsi b/arch/arm64/boot/dts/apple/t8103.dtsi
index 6f5a2334e5b1..9859219699f4 100644
--- a/arch/arm64/boot/dts/apple/t8103.dtsi
+++ b/arch/arm64/boot/dts/apple/t8103.dtsi
@@ -63,6 +63,9 @@
operating-points-v2 = <&ecluster_opp>;
capacity-dmips-mhz = <714>;
performance-domains = <&cpufreq_e>;
+ next-level-cache = <&l2_cache_0>;
+ i-cache-size = <0x20000>;
+ d-cache-size = <0x10000>;
};
cpu_e1: cpu@1 {
@@ -74,6 +77,9 @@
operating-points-v2 = <&ecluster_opp>;
capacity-dmips-mhz = <714>;
performance-domains = <&cpufreq_e>;
+ next-level-cache = <&l2_cache_0>;
+ i-cache-size = <0x20000>;
+ d-cache-size = <0x10000>;
};
cpu_e2: cpu@2 {
@@ -85,6 +91,9 @@
operating-points-v2 = <&ecluster_opp>;
capacity-dmips-mhz = <714>;
performance-domains = <&cpufreq_e>;
+ next-level-cache = <&l2_cache_0>;
+ i-cache-size = <0x20000>;
+ d-cache-size = <0x10000>;
};
cpu_e3: cpu@3 {
@@ -96,6 +105,9 @@
operating-points-v2 = <&ecluster_opp>;
capacity-dmips-mhz = <714>;
performance-domains = <&cpufreq_e>;
+ next-level-cache = <&l2_cache_0>;
+ i-cache-size = <0x20000>;
+ d-cache-size = <0x10000>;
};
cpu_p0: cpu@10100 {
@@ -107,6 +119,9 @@
operating-points-v2 = <&pcluster_opp>;
capacity-dmips-mhz = <1024>;
performance-domains = <&cpufreq_p>;
+ next-level-cache = <&l2_cache_1>;
+ i-cache-size = <0x30000>;
+ d-cache-size = <0x20000>;
};
cpu_p1: cpu@10101 {
@@ -118,6 +133,9 @@
operating-points-v2 = <&pcluster_opp>;
capacity-dmips-mhz = <1024>;
performance-domains = <&cpufreq_p>;
+ next-level-cache = <&l2_cache_1>;
+ i-cache-size = <0x30000>;
+ d-cache-size = <0x20000>;
};
cpu_p2: cpu@10102 {
@@ -129,6 +147,9 @@
operating-points-v2 = <&pcluster_opp>;
capacity-dmips-mhz = <1024>;
performance-domains = <&cpufreq_p>;
+ next-level-cache = <&l2_cache_1>;
+ i-cache-size = <0x30000>;
+ d-cache-size = <0x20000>;
};
cpu_p3: cpu@10103 {
@@ -140,6 +161,23 @@
operating-points-v2 = <&pcluster_opp>;
capacity-dmips-mhz = <1024>;
performance-domains = <&cpufreq_p>;
+ next-level-cache = <&l2_cache_1>;
+ i-cache-size = <0x30000>;
+ d-cache-size = <0x20000>;
+ };
+
+ l2_cache_0: l2-cache-0 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ cache-size = <0x400000>;
+ };
+
+ l2_cache_1: l2-cache-1 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ cache-size = <0xc00000>;
};
};
@@ -318,7 +356,7 @@
#performance-domain-cells = <0>;
};
- dart_sio: iommu@235004000 {
+ sio_dart: iommu@235004000 {
compatible = "apple,t8103-dart";
reg = <0x2 0x35004000 0x0 0x4000>;
interrupt-parent = <&aic>;
@@ -431,7 +469,7 @@
<0>,
<0>;
#dma-cells = <1>;
- iommus = <&dart_sio 2>;
+ iommus = <&sio_dart 2>;
power-domains = <&ps_sio_adma>;
resets = <&ps_audio_p>;
};
@@ -670,7 +708,7 @@
resets = <&ps_ans2>;
};
- pcie0_dart_0: dart@681008000 {
+ pcie0_dart_0: iommu@681008000 {
compatible = "apple,t8103-dart";
reg = <0x6 0x81008000 0x0 0x4000>;
#iommu-cells = <1>;
@@ -679,7 +717,7 @@
power-domains = <&ps_apcie_gp>;
};
- pcie0_dart_1: dart@682008000 {
+ pcie0_dart_1: iommu@682008000 {
compatible = "apple,t8103-dart";
reg = <0x6 0x82008000 0x0 0x4000>;
#iommu-cells = <1>;
@@ -688,7 +726,7 @@
power-domains = <&ps_apcie_gp>;
};
- pcie0_dart_2: dart@683008000 {
+ pcie0_dart_2: iommu@683008000 {
compatible = "apple,t8103-dart";
reg = <0x6 0x83008000 0x0 0x4000>;
#iommu-cells = <1>;