diff options
Diffstat (limited to 'arch/arm/plat-samsung')
27 files changed, 218 insertions, 467 deletions
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig index 32be05cf82a3..4d79519d19a4 100644 --- a/arch/arm/plat-samsung/Kconfig +++ b/arch/arm/plat-samsung/Kconfig @@ -8,6 +8,7 @@ config PLAT_SAMSUNG bool depends on PLAT_S3C24XX || ARCH_S3C64XX || PLAT_S5P select NO_IOPORT + select GENERIC_IRQ_CHIP default y help Base platform code for all Samsung SoC based systems @@ -273,6 +274,19 @@ config SAMSUNG_DEV_KEYPAD help Compile in platform device definitions for keypad +config SAMSUNG_DEV_PWM + bool + default y if ARCH_S3C2410 + help + Compile in platform device definition for PWM Timer + +config S3C24XX_PWM + bool "PWM device support" + select HAVE_PWM + help + Support for exporting the PWM timer blocks via the pwm device + system + # DMA config S3C_DMA diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile index 29932f88a8d6..53eb15b0a07d 100644 --- a/arch/arm/plat-samsung/Makefile +++ b/arch/arm/plat-samsung/Makefile @@ -19,7 +19,6 @@ obj-y += gpio.o obj-y += gpio-config.o obj-y += dev-asocdma.o -obj-$(CONFIG_SAMSUNG_GPIOLIB_4BIT) += gpiolib.o obj-$(CONFIG_SAMSUNG_CLKSRC) += clock-clksrc.o obj-$(CONFIG_SAMSUNG_IRQ_UART) += irq-uart.o @@ -59,6 +58,7 @@ obj-$(CONFIG_SAMSUNG_DEV_ADC) += dev-adc.o obj-$(CONFIG_SAMSUNG_DEV_IDE) += dev-ide.o obj-$(CONFIG_SAMSUNG_DEV_TS) += dev-ts.o obj-$(CONFIG_SAMSUNG_DEV_KEYPAD) += dev-keypad.o +obj-$(CONFIG_SAMSUNG_DEV_PWM) += dev-pwm.o # DMA support diff --git a/arch/arm/plat-samsung/dev-pwm.c b/arch/arm/plat-samsung/dev-pwm.c new file mode 100644 index 000000000000..dab47b0e1900 --- /dev/null +++ b/arch/arm/plat-samsung/dev-pwm.c @@ -0,0 +1,53 @@ +/* linux/arch/arm/plat-samsung/dev-pwm.c + * + * Copyright (c) 2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Copyright (c) 2007 Ben Dooks + * Copyright (c) 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk>, <ben-linux@fluff.org> + * + * S3C series device definition for the PWM timer + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/platform_device.h> + +#include <mach/irqs.h> + +#include <plat/devs.h> + +#define TIMER_RESOURCE_SIZE (1) + +#define TIMER_RESOURCE(_tmr, _irq) \ + (struct resource [TIMER_RESOURCE_SIZE]) { \ + [0] = { \ + .start = _irq, \ + .end = _irq, \ + .flags = IORESOURCE_IRQ \ + } \ + } + +#define DEFINE_S3C_TIMER(_tmr_no, _irq) \ + .name = "s3c24xx-pwm", \ + .id = _tmr_no, \ + .num_resources = TIMER_RESOURCE_SIZE, \ + .resource = TIMER_RESOURCE(_tmr_no, _irq), \ + +/* + * since we already have an static mapping for the timer, + * we do not bother setting any IO resource for the base. + */ + +struct platform_device s3c_device_timer[] = { + [0] = { DEFINE_S3C_TIMER(0, IRQ_TIMER0) }, + [1] = { DEFINE_S3C_TIMER(1, IRQ_TIMER1) }, + [2] = { DEFINE_S3C_TIMER(2, IRQ_TIMER2) }, + [3] = { DEFINE_S3C_TIMER(3, IRQ_TIMER3) }, + [4] = { DEFINE_S3C_TIMER(4, IRQ_TIMER4) }, +}; +EXPORT_SYMBOL(s3c_device_timer); diff --git a/arch/arm/plat-samsung/gpiolib.c b/arch/arm/plat-samsung/gpiolib.c deleted file mode 100644 index ea37c0461788..000000000000 --- a/arch/arm/plat-samsung/gpiolib.c +++ /dev/null @@ -1,206 +0,0 @@ -/* arch/arm/plat-samsung/gpiolib.c - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * Copyright (c) 2009 Samsung Electronics Co., Ltd. - * http://www.samsung.com/ - * - * SAMSUNG - GPIOlib support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/kernel.h> -#include <linux/irq.h> -#include <linux/io.h> -#include <linux/gpio.h> -#include <plat/gpio-core.h> -#include <plat/gpio-cfg.h> -#include <plat/gpio-cfg-helpers.h> - -#ifndef DEBUG_GPIO -#define gpio_dbg(x...) do { } while (0) -#else -#define gpio_dbg(x...) printk(KERN_DEBUG x) -#endif - -/* The samsung_gpiolib_4bit routines are to control the gpio banks where - * the gpio configuration register (GPxCON) has 4 bits per GPIO, as the - * following example: - * - * base + 0x00: Control register, 4 bits per gpio - * gpio n: 4 bits starting at (4*n) - * 0000 = input, 0001 = output, others mean special-function - * base + 0x04: Data register, 1 bit per gpio - * bit n: data bit n - * - * Note, since the data register is one bit per gpio and is at base + 0x4 - * we can use s3c_gpiolib_get and s3c_gpiolib_set to change the state of - * the output. -*/ - -static int samsung_gpiolib_4bit_input(struct gpio_chip *chip, - unsigned int offset) -{ - struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); - void __iomem *base = ourchip->base; - unsigned long con; - - con = __raw_readl(base + GPIOCON_OFF); - con &= ~(0xf << con_4bit_shift(offset)); - __raw_writel(con, base + GPIOCON_OFF); - - gpio_dbg("%s: %p: CON now %08lx\n", __func__, base, con); - - return 0; -} - -static int samsung_gpiolib_4bit_output(struct gpio_chip *chip, - unsigned int offset, int value) -{ - struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); - void __iomem *base = ourchip->base; - unsigned long con; - unsigned long dat; - - con = __raw_readl(base + GPIOCON_OFF); - con &= ~(0xf << con_4bit_shift(offset)); - con |= 0x1 << con_4bit_shift(offset); - - dat = __raw_readl(base + GPIODAT_OFF); - - if (value) - dat |= 1 << offset; - else - dat &= ~(1 << offset); - - __raw_writel(dat, base + GPIODAT_OFF); - __raw_writel(con, base + GPIOCON_OFF); - __raw_writel(dat, base + GPIODAT_OFF); - - gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat); - - return 0; -} - -/* The next set of routines are for the case where the GPIO configuration - * registers are 4 bits per GPIO but there is more than one register (the - * bank has more than 8 GPIOs. - * - * This case is the similar to the 4 bit case, but the registers are as - * follows: - * - * base + 0x00: Control register, 4 bits per gpio (lower 8 GPIOs) - * gpio n: 4 bits starting at (4*n) - * 0000 = input, 0001 = output, others mean special-function - * base + 0x04: Control register, 4 bits per gpio (up to 8 additions GPIOs) - * gpio n: 4 bits starting at (4*n) - * 0000 = input, 0001 = output, others mean special-function - * base + 0x08: Data register, 1 bit per gpio - * bit n: data bit n - * - * To allow us to use the s3c_gpiolib_get and s3c_gpiolib_set routines we - * store the 'base + 0x4' address so that these routines see the data - * register at ourchip->base + 0x04. - */ - -static int samsung_gpiolib_4bit2_input(struct gpio_chip *chip, - unsigned int offset) -{ - struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); - void __iomem *base = ourchip->base; - void __iomem *regcon = base; - unsigned long con; - - if (offset > 7) - offset -= 8; - else - regcon -= 4; - - con = __raw_readl(regcon); - con &= ~(0xf << con_4bit_shift(offset)); - __raw_writel(con, regcon); - - gpio_dbg("%s: %p: CON %08lx\n", __func__, base, con); - - return 0; -} - -static int samsung_gpiolib_4bit2_output(struct gpio_chip *chip, - unsigned int offset, int value) -{ - struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); - void __iomem *base = ourchip->base; - void __iomem *regcon = base; - unsigned long con; - unsigned long dat; - unsigned con_offset = offset; - - if (con_offset > 7) - con_offset -= 8; - else - regcon -= 4; - - con = __raw_readl(regcon); - con &= ~(0xf << con_4bit_shift(con_offset)); - con |= 0x1 << con_4bit_shift(con_offset); - - dat = __raw_readl(base + GPIODAT_OFF); - - if (value) - dat |= 1 << offset; - else - dat &= ~(1 << offset); - - __raw_writel(dat, base + GPIODAT_OFF); - __raw_writel(con, regcon); - __raw_writel(dat, base + GPIODAT_OFF); - - gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat); - - return 0; -} - -void __init samsung_gpiolib_add_4bit(struct s3c_gpio_chip *chip) -{ - chip->chip.direction_input = samsung_gpiolib_4bit_input; - chip->chip.direction_output = samsung_gpiolib_4bit_output; - chip->pm = __gpio_pm(&s3c_gpio_pm_4bit); -} - -void __init samsung_gpiolib_add_4bit2(struct s3c_gpio_chip *chip) -{ - chip->chip.direction_input = samsung_gpiolib_4bit2_input; - chip->chip.direction_output = samsung_gpiolib_4bit2_output; - chip->pm = __gpio_pm(&s3c_gpio_pm_4bit); -} - -void __init samsung_gpiolib_add_4bit_chips(struct s3c_gpio_chip *chip, - int nr_chips) -{ - for (; nr_chips > 0; nr_chips--, chip++) { - samsung_gpiolib_add_4bit(chip); - s3c_gpiolib_add(chip); - } -} - -void __init samsung_gpiolib_add_4bit2_chips(struct s3c_gpio_chip *chip, - int nr_chips) -{ - for (; nr_chips > 0; nr_chips--, chip++) { - samsung_gpiolib_add_4bit2(chip); - s3c_gpiolib_add(chip); - } -} - -void __init samsung_gpiolib_add_2bit_chips(struct s3c_gpio_chip *chip, - int nr_chips) -{ - for (; nr_chips > 0; nr_chips--, chip++) - s3c_gpiolib_add(chip); -} diff --git a/arch/arm/plat-samsung/include/plat/clock.h b/arch/arm/plat-samsung/include/plat/clock.h index 9a82b8874918..983c578b8276 100644 --- a/arch/arm/plat-samsung/include/plat/clock.h +++ b/arch/arm/plat-samsung/include/plat/clock.h @@ -21,7 +21,7 @@ struct clk; * @set_parent: set the clock's parent, see clk_set_parent(). * * Group the common clock implementations together so that we - * don't have to keep setting the same fiels again. We leave + * don't have to keep setting the same fields again. We leave * enable in struct clk. * * Adding an extra layer of indirection into the process should diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h index 9addb3dfb4bc..c0a5741b23e6 100644 --- a/arch/arm/plat-samsung/include/plat/cpu.h +++ b/arch/arm/plat-samsung/include/plat/cpu.h @@ -68,6 +68,12 @@ extern void s3c24xx_init_uartdevs(char *name, struct sys_timer; extern struct sys_timer s3c24xx_timer; +extern struct syscore_ops s3c2410_pm_syscore_ops; +extern struct syscore_ops s3c2412_pm_syscore_ops; +extern struct syscore_ops s3c2416_pm_syscore_ops; +extern struct syscore_ops s3c244x_pm_syscore_ops; +extern struct syscore_ops s3c64xx_irq_syscore_ops; + /* system device classes */ extern struct sysdev_class s3c2410_sysclass; @@ -80,8 +86,8 @@ extern struct sysdev_class s3c2443_sysclass; extern struct sysdev_class s3c6410_sysclass; extern struct sysdev_class s3c64xx_sysclass; extern struct sysdev_class s5p64x0_sysclass; -extern struct sysdev_class s5p6442_sysclass; extern struct sysdev_class s5pv210_sysclass; +extern struct sysdev_class exynos4_sysclass; extern void (*s5pc1xx_idle)(void); diff --git a/arch/arm/plat-samsung/include/plat/debug-macro.S b/arch/arm/plat-samsung/include/plat/debug-macro.S index dc6efd90e8ff..207e275362a8 100644 --- a/arch/arm/plat-samsung/include/plat/debug-macro.S +++ b/arch/arm/plat-samsung/include/plat/debug-macro.S @@ -11,7 +11,7 @@ #include <plat/regs-serial.h> -/* The S5PV210/S5PC110 and S5P6442 implementations are as belows. */ +/* The S5PV210/S5PC110 implementations are as belows. */ .macro fifo_level_s5pv210 rd, rx ldr \rd, [ \rx, # S3C2410_UFSTAT ] diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h index b4d208b42957..b61b8ee7cc52 100644 --- a/arch/arm/plat-samsung/include/plat/devs.h +++ b/arch/arm/plat-samsung/include/plat/devs.h @@ -1,5 +1,8 @@ /* arch/arm/plat-samsung/include/plat/devs.h * + * Copyright (c) 2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * * Copyright (c) 2004 Simtec Electronics * Ben Dooks <ben@simtec.co.uk> * @@ -85,6 +88,7 @@ extern struct platform_device s3c64xx_device_onenand1; extern struct platform_device s5p_device_onenand; extern struct platform_device s3c_device_usbgadget; +extern struct platform_device s3c_device_usb_hsudc; extern struct platform_device s3c_device_usb_hsotg; extern struct platform_device s5pv210_device_ac97; @@ -96,21 +100,16 @@ extern struct platform_device s5pv210_device_iis1; extern struct platform_device s5pv210_device_iis2; extern struct platform_device s5pv210_device_spdif; -extern struct platform_device s5pv310_device_ac97; -extern struct platform_device s5pv310_device_pcm0; -extern struct platform_device s5pv310_device_pcm1; -extern struct platform_device s5pv310_device_pcm2; -extern struct platform_device s5pv310_device_i2s0; -extern struct platform_device s5pv310_device_i2s1; -extern struct platform_device s5pv310_device_i2s2; -extern struct platform_device s5pv310_device_spdif; -extern struct platform_device s5pv310_device_pd[]; - -extern struct platform_device s5p6442_device_pcm0; -extern struct platform_device s5p6442_device_pcm1; -extern struct platform_device s5p6442_device_iis0; -extern struct platform_device s5p6442_device_iis1; -extern struct platform_device s5p6442_device_spi; +extern struct platform_device exynos4_device_ac97; +extern struct platform_device exynos4_device_pcm0; +extern struct platform_device exynos4_device_pcm1; +extern struct platform_device exynos4_device_pcm2; +extern struct platform_device exynos4_device_i2s0; +extern struct platform_device exynos4_device_i2s1; +extern struct platform_device exynos4_device_i2s2; +extern struct platform_device exynos4_device_spdif; +extern struct platform_device exynos4_device_pd[]; +extern struct platform_device exynos4_device_ahci; extern struct platform_device s5p6440_device_pcm; extern struct platform_device s5p6440_device_iis; @@ -133,11 +132,14 @@ extern struct platform_device samsung_device_keypad; extern struct platform_device s5p_device_fimc0; extern struct platform_device s5p_device_fimc1; extern struct platform_device s5p_device_fimc2; +extern struct platform_device s5p_device_fimc3; extern struct platform_device s5p_device_mipi_csis0; extern struct platform_device s5p_device_mipi_csis1; -extern struct platform_device s5pv310_device_sysmmu; +extern struct platform_device s5p_device_ehci; + +extern struct platform_device exynos4_device_sysmmu; /* s3c2440 specific devices */ diff --git a/arch/arm/plat-samsung/include/plat/fimc-core.h b/arch/arm/plat-samsung/include/plat/fimc-core.h index 81a3bfeeccad..945a99d59563 100644 --- a/arch/arm/plat-samsung/include/plat/fimc-core.h +++ b/arch/arm/plat-samsung/include/plat/fimc-core.h @@ -38,6 +38,11 @@ static inline void s3c_fimc_setname(int id, char *name) s5p_device_fimc2.name = name; break; #endif +#ifdef CONFIG_S5P_DEV_FIMC3 + case 3: + s5p_device_fimc3.name = name; + break; +#endif } } diff --git a/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h b/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h index 5603db0b79bc..3ad8386599c3 100644 --- a/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h +++ b/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h @@ -114,7 +114,7 @@ extern unsigned s3c_gpio_getcfg_s3c24xx_a(struct s3c_gpio_chip *chip, * of control per GPIO, generally in the form of: * 0000 = Input * 0001 = Output - * others = Special functions (dependant on bank) + * others = Special functions (dependent on bank) * * Note, since the code to deal with the case where there are two control * registers instead of one, we do not have a separate set of functions for diff --git a/arch/arm/plat-samsung/include/plat/gpio-cfg.h b/arch/arm/plat-samsung/include/plat/gpio-cfg.h index e4b5cf126fa9..1762dcb4cb9e 100644 --- a/arch/arm/plat-samsung/include/plat/gpio-cfg.h +++ b/arch/arm/plat-samsung/include/plat/gpio-cfg.h @@ -125,7 +125,7 @@ extern int s3c_gpio_cfgpin_range(unsigned int start, unsigned int nr, * * These values control the state of the weak pull-{up,down} resistors * available on most pins on the S3C series. Not all chips support both - * up or down settings, and it may be dependant on the chip that is being + * up or down settings, and it may be dependent on the chip that is being * used to whether the particular mode is available. */ #define S3C_GPIO_PULL_NONE ((__force s3c_gpio_pull_t)0x00) @@ -138,7 +138,7 @@ extern int s3c_gpio_cfgpin_range(unsigned int start, unsigned int nr, * @pull: The configuration for the pull resistor. * * This function sets the state of the pull-{up,down} resistor for the - * specified pin. It will return 0 if successfull, or a negative error + * specified pin. It will return 0 if successful, or a negative error * code if the pin cannot support the requested pull setting. * * @pull is one of S3C_GPIO_PULL_NONE, S3C_GPIO_PULL_DOWN or S3C_GPIO_PULL_UP. @@ -202,7 +202,7 @@ extern s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin); * @drvstr: The new value of the driver strength * * This function sets the driver strength value for the specified pin. - * It will return 0 if successfull, or a negative error code if the pin + * It will return 0 if successful, or a negative error code if the pin * cannot support the requested setting. */ extern int s5p_gpio_set_drvstr(unsigned int pin, s5p_gpio_drvstr_t drvstr); @@ -225,4 +225,20 @@ extern int s5p_gpio_set_drvstr(unsigned int pin, s5p_gpio_drvstr_t drvstr); */ extern int s5p_register_gpio_interrupt(int pin); +/** s5p_register_gpioint_bank() - add gpio bank for further gpio interrupt + * registration (see s5p_register_gpio_interrupt function) + * @chain_irq: chained irq number for the gpio int handler for this bank + * @start: start gpio group number of this bank + * @nr_groups: number of gpio groups handled by this bank + * + * This functions registers initial information about gpio banks that + * can be later used by the s5p_register_gpio_interrupt() function to + * enable support for gpio interrupt for particular gpio group. + */ +#ifdef CONFIG_S5P_GPIO_INT +extern int s5p_register_gpioint_bank(int chain_irq, int start, int nr_groups); +#else +#define s5p_register_gpioint_bank(chain_irq, start, nr_groups) do { } while (0) +#endif + #endif /* __PLAT_GPIO_CFG_H */ diff --git a/arch/arm/plat-samsung/include/plat/gpio-core.h b/arch/arm/plat-samsung/include/plat/gpio-core.h index dac35d0a711d..8cad4cf19c3c 100644 --- a/arch/arm/plat-samsung/include/plat/gpio-core.h +++ b/arch/arm/plat-samsung/include/plat/gpio-core.h @@ -108,7 +108,7 @@ extern void s3c_gpiolib_add(struct s3c_gpio_chip *chip); * of control per GPIO, generally in the form of: * 0000 = Input * 0001 = Output - * others = Special functions (dependant on bank) + * others = Special functions (dependent on bank) * * Note, since the code to deal with the case where there are two control * registers instead of one, we do not have a separate set of function diff --git a/arch/arm/plat-samsung/include/plat/irq-vic-timer.h b/arch/arm/plat-samsung/include/plat/irq-vic-timer.h index a90b53431b5b..5b9c42fd32d7 100644 --- a/arch/arm/plat-samsung/include/plat/irq-vic-timer.h +++ b/arch/arm/plat-samsung/include/plat/irq-vic-timer.h @@ -10,4 +10,4 @@ * published by the Free Software Foundation. */ -extern void s3c_init_vic_timer_irq(unsigned int vic, unsigned int timer); +extern void s3c_init_vic_timer_irq(unsigned int num, unsigned int timer_irq); diff --git a/arch/arm/plat-samsung/include/plat/pd.h b/arch/arm/plat-samsung/include/plat/pd.h index 5f0ad85783db..abb4bc32716a 100644 --- a/arch/arm/plat-samsung/include/plat/pd.h +++ b/arch/arm/plat-samsung/include/plat/pd.h @@ -1,6 +1,6 @@ /* linux/arch/arm/plat-samsung/include/plat/pd.h * - * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. * http://www.samsung.com * * This program is free software; you can redistribute it and/or modify @@ -17,7 +17,7 @@ struct samsung_pd_info { void __iomem *base; }; -enum s5pv310_pd_block { +enum exynos4_pd_block { PD_MFC, PD_G3D, PD_LCD0, diff --git a/arch/arm/plat-samsung/include/plat/pm.h b/arch/arm/plat-samsung/include/plat/pm.h index 30518cc9a67c..7fb6f6be8c81 100644 --- a/arch/arm/plat-samsung/include/plat/pm.h +++ b/arch/arm/plat-samsung/include/plat/pm.h @@ -52,13 +52,11 @@ extern unsigned char pm_uart_udivslot; /* true to save UART UDIVSLOT */ /* from sleep.S */ -extern int s3c_cpu_save(unsigned long *saveblk); +extern int s3c_cpu_save(unsigned long *saveblk, long); extern void s3c_cpu_resume(void); extern void s3c2410_cpu_suspend(void); -extern unsigned long s3c_sleep_save_phys; - /* sleep save info */ /** @@ -105,14 +103,16 @@ extern void s3c_pm_do_restore_core(struct sleep_save *ptr, int count); #ifdef CONFIG_PM extern int s3c_irqext_wake(struct irq_data *data, unsigned int state); -extern int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state); -extern int s3c24xx_irq_resume(struct sys_device *dev); +extern int s3c24xx_irq_suspend(void); +extern void s3c24xx_irq_resume(void); #else #define s3c_irqext_wake NULL #define s3c24xx_irq_suspend NULL #define s3c24xx_irq_resume NULL #endif +extern struct syscore_ops s3c24xx_irq_syscore_ops; + /* PM debug functions */ #ifdef CONFIG_SAMSUNG_PM_DEBUG @@ -181,13 +181,5 @@ extern void s3c_pm_restore_gpios(void); */ extern void s3c_pm_save_gpios(void); -/** - * s3c_pm_cb_flushcache - callback for assembly code - * - * Callback to issue flush_cache_all() as this call is - * not a directly callable object. - */ -extern void s3c_pm_cb_flushcache(void); - extern void s3c_pm_save_core(void); extern void s3c_pm_restore_core(void); diff --git a/arch/arm/plat-samsung/include/plat/regs-serial.h b/arch/arm/plat-samsung/include/plat/regs-serial.h index 788837e99cb3..c151c5f94a87 100644 --- a/arch/arm/plat-samsung/include/plat/regs-serial.h +++ b/arch/arm/plat-samsung/include/plat/regs-serial.h @@ -194,7 +194,7 @@ #define S3C64XX_UINTSP 0x34 #define S3C64XX_UINTM 0x38 -/* Following are specific to S5PV210 and S5P6442 */ +/* Following are specific to S5PV210 */ #define S5PV210_UCON_CLKMASK (1<<10) #define S5PV210_UCON_PCLK (0<<10) #define S5PV210_UCON_UCLK (1<<10) diff --git a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h index ff1a561b326e..0ffe34a21554 100644 --- a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h +++ b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h @@ -69,6 +69,5 @@ extern void s3c64xx_spi_set_info(int cntrlr, int src_clk_nr, int num_cs); extern void s5pc100_spi_set_info(int cntrlr, int src_clk_nr, int num_cs); extern void s5pv210_spi_set_info(int cntrlr, int src_clk_nr, int num_cs); extern void s5p64x0_spi_set_info(int cntrlr, int src_clk_nr, int num_cs); -extern void s5p6442_spi_set_info(int cntrlr, int src_clk_nr, int num_cs); #endif /* __S3C64XX_PLAT_SPI_H */ diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h index 5a41a0b69eec..058e09654fe8 100644 --- a/arch/arm/plat-samsung/include/plat/sdhci.h +++ b/arch/arm/plat-samsung/include/plat/sdhci.h @@ -1,4 +1,7 @@ -/* linux/arch/arm/plat-s3c/include/plat/sdhci.h +/* linux/arch/arm/plat-samsung/include/plat/sdhci.h + * + * Copyright (c) 2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com * * Copyright 2008 Openmoko, Inc. * Copyright 2008 Simtec Electronics @@ -54,7 +57,7 @@ enum clk_types { * @cfg_gpio: Configure the GPIO for a specific card bit-width * @cfg_card: Configure the interface for a specific card and speed. This * is necessary the controllers and/or GPIO blocks require the - * changing of driver-strength and other controls dependant on + * changing of driver-strength and other controls dependent on * the card and speed of operation. * * Initialisation data specific to either the machine or the platform @@ -105,7 +108,7 @@ extern struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata; extern struct s3c_sdhci_platdata s3c_hsmmc2_def_platdata; extern struct s3c_sdhci_platdata s3c_hsmmc3_def_platdata; -/* Helper function availablity */ +/* Helper function availability */ extern void s3c2416_setup_sdhci0_cfg_gpio(struct platform_device *, int w); extern void s3c2416_setup_sdhci1_cfg_gpio(struct platform_device *, int w); @@ -119,10 +122,10 @@ extern void s5pv210_setup_sdhci0_cfg_gpio(struct platform_device *, int w); extern void s5pv210_setup_sdhci1_cfg_gpio(struct platform_device *, int w); extern void s5pv210_setup_sdhci2_cfg_gpio(struct platform_device *, int w); extern void s5pv210_setup_sdhci3_cfg_gpio(struct platform_device *, int w); -extern void s5pv310_setup_sdhci0_cfg_gpio(struct platform_device *, int w); -extern void s5pv310_setup_sdhci1_cfg_gpio(struct platform_device *, int w); -extern void s5pv310_setup_sdhci2_cfg_gpio(struct platform_device *, int w); -extern void s5pv310_setup_sdhci3_cfg_gpio(struct platform_device *, int w); +extern void exynos4_setup_sdhci0_cfg_gpio(struct platform_device *, int w); +extern void exynos4_setup_sdhci1_cfg_gpio(struct platform_device *, int w); +extern void exynos4_setup_sdhci2_cfg_gpio(struct platform_device *, int w); +extern void exynos4_setup_sdhci3_cfg_gpio(struct platform_device *, int w); /* S3C2416 SDHCI setup */ @@ -334,57 +337,57 @@ static inline void s5pv210_default_sdhci3(void) { } #endif /* CONFIG_S5PV210_SETUP_SDHCI */ -/* S5PV310 SDHCI setup */ -#ifdef CONFIG_S5PV310_SETUP_SDHCI -extern char *s5pv310_hsmmc_clksrcs[4]; +/* EXYNOS4 SDHCI setup */ +#ifdef CONFIG_EXYNOS4_SETUP_SDHCI +extern char *exynos4_hsmmc_clksrcs[4]; -extern void s5pv310_setup_sdhci_cfg_card(struct platform_device *dev, +extern void exynos4_setup_sdhci_cfg_card(struct platform_device *dev, void __iomem *r, struct mmc_ios *ios, struct mmc_card *card); -static inline void s5pv310_default_sdhci0(void) +static inline void exynos4_default_sdhci0(void) { #ifdef CONFIG_S3C_DEV_HSMMC - s3c_hsmmc0_def_platdata.clocks = s5pv310_hsmmc_clksrcs; - s3c_hsmmc0_def_platdata.cfg_gpio = s5pv310_setup_sdhci0_cfg_gpio; - s3c_hsmmc0_def_platdata.cfg_card = s5pv310_setup_sdhci_cfg_card; + s3c_hsmmc0_def_platdata.clocks = exynos4_hsmmc_clksrcs; + s3c_hsmmc0_def_platdata.cfg_gpio = exynos4_setup_sdhci0_cfg_gpio; + s3c_hsmmc0_def_platdata.cfg_card = exynos4_setup_sdhci_cfg_card; #endif } -static inline void s5pv310_default_sdhci1(void) +static inline void exynos4_default_sdhci1(void) { #ifdef CONFIG_S3C_DEV_HSMMC1 - s3c_hsmmc1_def_platdata.clocks = s5pv310_hsmmc_clksrcs; - s3c_hsmmc1_def_platdata.cfg_gpio = s5pv310_setup_sdhci1_cfg_gpio; - s3c_hsmmc1_def_platdata.cfg_card = s5pv310_setup_sdhci_cfg_card; + s3c_hsmmc1_def_platdata.clocks = exynos4_hsmmc_clksrcs; + s3c_hsmmc1_def_platdata.cfg_gpio = exynos4_setup_sdhci1_cfg_gpio; + s3c_hsmmc1_def_platdata.cfg_card = exynos4_setup_sdhci_cfg_card; #endif } -static inline void s5pv310_default_sdhci2(void) +static inline void exynos4_default_sdhci2(void) { #ifdef CONFIG_S3C_DEV_HSMMC2 - s3c_hsmmc2_def_platdata.clocks = s5pv310_hsmmc_clksrcs; - s3c_hsmmc2_def_platdata.cfg_gpio = s5pv310_setup_sdhci2_cfg_gpio; - s3c_hsmmc2_def_platdata.cfg_card = s5pv310_setup_sdhci_cfg_card; + s3c_hsmmc2_def_platdata.clocks = exynos4_hsmmc_clksrcs; + s3c_hsmmc2_def_platdata.cfg_gpio = exynos4_setup_sdhci2_cfg_gpio; + s3c_hsmmc2_def_platdata.cfg_card = exynos4_setup_sdhci_cfg_card; #endif } -static inline void s5pv310_default_sdhci3(void) +static inline void exynos4_default_sdhci3(void) { #ifdef CONFIG_S3C_DEV_HSMMC3 - s3c_hsmmc3_def_platdata.clocks = s5pv310_hsmmc_clksrcs; - s3c_hsmmc3_def_platdata.cfg_gpio = s5pv310_setup_sdhci3_cfg_gpio; - s3c_hsmmc3_def_platdata.cfg_card = s5pv310_setup_sdhci_cfg_card; + s3c_hsmmc3_def_platdata.clocks = exynos4_hsmmc_clksrcs; + s3c_hsmmc3_def_platdata.cfg_gpio = exynos4_setup_sdhci3_cfg_gpio; + s3c_hsmmc3_def_platdata.cfg_card = exynos4_setup_sdhci_cfg_card; #endif } #else -static inline void s5pv310_default_sdhci0(void) { } -static inline void s5pv310_default_sdhci1(void) { } -static inline void s5pv310_default_sdhci2(void) { } -static inline void s5pv310_default_sdhci3(void) { } +static inline void exynos4_default_sdhci0(void) { } +static inline void exynos4_default_sdhci1(void) { } +static inline void exynos4_default_sdhci2(void) { } +static inline void exynos4_default_sdhci3(void) { } -#endif /* CONFIG_S5PV310_SETUP_SDHCI */ +#endif /* CONFIG_EXYNOS4_SETUP_SDHCI */ #endif /* __PLAT_S3C_SDHCI_H */ diff --git a/arch/arm/plat-samsung/include/plat/uncompress.h b/arch/arm/plat-samsung/include/plat/uncompress.h index 7d6ed7263d57..ee48e12a1e72 100644 --- a/arch/arm/plat-samsung/include/plat/uncompress.h +++ b/arch/arm/plat-samsung/include/plat/uncompress.h @@ -18,8 +18,8 @@ typedef unsigned int upf_t; /* cannot include linux/serial_core.h */ /* uart setup */ -static unsigned int fifo_mask; -static unsigned int fifo_max; +unsigned int fifo_mask; +unsigned int fifo_max; /* forward declerations */ diff --git a/arch/arm/plat-samsung/init.c b/arch/arm/plat-samsung/init.c index 6790edfaca6f..79d10fca9090 100644 --- a/arch/arm/plat-samsung/init.c +++ b/arch/arm/plat-samsung/init.c @@ -36,7 +36,7 @@ static struct cpu_table * __init s3c_lookup_cpu(unsigned long idcode, unsigned int count) { for (; count != 0; count--, tab++) { - if ((idcode & tab->idmask) == tab->idcode) + if ((idcode & tab->idmask) == (tab->idcode & tab->idmask)) return tab; } diff --git a/arch/arm/plat-samsung/irq-uart.c b/arch/arm/plat-samsung/irq-uart.c index 4e770355ccbc..32582c0958e3 100644 --- a/arch/arm/plat-samsung/irq-uart.c +++ b/arch/arm/plat-samsung/irq-uart.c @@ -27,60 +27,6 @@ /* Note, we make use of the fact that the parent IRQs, IRQ_UART[0..3] * are consecutive when looking up the interrupt in the demux routines. */ - -static inline void __iomem *s3c_irq_uart_base(struct irq_data *data) -{ - struct s3c_uart_irq *uirq = irq_data_get_irq_chip_data(data); - return uirq->regs; -} - -static inline unsigned int s3c_irq_uart_bit(unsigned int irq) -{ - return irq & 3; -} - -static void s3c_irq_uart_mask(struct irq_data *data) -{ - void __iomem *regs = s3c_irq_uart_base(data); - unsigned int bit = s3c_irq_uart_bit(data->irq); - u32 reg; - - reg = __raw_readl(regs + S3C64XX_UINTM); - reg |= (1 << bit); - __raw_writel(reg, regs + S3C64XX_UINTM); -} - -static void s3c_irq_uart_maskack(struct irq_data *data) -{ - void __iomem *regs = s3c_irq_uart_base(data); - unsigned int bit = s3c_irq_uart_bit(data->irq); - u32 reg; - - reg = __raw_readl(regs + S3C64XX_UINTM); - reg |= (1 << bit); - __raw_writel(reg, regs + S3C64XX_UINTM); - __raw_writel(1 << bit, regs + S3C64XX_UINTP); -} - -static void s3c_irq_uart_unmask(struct irq_data *data) -{ - void __iomem *regs = s3c_irq_uart_base(data); - unsigned int bit = s3c_irq_uart_bit(data->irq); - u32 reg; - - reg = __raw_readl(regs + S3C64XX_UINTM); - reg &= ~(1 << bit); - __raw_writel(reg, regs + S3C64XX_UINTM); -} - -static void s3c_irq_uart_ack(struct irq_data *data) -{ - void __iomem *regs = s3c_irq_uart_base(data); - unsigned int bit = s3c_irq_uart_bit(data->irq); - - __raw_writel(1 << bit, regs + S3C64XX_UINTP); -} - static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc) { struct s3c_uart_irq *uirq = desc->irq_data.handler_data; @@ -97,35 +43,28 @@ static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc) generic_handle_irq(base + 3); } -static struct irq_chip s3c_irq_uart = { - .name = "s3c-uart", - .irq_mask = s3c_irq_uart_mask, - .irq_unmask = s3c_irq_uart_unmask, - .irq_mask_ack = s3c_irq_uart_maskack, - .irq_ack = s3c_irq_uart_ack, -}; - static void __init s3c_init_uart_irq(struct s3c_uart_irq *uirq) { - struct irq_desc *desc = irq_to_desc(uirq->parent_irq); void __iomem *reg_base = uirq->regs; - unsigned int irq; - int offs; + struct irq_chip_generic *gc; + struct irq_chip_type *ct; /* mask all interrupts at the start. */ __raw_writel(0xf, reg_base + S3C64XX_UINTM); - for (offs = 0; offs < 3; offs++) { - irq = uirq->base_irq + offs; - - set_irq_chip(irq, &s3c_irq_uart); - set_irq_chip_data(irq, uirq); - set_irq_handler(irq, handle_level_irq); - set_irq_flags(irq, IRQF_VALID); - } - - desc->irq_data.handler_data = uirq; - set_irq_chained_handler(uirq->parent_irq, s3c_irq_demux_uart); + gc = irq_alloc_generic_chip("s3c-uart", 1, uirq->base_irq, reg_base, + handle_level_irq); + ct = gc->chip_types; + ct->chip.irq_ack = irq_gc_ack; + ct->chip.irq_mask = irq_gc_mask_set_bit; + ct->chip.irq_unmask = irq_gc_mask_clr_bit; + ct->regs.ack = S3C64XX_UINTP; + ct->regs.mask = S3C64XX_UINTM; + irq_setup_generic_chip(gc, IRQ_MSK(4), IRQ_GC_INIT_MASK_CACHE, + IRQ_NOREQUEST | IRQ_NOPROBE, 0); + + irq_set_handler_data(uirq->parent_irq, uirq); + irq_set_chained_handler(uirq->parent_irq, s3c_irq_demux_uart); } /** diff --git a/arch/arm/plat-samsung/irq-vic-timer.c b/arch/arm/plat-samsung/irq-vic-timer.c index dd8692ae5c4c..a607546ddbd0 100644 --- a/arch/arm/plat-samsung/irq-vic-timer.c +++ b/arch/arm/plat-samsung/irq-vic-timer.c @@ -28,63 +28,43 @@ static void s3c_irq_demux_vic_timer(unsigned int irq, struct irq_desc *desc) } /* We assume the IRQ_TIMER0..IRQ_TIMER4 range is continuous. */ - -static void s3c_irq_timer_mask(struct irq_data *data) -{ - u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); - u32 mask = (u32)data->chip_data; - - reg &= 0x1f; /* mask out pending interrupts */ - reg &= ~mask; - __raw_writel(reg, S3C64XX_TINT_CSTAT); -} - -static void s3c_irq_timer_unmask(struct irq_data *data) +static void s3c_irq_timer_ack(struct irq_data *d) { - u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); - u32 mask = (u32)data->chip_data; + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); + u32 mask = (1 << 5) << (d->irq - gc->irq_base); - reg &= 0x1f; /* mask out pending interrupts */ - reg |= mask; - __raw_writel(reg, S3C64XX_TINT_CSTAT); + irq_reg_writel(mask | gc->mask_cache, gc->reg_base); } -static void s3c_irq_timer_ack(struct irq_data *data) -{ - u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); - u32 mask = (u32)data->chip_data; - - reg &= 0x1f; - reg |= mask << 5; - __raw_writel(reg, S3C64XX_TINT_CSTAT); -} - -static struct irq_chip s3c_irq_timer = { - .name = "s3c-timer", - .irq_mask = s3c_irq_timer_mask, - .irq_unmask = s3c_irq_timer_unmask, - .irq_ack = s3c_irq_timer_ack, -}; - /** * s3c_init_vic_timer_irq() - initialise timer irq chanined off VIC.\ - * @parent_irq: The parent IRQ on the VIC for the timer. - * @timer_irq: The IRQ to be used for the timer. + * @num: Number of timers to initialize + * @timer_irq: Base IRQ number to be used for the timers. * * Register the necessary IRQ chaining and support for the timer IRQs * chained of the VIC. */ -void __init s3c_init_vic_timer_irq(unsigned int parent_irq, - unsigned int timer_irq) +void __init s3c_init_vic_timer_irq(unsigned int num, unsigned int timer_irq) { - struct irq_desc *desc = irq_to_desc(parent_irq); - - set_irq_chained_handler(parent_irq, s3c_irq_demux_vic_timer); + unsigned int pirq[5] = { IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC, + IRQ_TIMER3_VIC, IRQ_TIMER4_VIC }; + struct irq_chip_generic *s3c_tgc; + struct irq_chip_type *ct; + unsigned int i; - set_irq_chip(timer_irq, &s3c_irq_timer); - set_irq_chip_data(timer_irq, (void *)(1 << (timer_irq - IRQ_TIMER0))); - set_irq_handler(timer_irq, handle_level_irq); - set_irq_flags(timer_irq, IRQF_VALID); + s3c_tgc = irq_alloc_generic_chip("s3c-timer", 1, timer_irq, + S3C64XX_TINT_CSTAT, handle_level_irq); + ct = s3c_tgc->chip_types; + ct->chip.irq_mask = irq_gc_mask_clr_bit; + ct->chip.irq_unmask = irq_gc_mask_set_bit; + ct->chip.irq_ack = s3c_irq_timer_ack; + irq_setup_generic_chip(s3c_tgc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, + IRQ_NOREQUEST | IRQ_NOPROBE, 0); + /* Clear the upper bits of the mask_cache*/ + s3c_tgc->mask_cache &= 0x1f; - desc->irq_data.handler_data = (void *)timer_irq; + for (i = 0; i < num; i++, timer_irq++) { + irq_set_chained_handler(pirq[i], s3c_irq_demux_vic_timer); + irq_set_handler_data(pirq[i], (void *)timer_irq); + } } diff --git a/arch/arm/plat-samsung/pm-check.c b/arch/arm/plat-samsung/pm-check.c index e4baf76f374a..6b733fafe7cd 100644 --- a/arch/arm/plat-samsung/pm-check.c +++ b/arch/arm/plat-samsung/pm-check.c @@ -164,7 +164,6 @@ static inline int in_region(void *ptr, int size, void *what, size_t whatsz) */ static u32 *s3c_pm_runcheck(struct resource *res, u32 *val) { - void *save_at = phys_to_virt(s3c_sleep_save_phys); unsigned long addr; unsigned long left; void *stkpage; @@ -192,11 +191,6 @@ static u32 *s3c_pm_runcheck(struct resource *res, u32 *val) goto skip_check; } - if (in_region(ptr, left, save_at, 32*4 )) { - S3C_PMDBG("skipping %08lx, has save block in\n", addr); - goto skip_check; - } - /* calculate and check the checksum */ calc = crc32_le(~0, ptr, left); diff --git a/arch/arm/plat-samsung/pm.c b/arch/arm/plat-samsung/pm.c index 02d531fb3f81..5c0a440d6e16 100644 --- a/arch/arm/plat-samsung/pm.c +++ b/arch/arm/plat-samsung/pm.c @@ -214,8 +214,9 @@ void s3c_pm_do_restore_core(struct sleep_save *ptr, int count) * * print any IRQs asserted at resume time (ie, we woke from) */ -static void s3c_pm_show_resume_irqs(int start, unsigned long which, - unsigned long mask) +static void __maybe_unused s3c_pm_show_resume_irqs(int start, + unsigned long which, + unsigned long mask) { int i; @@ -241,8 +242,6 @@ void (*pm_cpu_sleep)(void); static int s3c_pm_enter(suspend_state_t state) { - static unsigned long regs_save[16]; - /* ensure the debug is initialised (if enabled) */ s3c_pm_debug_init(); @@ -266,12 +265,6 @@ static int s3c_pm_enter(suspend_state_t state) return -EINVAL; } - /* store the physical address of the register recovery block */ - - s3c_sleep_save_phys = virt_to_phys(regs_save); - - S3C_PMDBG("s3c_sleep_save_phys=0x%08lx\n", s3c_sleep_save_phys); - /* save all necessary core registers not covered by the drivers */ s3c_pm_save_gpios(); @@ -305,7 +298,7 @@ static int s3c_pm_enter(suspend_state_t state) * we resume as it saves its own register state and restores it * during the resume. */ - s3c_cpu_save(regs_save); + s3c_cpu_save(0, PLAT_PHYS_OFFSET - PAGE_OFFSET); /* restore the cpu state using the kernel's cpu init code. */ @@ -336,12 +329,6 @@ static int s3c_pm_enter(suspend_state_t state) return 0; } -/* callback from assembly code */ -void s3c_pm_cb_flushcache(void) -{ - flush_cache_all(); -} - static int s3c_pm_prepare(void) { /* prepare check area if configured */ diff --git a/arch/arm/plat-samsung/pwm.c b/arch/arm/plat-samsung/pwm.c index 2eeb49fa056d..f37457c52064 100644 --- a/arch/arm/plat-samsung/pwm.c +++ b/arch/arm/plat-samsung/pwm.c @@ -20,10 +20,8 @@ #include <linux/io.h> #include <linux/pwm.h> -#include <mach/irqs.h> #include <mach/map.h> -#include <plat/devs.h> #include <plat/regs-timer.h> struct pwm_device { @@ -47,37 +45,6 @@ struct pwm_device { static struct clk *clk_scaler[2]; -/* Standard setup for a timer block. */ - -#define TIMER_RESOURCE_SIZE (1) - -#define TIMER_RESOURCE(_tmr, _irq) \ - (struct resource [TIMER_RESOURCE_SIZE]) { \ - [0] = { \ - .start = _irq, \ - .end = _irq, \ - .flags = IORESOURCE_IRQ \ - } \ - } - -#define DEFINE_S3C_TIMER(_tmr_no, _irq) \ - .name = "s3c24xx-pwm", \ - .id = _tmr_no, \ - .num_resources = TIMER_RESOURCE_SIZE, \ - .resource = TIMER_RESOURCE(_tmr_no, _irq), \ - -/* since we already have an static mapping for the timer, we do not - * bother setting any IO resource for the base. - */ - -struct platform_device s3c_device_timer[] = { - [0] = { DEFINE_S3C_TIMER(0, IRQ_TIMER0) }, - [1] = { DEFINE_S3C_TIMER(1, IRQ_TIMER1) }, - [2] = { DEFINE_S3C_TIMER(2, IRQ_TIMER2) }, - [3] = { DEFINE_S3C_TIMER(3, IRQ_TIMER3) }, - [4] = { DEFINE_S3C_TIMER(4, IRQ_TIMER4) }, -}; - static inline int pwm_is_tdiv(struct pwm_device *pwm) { return clk_get_parent(pwm->clk) == pwm->clk_div; diff --git a/arch/arm/plat-samsung/s3c-pl330.c b/arch/arm/plat-samsung/s3c-pl330.c index b4ff8d74ac40..f85638c6f5ae 100644 --- a/arch/arm/plat-samsung/s3c-pl330.c +++ b/arch/arm/plat-samsung/s3c-pl330.c @@ -68,7 +68,7 @@ struct s3c_pl330_xfer { * @req: Two requests to communicate with the PL330 engine. * @callback_fn: Callback function to the client. * @rqcfg: Channel configuration for the xfers. - * @xfer_head: Pointer to the xfer to be next excecuted. + * @xfer_head: Pointer to the xfer to be next executed. * @dmac: Pointer to the DMAC that manages this channel, NULL if the * channel is available to be acquired. * @client: Client of this channel. NULL if the diff --git a/arch/arm/plat-samsung/wakeup-mask.c b/arch/arm/plat-samsung/wakeup-mask.c index 2e09b6ad84ca..dc814037297b 100644 --- a/arch/arm/plat-samsung/wakeup-mask.c +++ b/arch/arm/plat-samsung/wakeup-mask.c @@ -22,7 +22,7 @@ void samsung_sync_wakemask(void __iomem *reg, struct samsung_wakeup_mask *mask, int nr_mask) { - struct irq_desc *desc; + struct irq_data *data; u32 val; val = __raw_readl(reg); @@ -33,10 +33,10 @@ void samsung_sync_wakemask(void __iomem *reg, continue; } - desc = irq_to_desc(mask->irq); + data = irq_get_irq_data(mask->irq); - /* bit of a liberty to read this directly from irq_desc. */ - if (desc->wake_depth > 0) + /* bit of a liberty to read this directly from irq_data. */ + if (irqd_is_wakeup_set(data)) val &= ~mask->bit; else val |= mask->bit; |