diff options
Diffstat (limited to 'arch/arm/mach-shmobile')
| -rw-r--r-- | arch/arm/mach-shmobile/Kconfig | 1 | ||||
| -rw-r--r-- | arch/arm/mach-shmobile/platsmp-apmu.c | 47 | ||||
| -rw-r--r-- | arch/arm/mach-shmobile/platsmp-scu.c | 4 | ||||
| -rw-r--r-- | arch/arm/mach-shmobile/pm-rcar-gen2.c | 40 | ||||
| -rw-r--r-- | arch/arm/mach-shmobile/rcar-gen2.h | 2 | ||||
| -rw-r--r-- | arch/arm/mach-shmobile/setup-rcar-gen2.c | 18 | ||||
| -rw-r--r-- | arch/arm/mach-shmobile/smp-r8a7791.c | 14 |
7 files changed, 60 insertions, 66 deletions
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index 2bb4b09f079e..ad7d604ff001 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig @@ -57,6 +57,7 @@ config ARCH_R7S72100 select PM select PM_GENERIC_DOMAINS select SYS_SUPPORTS_SH_MTU2 + select RENESAS_OSTM config ARCH_R8A73A4 bool "R-Mobile APE6 (R8A73A40)" diff --git a/arch/arm/mach-shmobile/platsmp-apmu.c b/arch/arm/mach-shmobile/platsmp-apmu.c index 0c6bb458b7a4..3ca2c13346f0 100644 --- a/arch/arm/mach-shmobile/platsmp-apmu.c +++ b/arch/arm/mach-shmobile/platsmp-apmu.c @@ -31,9 +31,21 @@ static struct { int bit; } apmu_cpus[NR_CPUS]; -#define WUPCR_OFFS 0x10 -#define PSTR_OFFS 0x40 -#define CPUNCR_OFFS(n) (0x100 + (0x10 * (n))) +#define WUPCR_OFFS 0x10 /* Wake Up Control Register */ +#define PSTR_OFFS 0x40 /* Power Status Register */ +#define CPUNCR_OFFS(n) (0x100 + (0x10 * (n))) + /* CPUn Power Status Control Register */ +#define DBGRCR_OFFS 0x180 /* Debug Resource Reset Control Reg. */ + +/* Power Status Register */ +#define CPUNST(r, n) (((r) >> (n * 4)) & 3) /* CPUn Status Bit */ +#define CPUST_RUN 0 /* Run Mode */ +#define CPUST_STANDBY 3 /* CoreStandby Mode */ + +/* Debug Resource Reset Control Register */ +#define DBGCPUREN BIT(24) /* CPU Other Reset Request Enable */ +#define DBGCPUNREN(n) BIT((n) + 20) /* CPUn Reset Request Enable */ +#define DBGCPUPREN BIT(19) /* CPU Peripheral Reset Req. Enable */ static int __maybe_unused apmu_power_on(void __iomem *p, int bit) { @@ -59,7 +71,7 @@ static int __maybe_unused apmu_power_off_poll(void __iomem *p, int bit) int k; for (k = 0; k < 1000; k++) { - if (((readl_relaxed(p + PSTR_OFFS) >> (bit * 4)) & 0x03) == 3) + if (CPUNST(readl_relaxed(p + PSTR_OFFS), bit) == CPUST_STANDBY) return 1; mdelay(1); @@ -78,6 +90,8 @@ static int __maybe_unused apmu_wrap(int cpu, int (*fn)(void __iomem *p, int cpu) #ifdef CONFIG_SMP static void apmu_init_cpu(struct resource *res, int cpu, int bit) { + u32 x; + if ((cpu >= ARRAY_SIZE(apmu_cpus)) || apmu_cpus[cpu].iomem) return; @@ -85,6 +99,11 @@ static void apmu_init_cpu(struct resource *res, int cpu, int bit) apmu_cpus[cpu].bit = bit; pr_debug("apmu ioremap %d %d %pr\n", cpu, bit, res); + + /* Setup for debug mode */ + x = readl(apmu_cpus[cpu].iomem + DBGRCR_OFFS); + x |= DBGCPUREN | DBGCPUNREN(bit) | DBGCPUPREN; + writel(x, apmu_cpus[cpu].iomem + DBGRCR_OFFS); } static void apmu_parse_cfg(void (*fn)(struct resource *res, int cpu, int bit), @@ -171,7 +190,7 @@ static void apmu_parse_dt(void (*fn)(struct resource *res, int cpu, int bit)) static void __init shmobile_smp_apmu_setup_boot(void) { /* install boot code shared by all CPUs */ - shmobile_boot_fn = virt_to_phys(shmobile_smp_boot); + shmobile_boot_fn = __pa_symbol(shmobile_smp_boot); } void __init shmobile_smp_apmu_prepare_cpus(unsigned int max_cpus, @@ -185,7 +204,7 @@ void __init shmobile_smp_apmu_prepare_cpus(unsigned int max_cpus, int shmobile_smp_apmu_boot_secondary(unsigned int cpu, struct task_struct *idle) { /* For this particular CPU register boot vector */ - shmobile_smp_hook(cpu, virt_to_phys(secondary_startup), 0); + shmobile_smp_hook(cpu, __pa_symbol(secondary_startup), 0); return apmu_wrap(cpu, apmu_power_on); } @@ -197,21 +216,9 @@ static void __init shmobile_smp_apmu_prepare_cpus_dt(unsigned int max_cpus) rcar_gen2_pm_init(); } -static int shmobile_smp_apmu_boot_secondary_md21(unsigned int cpu, - struct task_struct *idle) -{ - /* Error out when hardware debug mode is enabled */ - if (rcar_gen2_read_mode_pins() & BIT(21)) { - pr_warn("Unable to boot CPU%u when MD21 is set\n", cpu); - return -ENOTSUPP; - } - - return shmobile_smp_apmu_boot_secondary(cpu, idle); -} - static struct smp_operations apmu_smp_ops __initdata = { .smp_prepare_cpus = shmobile_smp_apmu_prepare_cpus_dt, - .smp_boot_secondary = shmobile_smp_apmu_boot_secondary_md21, + .smp_boot_secondary = shmobile_smp_apmu_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU .cpu_can_disable = shmobile_smp_cpu_can_disable, .cpu_die = shmobile_smp_apmu_cpu_die, @@ -301,7 +308,7 @@ int shmobile_smp_apmu_cpu_kill(unsigned int cpu) #if defined(CONFIG_SUSPEND) static int shmobile_smp_apmu_do_suspend(unsigned long cpu) { - shmobile_smp_hook(cpu, virt_to_phys(cpu_resume), 0); + shmobile_smp_hook(cpu, __pa_symbol(cpu_resume), 0); shmobile_smp_apmu_cpu_shutdown(cpu); cpu_do_idle(); /* WFI selects Core Standby */ return 1; diff --git a/arch/arm/mach-shmobile/platsmp-scu.c b/arch/arm/mach-shmobile/platsmp-scu.c index d1ecaf37d142..f1a1efde4beb 100644 --- a/arch/arm/mach-shmobile/platsmp-scu.c +++ b/arch/arm/mach-shmobile/platsmp-scu.c @@ -24,7 +24,7 @@ static void __iomem *shmobile_scu_base; static int shmobile_scu_cpu_prepare(unsigned int cpu) { /* For this particular CPU register SCU SMP boot vector */ - shmobile_smp_hook(cpu, virt_to_phys(shmobile_boot_scu), + shmobile_smp_hook(cpu, __pa_symbol(shmobile_boot_scu), shmobile_scu_base_phys); return 0; } @@ -33,7 +33,7 @@ void __init shmobile_smp_scu_prepare_cpus(phys_addr_t scu_base_phys, unsigned int max_cpus) { /* install boot code shared by all CPUs */ - shmobile_boot_fn = virt_to_phys(shmobile_smp_boot); + shmobile_boot_fn = __pa_symbol(shmobile_smp_boot); /* enable SCU and cache coherency on booting CPU */ shmobile_scu_base_phys = scu_base_phys; diff --git a/arch/arm/mach-shmobile/pm-rcar-gen2.c b/arch/arm/mach-shmobile/pm-rcar-gen2.c index dd9ac366868f..0178da7ace82 100644 --- a/arch/arm/mach-shmobile/pm-rcar-gen2.c +++ b/arch/arm/mach-shmobile/pm-rcar-gen2.c @@ -20,14 +20,30 @@ /* RST */ #define RST 0xe6160000 -#define CA15BAR 0x0020 -#define CA7BAR 0x0030 -#define CA15RESCNT 0x0040 -#define CA7RESCNT 0x0044 + +#define CA15BAR 0x0020 /* CA15 Boot Address Register */ +#define CA7BAR 0x0030 /* CA7 Boot Address Register */ +#define CA15RESCNT 0x0040 /* CA15 Reset Control Register */ +#define CA7RESCNT 0x0044 /* CA7 Reset Control Register */ + +/* SYS Boot Address Register */ +#define SBAR_BAREN BIT(4) /* SBAR is valid */ + +/* Reset Control Registers */ +#define CA15RESCNT_CODE 0xa5a50000 +#define CA15RESCNT_CPUS 0xf /* CPU0-3 */ +#define CA7RESCNT_CODE 0x5a5a0000 +#define CA7RESCNT_CPUS 0xf /* CPU0-3 */ + /* On-chip RAM */ #define ICRAM1 0xe63c0000 /* Inter Connect RAM1 (4 KiB) */ +static inline u32 phys_to_sbar(phys_addr_t addr) +{ + return (addr >> 8) & 0xfffffc00; +} + /* SYSC */ #define SYSCIER 0x0c #define SYSCIMR 0x10 @@ -82,22 +98,24 @@ void __init rcar_gen2_pm_init(void) /* setup reset vectors */ p = ioremap_nocache(RST, 0x63); - bar = (boot_vector_addr >> 8) & 0xfffffc00; + bar = phys_to_sbar(boot_vector_addr); if (has_a15) { writel_relaxed(bar, p + CA15BAR); - writel_relaxed(bar | 0x10, p + CA15BAR); + writel_relaxed(bar | SBAR_BAREN, p + CA15BAR); /* de-assert reset for CA15 CPUs */ - writel_relaxed((readl_relaxed(p + CA15RESCNT) & ~0x0f) | - 0xa5a50000, p + CA15RESCNT); + writel_relaxed((readl_relaxed(p + CA15RESCNT) & + ~CA15RESCNT_CPUS) | CA15RESCNT_CODE, + p + CA15RESCNT); } if (has_a7) { writel_relaxed(bar, p + CA7BAR); - writel_relaxed(bar | 0x10, p + CA7BAR); + writel_relaxed(bar | SBAR_BAREN, p + CA7BAR); /* de-assert reset for CA7 CPUs */ - writel_relaxed((readl_relaxed(p + CA7RESCNT) & ~0x0f) | - 0x5a5a0000, p + CA7RESCNT); + writel_relaxed((readl_relaxed(p + CA7RESCNT) & + ~CA7RESCNT_CPUS) | CA7RESCNT_CODE, + p + CA7RESCNT); } iounmap(p); diff --git a/arch/arm/mach-shmobile/rcar-gen2.h b/arch/arm/mach-shmobile/rcar-gen2.h index 8a66b4aae035..6792e249cf56 100644 --- a/arch/arm/mach-shmobile/rcar-gen2.h +++ b/arch/arm/mach-shmobile/rcar-gen2.h @@ -2,8 +2,6 @@ #define __ASM_RCAR_GEN2_H__ void rcar_gen2_timer_init(void); -#define MD(nr) BIT(nr) -u32 rcar_gen2_read_mode_pins(void); void rcar_gen2_reserve(void); void rcar_gen2_pm_init(void); diff --git a/arch/arm/mach-shmobile/setup-rcar-gen2.c b/arch/arm/mach-shmobile/setup-rcar-gen2.c index ac63fa407b64..52d466b75973 100644 --- a/arch/arm/mach-shmobile/setup-rcar-gen2.c +++ b/arch/arm/mach-shmobile/setup-rcar-gen2.c @@ -29,24 +29,6 @@ #include "common.h" #include "rcar-gen2.h" -#define MODEMR 0xe6160060 - -u32 rcar_gen2_read_mode_pins(void) -{ - static u32 mode; - static bool mode_valid; - - if (!mode_valid) { - void __iomem *modemr = ioremap_nocache(MODEMR, 4); - BUG_ON(!modemr); - mode = ioread32(modemr); - iounmap(modemr); - mode_valid = true; - } - - return mode; -} - static unsigned int __init get_extal_freq(void) { struct device_node *cpg, *extal; diff --git a/arch/arm/mach-shmobile/smp-r8a7791.c b/arch/arm/mach-shmobile/smp-r8a7791.c index 2d6417af73b5..2948c22cfc53 100644 --- a/arch/arm/mach-shmobile/smp-r8a7791.c +++ b/arch/arm/mach-shmobile/smp-r8a7791.c @@ -42,21 +42,9 @@ static void __init r8a7791_smp_prepare_cpus(unsigned int max_cpus) rcar_gen2_pm_init(); } -static int r8a7791_smp_boot_secondary(unsigned int cpu, - struct task_struct *idle) -{ - /* Error out when hardware debug mode is enabled */ - if (rcar_gen2_read_mode_pins() & BIT(21)) { - pr_warn("Unable to boot CPU%u when MD21 is set\n", cpu); - return -ENOTSUPP; - } - - return shmobile_smp_apmu_boot_secondary(cpu, idle); -} - const struct smp_operations r8a7791_smp_ops __initconst = { .smp_prepare_cpus = r8a7791_smp_prepare_cpus, - .smp_boot_secondary = r8a7791_smp_boot_secondary, + .smp_boot_secondary = shmobile_smp_apmu_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU .cpu_can_disable = shmobile_smp_cpu_can_disable, .cpu_die = shmobile_smp_apmu_cpu_die, |