diff options
Diffstat (limited to 'arch/arm/mach-shmobile')
28 files changed, 1516 insertions, 496 deletions
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index 0c8f6cf3e948..0828fab2b65c 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig @@ -26,6 +26,7 @@ config ARCH_SH73A0 select SH_CLK_CPG select ARCH_WANT_OPTIONAL_GPIOLIB select ARM_GIC + select I2C comment "SH-Mobile Board Type" @@ -69,6 +70,11 @@ config MACH_MACKEREL depends on ARCH_SH7372 select ARCH_REQUIRE_GPIOLIB +config MACH_KOTA2 + bool "KOTA2 board" + select ARCH_REQUIRE_GPIOLIB + depends on ARCH_SH73A0 + comment "SH-Mobile System Configuration" menu "Memory configuration" @@ -78,6 +84,7 @@ config MEMORY_START default "0x50000000" if MACH_G3EVM default "0x40000000" if MACH_G4EVM || MACH_AP4EVB || MACH_AG5EVM || \ MACH_MACKEREL + default "0x41000000" if MACH_KOTA2 default "0x00000000" ---help--- Tweak this only when porting to a new machine which does not @@ -89,6 +96,7 @@ config MEMORY_SIZE default "0x08000000" if MACH_G3EVM default "0x08000000" if MACH_G4EVM default "0x20000000" if MACH_AG5EVM + default "0x1e000000" if MACH_KOTA2 default "0x10000000" if MACH_AP4EVB || MACH_MACKEREL default "0x04000000" help diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile index 612b27000c3e..2aec2f732515 100644 --- a/arch/arm/mach-shmobile/Makefile +++ b/arch/arm/mach-shmobile/Makefile @@ -41,6 +41,7 @@ obj-$(CONFIG_MACH_G4EVM) += board-g4evm.o obj-$(CONFIG_MACH_AP4EVB) += board-ap4evb.o obj-$(CONFIG_MACH_AG5EVM) += board-ag5evm.o obj-$(CONFIG_MACH_MACKEREL) += board-mackerel.o +obj-$(CONFIG_MACH_KOTA2) += board-kota2.o # Framework support obj-$(CONFIG_SMP) += $(smp-y) diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c index cdfdd624d21d..83624e26b884 100644 --- a/arch/arm/mach-shmobile/board-ag5evm.c +++ b/arch/arm/mach-shmobile/board-ag5evm.c @@ -37,6 +37,7 @@ #include <linux/mmc/sh_mobile_sdhi.h> #include <linux/mfd/tmio.h> #include <linux/sh_clk.h> +#include <linux/dma-mapping.h> #include <video/sh_mobile_lcdc.h> #include <video/sh_mipi_dsi.h> #include <sound/sh_fsi.h> @@ -58,7 +59,7 @@ static struct resource smsc9220_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = gic_spi(33), /* PINT1 */ + .start = SH73A0_PINT0_IRQ(2), /* PINTA2 */ .flags = IORESOURCE_IRQ, }, }; @@ -338,6 +339,18 @@ static struct platform_device mipidsi0_device = { }, }; +/* SDHI0 */ +static irqreturn_t ag5evm_sdhi0_gpio_cd(int irq, void *arg) +{ + struct device *dev = arg; + struct sh_mobile_sdhi_info *info = dev->platform_data; + struct tmio_mmc_data *pdata = info->pdata; + + tmio_mmc_cd_wakeup(pdata); + + return IRQ_HANDLED; +} + static struct sh_mobile_sdhi_info sdhi0_info = { .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX, .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX, @@ -354,14 +367,17 @@ static struct resource sdhi0_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { + .name = SH_MOBILE_SDHI_IRQ_CARD_DETECT, .start = gic_spi(83), .flags = IORESOURCE_IRQ, }, [2] = { + .name = SH_MOBILE_SDHI_IRQ_SDCARD, .start = gic_spi(84), .flags = IORESOURCE_IRQ, }, [3] = { + .name = SH_MOBILE_SDHI_IRQ_SDIO, .start = gic_spi(85), .flags = IORESOURCE_IRQ, }, @@ -397,14 +413,17 @@ static struct resource sdhi1_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { + .name = SH_MOBILE_SDHI_IRQ_CARD_DETECT, .start = gic_spi(87), .flags = IORESOURCE_IRQ, }, [2] = { + .name = SH_MOBILE_SDHI_IRQ_SDCARD, .start = gic_spi(88), .flags = IORESOURCE_IRQ, }, [3] = { + .name = SH_MOBILE_SDHI_IRQ_SDIO, .start = gic_spi(89), .flags = IORESOURCE_IRQ, }, @@ -447,25 +466,14 @@ static struct map_desc ag5evm_io_desc[] __initdata = { static void __init ag5evm_map_io(void) { iotable_init(ag5evm_io_desc, ARRAY_SIZE(ag5evm_io_desc)); + /* DMA memory at 0xf6000000 - 0xffdfffff */ + init_consistent_dma_size(158 << 20); /* setup early devices and console here as well */ sh73a0_add_early_devices(); shmobile_setup_console(); } -#define PINTC_ADDR 0xe6900000 -#define PINTER0A (PINTC_ADDR + 0xa0) -#define PINTCR0A (PINTC_ADDR + 0xb0) - -void __init ag5evm_init_irq(void) -{ - sh73a0_init_irq(); - - /* setup PINT: enable PINTA2 as active low */ - __raw_writel(__raw_readl(PINTER0A) | (1<<29), PINTER0A); - __raw_writew(__raw_readw(PINTCR0A) | (2<<10), PINTCR0A); -} - #define DSI0PHYCR 0xe615006c static void __init ag5evm_init(void) @@ -561,6 +569,13 @@ static void __init ag5evm_init(void) gpio_request(GPIO_FN_SDHID0_1, NULL); gpio_request(GPIO_FN_SDHID0_0, NULL); + if (!request_irq(intcs_evt2irq(0x3c0), ag5evm_sdhi0_gpio_cd, + IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, + "sdhi0 cd", &sdhi0_device.dev)) + sdhi0_info.tmio_flags |= TMIO_MMC_HAS_COLD_CD; + else + pr_warn("Unable to setup SDHI0 GPIO IRQ\n"); + /* enable SDHI1 on CN4 [WLAN I/F] */ gpio_request(GPIO_FN_SDHICLK1, NULL); gpio_request(GPIO_FN_SDHICMD1_PU, NULL); @@ -592,7 +607,7 @@ struct sys_timer ag5evm_timer = { MACHINE_START(AG5EVM, "ag5evm") .map_io = ag5evm_map_io, - .init_irq = ag5evm_init_irq, + .init_irq = sh73a0_init_irq, .handle_irq = shmobile_handle_irq_gic, .init_machine = ag5evm_init, .timer = &ag5evm_timer, diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c index 523f608eb8cf..a3aa0f6df964 100644 --- a/arch/arm/mach-shmobile/board-ap4evb.c +++ b/arch/arm/mach-shmobile/board-ap4evb.c @@ -42,6 +42,8 @@ #include <linux/leds.h> #include <linux/input/sh_keysc.h> #include <linux/usb/r8a66597.h> +#include <linux/pm_clock.h> +#include <linux/dma-mapping.h> #include <media/sh_mobile_ceu.h> #include <media/sh_mobile_csi2.h> @@ -198,8 +200,8 @@ static struct physmap_flash_data nor_flash_data = { static struct resource nor_flash_resources[] = { [0] = { - .start = 0x00000000, - .end = 0x08000000 - 1, + .start = 0x20000000, /* CS0 shadow instead of regular CS0 */ + .end = 0x28000000 - 1, /* needed by USB MASK ROM boot */ .flags = IORESOURCE_MEM, } }; @@ -931,7 +933,7 @@ static struct platform_device ap4evb_camera = { static struct sh_csi2_client_config csi2_clients[] = { { .phy = SH_CSI2_PHY_MAIN, - .lanes = 3, + .lanes = 0, /* default: 2 lanes */ .channel = 0, .pdev = &ap4evb_camera, }, @@ -1170,6 +1172,8 @@ static struct map_desc ap4evb_io_desc[] __initdata = { static void __init ap4evb_map_io(void) { iotable_init(ap4evb_io_desc, ARRAY_SIZE(ap4evb_io_desc)); + /* DMA memory at 0xf6000000 - 0xffdfffff */ + init_consistent_dma_size(158 << 20); /* setup early devices and console here as well */ sh7372_add_early_devices(); @@ -1408,6 +1412,11 @@ static void __init ap4evb_init(void) sh7372_add_device_to_domain(&sh7372_a4lc, &lcdc_device); sh7372_add_device_to_domain(&sh7372_a4mp, &fsi_device); + sh7372_add_device_to_domain(&sh7372_a3sp, &sh_mmcif_device); + sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi0_device); + sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi1_device); + sh7372_add_device_to_domain(&sh7372_a4r, &ceu_device); + hdmi_init_pm_clock(); fsi_init_pm_clock(); sh7372_pm_init(); diff --git a/arch/arm/mach-shmobile/board-g3evm.c b/arch/arm/mach-shmobile/board-g3evm.c index ef4613b993a2..8b620bf06221 100644 --- a/arch/arm/mach-shmobile/board-g3evm.c +++ b/arch/arm/mach-shmobile/board-g3evm.c @@ -32,6 +32,7 @@ #include <linux/gpio.h> #include <linux/input.h> #include <linux/input/sh_keysc.h> +#include <linux/dma-mapping.h> #include <mach/sh7367.h> #include <mach/common.h> #include <asm/mach-types.h> @@ -260,6 +261,8 @@ static struct map_desc g3evm_io_desc[] __initdata = { static void __init g3evm_map_io(void) { iotable_init(g3evm_io_desc, ARRAY_SIZE(g3evm_io_desc)); + /* DMA memory at 0xf6000000 - 0xffdfffff */ + init_consistent_dma_size(158 << 20); /* setup early devices and console here as well */ sh7367_add_early_devices(); diff --git a/arch/arm/mach-shmobile/board-g4evm.c b/arch/arm/mach-shmobile/board-g4evm.c index 8e3c5559f27f..7719ddc5f591 100644 --- a/arch/arm/mach-shmobile/board-g4evm.c +++ b/arch/arm/mach-shmobile/board-g4evm.c @@ -33,6 +33,7 @@ #include <linux/mmc/host.h> #include <linux/mmc/sh_mobile_sdhi.h> #include <linux/gpio.h> +#include <linux/dma-mapping.h> #include <mach/sh7377.h> #include <mach/common.h> #include <asm/mach-types.h> @@ -274,6 +275,8 @@ static struct map_desc g4evm_io_desc[] __initdata = { static void __init g4evm_map_io(void) { iotable_init(g4evm_io_desc, ARRAY_SIZE(g4evm_io_desc)); + /* DMA memory at 0xf6000000 - 0xffdfffff */ + init_consistent_dma_size(158 << 20); /* setup early devices and console here as well */ sh7377_add_early_devices(); diff --git a/arch/arm/mach-shmobile/board-kota2.c b/arch/arm/mach-shmobile/board-kota2.c new file mode 100644 index 000000000000..adc73122bf20 --- /dev/null +++ b/arch/arm/mach-shmobile/board-kota2.c @@ -0,0 +1,447 @@ +/* + * kota2 board support + * + * Copyright (C) 2011 Renesas Solutions Corp. + * Copyright (C) 2011 Magnus Damm + * Copyright (C) 2010 Takashi Yoshii <yoshii.takashi.zj@renesas.com> + * Copyright (C) 2009 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/platform_device.h> +#include <linux/delay.h> +#include <linux/io.h> +#include <linux/smsc911x.h> +#include <linux/gpio.h> +#include <linux/input.h> +#include <linux/input/sh_keysc.h> +#include <linux/gpio_keys.h> +#include <linux/leds.h> +#include <linux/mmc/host.h> +#include <linux/mmc/sh_mmcif.h> +#include <linux/mfd/tmio.h> +#include <linux/mmc/sh_mobile_sdhi.h> +#include <mach/hardware.h> +#include <mach/sh73a0.h> +#include <mach/common.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <asm/mach/time.h> +#include <asm/hardware/gic.h> +#include <asm/hardware/cache-l2x0.h> +#include <asm/traps.h> + +static struct resource smsc9220_resources[] = { + [0] = { + .start = 0x14000000, /* CS5A */ + .end = 0x140000ff, /* A1->A7 */ + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = gic_spi(33), /* PINTA2 @ PORT144 */ + .flags = IORESOURCE_IRQ, + }, +}; + +static struct smsc911x_platform_config smsc9220_platdata = { + .flags = SMSC911X_USE_32BIT, /* 32-bit SW on 16-bit HW bus */ + .phy_interface = PHY_INTERFACE_MODE_MII, + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, + .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, +}; + +static struct platform_device eth_device = { + .name = "smsc911x", + .id = 0, + .dev = { + .platform_data = &smsc9220_platdata, + }, + .resource = smsc9220_resources, + .num_resources = ARRAY_SIZE(smsc9220_resources), +}; + +static struct sh_keysc_info keysc_platdata = { + .mode = SH_KEYSC_MODE_6, + .scan_timing = 3, + .delay = 100, + .keycodes = { + KEY_NUMERIC_STAR, KEY_NUMERIC_0, KEY_NUMERIC_POUND, + 0, 0, 0, 0, 0, + KEY_NUMERIC_7, KEY_NUMERIC_8, KEY_NUMERIC_9, + 0, KEY_DOWN, 0, 0, 0, + KEY_NUMERIC_4, KEY_NUMERIC_5, KEY_NUMERIC_6, + KEY_LEFT, KEY_ENTER, KEY_RIGHT, 0, 0, + KEY_NUMERIC_1, KEY_NUMERIC_2, KEY_NUMERIC_3, + 0, KEY_UP, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + }, +}; + +static struct resource keysc_resources[] = { + [0] = { + .name = "KEYSC", + .start = 0xe61b0000, + .end = 0xe61b0098 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = gic_spi(71), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device keysc_device = { + .name = "sh_keysc", + .id = 0, + .num_resources = ARRAY_SIZE(keysc_resources), + .resource = keysc_resources, + .dev = { + .platform_data = &keysc_platdata, + }, +}; + +#define GPIO_KEY(c, g, d) { .code = c, .gpio = g, .desc = d, .active_low = 1 } + +static struct gpio_keys_button gpio_buttons[] = { + GPIO_KEY(KEY_VOLUMEUP, GPIO_PORT56, "+"), /* S2: VOL+ [IRQ9] */ + GPIO_KEY(KEY_VOLUMEDOWN, GPIO_PORT54, "-"), /* S3: VOL- [IRQ10] */ + GPIO_KEY(KEY_MENU, GPIO_PORT27, "Menu"), /* S4: MENU [IRQ30] */ + GPIO_KEY(KEY_HOMEPAGE, GPIO_PORT26, "Home"), /* S5: HOME [IRQ31] */ + GPIO_KEY(KEY_BACK, GPIO_PORT11, "Back"), /* S6: BACK [IRQ0] */ + GPIO_KEY(KEY_PHONE, GPIO_PORT238, "Tel"), /* S7: TEL [IRQ11] */ + GPIO_KEY(KEY_POWER, GPIO_PORT239, "C1"), /* S8: CAM [IRQ13] */ + GPIO_KEY(KEY_MAIL, GPIO_PORT224, "Mail"), /* S9: MAIL [IRQ3] */ + /* Omitted button "C3?": GPIO_PORT223 - S10: CUST [IRQ8] */ + GPIO_KEY(KEY_CAMERA, GPIO_PORT164, "C2"), /* S11: CAM_HALF [IRQ25] */ + /* Omitted button "?": GPIO_PORT152 - S12: CAM_FULL [No IRQ] */ +}; + +static struct gpio_keys_platform_data gpio_key_info = { + .buttons = gpio_buttons, + .nbuttons = ARRAY_SIZE(gpio_buttons), + .poll_interval = 250, /* polled for now */ +}; + +static struct platform_device gpio_keys_device = { + .name = "gpio-keys-polled", /* polled for now */ + .id = -1, + .dev = { + .platform_data = &gpio_key_info, + }, +}; + +#define GPIO_LED(n, g) { .name = n, .gpio = g } + +static struct gpio_led gpio_leds[] = { + GPIO_LED("V2513", GPIO_PORT153), /* PORT153 [TPU1T02] -> V2513 */ + GPIO_LED("V2514", GPIO_PORT199), /* PORT199 [TPU4TO1] -> V2514 */ + GPIO_LED("V2515", GPIO_PORT197), /* PORT197 [TPU2TO1] -> V2515 */ + GPIO_LED("KEYLED", GPIO_PORT163), /* PORT163 [TPU3TO0] -> KEYLED */ + GPIO_LED("G", GPIO_PORT20), /* PORT20 [GPO0] -> LED7 -> "G" */ + GPIO_LED("H", GPIO_PORT21), /* PORT21 [GPO1] -> LED8 -> "H" */ + GPIO_LED("J", GPIO_PORT22), /* PORT22 [GPO2] -> LED9 -> "J" */ +}; + +static struct gpio_led_platform_data gpio_leds_info = { + .leds = gpio_leds, + .num_leds = ARRAY_SIZE(gpio_leds), +}; + +static struct platform_device gpio_leds_device = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &gpio_leds_info, + }, +}; + +static struct resource mmcif_resources[] = { + [0] = { + .name = "MMCIF", + .start = 0xe6bd0000, + .end = 0xe6bd00ff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = gic_spi(140), + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = gic_spi(141), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct sh_mmcif_plat_data mmcif_info = { + .ocr = MMC_VDD_165_195, + .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE, +}; + +static struct platform_device mmcif_device = { + .name = "sh_mmcif", + .id = 0, + .dev = { + .platform_data = &mmcif_info, + }, + .num_resources = ARRAY_SIZE(mmcif_resources), + .resource = mmcif_resources, +}; + +static struct sh_mobile_sdhi_info sdhi0_info = { + .tmio_caps = MMC_CAP_SD_HIGHSPEED, + .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE | TMIO_MMC_HAS_IDLE_WAIT, +}; + +static struct resource sdhi0_resources[] = { + [0] = { + .name = "SDHI0", + .start = 0xee100000, + .end = 0xee1000ff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = gic_spi(83), + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = gic_spi(84), + .flags = IORESOURCE_IRQ, + }, + [3] = { + .start = gic_spi(85), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device sdhi0_device = { + .name = "sh_mobile_sdhi", + .id = 0, + .num_resources = ARRAY_SIZE(sdhi0_resources), + .resource = sdhi0_resources, + .dev = { + .platform_data = &sdhi0_info, + }, +}; + +static struct sh_mobile_sdhi_info sdhi1_info = { + .tmio_caps = MMC_CAP_NONREMOVABLE | MMC_CAP_SDIO_IRQ, + .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE | TMIO_MMC_HAS_IDLE_WAIT, +}; + +static struct resource sdhi1_resources[] = { + [0] = { + .name = "SDHI1", + .start = 0xee120000, + .end = 0xee1200ff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = gic_spi(87), + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = gic_spi(88), + .flags = IORESOURCE_IRQ, + }, + [3] = { + .start = gic_spi(89), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device sdhi1_device = { + .name = "sh_mobile_sdhi", + .id = 1, + .num_resources = ARRAY_SIZE(sdhi1_resources), + .resource = sdhi1_resources, + .dev = { + .platform_data = &sdhi1_info, + }, +}; + +static struct platform_device *kota2_devices[] __initdata = { + ð_device, + &keysc_device, + &gpio_keys_device, + &gpio_leds_device, + &mmcif_device, + &sdhi0_device, + &sdhi1_device, +}; + +static struct map_desc kota2_io_desc[] __initdata = { + /* create a 1:1 entity map for 0xe6xxxxxx + * used by CPGA, INTC and PFC. + */ + { + .virtual = 0xe6000000, + .pfn = __phys_to_pfn(0xe6000000), + .length = 256 << 20, + .type = MT_DEVICE_NONSHARED + }, +}; + +static void __init kota2_map_io(void) +{ + iotable_init(kota2_io_desc, ARRAY_SIZE(kota2_io_desc)); + + /* setup early devices and console here as well */ + sh73a0_add_early_devices(); + shmobile_setup_console(); +} + +#define PINTER0A 0xe69000a0 +#define PINTCR0A 0xe69000b0 + +void __init kota2_init_irq(void) +{ + sh73a0_init_irq(); + + /* setup PINT: enable PINTA2 as active low */ + __raw_writel(1 << 29, PINTER0A); + __raw_writew(2 << 10, PINTCR0A); +} + +static void __init kota2_init(void) +{ + sh73a0_pinmux_init(); + + /* SCIFA2 (UART2) */ + gpio_request(GPIO_FN_SCIFA2_TXD1, NULL); + gpio_request(GPIO_FN_SCIFA2_RXD1, NULL); + gpio_request(GPIO_FN_SCIFA2_RTS1_, NULL); + gpio_request(GPIO_FN_SCIFA2_CTS1_, NULL); + + /* SCIFA4 (UART1) */ + gpio_request(GPIO_FN_SCIFA4_TXD, NULL); + gpio_request(GPIO_FN_SCIFA4_RXD, NULL); + gpio_request(GPIO_FN_SCIFA4_RTS_, NULL); + gpio_request(GPIO_FN_SCIFA4_CTS_, NULL); + + /* SMSC911X */ + gpio_request(GPIO_FN_D0_NAF0, NULL); + gpio_request(GPIO_FN_D1_NAF1, NULL); + gpio_request(GPIO_FN_D2_NAF2, NULL); + gpio_request(GPIO_FN_D3_NAF3, NULL); + gpio_request(GPIO_FN_D4_NAF4, NULL); + gpio_request(GPIO_FN_D5_NAF5, NULL); + gpio_request(GPIO_FN_D6_NAF6, NULL); + gpio_request(GPIO_FN_D7_NAF7, NULL); + gpio_request(GPIO_FN_D8_NAF8, NULL); + gpio_request(GPIO_FN_D9_NAF9, NULL); + gpio_request(GPIO_FN_D10_NAF10, NULL); + gpio_request(GPIO_FN_D11_NAF11, NULL); + gpio_request(GPIO_FN_D12_NAF12, NULL); + gpio_request(GPIO_FN_D13_NAF13, NULL); + gpio_request(GPIO_FN_D14_NAF14, NULL); + gpio_request(GPIO_FN_D15_NAF15, NULL); + gpio_request(GPIO_FN_CS5A_, NULL); + gpio_request(GPIO_FN_WE0__FWE, NULL); + gpio_request(GPIO_PORT144, NULL); /* PINTA2 */ + gpio_direction_input(GPIO_PORT144); + gpio_request(GPIO_PORT145, NULL); /* RESET */ + gpio_direction_output(GPIO_PORT145, 1); + + /* KEYSC */ + gpio_request(GPIO_FN_KEYIN0_PU, NULL); + gpio_request(GPIO_FN_KEYIN1_PU, NULL); + gpio_request(GPIO_FN_KEYIN2_PU, NULL); + gpio_request(GPIO_FN_KEYIN3_PU, NULL); + gpio_request(GPIO_FN_KEYIN4_PU, NULL); + gpio_request(GPIO_FN_KEYIN5_PU, NULL); + gpio_request(GPIO_FN_KEYIN6_PU, NULL); + gpio_request(GPIO_FN_KEYIN7_PU, NULL); + gpio_request(GPIO_FN_KEYOUT0, NULL); + gpio_request(GPIO_FN_KEYOUT1, NULL); + gpio_request(GPIO_FN_KEYOUT2, NULL); + gpio_request(GPIO_FN_KEYOUT3, NULL); + gpio_request(GPIO_FN_KEYOUT4, NULL); + gpio_request(GPIO_FN_KEYOUT5, NULL); + gpio_request(GPIO_FN_PORT59_KEYOUT6, NULL); + gpio_request(GPIO_FN_PORT58_KEYOUT7, NULL); + gpio_request(GPIO_FN_KEYOUT8, NULL); + + /* MMCIF */ + gpio_request(GPIO_FN_MMCCLK0, NULL); + gpio_request(GPIO_FN_MMCD0_0, NULL); + gpio_request(GPIO_FN_MMCD0_1, NULL); + gpio_request(GPIO_FN_MMCD0_2, NULL); + gpio_request(GPIO_FN_MMCD0_3, NULL); + gpio_request(GPIO_FN_MMCD0_4, NULL); + gpio_request(GPIO_FN_MMCD0_5, NULL); + gpio_request(GPIO_FN_MMCD0_6, NULL); + gpio_request(GPIO_FN_MMCD0_7, NULL); + gpio_request(GPIO_FN_MMCCMD0, NULL); + gpio_request(GPIO_PORT208, NULL); /* Reset */ + gpio_direction_output(GPIO_PORT208, 1); + + /* SDHI0 (microSD) */ + gpio_request(GPIO_FN_SDHICD0_PU, NULL); + gpio_request(GPIO_FN_SDHICMD0_PU, NULL); + gpio_request(GPIO_FN_SDHICLK0, NULL); + gpio_request(GPIO_FN_SDHID0_3_PU, NULL); + gpio_request(GPIO_FN_SDHID0_2_PU, NULL); + gpio_request(GPIO_FN_SDHID0_1_PU, NULL); + gpio_request(GPIO_FN_SDHID0_0_PU, NULL); + + /* SCIFB (BT) */ + gpio_request(GPIO_FN_PORT159_SCIFB_SCK, NULL); + gpio_request(GPIO_FN_PORT160_SCIFB_TXD, NULL); + gpio_request(GPIO_FN_PORT161_SCIFB_CTS_, NULL); + gpio_request(GPIO_FN_PORT162_SCIFB_RXD, NULL); + gpio_request(GPIO_FN_PORT163_SCIFB_RTS_, NULL); + + /* SDHI1 (BCM4330) */ + gpio_request(GPIO_FN_SDHICLK1, NULL); + gpio_request(GPIO_FN_SDHICMD1_PU, NULL); + gpio_request(GPIO_FN_SDHID1_3_PU, NULL); + gpio_request(GPIO_FN_SDHID1_2_PU, NULL); + gpio_request(GPIO_FN_SDHID1_1_PU, NULL); + gpio_request(GPIO_FN_SDHID1_0_PU, NULL); + +#ifdef CONFIG_CACHE_L2X0 + /* Early BRESP enable, Shared attribute override enable, 64K*8way */ + l2x0_init(__io(0xf0100000), 0x40460000, 0x82000fff); +#endif + sh73a0_add_standard_devices(); + platform_add_devices(kota2_devices, ARRAY_SIZE(kota2_devices)); +} + +static void __init kota2_timer_init(void) +{ + sh73a0_clock_init(); + shmobile_timer.init(); + return; +} + +struct sys_timer kota2_timer = { + .init = kota2_timer_init, +}; + +MACHINE_START(KOTA2, "kota2") + .map_io = kota2_map_io, + .init_irq = kota2_init_irq, + .handle_irq = shmobile_handle_irq_gic, + .init_machine = kota2_init, + .timer = &kota2_timer, +MACHINE_END diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c index 17c19dc25604..9c5e598e0e3d 100644 --- a/arch/arm/mach-shmobile/board-mackerel.c +++ b/arch/arm/mach-shmobile/board-mackerel.c @@ -39,12 +39,13 @@ #include <linux/mtd/mtd.h> #include <linux/mtd/partitions.h> #include <linux/mtd/physmap.h> -#include <linux/pm_runtime.h> +#include <linux/pm_clock.h> #include <linux/smsc911x.h> #include <linux/sh_intc.h> #include <linux/tca6416_keypad.h> #include <linux/usb/r8a66597.h> #include <linux/usb/renesas_usbhs.h> +#include <linux/dma-mapping.h> #include <video/sh_mobile_hdmi.h> #include <video/sh_mobile_lcdc.h> @@ -272,8 +273,8 @@ static struct physmap_flash_data nor_flash_data = { static struct resource nor_flash_resources[] = { [0] = { - .start = 0x00000000, - .end = 0x08000000 - 1, + .start = 0x20000000, /* CS0 shadow instead of regular CS0 */ + .end = 0x28000000 - 1, /* needed by USB MASK ROM boot */ .flags = IORESOURCE_MEM, } }; @@ -810,6 +811,7 @@ static struct usbhs_private usbhs1_private = { }, .driver_param = { .buswait_bwait = 4, + .has_otg = 1, .pipe_type = usbhs1_pipe_cfg, .pipe_size = ARRAY_SIZE(usbhs1_pipe_cfg), .d0_tx_id = SHDMA_SLAVE_USB1_TX, @@ -1070,14 +1072,17 @@ static struct resource sdhi1_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { + .name = SH_MOBILE_SDHI_IRQ_CARD_DETECT, .start = evt2irq(0x0e80), /* SDHI1_SDHI1I0 */ .flags = IORESOURCE_IRQ, }, [2] = { + .name = SH_MOBILE_SDHI_IRQ_SDCARD, .start = evt2irq(0x0ea0), /* SDHI1_SDHI1I1 */ .flags = IORESOURCE_IRQ, }, [3] = { + .name = SH_MOBILE_SDHI_IRQ_SDIO, .start = evt2irq(0x0ec0), /* SDHI1_SDHI1I2 */ .flags = IORESOURCE_IRQ, }, @@ -1121,14 +1126,17 @@ static struct resource sdhi2_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { + .name = SH_MOBILE_SDHI_IRQ_CARD_DETECT, .start = evt2irq(0x1200), /* SDHI2_SDHI2I0 */ .flags = IORESOURCE_IRQ, }, [2] = { + .name = SH_MOBILE_SDHI_IRQ_SDCARD, .start = evt2irq(0x1220), /* SDHI2_SDHI2I1 */ .flags = IORESOURCE_IRQ, }, [3] = { + .name = SH_MOBILE_SDHI_IRQ_SDIO, .start = evt2irq(0x1240), /* SDHI2_SDHI2I2 */ .flags = IORESOURCE_IRQ, }, @@ -1215,9 +1223,10 @@ static struct soc_camera_platform_info camera_info = { .width = 640, .height = 480, }, - .bus_param = SOCAM_PCLK_SAMPLE_RISING | SOCAM_HSYNC_ACTIVE_HIGH | - SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_MASTER | SOCAM_DATAWIDTH_8 | - SOCAM_DATA_ACTIVE_HIGH, + .mbus_param = V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_MASTER | + V4L2_MBUS_VSYNC_ACTIVE_HIGH | V4L2_MBUS_HSYNC_ACTIVE_HIGH | + V4L2_MBUS_DATA_ACTIVE_HIGH, + .mbus_type = V4L2_MBUS_PARALLEL, .set_capture = camera_set_capture, }; @@ -1381,6 +1390,8 @@ static struct map_desc mackerel_io_desc[] __initdata = { static void __init mackerel_map_io(void) { iotable_init(mackerel_io_desc, ARRAY_SIZE(mackerel_io_desc)); + /* DMA memory at 0xf6000000 - 0xffdfffff */ + init_consistent_dma_size(158 << 20); /* setup early devices and console here as well */ sh7372_add_early_devices(); @@ -1587,7 +1598,17 @@ static void __init mackerel_init(void) sh7372_add_device_to_domain(&sh7372_a4lc, &lcdc_device); sh7372_add_device_to_domain(&sh7372_a4lc, &hdmi_lcdc_device); + sh7372_add_device_to_domain(&sh7372_a4lc, &meram_device); sh7372_add_device_to_domain(&sh7372_a4mp, &fsi_device); + sh7372_add_device_to_domain(&sh7372_a3sp, &usbhs0_device); + sh7372_add_device_to_domain(&sh7372_a3sp, &usbhs1_device); + sh7372_add_device_to_domain(&sh7372_a3sp, &sh_mmcif_device); + sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi0_device); +#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE) + sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi1_device); +#endif + sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi2_device); + sh7372_add_device_to_domain(&sh7372_a4r, &ceu_device); hdmi_init_pm_clock(); sh7372_pm_init(); diff --git a/arch/arm/mach-shmobile/clock.c b/arch/arm/mach-shmobile/clock.c index 6b7c7c42bc8f..31654d78b96b 100644 --- a/arch/arm/mach-shmobile/clock.c +++ b/arch/arm/mach-shmobile/clock.c @@ -22,6 +22,7 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/sh_clk.h> +#include <linux/export.h> int __init clk_init(void) { diff --git a/arch/arm/mach-shmobile/entry-intc.S b/arch/arm/mach-shmobile/entry-intc.S index cac0a7ae2084..1a1c00ca39a2 100644 --- a/arch/arm/mach-shmobile/entry-intc.S +++ b/arch/arm/mach-shmobile/entry-intc.S @@ -51,7 +51,4 @@ .macro test_for_ipi, irqnr, irqstat, base, tmp .endm - .macro test_for_ltirq, irqnr, irqstat, base, tmp - .endm - arch_irq_handler shmobile_handle_irq_intc diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h index 06aecb31d9c7..c0cdbf997c91 100644 --- a/arch/arm/mach-shmobile/include/mach/common.h +++ b/arch/arm/mach-shmobile/include/mach/common.h @@ -35,8 +35,8 @@ extern void sh7372_add_standard_devices(void); extern void sh7372_clock_init(void); extern void sh7372_pinmux_init(void); extern void sh7372_pm_init(void); -extern void sh7372_cpu_suspend(void); -extern void sh7372_cpu_resume(void); +extern void sh7372_resume_core_standby_a3sm(void); +extern int sh7372_do_idle_a3sm(unsigned long unused); extern struct clk sh7372_extal1_clk; extern struct clk sh7372_extal2_clk; diff --git a/arch/arm/mach-shmobile/include/mach/entry-macro.S b/arch/arm/mach-shmobile/include/mach/entry-macro.S index d791f10eeac7..8d4a416d4285 100644 --- a/arch/arm/mach-shmobile/include/mach/entry-macro.S +++ b/arch/arm/mach-shmobile/include/mach/entry-macro.S @@ -27,8 +27,5 @@ .macro test_for_ipi, irqnr, irqstat, base, tmp .endm - .macro test_for_ltirq, irqnr, irqstat, base, tmp - .endm - .macro arch_ret_to_user, tmp1, tmp2 .endm diff --git a/arch/arm/mach-shmobile/include/mach/gpio.h b/arch/arm/mach-shmobile/include/mach/gpio.h index 2b1bb9e43dda..7bf0890e16ba 100644 --- a/arch/arm/mach-shmobile/include/mach/gpio.h +++ b/arch/arm/mach-shmobile/include/mach/gpio.h @@ -18,31 +18,15 @@ #ifdef CONFIG_GPIOLIB -static inline int gpio_get_value(unsigned gpio) -{ - return __gpio_get_value(gpio); -} - -static inline void gpio_set_value(unsigned gpio, int value) -{ - __gpio_set_value(gpio, value); -} - -static inline int gpio_cansleep(unsigned gpio) -{ - return __gpio_cansleep(gpio); -} - -static inline int gpio_to_irq(unsigned gpio) -{ - return __gpio_to_irq(gpio); -} - static inline int irq_to_gpio(unsigned int irq) { return -ENOSYS; } +#else + +#define __ARM_GPIOLIB_COMPLEX + #endif /* CONFIG_GPIOLIB */ #endif /* __ASM_ARCH_GPIO_H */ diff --git a/arch/arm/mach-shmobile/include/mach/intc.h b/arch/arm/mach-shmobile/include/mach/intc.h new file mode 100644 index 000000000000..8b22258c8caa --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/intc.h @@ -0,0 +1,246 @@ +#ifndef __ASM_MACH_INTC_H +#define __ASM_MACH_INTC_H +#include <linux/sh_intc.h> + +#define INTC_IRQ_PINS_ENUM_16L(p) \ + p ## _IRQ0, p ## _IRQ1, p ## _IRQ2, p ## _IRQ3, \ + p ## _IRQ4, p ## _IRQ5, p ## _IRQ6, p ## _IRQ7, \ + p ## _IRQ8, p ## _IRQ9, p ## _IRQ10, p ## _IRQ11, \ + p ## _IRQ12, p ## _IRQ13, p ## _IRQ14, p ## _IRQ15 + +#define INTC_IRQ_PINS_ENUM_16H(p) \ + p ## _IRQ16, p ## _IRQ17, p ## _IRQ18, p ## _IRQ19, \ + p ## _IRQ20, p ## _IRQ21, p ## _IRQ22, p ## _IRQ23, \ + p ## _IRQ24, p ## _IRQ25, p ## _IRQ26, p ## _IRQ27, \ + p ## _IRQ28, p ## _IRQ29, p ## _IRQ30, p ## _IRQ31 + +#define INTC_IRQ_PINS_VECT_16L(p, vect) \ + vect(p ## _IRQ0, 0x0200), vect(p ## _IRQ1, 0x0220), \ + vect(p ## _IRQ2, 0x0240), vect(p ## _IRQ3, 0x0260), \ + vect(p ## _IRQ4, 0x0280), vect(p ## _IRQ5, 0x02a0), \ + vect(p ## _IRQ6, 0x02c0), vect(p ## _IRQ7, 0x02e0), \ + vect(p ## _IRQ8, 0x0300), vect(p ## _IRQ9, 0x0320), \ + vect(p ## _IRQ10, 0x0340), vect(p ## _IRQ11, 0x0360), \ + vect(p ## _IRQ12, 0x0380), vect(p ## _IRQ13, 0x03a0), \ + vect(p ## _IRQ14, 0x03c0), vect(p ## _IRQ15, 0x03e0) + +#define INTC_IRQ_PINS_VECT_16H(p, vect) \ + vect(p ## _IRQ16, 0x3200), vect(p ## _IRQ17, 0x3220), \ + vect(p ## _IRQ18, 0x3240), vect(p ## _IRQ19, 0x3260), \ + vect(p ## _IRQ20, 0x3280), vect(p ## _IRQ21, 0x32a0), \ + vect(p ## _IRQ22, 0x32c0), vect(p ## _IRQ23, 0x32e0), \ + vect(p ## _IRQ24, 0x3300), vect(p ## _IRQ25, 0x3320), \ + vect(p ## _IRQ26, 0x3340), vect(p ## _IRQ27, 0x3360), \ + vect(p ## _IRQ28, 0x3380), vect(p ## _IRQ29, 0x33a0), \ + vect(p ## _IRQ30, 0x33c0), vect(p ## _IRQ31, 0x33e0) + +#define INTC_IRQ_PINS_MASK_16L(p, base) \ + { base + 0x40, base + 0x60, 8, /* INTMSK00A / INTMSKCLR00A */ \ + { p ## _IRQ0, p ## _IRQ1, p ## _IRQ2, p ## _IRQ3, \ + p ## _IRQ4, p ## _IRQ5, p ## _IRQ6, p ## _IRQ7 } }, \ + { base + 0x44, base + 0x64, 8, /* INTMSK10A / INTMSKCLR10A */ \ + { p ## _IRQ8, p ## _IRQ9, p ## _IRQ10, p ## _IRQ11, \ + p ## _IRQ12, p ## _IRQ13, p ## _IRQ14, p ## _IRQ15 } } + +#define INTC_IRQ_PINS_MASK_16H(p, base) \ + { base + 0x48, base + 0x68, 8, /* INTMSK20A / INTMSKCLR20A */ \ + { p ## _IRQ16, p ## _IRQ17, p ## _IRQ18, p ## _IRQ19, \ + p ## _IRQ20, p ## _IRQ21, p ## _IRQ22, p ## _IRQ23 } }, \ + { base + 0x4c, base + 0x6c, 8, /* INTMSK30A / INTMSKCLR30A */ \ + { p ## _IRQ24, p ## _IRQ25, p ## _IRQ26, p ## _IRQ27, \ + p ## _IRQ28, p ## _IRQ29, p ## _IRQ30, p ## _IRQ31 } } + +#define INTC_IRQ_PINS_PRIO_16L(p, base) \ + { base + 0x10, 0, 32, 4, /* INTPRI00A */ \ + { p ## _IRQ0, p ## _IRQ1, p ## _IRQ2, p ## _IRQ3, \ + p ## _IRQ4, p ## _IRQ5, p ## _IRQ6, p ## _IRQ7 } }, \ + { base + 0x14, 0, 32, 4, /* INTPRI10A */ \ + { p ## _IRQ8, p ## _IRQ9, p ## _IRQ10, p ## _IRQ11, \ + p ## _IRQ12, p ## _IRQ13, p ## _IRQ14, p ## _IRQ15 } } + +#define INTC_IRQ_PINS_PRIO_16H(p, base) \ + { base + 0x18, 0, 32, 4, /* INTPRI20A */ \ + { p ## _IRQ16, p ## _IRQ17, p ## _IRQ18, p ## _IRQ19, \ + p ## _IRQ20, p ## _IRQ21, p ## _IRQ22, p ## _IRQ23 } }, \ + { base + 0x1c, 0, 32, 4, /* INTPRI30A */ \ + { p ## _IRQ24, p ## _IRQ25, p ## _IRQ26, p ## _IRQ27, \ + p ## _IRQ28, p ## _IRQ29, p ## _IRQ30, p ## _IRQ31 } } + +#define INTC_IRQ_PINS_SENSE_16L(p, base) \ + { base + 0x00, 32, 4, /* ICR1A */ \ + { p ## _IRQ0, p ## _IRQ1, p ## _IRQ2, p ## _IRQ3, \ + p ## _IRQ4, p ## _IRQ5, p ## _IRQ6, p ## _IRQ7 } }, \ + { base + 0x04, 32, 4, /* ICR2A */ \ + { p ## _IRQ8, p ## _IRQ9, p ## _IRQ10, p ## _IRQ11, \ + p ## _IRQ12, p ## _IRQ13, p ## _IRQ14, p ## _IRQ15 } } + +#define INTC_IRQ_PINS_SENSE_16H(p, base) \ + { base + 0x08, 32, 4, /* ICR3A */ \ + { p ## _IRQ16, p ## _IRQ17, p ## _IRQ18, p ## _IRQ19, \ + p ## _IRQ20, p ## _IRQ21, p ## _IRQ22, p ## _IRQ23 } }, \ + { base + 0x0c, 32, 4, /* ICR4A */ \ + { p ## _IRQ24, p ## _IRQ25, p ## _IRQ26, p ## _IRQ27, \ + p ## _IRQ28, p ## _IRQ29, p ## _IRQ30, p ## _IRQ31 } } + +#define INTC_IRQ_PINS_ACK_16L(p, base) \ + { base + 0x20, 0, 8, /* INTREQ00A */ \ + { p ## _IRQ0, p ## _IRQ1, p ## _IRQ2, p ## _IRQ3, \ + p ## _IRQ4, p ## _IRQ5, p ## _IRQ6, p ## _IRQ7 } }, \ + { base + 0x24, 0, 8, /* INTREQ10A */ \ + { p ## _IRQ8, p ## _IRQ9, p ## _IRQ10, p ## _IRQ11, \ + p ## _IRQ12, p ## _IRQ13, p ## _IRQ14, p ## _IRQ15 } } + +#define INTC_IRQ_PINS_ACK_16H(p, base) \ + { base + 0x28, 0, 8, /* INTREQ20A */ \ + { p ## _IRQ16, p ## _IRQ17, p ## _IRQ18, p ## _IRQ19, \ + p ## _IRQ20, p ## _IRQ21, p ## _IRQ22, p ## _IRQ23 } }, \ + { base + 0x2c, 0, 8, /* INTREQ30A */ \ + { p ## _IRQ24, p ## _IRQ25, p ## _IRQ26, p ## _IRQ27, \ + p ## _IRQ28, p ## _IRQ29, p ## _IRQ30, p ## _IRQ31 } } + +#define INTC_IRQ_PINS_16(p, base, vect, str) \ + \ +static struct resource p ## _resources[] __initdata = { \ + [0] = { \ + .start = base, \ + .end = base + 0x64, \ + .flags = IORESOURCE_MEM, \ + }, \ +}; \ + \ +enum { \ + p ## _UNUSED = 0, \ + INTC_IRQ_PINS_ENUM_16L(p), \ +}; \ + \ +static struct intc_vect p ## _vectors[] __initdata = { \ + INTC_IRQ_PINS_VECT_16L(p, vect), \ +}; \ + \ +static struct intc_mask_reg p ## _mask_registers[] __initdata = { \ + INTC_IRQ_PINS_MASK_16L(p, base), \ +}; \ + \ +static struct intc_prio_reg p ## _prio_registers[] __initdata = { \ + INTC_IRQ_PINS_PRIO_16L(p, base), \ +}; \ + \ +static struct intc_sense_reg p ## _sense_registers[] __initdata = { \ + INTC_IRQ_PINS_SENSE_16L(p, base), \ +}; \ + \ +static struct intc_mask_reg p ## _ack_registers[] __initdata = { \ + INTC_IRQ_PINS_ACK_16L(p, base), \ +}; \ + \ +static struct intc_desc p ## _desc __initdata = { \ + .name = str, \ + .resource = p ## _resources, \ + .num_resources = ARRAY_SIZE(p ## _resources), \ + .hw = INTC_HW_DESC(p ## _vectors, NULL, \ + p ## _mask_registers, p ## _prio_registers, \ + p ## _sense_registers, p ## _ack_registers) \ +} + +#define INTC_IRQ_PINS_32(p, base, vect, str) \ + \ +static struct resource p ## _resources[] __initdata = { \ + [0] = { \ + .start = base, \ + .end = base + 0x6c, \ + .flags = IORESOURCE_MEM, \ + }, \ +}; \ + \ +enum { \ + p ## _UNUSED = 0, \ + INTC_IRQ_PINS_ENUM_16L(p), \ + INTC_IRQ_PINS_ENUM_16H(p), \ +}; \ + \ +static struct intc_vect p ## _vectors[] __initdata = { \ + INTC_IRQ_PINS_VECT_16L(p, vect), \ + INTC_IRQ_PINS_VECT_16H(p, vect), \ +}; \ + \ +static struct intc_mask_reg p ## _mask_registers[] __initdata = { \ + INTC_IRQ_PINS_MASK_16L(p, base), \ + INTC_IRQ_PINS_MASK_16H(p, base), \ +}; \ + \ +static struct intc_prio_reg p ## _prio_registers[] __initdata = { \ + INTC_IRQ_PINS_PRIO_16L(p, base), \ + INTC_IRQ_PINS_PRIO_16H(p, base), \ +}; \ + \ +static struct intc_sense_reg p ## _sense_registers[] __initdata = { \ + INTC_IRQ_PINS_SENSE_16L(p, base), \ + INTC_IRQ_PINS_SENSE_16H(p, base), \ +}; \ + \ +static struct intc_mask_reg p ## _ack_registers[] __initdata = { \ + INTC_IRQ_PINS_ACK_16L(p, base), \ + INTC_IRQ_PINS_ACK_16H(p, base), \ +}; \ + \ +static struct intc_desc p ## _desc __initdata = { \ + .name = str, \ + .resource = p ## _resources, \ + .num_resources = ARRAY_SIZE(p ## _resources), \ + .hw = INTC_HW_DESC(p ## _vectors, NULL, \ + p ## _mask_registers, p ## _prio_registers, \ + p ## _sense_registers, p ## _ack_registers) \ +} + +#define INTC_PINT_E_EMPTY +#define INTC_PINT_E_NONE 0, 0, 0, 0, 0, 0, 0, 0, +#define INTC_PINT_E(p) \ + PINT ## p ## 0, PINT ## p ## 1, PINT ## p ## 2, PINT ## p ## 3, \ + PINT ## p ## 4, PINT ## p ## 5, PINT ## p ## 6, PINT ## p ## 7, + +#define INTC_PINT_V_NONE +#define INTC_PINT_V(p, vect) \ + vect(PINT ## p ## 0, 0), vect(PINT ## p ## 1, 1), \ + vect(PINT ## p ## 2, 2), vect(PINT ## p ## 3, 3), \ + vect(PINT ## p ## 4, 4), vect(PINT ## p ## 5, 5), \ + vect(PINT ## p ## 6, 6), vect(PINT ## p ## 7, 7), + +#define INTC_PINT(p, mask_reg, sense_base, str, \ + enums_1, enums_2, enums_3, enums_4, \ + vect_1, vect_2, vect_3, vect_4, \ + mask_a, mask_b, mask_c, mask_d, \ + sense_a, sense_b, sense_c, sense_d) \ + \ +enum { \ + PINT ## p ## _UNUSED = 0, \ + enums_1 enums_2 enums_3 enums_4 \ +}; \ + \ +static struct intc_vect p ## _vectors[] __initdata = { \ + vect_1 vect_2 vect_3 vect_4 \ +}; \ + \ +static struct intc_mask_reg p ## _mask_registers[] __initdata = { \ + { mask_reg, 0, 32, /* PINTER */ \ + { mask_a mask_b mask_c mask_d } } \ +}; \ + \ +static struct intc_sense_reg p ## _sense_registers[] __initdata = { \ + { sense_base + 0x00, 16, 2, /* PINTCR */ \ + { sense_a } }, \ + { sense_base + 0x04, 16, 2, /* PINTCR */ \ + { sense_b } }, \ + { sense_base + 0x08, 16, 2, /* PINTCR */ \ + { sense_c } }, \ + { sense_base + 0x0c, 16, 2, /* PINTCR */ \ + { sense_d } }, \ +}; \ + \ +static struct intc_desc p ## _desc __initdata = { \ + .name = str, \ + .hw = INTC_HW_DESC(p ## _vectors, NULL, \ + p ## _mask_registers, NULL, \ + p ## _sense_registers, NULL), \ +} + +#endif /* __ASM_MACH_INTC_H */ diff --git a/arch/arm/mach-shmobile/include/mach/memory.h b/arch/arm/mach-shmobile/include/mach/memory.h index ad00c3c258f4..0ffbe8155c76 100644 --- a/arch/arm/mach-shmobile/include/mach/memory.h +++ b/arch/arm/mach-shmobile/include/mach/memory.h @@ -4,7 +4,4 @@ #define PLAT_PHYS_OFFSET UL(CONFIG_MEMORY_START) #define MEM_SIZE UL(CONFIG_MEMORY_SIZE) -/* DMA memory at 0xf6000000 - 0xffdfffff */ -#define CONSISTENT_DMA_SIZE (158 << 20) - #endif /* __ASM_MACH_MEMORY_H */ diff --git a/arch/arm/mach-shmobile/include/mach/sh7372.h b/arch/arm/mach-shmobile/include/mach/sh7372.h index 24e63a85e669..84532f9629b2 100644 --- a/arch/arm/mach-shmobile/include/mach/sh7372.h +++ b/arch/arm/mach-shmobile/include/mach/sh7372.h @@ -479,7 +479,12 @@ struct platform_device; struct sh7372_pm_domain { struct generic_pm_domain genpd; + struct dev_power_governor *gov; + void (*suspend)(void); + void (*resume)(void); unsigned int bit_shift; + bool no_debug; + bool stay_on; }; static inline struct sh7372_pm_domain *to_sh7372_pd(struct generic_pm_domain *d) @@ -491,16 +496,24 @@ static inline struct sh7372_pm_domain *to_sh7372_pd(struct generic_pm_domain *d) extern struct sh7372_pm_domain sh7372_a4lc; extern struct sh7372_pm_domain sh7372_a4mp; extern struct sh7372_pm_domain sh7372_d4; +extern struct sh7372_pm_domain sh7372_a4r; extern struct sh7372_pm_domain sh7372_a3rv; extern struct sh7372_pm_domain sh7372_a3ri; +extern struct sh7372_pm_domain sh7372_a3sp; extern struct sh7372_pm_domain sh7372_a3sg; extern void sh7372_init_pm_domain(struct sh7372_pm_domain *sh7372_pd); extern void sh7372_add_device_to_domain(struct sh7372_pm_domain *sh7372_pd, struct platform_device *pdev); +extern void sh7372_pm_add_subdomain(struct sh7372_pm_domain *sh7372_pd, + struct sh7372_pm_domain *sh7372_sd); #else #define sh7372_init_pm_domain(pd) do { } while(0) #define sh7372_add_device_to_domain(pd, pdev) do { } while(0) +#define sh7372_pm_add_subdomain(pd, sd) do { } while(0) #endif /* CONFIG_PM */ +extern void sh7372_intcs_suspend(void); +extern void sh7372_intcs_resume(void); + #endif /* __ASM_SH7372_H__ */ diff --git a/arch/arm/mach-shmobile/include/mach/sh73a0.h b/arch/arm/mach-shmobile/include/mach/sh73a0.h index 216c3d695ef1..18ae6a990bc2 100644 --- a/arch/arm/mach-shmobile/include/mach/sh73a0.h +++ b/arch/arm/mach-shmobile/include/mach/sh73a0.h @@ -451,11 +451,23 @@ enum { GPIO_FN_KEYIN5_PU, GPIO_FN_KEYIN6_PU, GPIO_FN_KEYIN7_PU, + GPIO_FN_SDHICD0_PU, + GPIO_FN_SDHID0_0_PU, + GPIO_FN_SDHID0_1_PU, + GPIO_FN_SDHID0_2_PU, + GPIO_FN_SDHID0_3_PU, + GPIO_FN_SDHICMD0_PU, + GPIO_FN_SDHIWP0_PU, GPIO_FN_SDHID1_0_PU, GPIO_FN_SDHID1_1_PU, GPIO_FN_SDHID1_2_PU, GPIO_FN_SDHID1_3_PU, GPIO_FN_SDHICMD1_PU, + GPIO_FN_SDHID2_0_PU, + GPIO_FN_SDHID2_1_PU, + GPIO_FN_SDHID2_2_PU, + GPIO_FN_SDHID2_3_PU, + GPIO_FN_SDHICMD2_PU, GPIO_FN_MMCCMD0_PU, GPIO_FN_MMCCMD1_PU, GPIO_FN_FSIACK_PU, @@ -463,6 +475,7 @@ enum { GPIO_FN_FSIAIBT_PU, GPIO_FN_FSIAISLD_PU, }; + /* DMA slave IDs */ enum { SHDMA_SLAVE_INVALID, @@ -494,4 +507,8 @@ enum { SHDMA_SLAVE_MMCIF_RX, }; +/* PINT interrupts are located at Linux IRQ 768 and up */ +#define SH73A0_PINT0_IRQ(irq) ((irq) + 768) +#define SH73A0_PINT1_IRQ(irq) ((irq) + 800) + #endif /* __ASM_SH73A0_H__ */ diff --git a/arch/arm/mach-shmobile/intc-sh7367.c b/arch/arm/mach-shmobile/intc-sh7367.c index cc442d198cdc..cfde9bfc3669 100644 --- a/arch/arm/mach-shmobile/intc-sh7367.c +++ b/arch/arm/mach-shmobile/intc-sh7367.c @@ -22,6 +22,7 @@ #include <linux/irq.h> #include <linux/io.h> #include <linux/sh_intc.h> +#include <mach/intc.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -31,8 +32,6 @@ enum { DISABLED, /* interrupt sources INTCA */ - IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A, - IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A, DIRC, CRYPT1_ERR, CRYPT2_STD, IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1, @@ -76,14 +75,6 @@ enum { }; static struct intc_vect intca_vectors[] __initdata = { - INTC_VECT(IRQ0A, 0x0200), INTC_VECT(IRQ1A, 0x0220), - INTC_VECT(IRQ2A, 0x0240), INTC_VECT(IRQ3A, 0x0260), - INTC_VECT(IRQ4A, 0x0280), INTC_VECT(IRQ5A, 0x02a0), - INTC_VECT(IRQ6A, 0x02c0), INTC_VECT(IRQ7A, 0x02e0), - INTC_VECT(IRQ8A, 0x0300), INTC_VECT(IRQ9A, 0x0320), - INTC_VECT(IRQ10A, 0x0340), INTC_VECT(IRQ11A, 0x0360), - INTC_VECT(IRQ12A, 0x0380), INTC_VECT(IRQ13A, 0x03a0), - INTC_VECT(IRQ14A, 0x03c0), INTC_VECT(IRQ15A, 0x03e0), INTC_VECT(DIRC, 0x0560), INTC_VECT(CRYPT1_ERR, 0x05e0), INTC_VECT(CRYPT2_STD, 0x0700), @@ -163,10 +154,6 @@ static struct intc_group intca_groups[] __initdata = { }; static struct intc_mask_reg intca_mask_registers[] __initdata = { - { 0xe6900040, 0xe6900060, 8, /* INTMSK00A / INTMSKCLR00A */ - { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, - { 0xe6900044, 0xe6900064, 8, /* INTMSK10A / INTMSKCLR10A */ - { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } }, { 0xe6940080, 0xe69400c0, 8, /* IMR0A / IMCR0A */ { DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0, ARM11_IRQPMU, 0, ARM11_COMMTX, ARM11_COMMRX } }, @@ -212,11 +199,6 @@ static struct intc_mask_reg intca_mask_registers[] __initdata = { }; static struct intc_prio_reg intca_prio_registers[] __initdata = { - { 0xe6900010, 0, 32, 4, /* INTPRI00A */ - { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, - { 0xe6900014, 0, 32, 4, /* INTPRI10A */ - { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } }, - { 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, LCRC } }, { 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, ETM11, BBIF1, BBIF2 } }, { 0xe6940008, 0, 16, 4, /* IPRCA */ { CRYPT1_ERR, CRYPT2_STD, @@ -240,29 +222,18 @@ static struct intc_prio_reg intca_prio_registers[] __initdata = { { 0xe6940038, 0, 16, 4, /* IPROA */ { 0, 0, DIRC, SDHI2 } }, }; -static struct intc_sense_reg intca_sense_registers[] __initdata = { - { 0xe6900000, 16, 2, /* ICR1A */ - { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, - { 0xe6900004, 16, 2, /* ICR2A */ - { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } }, -}; - -static struct intc_mask_reg intca_ack_registers[] __initdata = { - { 0xe6900020, 0, 8, /* INTREQ00A */ - { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, - { 0xe6900024, 0, 8, /* INTREQ10A */ - { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } }, -}; - static struct intc_desc intca_desc __initdata = { .name = "sh7367-intca", .force_enable = ENABLED, .force_disable = DISABLED, .hw = INTC_HW_DESC(intca_vectors, intca_groups, intca_mask_registers, intca_prio_registers, - intca_sense_registers, intca_ack_registers), + NULL, NULL), }; +INTC_IRQ_PINS_16(intca_irq_pins, 0xe6900000, + INTC_VECT, "sh7367-intca-irq-pins"); + enum { UNUSED_INTCS = 0, @@ -432,6 +403,7 @@ void __init sh7367_init_irq(void) void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE); register_intc_controller(&intca_desc); + register_intc_controller(&intca_irq_pins_desc); register_intc_controller(&intcs_desc); /* demux using INTEVTSA */ diff --git a/arch/arm/mach-shmobile/intc-sh7372.c b/arch/arm/mach-shmobile/intc-sh7372.c index 739315e30eb9..2d8856df80e2 100644 --- a/arch/arm/mach-shmobile/intc-sh7372.c +++ b/arch/arm/mach-shmobile/intc-sh7372.c @@ -22,6 +22,7 @@ #include <linux/irq.h> #include <linux/io.h> #include <linux/sh_intc.h> +#include <mach/intc.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -29,10 +30,6 @@ enum { UNUSED_INTCA = 0, /* interrupt sources INTCA */ - IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A, - IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A, - IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A, - IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A, DIRC, CRYPT_STD, IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1, @@ -86,22 +83,6 @@ enum { }; static struct intc_vect intca_vectors[] __initdata = { - INTC_VECT(IRQ0A, 0x0200), INTC_VECT(IRQ1A, 0x0220), - INTC_VECT(IRQ2A, 0x0240), INTC_VECT(IRQ3A, 0x0260), - INTC_VECT(IRQ4A, 0x0280), INTC_VECT(IRQ5A, 0x02a0), - INTC_VECT(IRQ6A, 0x02c0), INTC_VECT(IRQ7A, 0x02e0), - INTC_VECT(IRQ8A, 0x0300), INTC_VECT(IRQ9A, 0x0320), - INTC_VECT(IRQ10A, 0x0340), INTC_VECT(IRQ11A, 0x0360), - INTC_VECT(IRQ12A, 0x0380), INTC_VECT(IRQ13A, 0x03a0), - INTC_VECT(IRQ14A, 0x03c0), INTC_VECT(IRQ15A, 0x03e0), - INTC_VECT(IRQ16A, 0x3200), INTC_VECT(IRQ17A, 0x3220), - INTC_VECT(IRQ18A, 0x3240), INTC_VECT(IRQ19A, 0x3260), - INTC_VECT(IRQ20A, 0x3280), INTC_VECT(IRQ21A, 0x32a0), - INTC_VECT(IRQ22A, 0x32c0), INTC_VECT(IRQ23A, 0x32e0), - INTC_VECT(IRQ24A, 0x3300), INTC_VECT(IRQ25A, 0x3320), - INTC_VECT(IRQ26A, 0x3340), INTC_VECT(IRQ27A, 0x3360), - INTC_VECT(IRQ28A, 0x3380), INTC_VECT(IRQ29A, 0x33a0), - INTC_VECT(IRQ30A, 0x33c0), INTC_VECT(IRQ31A, 0x33e0), INTC_VECT(DIRC, 0x0560), INTC_VECT(CRYPT_STD, 0x0700), INTC_VECT(IIC1_ALI1, 0x0780), INTC_VECT(IIC1_TACKI1, 0x07a0), @@ -203,15 +184,6 @@ static struct intc_group intca_groups[] __initdata = { }; static struct intc_mask_reg intca_mask_registers[] __initdata = { - { 0xe6900040, 0xe6900060, 8, /* INTMSK00A / INTMSKCLR00A */ - { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, - { 0xe6900044, 0xe6900064, 8, /* INTMSK10A / INTMSKCLR10A */ - { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } }, - { 0xe6900048, 0xe6900068, 8, /* INTMSK20A / INTMSKCLR20A */ - { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } }, - { 0xe690004c, 0xe690006c, 8, /* INTMSK30A / INTMSKCLR30A */ - { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } }, - { 0xe6940080, 0xe69400c0, 8, /* IMR0A / IMCR0A */ { DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0, AP_ARM_IRQPMU, 0, AP_ARM_COMMTX, AP_ARM_COMMRX } }, @@ -282,15 +254,6 @@ static struct intc_mask_reg intca_mask_registers[] __initdata = { }; static struct intc_prio_reg intca_prio_registers[] __initdata = { - { 0xe6900010, 0, 32, 4, /* INTPRI00A */ - { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, - { 0xe6900014, 0, 32, 4, /* INTPRI10A */ - { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } }, - { 0xe6900018, 0, 32, 4, /* INTPRI20A */ - { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } }, - { 0xe690001c, 0, 32, 4, /* INTPRI30A */ - { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } }, - { 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, 0 } }, { 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, 0, BBIF1, BBIF2 } }, { 0xe6940008, 0, 16, 4, /* IPRCA */ { 0, CRYPT_STD, @@ -336,33 +299,13 @@ static struct intc_prio_reg intca_prio_registers[] __initdata = { { 0xe6950050, 0, 16, 4, /* IPRUA3 */ { USBHSDMAC1_USHDMI, 0, 0, 0 } }, }; -static struct intc_sense_reg intca_sense_registers[] __initdata = { - { 0xe6900000, 32, 4, /* ICR1A */ - { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, - { 0xe6900004, 32, 4, /* ICR2A */ - { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } }, - { 0xe6900008, 32, 4, /* ICR3A */ - { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } }, - { 0xe690000c, 32, 4, /* ICR4A */ - { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } }, -}; - -static struct intc_mask_reg intca_ack_registers[] __initdata = { - { 0xe6900020, 0, 8, /* INTREQ00A */ - { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, - { 0xe6900024, 0, 8, /* INTREQ10A */ - { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } }, - { 0xe6900028, 0, 8, /* INTREQ20A */ - { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } }, - { 0xe690002c, 0, 8, /* INTREQ30A */ - { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } }, -}; - -static DECLARE_INTC_DESC_ACK(intca_desc, "sh7372-intca", - intca_vectors, intca_groups, - intca_mask_registers, intca_prio_registers, - intca_sense_registers, intca_ack_registers); +static DECLARE_INTC_DESC(intca_desc, "sh7372-intca", + intca_vectors, intca_groups, + intca_mask_registers, intca_prio_registers, + NULL); +INTC_IRQ_PINS_32(intca_irq_pins, 0xe6900000, + INTC_VECT, "sh7372-intca-irq-pins"); enum { UNUSED_INTCS = 0, ENABLED_INTCS, @@ -606,14 +549,65 @@ static void intcs_demux(unsigned int irq, struct irq_desc *desc) generic_handle_irq(intcs_evt2irq(evtcodeas)); } +static void __iomem *intcs_ffd2; +static void __iomem *intcs_ffd5; + void __init sh7372_init_irq(void) { - void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE); + void __iomem *intevtsa; + + intcs_ffd2 = ioremap_nocache(0xffd20000, PAGE_SIZE); + intevtsa = intcs_ffd2 + 0x100; + intcs_ffd5 = ioremap_nocache(0xffd50000, PAGE_SIZE); register_intc_controller(&intca_desc); + register_intc_controller(&intca_irq_pins_desc); register_intc_controller(&intcs_desc); /* demux using INTEVTSA */ irq_set_handler_data(evt2irq(0xf80), (void *)intevtsa); irq_set_chained_handler(evt2irq(0xf80), intcs_demux); } + +static unsigned short ffd2[0x200]; +static unsigned short ffd5[0x100]; + +void sh7372_intcs_suspend(void) +{ + int k; + + for (k = 0x00; k <= 0x30; k += 4) + ffd2[k] = __raw_readw(intcs_ffd2 + k); + + for (k = 0x80; k <= 0xb0; k += 4) + ffd2[k] = __raw_readb(intcs_ffd2 + k); + + for (k = 0x180; k <= 0x188; k += 4) + ffd2[k] = __raw_readb(intcs_ffd2 + k); + + for (k = 0x00; k <= 0x3c; k += 4) + ffd5[k] = __raw_readw(intcs_ffd5 + k); + + for (k = 0x80; k <= 0x9c; k += 4) + ffd5[k] = __raw_readb(intcs_ffd5 + k); +} + +void sh7372_intcs_resume(void) +{ + int k; + + for (k = 0x00; k <= 0x30; k += 4) + __raw_writew(ffd2[k], intcs_ffd2 + k); + + for (k = 0x80; k <= 0xb0; k += 4) + __raw_writeb(ffd2[k], intcs_ffd2 + k); + + for (k = 0x180; k <= 0x188; k += 4) + __raw_writeb(ffd2[k], intcs_ffd2 + k); + + for (k = 0x00; k <= 0x3c; k += 4) + __raw_writew(ffd5[k], intcs_ffd5 + k); + + for (k = 0x80; k <= 0x9c; k += 4) + __raw_writeb(ffd5[k], intcs_ffd5 + k); +} diff --git a/arch/arm/mach-shmobile/intc-sh7377.c b/arch/arm/mach-shmobile/intc-sh7377.c index fe45154ce660..2af4e6e9bc5b 100644 --- a/arch/arm/mach-shmobile/intc-sh7377.c +++ b/arch/arm/mach-shmobile/intc-sh7377.c @@ -22,6 +22,7 @@ #include <linux/irq.h> #include <linux/io.h> #include <linux/sh_intc.h> +#include <mach/intc.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -31,10 +32,6 @@ enum { DISABLED, /* interrupt sources INTCA */ - IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A, - IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A, - IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A, - IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A, DIRC, _2DG, CRYPT_STD, @@ -91,22 +88,6 @@ enum { }; static struct intc_vect intca_vectors[] __initdata = { - INTC_VECT(IRQ0A, 0x0200), INTC_VECT(IRQ1A, 0x0220), - INTC_VECT(IRQ2A, 0x0240), INTC_VECT(IRQ3A, 0x0260), - INTC_VECT(IRQ4A, 0x0280), INTC_VECT(IRQ5A, 0x02a0), - INTC_VECT(IRQ6A, 0x02c0), INTC_VECT(IRQ7A, 0x02e0), - INTC_VECT(IRQ8A, 0x0300), INTC_VECT(IRQ9A, 0x0320), - INTC_VECT(IRQ10A, 0x0340), INTC_VECT(IRQ11A, 0x0360), - INTC_VECT(IRQ12A, 0x0380), INTC_VECT(IRQ13A, 0x03a0), - INTC_VECT(IRQ14A, 0x03c0), INTC_VECT(IRQ15A, 0x03e0), - INTC_VECT(IRQ16A, 0x3200), INTC_VECT(IRQ17A, 0x3220), - INTC_VECT(IRQ18A, 0x3240), INTC_VECT(IRQ19A, 0x3260), - INTC_VECT(IRQ20A, 0x3280), INTC_VECT(IRQ31A, 0x32a0), - INTC_VECT(IRQ22A, 0x32c0), INTC_VECT(IRQ23A, 0x32e0), - INTC_VECT(IRQ24A, 0x3300), INTC_VECT(IRQ25A, 0x3320), - INTC_VECT(IRQ26A, 0x3340), INTC_VECT(IRQ27A, 0x3360), - INTC_VECT(IRQ28A, 0x3380), INTC_VECT(IRQ29A, 0x33a0), - INTC_VECT(IRQ30A, 0x33c0), INTC_VECT(IRQ31A, 0x33e0), INTC_VECT(DIRC, 0x0560), INTC_VECT(_2DG, 0x05e0), INTC_VECT(CRYPT_STD, 0x0700), @@ -203,15 +184,6 @@ static struct intc_group intca_groups[] __initdata = { }; static struct intc_mask_reg intca_mask_registers[] __initdata = { - { 0xe6900040, 0xe6900060, 8, /* INTMSK00A / INTMSKCLR00A */ - { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, - { 0xe6900044, 0xe6900064, 8, /* INTMSK10A / INTMSKCLR10A */ - { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } }, - { 0xe6900048, 0xe6900068, 8, /* INTMSK20A / INTMSKCLR20A */ - { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } }, - { 0xe690004c, 0xe690006c, 8, /* INTMSK30A / INTMSKCLR30A */ - { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } }, - { 0xe6940080, 0xe69400c0, 8, /* IMR0A / IMCR0A */ { DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0, AP_ARM_IRQPMU, 0, AP_ARM_COMMTX, AP_ARM_COMMRX } }, @@ -273,15 +245,6 @@ static struct intc_mask_reg intca_mask_registers[] __initdata = { }; static struct intc_prio_reg intca_prio_registers[] __initdata = { - { 0xe6900010, 0, 32, 4, /* INTPRI00A */ - { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, - { 0xe6900014, 0, 32, 4, /* INTPRI10A */ - { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } }, - { 0xe6900018, 0, 32, 4, /* INTPRI10A */ - { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } }, - { 0xe690001c, 0, 32, 4, /* INTPRI30A */ - { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } }, - { 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, LCRC } }, { 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, 0, BBIF1, BBIF2 } }, { 0xe6940008, 0, 16, 4, /* IPRCA */ { _2DG, CRYPT_STD, @@ -315,37 +278,18 @@ static struct intc_prio_reg intca_prio_registers[] __initdata = { { 0xe694003c, 0, 16, 4, /* IPRPA3 */ { SCIFA6, 0, 0, 0 } }, }; -static struct intc_sense_reg intca_sense_registers[] __initdata = { - { 0xe6900000, 16, 2, /* ICR1A */ - { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, - { 0xe6900004, 16, 2, /* ICR2A */ - { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } }, - { 0xe6900008, 16, 2, /* ICR3A */ - { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } }, - { 0xe690000c, 16, 2, /* ICR4A */ - { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } }, -}; - -static struct intc_mask_reg intca_ack_registers[] __initdata = { - { 0xe6900020, 0, 8, /* INTREQ00A */ - { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, - { 0xe6900024, 0, 8, /* INTREQ10A */ - { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } }, - { 0xe6900028, 0, 8, /* INTREQ20A */ - { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } }, - { 0xe690002c, 0, 8, /* INTREQ30A */ - { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } }, -}; - static struct intc_desc intca_desc __initdata = { .name = "sh7377-intca", .force_enable = ENABLED, .force_disable = DISABLED, .hw = INTC_HW_DESC(intca_vectors, intca_groups, intca_mask_registers, intca_prio_registers, - intca_sense_registers, intca_ack_registers), + NULL, NULL), }; +INTC_IRQ_PINS_32(intca_irq_pins, 0xe6900000, + INTC_VECT, "sh7377-intca-irq-pins"); + /* this macro ignore entry which is also in INTCA */ #define __IGNORE(a...) #define __IGNORE0(a...) 0 @@ -638,6 +582,7 @@ void __init sh7377_init_irq(void) void __iomem *intevtsa = ioremap_nocache(INTEVTSA, PAGE_SIZE); register_intc_controller(&intca_desc); + register_intc_controller(&intca_irq_pins_desc); register_intc_controller(&intcs_desc); /* demux using INTEVTSA */ diff --git a/arch/arm/mach-shmobile/intc-sh73a0.c b/arch/arm/mach-shmobile/intc-sh73a0.c index a911a60e7719..1eda6b0b69e3 100644 --- a/arch/arm/mach-shmobile/intc-sh73a0.c +++ b/arch/arm/mach-shmobile/intc-sh73a0.c @@ -22,6 +22,8 @@ #include <linux/irq.h> #include <linux/io.h> #include <linux/sh_intc.h> +#include <mach/intc.h> +#include <mach/sh73a0.h> #include <asm/hardware/gic.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -255,20 +257,205 @@ static int sh73a0_set_wake(struct irq_data *data, unsigned int on) return 0; /* always allow wakeup */ } +#define RELOC_BASE 0x1000 + +/* INTCA IRQ pins at INTCS + 0x1000 to make space for GIC+INTC handling */ +#define INTCS_VECT_RELOC(n, vect) INTCS_VECT((n), (vect) + RELOC_BASE) + +INTC_IRQ_PINS_32(intca_irq_pins, 0xe6900000, + INTCS_VECT_RELOC, "sh73a0-intca-irq-pins"); + +static int to_gic_irq(struct irq_data *data) +{ + unsigned int vect = irq2evt(data->irq) - INTCS_VECT_BASE; + + if (vect >= 0x3200) + vect -= 0x3000; + else + vect -= 0x0200; + + return gic_spi((vect >> 5) + 1); +} + +static int to_intca_reloc_irq(struct irq_data *data) +{ + return data->irq + (RELOC_BASE >> 5); +} + +#define irq_cb(cb, irq) irq_get_chip(irq)->cb(irq_get_irq_data(irq)) +#define irq_cbp(cb, irq, p...) irq_get_chip(irq)->cb(irq_get_irq_data(irq), p) + +static void intca_gic_enable(struct irq_data *data) +{ + irq_cb(irq_unmask, to_intca_reloc_irq(data)); + irq_cb(irq_unmask, to_gic_irq(data)); +} + +static void intca_gic_disable(struct irq_data *data) +{ + irq_cb(irq_mask, to_gic_irq(data)); + irq_cb(irq_mask, to_intca_reloc_irq(data)); +} + +static void intca_gic_mask_ack(struct irq_data *data) +{ + irq_cb(irq_mask, to_gic_irq(data)); + irq_cb(irq_mask_ack, to_intca_reloc_irq(data)); +} + +static void intca_gic_eoi(struct irq_data *data) +{ + irq_cb(irq_eoi, to_gic_irq(data)); +} + +static int intca_gic_set_type(struct irq_data *data, unsigned int type) +{ + return irq_cbp(irq_set_type, to_intca_reloc_irq(data), type); +} + +static int intca_gic_set_wake(struct irq_data *data, unsigned int on) +{ + return irq_cbp(irq_set_wake, to_intca_reloc_irq(data), on); +} + +#ifdef CONFIG_SMP +static int intca_gic_set_affinity(struct irq_data *data, + const struct cpumask *cpumask, + bool force) +{ + return irq_cbp(irq_set_affinity, to_gic_irq(data), cpumask, force); +} +#endif + +struct irq_chip intca_gic_irq_chip = { + .name = "INTCA-GIC", + .irq_mask = intca_gic_disable, + .irq_unmask = intca_gic_enable, + .irq_mask_ack = intca_gic_mask_ack, + .irq_eoi = intca_gic_eoi, + .irq_enable = intca_gic_enable, + .irq_disable = intca_gic_disable, + .irq_shutdown = intca_gic_disable, + .irq_set_type = intca_gic_set_type, + .irq_set_wake = intca_gic_set_wake, +#ifdef CONFIG_SMP + .irq_set_affinity = intca_gic_set_affinity, +#endif +}; + +static int to_intc_vect(int irq) +{ + unsigned int irq_pin = irq - gic_spi(1); + unsigned int offs; + + if (irq_pin < 16) + offs = 0x0200; + else + offs = 0x3000; + + return offs + (irq_pin << 5); +} + +static irqreturn_t sh73a0_irq_pin_demux(int irq, void *dev_id) +{ + generic_handle_irq(intcs_evt2irq(to_intc_vect(irq))); + return IRQ_HANDLED; +} + +static struct irqaction sh73a0_irq_pin_cascade[32]; + +#define PINTER0 0xe69000a0 +#define PINTER1 0xe69000a4 +#define PINTRR0 0xe69000d0 +#define PINTRR1 0xe69000d4 + +#define PINT0A_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT0_IRQ(irq)) +#define PINT0B_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT0_IRQ(irq + 8)) +#define PINT0C_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT0_IRQ(irq + 16)) +#define PINT0D_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT0_IRQ(irq + 24)) +#define PINT1E_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT1_IRQ(irq)) + +INTC_PINT(intc_pint0, PINTER0, 0xe69000b0, "sh73a0-pint0", \ + INTC_PINT_E(A), INTC_PINT_E(B), INTC_PINT_E(C), INTC_PINT_E(D), \ + INTC_PINT_V(A, PINT0A_IRQ), INTC_PINT_V(B, PINT0B_IRQ), \ + INTC_PINT_V(C, PINT0C_IRQ), INTC_PINT_V(D, PINT0D_IRQ), \ + INTC_PINT_E(A), INTC_PINT_E(B), INTC_PINT_E(C), INTC_PINT_E(D), \ + INTC_PINT_E(A), INTC_PINT_E(B), INTC_PINT_E(C), INTC_PINT_E(D)); + +INTC_PINT(intc_pint1, PINTER1, 0xe69000c0, "sh73a0-pint1", \ + INTC_PINT_E(E), INTC_PINT_E_EMPTY, INTC_PINT_E_EMPTY, INTC_PINT_E_EMPTY, \ + INTC_PINT_V(E, PINT1E_IRQ), INTC_PINT_V_NONE, \ + INTC_PINT_V_NONE, INTC_PINT_V_NONE, \ + INTC_PINT_E_NONE, INTC_PINT_E_NONE, INTC_PINT_E_NONE, INTC_PINT_E(E), \ + INTC_PINT_E(E), INTC_PINT_E_NONE, INTC_PINT_E_NONE, INTC_PINT_E_NONE); + +static struct irqaction sh73a0_pint0_cascade; +static struct irqaction sh73a0_pint1_cascade; + +static void pint_demux(unsigned long rr, unsigned long er, int base_irq) +{ + unsigned long value = ioread32(rr) & ioread32(er); + int k; + + for (k = 0; k < 32; k++) { + if (value & (1 << (31 - k))) { + generic_handle_irq(base_irq + k); + iowrite32(~(1 << (31 - k)), rr); + } + } +} + +static irqreturn_t sh73a0_pint0_demux(int irq, void *dev_id) +{ + pint_demux(PINTRR0, PINTER0, SH73A0_PINT0_IRQ(0)); + return IRQ_HANDLED; +} + +static irqreturn_t sh73a0_pint1_demux(int irq, void *dev_id) +{ + pint_demux(PINTRR1, PINTER1, SH73A0_PINT1_IRQ(0)); + return IRQ_HANDLED; +} + void __init sh73a0_init_irq(void) { void __iomem *gic_dist_base = __io(0xf0001000); void __iomem *gic_cpu_base = __io(0xf0000100); void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE); + int k, n; gic_init(0, 29, gic_dist_base, gic_cpu_base); gic_arch_extn.irq_set_wake = sh73a0_set_wake; register_intc_controller(&intcs_desc); + register_intc_controller(&intca_irq_pins_desc); + register_intc_controller(&intc_pint0_desc); + register_intc_controller(&intc_pint1_desc); /* demux using INTEVTSA */ sh73a0_intcs_cascade.name = "INTCS cascade"; sh73a0_intcs_cascade.handler = sh73a0_intcs_demux; sh73a0_intcs_cascade.dev_id = intevtsa; setup_irq(gic_spi(50), &sh73a0_intcs_cascade); + + /* IRQ pins require special handling through INTCA and GIC */ + for (k = 0; k < 32; k++) { + sh73a0_irq_pin_cascade[k].name = "INTCA-GIC cascade"; + sh73a0_irq_pin_cascade[k].handler = sh73a0_irq_pin_demux; + setup_irq(gic_spi(1 + k), &sh73a0_irq_pin_cascade[k]); + + n = intcs_evt2irq(to_intc_vect(gic_spi(1 + k))); + irq_set_chip_and_handler_name(n, &intca_gic_irq_chip, + handle_level_irq, "level"); + set_irq_flags(n, IRQF_VALID); /* yuck */ + } + + /* PINT pins are sanely tied to the GIC as SPI */ + sh73a0_pint0_cascade.name = "PINT0 cascade"; + sh73a0_pint0_cascade.handler = sh73a0_pint0_demux; + setup_irq(gic_spi(33), &sh73a0_pint0_cascade); + + sh73a0_pint1_cascade.name = "PINT1 cascade"; + sh73a0_pint1_cascade.handler = sh73a0_pint1_demux; + setup_irq(gic_spi(34), &sh73a0_pint1_cascade); } diff --git a/arch/arm/mach-shmobile/pfc-sh73a0.c b/arch/arm/mach-shmobile/pfc-sh73a0.c index 3eed44eb98b4..5abe02fbd6b9 100644 --- a/arch/arm/mach-shmobile/pfc-sh73a0.c +++ b/arch/arm/mach-shmobile/pfc-sh73a0.c @@ -22,6 +22,7 @@ #include <linux/kernel.h> #include <linux/gpio.h> #include <mach/sh73a0.h> +#include <mach/irqs.h> #define _1(fn, pfx, sfx) fn(pfx, sfx) @@ -488,13 +489,26 @@ enum { KEYIN5_PU_MARK, KEYIN6_PU_MARK, KEYIN7_PU_MARK, + SDHICD0_PU_MARK, + SDHID0_0_PU_MARK, + SDHID0_1_PU_MARK, + SDHID0_2_PU_MARK, + SDHID0_3_PU_MARK, + SDHICMD0_PU_MARK, + SDHIWP0_PU_MARK, SDHID1_0_PU_MARK, SDHID1_1_PU_MARK, SDHID1_2_PU_MARK, SDHID1_3_PU_MARK, SDHICMD1_PU_MARK, + SDHID2_0_PU_MARK, + SDHID2_1_PU_MARK, + SDHID2_2_PU_MARK, + SDHID2_3_PU_MARK, + SDHICMD2_PU_MARK, MMCCMD0_PU_MARK, MMCCMD1_PU_MARK, + FSIBISLD_PU_MARK, FSIACK_PU_MARK, FSIAILR_PU_MARK, FSIAIBT_PU_MARK, @@ -1387,19 +1401,28 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(TS_SCK4_MARK, PORT268_FN3), PINMUX_DATA(SDHICMD2_MARK, PORT269_FN1), PINMUX_DATA(MMCCLK0_MARK, PORT270_FN1, MSEL4CR_MSEL15_0), - PINMUX_DATA(MMCD0_0_MARK, PORT271_FN1, MSEL4CR_MSEL15_0), - PINMUX_DATA(MMCD0_1_MARK, PORT272_FN1, MSEL4CR_MSEL15_0), - PINMUX_DATA(MMCD0_2_MARK, PORT273_FN1, MSEL4CR_MSEL15_0), - PINMUX_DATA(MMCD0_3_MARK, PORT274_FN1, MSEL4CR_MSEL15_0), - PINMUX_DATA(MMCD0_4_MARK, PORT275_FN1, MSEL4CR_MSEL15_0), \ + PINMUX_DATA(MMCD0_0_MARK, PORT271_FN1, PORT271_IN_PU, + MSEL4CR_MSEL15_0), + PINMUX_DATA(MMCD0_1_MARK, PORT272_FN1, PORT272_IN_PU, + MSEL4CR_MSEL15_0), + PINMUX_DATA(MMCD0_2_MARK, PORT273_FN1, PORT273_IN_PU, + MSEL4CR_MSEL15_0), + PINMUX_DATA(MMCD0_3_MARK, PORT274_FN1, PORT274_IN_PU, + MSEL4CR_MSEL15_0), + PINMUX_DATA(MMCD0_4_MARK, PORT275_FN1, PORT275_IN_PU, + MSEL4CR_MSEL15_0), \ PINMUX_DATA(TS_SPSYNC5_MARK, PORT275_FN3), - PINMUX_DATA(MMCD0_5_MARK, PORT276_FN1, MSEL4CR_MSEL15_0), \ + PINMUX_DATA(MMCD0_5_MARK, PORT276_FN1, PORT276_IN_PU, + MSEL4CR_MSEL15_0), \ PINMUX_DATA(TS_SDAT5_MARK, PORT276_FN3), - PINMUX_DATA(MMCD0_6_MARK, PORT277_FN1, MSEL4CR_MSEL15_0), \ + PINMUX_DATA(MMCD0_6_MARK, PORT277_FN1, PORT277_IN_PU, + MSEL4CR_MSEL15_0), \ PINMUX_DATA(TS_SDEN5_MARK, PORT277_FN3), - PINMUX_DATA(MMCD0_7_MARK, PORT278_FN1, MSEL4CR_MSEL15_0), \ + PINMUX_DATA(MMCD0_7_MARK, PORT278_FN1, PORT278_IN_PU, + MSEL4CR_MSEL15_0), \ PINMUX_DATA(TS_SCK5_MARK, PORT278_FN3), - PINMUX_DATA(MMCCMD0_MARK, PORT279_FN1, MSEL4CR_MSEL15_0), + PINMUX_DATA(MMCCMD0_MARK, PORT279_FN1, PORT279_IN_PU, + MSEL4CR_MSEL15_0), PINMUX_DATA(RESETOUTS__MARK, PORT281_FN1), \ PINMUX_DATA(EXTAL2OUT_MARK, PORT281_FN2), PINMUX_DATA(MCP_WAIT__MCP_FRB_MARK, PORT288_FN1), @@ -1516,16 +1539,29 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(KEYIN6_PU_MARK, PORT72_FN2, PORT72_IN_PU), PINMUX_DATA(KEYIN7_PU_MARK, PORT73_FN2, PORT73_IN_PU), - PINMUX_DATA(SDHID1_0_PU_MARK, PORT259_IN_PU, PORT259_FN1), - PINMUX_DATA(SDHID1_1_PU_MARK, PORT260_IN_PU, PORT260_FN1), - PINMUX_DATA(SDHID1_2_PU_MARK, PORT261_IN_PU, PORT261_FN1), - PINMUX_DATA(SDHID1_3_PU_MARK, PORT262_IN_PU, PORT262_FN1), - PINMUX_DATA(SDHICMD1_PU_MARK, PORT263_IN_PU, PORT263_FN1), + PINMUX_DATA(SDHICD0_PU_MARK, PORT251_FN1, PORT251_IN_PU), + PINMUX_DATA(SDHID0_0_PU_MARK, PORT252_FN1, PORT252_IN_PU), + PINMUX_DATA(SDHID0_1_PU_MARK, PORT253_FN1, PORT253_IN_PU), + PINMUX_DATA(SDHID0_2_PU_MARK, PORT254_FN1, PORT254_IN_PU), + PINMUX_DATA(SDHID0_3_PU_MARK, PORT255_FN1, PORT255_IN_PU), + PINMUX_DATA(SDHICMD0_PU_MARK, PORT256_FN1, PORT256_IN_PU), + PINMUX_DATA(SDHIWP0_PU_MARK, PORT257_FN1, PORT256_IN_PU), + PINMUX_DATA(SDHID1_0_PU_MARK, PORT259_FN1, PORT259_IN_PU), + PINMUX_DATA(SDHID1_1_PU_MARK, PORT260_FN1, PORT260_IN_PU), + PINMUX_DATA(SDHID1_2_PU_MARK, PORT261_FN1, PORT261_IN_PU), + PINMUX_DATA(SDHID1_3_PU_MARK, PORT262_FN1, PORT262_IN_PU), + PINMUX_DATA(SDHICMD1_PU_MARK, PORT263_FN1, PORT263_IN_PU), + PINMUX_DATA(SDHID2_0_PU_MARK, PORT265_FN1, PORT265_IN_PU), + PINMUX_DATA(SDHID2_1_PU_MARK, PORT266_FN1, PORT266_IN_PU), + PINMUX_DATA(SDHID2_2_PU_MARK, PORT267_FN1, PORT267_IN_PU), + PINMUX_DATA(SDHID2_3_PU_MARK, PORT268_FN1, PORT268_IN_PU), + PINMUX_DATA(SDHICMD2_PU_MARK, PORT269_FN1, PORT269_IN_PU), PINMUX_DATA(MMCCMD0_PU_MARK, PORT279_FN1, PORT279_IN_PU, MSEL4CR_MSEL15_0), - PINMUX_DATA(MMCCMD1_PU_MARK, PORT297_FN2, PORT279_IN_PU, + PINMUX_DATA(MMCCMD1_PU_MARK, PORT297_FN2, PORT297_IN_PU, MSEL4CR_MSEL15_1), + PINMUX_DATA(FSIBISLD_PU_MARK, PORT39_FN1, PORT39_IN_PU), PINMUX_DATA(FSIACK_PU_MARK, PORT49_FN1, PORT49_IN_PU), PINMUX_DATA(FSIAILR_PU_MARK, PORT50_FN5, PORT50_IN_PU), PINMUX_DATA(FSIAIBT_PU_MARK, PORT51_FN5, PORT51_IN_PU), @@ -2181,11 +2217,23 @@ static struct pinmux_gpio pinmux_gpios[] = { GPIO_FN(KEYIN5_PU), GPIO_FN(KEYIN6_PU), GPIO_FN(KEYIN7_PU), + GPIO_FN(SDHICD0_PU), + GPIO_FN(SDHID0_0_PU), + GPIO_FN(SDHID0_1_PU), + GPIO_FN(SDHID0_2_PU), + GPIO_FN(SDHID0_3_PU), + GPIO_FN(SDHICMD0_PU), + GPIO_FN(SDHIWP0_PU), GPIO_FN(SDHID1_0_PU), GPIO_FN(SDHID1_1_PU), GPIO_FN(SDHID1_2_PU), GPIO_FN(SDHID1_3_PU), GPIO_FN(SDHICMD1_PU), + GPIO_FN(SDHID2_0_PU), + GPIO_FN(SDHID2_1_PU), + GPIO_FN(SDHID2_2_PU), + GPIO_FN(SDHID2_3_PU), + GPIO_FN(SDHICMD2_PU), GPIO_FN(MMCCMD0_PU), GPIO_FN(MMCCMD1_PU), GPIO_FN(FSIACK_PU), @@ -2718,6 +2766,45 @@ static struct pinmux_data_reg pinmux_data_regs[] = { { }, }; +/* IRQ pins through INTCS with IRQ0->15 from 0x200 and IRQ16-31 from 0x3200 */ +#define EXT_IRQ16L(n) intcs_evt2irq(0x200 + ((n) << 5)) +#define EXT_IRQ16H(n) intcs_evt2irq(0x3200 + ((n - 16) << 5)) + +static struct pinmux_irq pinmux_irqs[] = { + PINMUX_IRQ(EXT_IRQ16H(19), PORT9_FN0), + PINMUX_IRQ(EXT_IRQ16L(1), PORT10_FN0), + PINMUX_IRQ(EXT_IRQ16L(0), PORT11_FN0), + PINMUX_IRQ(EXT_IRQ16H(18), PORT13_FN0), + PINMUX_IRQ(EXT_IRQ16H(20), PORT14_FN0), + PINMUX_IRQ(EXT_IRQ16H(21), PORT15_FN0), + PINMUX_IRQ(EXT_IRQ16H(31), PORT26_FN0), + PINMUX_IRQ(EXT_IRQ16H(30), PORT27_FN0), + PINMUX_IRQ(EXT_IRQ16H(29), PORT28_FN0), + PINMUX_IRQ(EXT_IRQ16H(22), PORT40_FN0), + PINMUX_IRQ(EXT_IRQ16H(23), PORT53_FN0), + PINMUX_IRQ(EXT_IRQ16L(10), PORT54_FN0), + PINMUX_IRQ(EXT_IRQ16L(9), PORT56_FN0), + PINMUX_IRQ(EXT_IRQ16H(26), PORT115_FN0), + PINMUX_IRQ(EXT_IRQ16H(27), PORT116_FN0), + PINMUX_IRQ(EXT_IRQ16H(28), PORT117_FN0), + PINMUX_IRQ(EXT_IRQ16H(24), PORT118_FN0), + PINMUX_IRQ(EXT_IRQ16L(6), PORT147_FN0), + PINMUX_IRQ(EXT_IRQ16L(2), PORT149_FN0), + PINMUX_IRQ(EXT_IRQ16L(7), PORT150_FN0), + PINMUX_IRQ(EXT_IRQ16L(12), PORT156_FN0), + PINMUX_IRQ(EXT_IRQ16L(4), PORT159_FN0), + PINMUX_IRQ(EXT_IRQ16H(25), PORT164_FN0), + PINMUX_IRQ(EXT_IRQ16L(8), PORT223_FN0), + PINMUX_IRQ(EXT_IRQ16L(3), PORT224_FN0), + PINMUX_IRQ(EXT_IRQ16L(5), PORT227_FN0), + PINMUX_IRQ(EXT_IRQ16H(17), PORT234_FN0), + PINMUX_IRQ(EXT_IRQ16L(11), PORT238_FN0), + PINMUX_IRQ(EXT_IRQ16L(13), PORT239_FN0), + PINMUX_IRQ(EXT_IRQ16H(16), PORT249_FN0), + PINMUX_IRQ(EXT_IRQ16L(14), PORT251_FN0), + PINMUX_IRQ(EXT_IRQ16L(9), PORT308_FN0), +}; + static struct pinmux_info sh73a0_pinmux_info = { .name = "sh73a0_pfc", .reserved_id = PINMUX_RESERVED, @@ -2738,6 +2825,9 @@ static struct pinmux_info sh73a0_pinmux_info = { .gpio_data = pinmux_data, .gpio_data_size = ARRAY_SIZE(pinmux_data), + + .gpio_irq = pinmux_irqs, + .gpio_irq_size = ARRAY_SIZE(pinmux_irqs), }; void sh73a0_pinmux_init(void) diff --git a/arch/arm/mach-shmobile/platsmp.c b/arch/arm/mach-shmobile/platsmp.c index e4e485fa2532..c49a833bf9bb 100644 --- a/arch/arm/mach-shmobile/platsmp.c +++ b/arch/arm/mach-shmobile/platsmp.c @@ -21,9 +21,11 @@ #include <asm/mach-types.h> #include <mach/common.h> +#define is_sh73a0() (machine_is_ag5evm() || machine_is_kota2()) + static unsigned int __init shmobile_smp_get_core_count(void) { - if (machine_is_ag5evm()) + if (is_sh73a0()) return sh73a0_get_core_count(); return 1; @@ -31,7 +33,7 @@ static unsigned int __init shmobile_smp_get_core_count(void) static void __init shmobile_smp_prepare_cpus(void) { - if (machine_is_ag5evm()) + if (is_sh73a0()) sh73a0_smp_prepare_cpus(); } @@ -39,13 +41,13 @@ void __cpuinit platform_secondary_init(unsigned int cpu) { trace_hardirqs_off(); - if (machine_is_ag5evm()) + if (is_sh73a0()) sh73a0_secondary_init(cpu); } int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) { - if (machine_is_ag5evm()) + if (is_sh73a0()) return sh73a0_boot_secondary(cpu); return -ENOSYS; diff --git a/arch/arm/mach-shmobile/pm-sh7372.c b/arch/arm/mach-shmobile/pm-sh7372.c index 933fb411be0f..79612737c5b2 100644 --- a/arch/arm/mach-shmobile/pm-sh7372.c +++ b/arch/arm/mach-shmobile/pm-sh7372.c @@ -15,23 +15,61 @@ #include <linux/list.h> #include <linux/err.h> #include <linux/slab.h> -#include <linux/pm_runtime.h> +#include <linux/pm_clock.h> #include <linux/platform_device.h> #include <linux/delay.h> +#include <linux/irq.h> +#include <linux/bitrev.h> #include <asm/system.h> #include <asm/io.h> #include <asm/tlbflush.h> +#include <asm/suspend.h> #include <mach/common.h> #include <mach/sh7372.h> -#define SMFRAM 0xe6a70000 -#define SYSTBCR 0xe6150024 -#define SBAR 0xe6180020 -#define APARMBAREA 0xe6f10020 +/* DBG */ +#define DBGREG1 0xe6100020 +#define DBGREG9 0xe6100040 +/* CPGA */ +#define SYSTBCR 0xe6150024 +#define MSTPSR0 0xe6150030 +#define MSTPSR1 0xe6150038 +#define MSTPSR2 0xe6150040 +#define MSTPSR3 0xe6150048 +#define MSTPSR4 0xe615004c +#define PLLC01STPCR 0xe61500c8 + +/* SYSC */ #define SPDCR 0xe6180008 #define SWUCR 0xe6180014 +#define SBAR 0xe6180020 +#define WUPRMSK 0xe6180028 +#define WUPSMSK 0xe618002c +#define WUPSMSK2 0xe6180048 #define PSTR 0xe6180080 +#define WUPSFAC 0xe6180098 +#define IRQCR 0xe618022c +#define IRQCR2 0xe6180238 +#define IRQCR3 0xe6180244 +#define IRQCR4 0xe6180248 +#define PDNSEL 0xe6180254 + +/* INTC */ +#define ICR1A 0xe6900000 +#define ICR2A 0xe6900004 +#define ICR3A 0xe6900008 +#define ICR4A 0xe690000c +#define INTMSK00A 0xe6900040 +#define INTMSK10A 0xe6900044 +#define INTMSK20A 0xe6900048 +#define INTMSK30A 0xe690004c + +/* MFIS */ +#define SMFRAM 0xe6a70000 + +/* AP-System Core */ +#define APARMBAREA 0xe6f10020 #define PSTR_RETRIES 100 #define PSTR_DELAY_US 10 @@ -43,6 +81,12 @@ static int pd_power_down(struct generic_pm_domain *genpd) struct sh7372_pm_domain *sh7372_pd = to_sh7372_pd(genpd); unsigned int mask = 1 << sh7372_pd->bit_shift; + if (sh7372_pd->suspend) + sh7372_pd->suspend(); + + if (sh7372_pd->stay_on) + return 0; + if (__raw_readl(PSTR) & mask) { unsigned int retry_count; @@ -55,8 +99,9 @@ static int pd_power_down(struct generic_pm_domain *genpd) } } - pr_debug("sh7372 power domain down 0x%08x -> PSTR = 0x%08x\n", - mask, __raw_readl(PSTR)); + if (!sh7372_pd->no_debug) + pr_debug("sh7372 power domain down 0x%08x -> PSTR = 0x%08x\n", + mask, __raw_readl(PSTR)); return 0; } @@ -68,6 +113,9 @@ static int pd_power_up(struct generic_pm_domain *genpd) unsigned int retry_count; int ret = 0; + if (sh7372_pd->stay_on) + goto out; + if (__raw_readl(PSTR) & mask) goto out; @@ -84,66 +132,48 @@ static int pd_power_up(struct generic_pm_domain *genpd) if (__raw_readl(SWUCR) & mask) ret = -EIO; + if (!sh7372_pd->no_debug) + pr_debug("sh7372 power domain up 0x%08x -> PSTR = 0x%08x\n", + mask, __raw_readl(PSTR)); + out: - pr_debug("sh7372 power domain up 0x%08x -> PSTR = 0x%08x\n", - mask, __raw_readl(PSTR)); + if (ret == 0 && sh7372_pd->resume) + sh7372_pd->resume(); return ret; } -static int pd_power_up_a3rv(struct generic_pm_domain *genpd) +static void sh7372_a4r_suspend(void) { - int ret = pd_power_up(genpd); - - /* force A4LC on after A3RV has been requested on */ - pm_genpd_poweron(&sh7372_a4lc.genpd); - - return ret; + sh7372_intcs_suspend(); + __raw_writel(0x300fffff, WUPRMSK); /* avoid wakeup */ } -static int pd_power_down_a3rv(struct generic_pm_domain *genpd) +static bool pd_active_wakeup(struct device *dev) { - int ret = pd_power_down(genpd); - - /* try to power down A4LC after A3RV is requested off */ - genpd_queue_power_off_work(&sh7372_a4lc.genpd); - - return ret; + return true; } -static int pd_power_down_a4lc(struct generic_pm_domain *genpd) +static bool sh7372_power_down_forbidden(struct dev_pm_domain *domain) { - /* only power down A4LC if A3RV is off */ - if (!(__raw_readl(PSTR) & (1 << sh7372_a3rv.bit_shift))) - return pd_power_down(genpd); - - return -EBUSY; + return false; } -static bool pd_active_wakeup(struct device *dev) -{ - return true; -} +struct dev_power_governor sh7372_always_on_gov = { + .power_down_ok = sh7372_power_down_forbidden, +}; void sh7372_init_pm_domain(struct sh7372_pm_domain *sh7372_pd) { struct generic_pm_domain *genpd = &sh7372_pd->genpd; - pm_genpd_init(genpd, NULL, false); + pm_genpd_init(genpd, sh7372_pd->gov, false); genpd->stop_device = pm_clk_suspend; genpd->start_device = pm_clk_resume; + genpd->dev_irq_safe = true; genpd->active_wakeup = pd_active_wakeup; - - if (sh7372_pd == &sh7372_a4lc) { - genpd->power_off = pd_power_down_a4lc; - genpd->power_on = pd_power_up; - } else if (sh7372_pd == &sh7372_a3rv) { - genpd->power_off = pd_power_down_a3rv; - genpd->power_on = pd_power_up_a3rv; - } else { - genpd->power_off = pd_power_down; - genpd->power_on = pd_power_up; - } + genpd->power_off = pd_power_down; + genpd->power_on = pd_power_up; genpd->power_on(&sh7372_pd->genpd); } @@ -152,11 +182,15 @@ void sh7372_add_device_to_domain(struct sh7372_pm_domain *sh7372_pd, { struct device *dev = &pdev->dev; - if (!dev->power.subsys_data) { - pm_clk_init(dev); - pm_clk_add(dev, NULL); - } pm_genpd_add_device(&sh7372_pd->genpd, dev); + if (pm_clk_no_clocks(dev)) + pm_clk_add(dev, NULL); +} + +void sh7372_pm_add_subdomain(struct sh7372_pm_domain *sh7372_pd, + struct sh7372_pm_domain *sh7372_sd) +{ + pm_genpd_add_subdomain(&sh7372_pd->genpd, &sh7372_sd->genpd); } struct sh7372_pm_domain sh7372_a4lc = { @@ -171,6 +205,14 @@ struct sh7372_pm_domain sh7372_d4 = { .bit_shift = 3, }; +struct sh7372_pm_domain sh7372_a4r = { + .bit_shift = 5, + .gov = &sh7372_always_on_gov, + .suspend = sh7372_a4r_suspend, + .resume = sh7372_intcs_resume, + .stay_on = true, +}; + struct sh7372_pm_domain sh7372_a3rv = { .bit_shift = 6, }; @@ -179,39 +221,187 @@ struct sh7372_pm_domain sh7372_a3ri = { .bit_shift = 8, }; +struct sh7372_pm_domain sh7372_a3sp = { + .bit_shift = 11, + .gov = &sh7372_always_on_gov, + .no_debug = true, +}; + struct sh7372_pm_domain sh7372_a3sg = { .bit_shift = 13, }; #endif /* CONFIG_PM */ +#if defined(CONFIG_SUSPEND) || defined(CONFIG_CPU_IDLE) +static int sh7372_do_idle_core_standby(unsigned long unused) +{ + cpu_do_idle(); /* WFI when SYSTBCR == 0x10 -> Core Standby */ + return 0; +} + static void sh7372_enter_core_standby(void) { - void __iomem *smfram = (void __iomem *)SMFRAM; + /* set reset vector, translate 4k */ + __raw_writel(__pa(sh7372_resume_core_standby_a3sm), SBAR); + __raw_writel(0, APARMBAREA); - __raw_writel(0, APARMBAREA); /* translate 4k */ - __raw_writel(__pa(sh7372_cpu_resume), SBAR); /* set reset vector */ - __raw_writel(0x10, SYSTBCR); /* enable core standby */ + /* enter sleep mode with SYSTBCR to 0x10 */ + __raw_writel(0x10, SYSTBCR); + cpu_suspend(0, sh7372_do_idle_core_standby); + __raw_writel(0, SYSTBCR); - __raw_writel(0, smfram + 0x3c); /* clear page table address */ + /* disable reset vector translation */ + __raw_writel(0, SBAR); +} +#endif + +#ifdef CONFIG_SUSPEND +static void sh7372_enter_a3sm_common(int pllc0_on) +{ + /* set reset vector, translate 4k */ + __raw_writel(__pa(sh7372_resume_core_standby_a3sm), SBAR); + __raw_writel(0, APARMBAREA); + + if (pllc0_on) + __raw_writel(0, PLLC01STPCR); + else + __raw_writel(1 << 28, PLLC01STPCR); + + __raw_writel(0, PDNSEL); /* power-down A3SM only, not A4S */ + __raw_readl(WUPSFAC); /* read wakeup int. factor before sleep */ + cpu_suspend(0, sh7372_do_idle_a3sm); + __raw_readl(WUPSFAC); /* read wakeup int. factor after wakeup */ + + /* disable reset vector translation */ + __raw_writel(0, SBAR); +} + +static int sh7372_a3sm_valid(unsigned long *mskp, unsigned long *msk2p) +{ + unsigned long mstpsr0, mstpsr1, mstpsr2, mstpsr3, mstpsr4; + unsigned long msk, msk2; + + /* check active clocks to determine potential wakeup sources */ + + mstpsr0 = __raw_readl(MSTPSR0); + if ((mstpsr0 & 0x00000003) != 0x00000003) { + pr_debug("sh7372 mstpsr0 0x%08lx\n", mstpsr0); + return 0; + } + + mstpsr1 = __raw_readl(MSTPSR1); + if ((mstpsr1 & 0xff079b7f) != 0xff079b7f) { + pr_debug("sh7372 mstpsr1 0x%08lx\n", mstpsr1); + return 0; + } - sh7372_cpu_suspend(); - cpu_init(); + mstpsr2 = __raw_readl(MSTPSR2); + if ((mstpsr2 & 0x000741ff) != 0x000741ff) { + pr_debug("sh7372 mstpsr2 0x%08lx\n", mstpsr2); + return 0; + } - /* if page table address is non-NULL then we have been powered down */ - if (__raw_readl(smfram + 0x3c)) { - __raw_writel(__raw_readl(smfram + 0x40), - __va(__raw_readl(smfram + 0x3c))); + mstpsr3 = __raw_readl(MSTPSR3); + if ((mstpsr3 & 0x1a60f010) != 0x1a60f010) { + pr_debug("sh7372 mstpsr3 0x%08lx\n", mstpsr3); + return 0; + } - flush_tlb_all(); - set_cr(__raw_readl(smfram + 0x38)); + mstpsr4 = __raw_readl(MSTPSR4); + if ((mstpsr4 & 0x00008cf0) != 0x00008cf0) { + pr_debug("sh7372 mstpsr4 0x%08lx\n", mstpsr4); + return 0; } - __raw_writel(0, SYSTBCR); /* disable core standby */ - __raw_writel(0, SBAR); /* disable reset vector translation */ + msk = 0; + msk2 = 0; + + /* make bitmaps of limited number of wakeup sources */ + + if ((mstpsr2 & (1 << 23)) == 0) /* SPU2 */ + msk |= 1 << 31; + + if ((mstpsr2 & (1 << 12)) == 0) /* MFI_MFIM */ + msk |= 1 << 21; + + if ((mstpsr4 & (1 << 3)) == 0) /* KEYSC */ + msk |= 1 << 2; + + if ((mstpsr1 & (1 << 24)) == 0) /* CMT0 */ + msk |= 1 << 1; + + if ((mstpsr3 & (1 << 29)) == 0) /* CMT1 */ + msk |= 1 << 1; + + if ((mstpsr4 & (1 << 0)) == 0) /* CMT2 */ + msk |= 1 << 1; + + if ((mstpsr2 & (1 << 13)) == 0) /* MFI_MFIS */ + msk2 |= 1 << 17; + + *mskp = msk; + *msk2p = msk2; + + return 1; +} + +static void sh7372_icr_to_irqcr(unsigned long icr, u16 *irqcr1p, u16 *irqcr2p) +{ + u16 tmp, irqcr1, irqcr2; + int k; + + irqcr1 = 0; + irqcr2 = 0; + + /* convert INTCA ICR register layout to SYSC IRQCR+IRQCR2 */ + for (k = 0; k <= 7; k++) { + tmp = (icr >> ((7 - k) * 4)) & 0xf; + irqcr1 |= (tmp & 0x03) << (k * 2); + irqcr2 |= (tmp >> 2) << (k * 2); + } + + *irqcr1p = irqcr1; + *irqcr2p = irqcr2; +} + +static void sh7372_setup_a3sm(unsigned long msk, unsigned long msk2) +{ + u16 irqcrx_low, irqcrx_high, irqcry_low, irqcry_high; + unsigned long tmp; + + /* read IRQ0A -> IRQ15A mask */ + tmp = bitrev8(__raw_readb(INTMSK00A)); + tmp |= bitrev8(__raw_readb(INTMSK10A)) << 8; + + /* setup WUPSMSK from clocks and external IRQ mask */ + msk = (~msk & 0xc030000f) | (tmp << 4); + __raw_writel(msk, WUPSMSK); + + /* propage level/edge trigger for external IRQ 0->15 */ + sh7372_icr_to_irqcr(__raw_readl(ICR1A), &irqcrx_low, &irqcry_low); + sh7372_icr_to_irqcr(__raw_readl(ICR2A), &irqcrx_high, &irqcry_high); + __raw_writel((irqcrx_high << 16) | irqcrx_low, IRQCR); + __raw_writel((irqcry_high << 16) | irqcry_low, IRQCR2); + + /* read IRQ16A -> IRQ31A mask */ + tmp = bitrev8(__raw_readb(INTMSK20A)); + tmp |= bitrev8(__raw_readb(INTMSK30A)) << 8; + + /* setup WUPSMSK2 from clocks and external IRQ mask */ + msk2 = (~msk2 & 0x00030000) | tmp; + __raw_writel(msk2, WUPSMSK2); + + /* propage level/edge trigger for external IRQ 16->31 */ + sh7372_icr_to_irqcr(__raw_readl(ICR3A), &irqcrx_low, &irqcry_low); + sh7372_icr_to_irqcr(__raw_readl(ICR4A), &irqcrx_high, &irqcry_high); + __raw_writel((irqcrx_high << 16) | irqcrx_low, IRQCR3); + __raw_writel((irqcry_high << 16) | irqcry_low, IRQCR4); } +#endif #ifdef CONFIG_CPU_IDLE + static void sh7372_cpuidle_setup(struct cpuidle_device *dev) { struct cpuidle_state *state; @@ -239,9 +429,25 @@ static void sh7372_cpuidle_init(void) {} #endif #ifdef CONFIG_SUSPEND + static int sh7372_enter_suspend(suspend_state_t suspend_state) { - sh7372_enter_core_standby(); + unsigned long msk, msk2; + + /* check active clocks to determine potential wakeup sources */ + if (sh7372_a3sm_valid(&msk, &msk2)) { + + /* convert INTC mask and sense to SYSC mask and sense */ + sh7372_setup_a3sm(msk, msk2); + + /* enter A3SM sleep with PLLC0 off */ + pr_debug("entering A3SM\n"); + sh7372_enter_a3sm_common(0); + } else { + /* default to Core Standby that supports all wakeup sources */ + pr_debug("entering Core Standby\n"); + sh7372_enter_core_standby(); + } return 0; } @@ -253,9 +459,6 @@ static void sh7372_suspend_init(void) static void sh7372_suspend_init(void) {} #endif -#define DBGREG1 0xe6100020 -#define DBGREG9 0xe6100040 - void __init sh7372_pm_init(void) { /* enable DBG hardware block to kick SYSC */ @@ -263,6 +466,9 @@ void __init sh7372_pm_init(void) __raw_writel(0x0000a501, DBGREG9); __raw_writel(0x00000000, DBGREG1); + /* do not convert A3SM, A3SP, A3SG, A4R power down into A4S */ + __raw_writel(0, PDNSEL); + sh7372_suspend_init(); sh7372_cpuidle_init(); } diff --git a/arch/arm/mach-shmobile/pm_runtime.c b/arch/arm/mach-shmobile/pm_runtime.c index 6ec454e1e063..bd5c6a3b8c55 100644 --- a/arch/arm/mach-shmobile/pm_runtime.c +++ b/arch/arm/mach-shmobile/pm_runtime.c @@ -15,6 +15,7 @@ #include <linux/io.h> #include <linux/pm_runtime.h> #include <linux/pm_domain.h> +#include <linux/pm_clock.h> #include <linux/platform_device.h> #include <linux/clk.h> #include <linux/sh_clk.h> diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c index 2d9b1b1a2538..2380389e6ac5 100644 --- a/arch/arm/mach-shmobile/setup-sh7372.c +++ b/arch/arm/mach-shmobile/setup-sh7372.c @@ -30,6 +30,7 @@ #include <linux/sh_dma.h> #include <linux/sh_intc.h> #include <linux/sh_timer.h> +#include <linux/pm_domain.h> #include <mach/hardware.h> #include <mach/sh7372.h> #include <asm/mach-types.h> @@ -990,9 +991,14 @@ void __init sh7372_add_standard_devices(void) sh7372_init_pm_domain(&sh7372_a4lc); sh7372_init_pm_domain(&sh7372_a4mp); sh7372_init_pm_domain(&sh7372_d4); + sh7372_init_pm_domain(&sh7372_a4r); sh7372_init_pm_domain(&sh7372_a3rv); sh7372_init_pm_domain(&sh7372_a3ri); sh7372_init_pm_domain(&sh7372_a3sg); + sh7372_init_pm_domain(&sh7372_a3sp); + + sh7372_pm_add_subdomain(&sh7372_a4lc, &sh7372_a3rv); + sh7372_pm_add_subdomain(&sh7372_a4r, &sh7372_a4lc); platform_add_devices(sh7372_early_devices, ARRAY_SIZE(sh7372_early_devices)); @@ -1003,6 +1009,25 @@ void __init sh7372_add_standard_devices(void) sh7372_add_device_to_domain(&sh7372_a3rv, &vpu_device); sh7372_add_device_to_domain(&sh7372_a4mp, &spu0_device); sh7372_add_device_to_domain(&sh7372_a4mp, &spu1_device); + sh7372_add_device_to_domain(&sh7372_a3sp, &scif0_device); + sh7372_add_device_to_domain(&sh7372_a3sp, &scif1_device); + sh7372_add_device_to_domain(&sh7372_a3sp, &scif2_device); + sh7372_add_device_to_domain(&sh7372_a3sp, &scif3_device); + sh7372_add_device_to_domain(&sh7372_a3sp, &scif4_device); + sh7372_add_device_to_domain(&sh7372_a3sp, &scif5_device); + sh7372_add_device_to_domain(&sh7372_a3sp, &scif6_device); + sh7372_add_device_to_domain(&sh7372_a3sp, &iic1_device); + sh7372_add_device_to_domain(&sh7372_a3sp, &dma0_device); + sh7372_add_device_to_domain(&sh7372_a3sp, &dma1_device); + sh7372_add_device_to_domain(&sh7372_a3sp, &dma2_device); + sh7372_add_device_to_domain(&sh7372_a3sp, &usb_dma0_device); + sh7372_add_device_to_domain(&sh7372_a3sp, &usb_dma1_device); + sh7372_add_device_to_domain(&sh7372_a4r, &iic0_device); + sh7372_add_device_to_domain(&sh7372_a4r, &veu0_device); + sh7372_add_device_to_domain(&sh7372_a4r, &veu1_device); + sh7372_add_device_to_domain(&sh7372_a4r, &veu2_device); + sh7372_add_device_to_domain(&sh7372_a4r, &veu3_device); + sh7372_add_device_to_domain(&sh7372_a4r, &jpu_device); } void __init sh7372_add_early_devices(void) diff --git a/arch/arm/mach-shmobile/sleep-sh7372.S b/arch/arm/mach-shmobile/sleep-sh7372.S index d37d3ca4d18f..f3ab3c5810ea 100644 --- a/arch/arm/mach-shmobile/sleep-sh7372.S +++ b/arch/arm/mach-shmobile/sleep-sh7372.S @@ -30,58 +30,20 @@ */ #include <linux/linkage.h> +#include <linux/init.h> +#include <asm/memory.h> #include <asm/assembler.h> -#define SMFRAM 0xe6a70000 - - .align -kernel_flush: - .word v7_flush_dcache_all - - .align 3 -ENTRY(sh7372_cpu_suspend) - stmfd sp!, {r0-r12, lr} @ save registers on stack - - ldr r8, =SMFRAM - - mov r4, sp @ Store sp - mrs r5, spsr @ Store spsr - mov r6, lr @ Store lr - stmia r8!, {r4-r6} - - mrc p15, 0, r4, c1, c0, 2 @ Coprocessor access control register - mrc p15, 0, r5, c2, c0, 0 @ TTBR0 - mrc p15, 0, r6, c2, c0, 1 @ TTBR1 - mrc p15, 0, r7, c2, c0, 2 @ TTBCR - stmia r8!, {r4-r7} - - mrc p15, 0, r4, c3, c0, 0 @ Domain access Control Register - mrc p15, 0, r5, c10, c2, 0 @ PRRR - mrc p15, 0, r6, c10, c2, 1 @ NMRR - stmia r8!,{r4-r6} - - mrc p15, 0, r4, c13, c0, 1 @ Context ID - mrc p15, 0, r5, c13, c0, 2 @ User r/w thread and process ID - mrc p15, 0, r6, c12, c0, 0 @ Secure or NS vector base address - mrs r7, cpsr @ Store current cpsr - stmia r8!, {r4-r7} - - mrc p15, 0, r4, c1, c0, 0 @ save control register - stmia r8!, {r4} - - /* - * jump out to kernel flush routine - * - reuse that code is better - * - it executes in a cached space so is faster than refetch per-block - * - should be faster and will change with kernel - * - 'might' have to copy address, load and jump to it - * Flush all data from the L1 data cache before disabling - * SCTLR.C bit. - */ - ldr r1, kernel_flush - mov lr, pc - bx r1 +#if defined(CONFIG_SUSPEND) || defined(CONFIG_CPU_IDLE) + .align 12 + .text + .global sh7372_resume_core_standby_a3sm +sh7372_resume_core_standby_a3sm: + ldr pc, 1f +1: .long cpu_resume - PAGE_OFFSET + PLAT_PHYS_OFFSET + .global sh7372_do_idle_a3sm +sh7372_do_idle_a3sm: /* * Clear the SCTLR.C bit to prevent further data cache * allocation. Clearing SCTLR.C would make all the data accesses @@ -92,10 +54,13 @@ ENTRY(sh7372_cpu_suspend) mcr p15, 0, r0, c1, c0, 0 isb + /* disable L2 cache in the aux control register */ + mrc p15, 0, r10, c1, c0, 1 + bic r10, r10, #2 + mcr p15, 0, r10, c1, c0, 1 + /* - * Invalidate L1 data cache. Even though only invalidate is - * necessary exported flush API is used here. Doing clean - * on already clean cache would be almost NOP. + * Invalidate data cache again. */ ldr r1, kernel_flush blx r1 @@ -115,146 +80,16 @@ ENTRY(sh7372_cpu_suspend) dsb dmb -/* - * =================================== - * == WFI instruction => Enter idle == - * =================================== - */ - wfi @ wait for interrupt - -/* - * =================================== - * == Resume path for non-OFF modes == - * =================================== - */ - mrc p15, 0, r0, c1, c0, 0 - tst r0, #(1 << 2) @ Check C bit enabled? - orreq r0, r0, #(1 << 2) @ Enable the C bit if cleared - mcreq p15, 0, r0, c1, c0, 0 - isb - -/* - * =================================== - * == Exit point from non-OFF modes == - * =================================== - */ - ldmfd sp!, {r0-r12, pc} @ restore regs and return +#define SPDCR 0xe6180008 +#define A3SM (1 << 12) - .pool + /* A3SM power down */ + ldr r0, =SPDCR + ldr r1, =A3SM + str r1, [r0] +1: + b 1b - .align 12 - .text - .global sh7372_cpu_resume -sh7372_cpu_resume: - - mov r1, #0 - /* - * Invalidate all instruction caches to PoU - * and flush branch target cache - */ - mcr p15, 0, r1, c7, c5, 0 - - ldr r3, =SMFRAM - - ldmia r3!, {r4-r6} - mov sp, r4 @ Restore sp - msr spsr_cxsf, r5 @ Restore spsr - mov lr, r6 @ Restore lr - - ldmia r3!, {r4-r7} - mcr p15, 0, r4, c1, c0, 2 @ Coprocessor access Control Register - mcr p15, 0, r5, c2, c0, 0 @ TTBR0 - mcr p15, 0, r6, c2, c0, 1 @ TTBR1 - mcr p15, 0, r7, c2, c0, 2 @ TTBCR - - ldmia r3!,{r4-r6} - mcr p15, 0, r4, c3, c0, 0 @ Domain access Control Register - mcr p15, 0, r5, c10, c2, 0 @ PRRR - mcr p15, 0, r6, c10, c2, 1 @ NMRR - - ldmia r3!,{r4-r7} - mcr p15, 0, r4, c13, c0, 1 @ Context ID - mcr p15, 0, r5, c13, c0, 2 @ User r/w thread and process ID - mrc p15, 0, r6, c12, c0, 0 @ Secure or NS vector base address - msr cpsr, r7 @ store cpsr - - /* Starting to enable MMU here */ - mrc p15, 0, r7, c2, c0, 2 @ Read TTBRControl - /* Extract N (0:2) bits and decide whether to use TTBR0 or TTBR1 */ - and r7, #0x7 - cmp r7, #0x0 - beq usettbr0 -ttbr_error: - /* - * More work needs to be done to support N[0:2] value other than 0 - * So looping here so that the error can be detected - */ - b ttbr_error - - .align -cache_pred_disable_mask: - .word 0xFFFFE7FB -ttbrbit_mask: - .word 0xFFFFC000 -table_index_mask: - .word 0xFFF00000 -table_entry: - .word 0x00000C02 -usettbr0: - - mrc p15, 0, r2, c2, c0, 0 - ldr r5, ttbrbit_mask - and r2, r5 - mov r4, pc - ldr r5, table_index_mask - and r4, r5 @ r4 = 31 to 20 bits of pc - /* Extract the value to be written to table entry */ - ldr r6, table_entry - /* r6 has the value to be written to table entry */ - add r6, r6, r4 - /* Getting the address of table entry to modify */ - lsr r4, #18 - /* r2 has the location which needs to be modified */ - add r2, r4 - ldr r4, [r2] - str r6, [r2] /* modify the table entry */ - - mov r7, r6 - mov r5, r2 - mov r6, r4 - /* r5 = original page table address */ - /* r6 = original page table data */ - - mov r0, #0 - mcr p15, 0, r0, c7, c5, 4 @ Flush prefetch buffer - mcr p15, 0, r0, c7, c5, 6 @ Invalidate branch predictor array - mcr p15, 0, r0, c8, c5, 0 @ Invalidate instruction TLB - mcr p15, 0, r0, c8, c6, 0 @ Invalidate data TLB - - /* - * Restore control register. This enables the MMU. - * The caches and prediction are not enabled here, they - * will be enabled after restoring the MMU table entry. - */ - ldmia r3!, {r4} - stmia r3!, {r5} /* save original page table address */ - stmia r3!, {r6} /* save original page table data */ - stmia r3!, {r7} /* save modified page table data */ - - ldr r2, cache_pred_disable_mask - and r4, r2 - mcr p15, 0, r4, c1, c0, 0 - dsb - isb - - ldr r0, =restoremmu_on - bx r0 - -/* - * ============================== - * == Exit point from OFF mode == - * ============================== - */ -restoremmu_on: - - ldmfd sp!, {r0-r12, pc} @ restore regs and return +kernel_flush: + .word v7_flush_dcache_all +#endif diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c index 3ffdbc92ba82..be1ade76ccc8 100644 --- a/arch/arm/mach-shmobile/smp-sh73a0.c +++ b/arch/arm/mach-shmobile/smp-sh73a0.c @@ -74,6 +74,8 @@ void __cpuinit sh73a0_secondary_init(unsigned int cpu) int __cpuinit sh73a0_boot_secondary(unsigned int cpu) { + cpu = cpu_logical_map(cpu); + /* enable cache coherency */ modify_scu_cpu_psr(0, 3 << (cpu * 8)); @@ -87,6 +89,8 @@ int __cpuinit sh73a0_boot_secondary(unsigned int cpu) void __init sh73a0_smp_prepare_cpus(void) { + int cpu = cpu_logical_map(0); + scu_enable(scu_base_addr()); /* Map the reset vector (in headsmp.S) */ @@ -94,5 +98,5 @@ void __init sh73a0_smp_prepare_cpus(void) __raw_writel(__pa(shmobile_secondary_vector), __io(SBAR)); /* enable cache coherency on CPU0 */ - modify_scu_cpu_psr(0, 3 << (0 * 8)); + modify_scu_cpu_psr(0, 3 << (cpu * 8)); } |