diff options
Diffstat (limited to 'arch/arm/mach-s5pv210/clock.c')
| -rw-r--r-- | arch/arm/mach-s5pv210/clock.c | 207 |
1 files changed, 195 insertions, 12 deletions
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c index d562670e1b0b..019c3a69b0e4 100644 --- a/arch/arm/mach-s5pv210/clock.c +++ b/arch/arm/mach-s5pv210/clock.c @@ -31,6 +31,8 @@ #include <plat/clock-clksrc.h> #include <plat/s5pv210.h> +static unsigned long xtal; + static struct clksrc_clk clk_mout_apll = { .clk = { .name = "mout_apll", @@ -259,6 +261,36 @@ static struct clksrc_clk clk_sclk_vpll = { .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 }, }; +static struct clk *clkset_moutdmc0src_list[] = { + [0] = &clk_sclk_a2m.clk, + [1] = &clk_mout_mpll.clk, + [2] = NULL, + [3] = NULL, +}; + +static struct clksrc_sources clkset_moutdmc0src = { + .sources = clkset_moutdmc0src_list, + .nr_sources = ARRAY_SIZE(clkset_moutdmc0src_list), +}; + +static struct clksrc_clk clk_mout_dmc0 = { + .clk = { + .name = "mout_dmc0", + .id = -1, + }, + .sources = &clkset_moutdmc0src, + .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 }, +}; + +static struct clksrc_clk clk_sclk_dmc0 = { + .clk = { + .name = "sclk_dmc0", + .id = -1, + .parent = &clk_mout_dmc0.clk, + }, + .reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 }, +}; + static unsigned long s5pv210_clk_imem_get_rate(struct clk *clk) { return clk_get_rate(clk->parent) / 2; @@ -268,8 +300,29 @@ static struct clk_ops clk_hclk_imem_ops = { .get_rate = s5pv210_clk_imem_get_rate, }; +static unsigned long s5pv210_clk_fout_apll_get_rate(struct clk *clk) +{ + return s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508); +} + +static struct clk_ops clk_fout_apll_ops = { + .get_rate = s5pv210_clk_fout_apll_get_rate, +}; + static struct clk init_clocks_disable[] = { { + .name = "pdma", + .id = 0, + .parent = &clk_hclk_psys.clk, + .enable = s5pv210_clk_ip0_ctrl, + .ctrlbit = (1 << 3), + }, { + .name = "pdma", + .id = 1, + .parent = &clk_hclk_psys.clk, + .enable = s5pv210_clk_ip0_ctrl, + .ctrlbit = (1 << 4), + }, { .name = "rot", .id = -1, .parent = &clk_hclk_dsys.clk, @@ -431,6 +484,12 @@ static struct clk init_clocks_disable[] = { .parent = &clk_p, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1 << 6), + }, { + .name = "spdif", + .id = -1, + .parent = &clk_p, + .enable = s5pv210_clk_ip3_ctrl, + .ctrlbit = (1 << 0), }, }; @@ -660,6 +719,53 @@ static struct clksrc_sources clkset_sclk_spdif = { .nr_sources = ARRAY_SIZE(clkset_sclk_spdif_list), }; +static int s5pv210_spdif_set_rate(struct clk *clk, unsigned long rate) +{ + struct clk *pclk; + int ret; + + pclk = clk_get_parent(clk); + if (IS_ERR(pclk)) + return -EINVAL; + + ret = pclk->ops->set_rate(pclk, rate); + clk_put(pclk); + + return ret; +} + +static unsigned long s5pv210_spdif_get_rate(struct clk *clk) +{ + struct clk *pclk; + int rate; + + pclk = clk_get_parent(clk); + if (IS_ERR(pclk)) + return -EINVAL; + + rate = pclk->ops->get_rate(clk); + clk_put(pclk); + + return rate; +} + +static struct clk_ops s5pv210_sclk_spdif_ops = { + .set_rate = s5pv210_spdif_set_rate, + .get_rate = s5pv210_spdif_get_rate, +}; + +static struct clksrc_clk clk_sclk_spdif = { + .clk = { + .name = "sclk_spdif", + .id = -1, + .enable = s5pv210_clk_mask0_ctrl, + .ctrlbit = (1 << 27), + .ops = &s5pv210_sclk_spdif_ops, + }, + .sources = &clkset_sclk_spdif, + .reg_src = { .reg = S5P_CLK_SRC6, .shift = 12, .size = 2 }, +}; + static struct clk *clkset_group2_list[] = { [0] = &clk_ext_xtal_mux, [1] = &clk_xusbxti, @@ -744,15 +850,6 @@ static struct clksrc_clk clksrcs[] = { .sources = &clkset_sclk_mixer, .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 1 }, }, { - .clk = { - .name = "sclk_spdif", - .id = -1, - .enable = s5pv210_clk_mask0_ctrl, - .ctrlbit = (1 << 27), - }, - .sources = &clkset_sclk_spdif, - .reg_src = { .reg = S5P_CLK_SRC6, .shift = 12, .size = 2 }, - }, { .clk = { .name = "sclk_fimc", .id = 0, @@ -953,12 +1050,93 @@ static struct clksrc_clk *sysclks[] = { &clk_sclk_dac, &clk_sclk_pixel, &clk_sclk_hdmi, + &clk_mout_dmc0, + &clk_sclk_dmc0, + &clk_sclk_audio0, + &clk_sclk_audio1, + &clk_sclk_audio2, + &clk_sclk_spdif, +}; + +static u32 epll_div[][6] = { + { 48000000, 0, 48, 3, 3, 0 }, + { 96000000, 0, 48, 3, 2, 0 }, + { 144000000, 1, 72, 3, 2, 0 }, + { 192000000, 0, 48, 3, 1, 0 }, + { 288000000, 1, 72, 3, 1, 0 }, + { 32750000, 1, 65, 3, 4, 35127 }, + { 32768000, 1, 65, 3, 4, 35127 }, + { 45158400, 0, 45, 3, 3, 10355 }, + { 45000000, 0, 45, 3, 3, 10355 }, + { 45158000, 0, 45, 3, 3, 10355 }, + { 49125000, 0, 49, 3, 3, 9961 }, + { 49152000, 0, 49, 3, 3, 9961 }, + { 67737600, 1, 67, 3, 3, 48366 }, + { 67738000, 1, 67, 3, 3, 48366 }, + { 73800000, 1, 73, 3, 3, 47710 }, + { 73728000, 1, 73, 3, 3, 47710 }, + { 36000000, 1, 32, 3, 4, 0 }, + { 60000000, 1, 60, 3, 3, 0 }, + { 72000000, 1, 72, 3, 3, 0 }, + { 80000000, 1, 80, 3, 3, 0 }, + { 84000000, 0, 42, 3, 2, 0 }, + { 50000000, 0, 50, 3, 3, 0 }, +}; + +static int s5pv210_epll_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned int epll_con, epll_con_k; + unsigned int i; + + /* Return if nothing changed */ + if (clk->rate == rate) + return 0; + + epll_con = __raw_readl(S5P_EPLL_CON); + epll_con_k = __raw_readl(S5P_EPLL_CON1); + + epll_con_k &= ~PLL46XX_KDIV_MASK; + epll_con &= ~(1 << 27 | + PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT | + PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | + PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT); + + for (i = 0; i < ARRAY_SIZE(epll_div); i++) { + if (epll_div[i][0] == rate) { + epll_con_k |= epll_div[i][5] << 0; + epll_con |= (epll_div[i][1] << 27 | + epll_div[i][2] << PLL46XX_MDIV_SHIFT | + epll_div[i][3] << PLL46XX_PDIV_SHIFT | + epll_div[i][4] << PLL46XX_SDIV_SHIFT); + break; + } + } + + if (i == ARRAY_SIZE(epll_div)) { + printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", + __func__); + return -EINVAL; + } + + __raw_writel(epll_con, S5P_EPLL_CON); + __raw_writel(epll_con_k, S5P_EPLL_CON1); + + printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n", + clk->rate, rate); + + clk->rate = rate; + + return 0; +} + +static struct clk_ops s5pv210_epll_ops = { + .set_rate = s5pv210_epll_set_rate, + .get_rate = s5p_epll_get_rate, }; void __init_or_cpufreq s5pv210_setup_clocks(void) { struct clk *xtal_clk; - unsigned long xtal; unsigned long vpllsrc; unsigned long armclk; unsigned long hclk_msys; @@ -974,6 +1152,10 @@ void __init_or_cpufreq s5pv210_setup_clocks(void) unsigned int ptr; u32 clkdiv0, clkdiv1; + /* Set functions for clk_fout_epll */ + clk_fout_epll.enable = s5p_epll_enable; + clk_fout_epll.ops = &s5pv210_epll_ops; + printk(KERN_DEBUG "%s: registering clocks\n", __func__); clkdiv0 = __raw_readl(S5P_CLK_DIV0); @@ -992,11 +1174,12 @@ void __init_or_cpufreq s5pv210_setup_clocks(void) apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508); mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502); - epll = s5p_get_pll45xx(xtal, __raw_readl(S5P_EPLL_CON), pll_4500); + epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON), + __raw_readl(S5P_EPLL_CON1), pll_4600); vpllsrc = clk_get_rate(&clk_vpllsrc.clk); vpll = s5p_get_pll45xx(vpllsrc, __raw_readl(S5P_VPLL_CON), pll_4502); - clk_fout_apll.rate = apll; + clk_fout_apll.ops = &clk_fout_apll_ops; clk_fout_mpll.rate = mpll; clk_fout_epll.rate = epll; clk_fout_vpll.rate = vpll; |