diff options
Diffstat (limited to 'arch/arm/mach-orion5x')
40 files changed, 1902 insertions, 83 deletions
diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig index ddcd41b15d17..f59a8d0e0824 100644 --- a/arch/arm/mach-orion5x/Kconfig +++ b/arch/arm/mach-orion5x/Kconfig @@ -36,6 +36,12 @@ config MACH_TS209 Say 'Y' here if you want your kernel to support the QNAP TS-109/TS-209 platform. +config MACH_TERASTATION_PRO2 + bool "Buffalo Terastation Pro II/Live" + help + Say 'Y' here if you want your kernel to support the + Buffalo Terastation Pro II/Live platform. + config MACH_LINKSTATION_PRO bool "Buffalo Linkstation Pro/Live" select I2C_BOARDINFO @@ -44,6 +50,13 @@ config MACH_LINKSTATION_PRO Buffalo Linkstation Pro/Live platform. Both v1 and v2 devices are supported. +config MACH_LINKSTATION_MINI + bool "Buffalo Linkstation Mini" + select I2C_BOARDINFO + help + Say 'Y' here if you want your kernel to support the + Buffalo Linkstation Mini platform. + config MACH_TS409 bool "QNAP TS-409" help @@ -68,6 +81,13 @@ config MACH_MV2120 Say 'Y' here if you want your kernel to support the HP Media Vault mv2120 or mv5100. +config MACH_EDMINI_V2 + bool "LaCie Ethernet Disk mini V2" + select I2C_BOARDINFO + help + Say 'Y' here if you want your kernel to support the + LaCie Ethernet Disk mini V2. + config MACH_MSS2 bool "Maxtor Shared Storage II" help @@ -92,6 +112,12 @@ config MACH_RD88F5181L_FXO Say 'Y' here if you want your kernel to support the Marvell Orion-VoIP FXO (88F5181L) RD. +config MACH_RD88F6183AP_GE + bool "Marvell Orion-1-90 AP GE Reference Design" + help + Say 'Y' here if you want your kernel to support the + Marvell Orion-1-90 (88F6183) AP GE RD. + endmenu endif diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile index fcc48a8864f3..3d4a1bc12355 100644 --- a/arch/arm/mach-orion5x/Makefile +++ b/arch/arm/mach-orion5x/Makefile @@ -2,14 +2,18 @@ obj-y += common.o addr-map.o pci.o gpio.o irq.o mpp.o obj-$(CONFIG_MACH_DB88F5281) += db88f5281-setup.o obj-$(CONFIG_MACH_RD88F5182) += rd88f5182-setup.o obj-$(CONFIG_MACH_KUROBOX_PRO) += kurobox_pro-setup.o +obj-$(CONFIG_MACH_TERASTATION_PRO2) += terastation_pro2-setup.o obj-$(CONFIG_MACH_LINKSTATION_PRO) += kurobox_pro-setup.o +obj-$(CONFIG_MACH_LINKSTATION_MINI) += lsmini-setup.o obj-$(CONFIG_MACH_DNS323) += dns323-setup.o obj-$(CONFIG_MACH_TS209) += ts209-setup.o tsx09-common.o obj-$(CONFIG_MACH_TS409) += ts409-setup.o tsx09-common.o obj-$(CONFIG_MACH_WRT350N_V2) += wrt350n-v2-setup.o obj-$(CONFIG_MACH_TS78XX) += ts78xx-setup.o obj-$(CONFIG_MACH_MV2120) += mv2120-setup.o +obj-$(CONFIG_MACH_EDMINI_V2) += edmini_v2-setup.o obj-$(CONFIG_MACH_MSS2) += mss2-setup.o obj-$(CONFIG_MACH_WNR854T) += wnr854t-setup.o obj-$(CONFIG_MACH_RD88F5181L_GE) += rd88f5181l-ge-setup.o obj-$(CONFIG_MACH_RD88F5181L_FXO) += rd88f5181l-fxo-setup.o +obj-$(CONFIG_MACH_RD88F6183AP_GE) += rd88f6183ap-ge-setup.o diff --git a/arch/arm/mach-orion5x/addr-map.c b/arch/arm/mach-orion5x/addr-map.c index 6f0dbda6c44c..719957e05d9e 100644 --- a/arch/arm/mach-orion5x/addr-map.c +++ b/arch/arm/mach-orion5x/addr-map.c @@ -13,8 +13,8 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/mbus.h> -#include <asm/hardware.h> -#include <asm/io.h> +#include <linux/io.h> +#include <mach/hardware.h> #include "common.h" /* diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c index faf4e3211918..9625ef5975d0 100644 --- a/arch/arm/mach-orion5x/common.c +++ b/arch/arm/mach-orion5x/common.c @@ -18,17 +18,19 @@ #include <linux/mv643xx_eth.h> #include <linux/mv643xx_i2c.h> #include <linux/ata_platform.h> +#include <linux/spi/orion_spi.h> #include <asm/page.h> #include <asm/setup.h> #include <asm/timex.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <asm/mach/time.h> -#include <asm/arch/hardware.h> -#include <asm/arch/orion5x.h> -#include <asm/plat-orion/ehci-orion.h> -#include <asm/plat-orion/orion_nand.h> -#include <asm/plat-orion/time.h> +#include <mach/hardware.h> +#include <mach/orion5x.h> +#include <plat/ehci-orion.h> +#include <plat/mv_xor.h> +#include <plat/orion_nand.h> +#include <plat/time.h> #include "common.h" /***************************************************************************** @@ -145,7 +147,6 @@ void __init orion5x_ehci1_init(void) ****************************************************************************/ struct mv643xx_eth_shared_platform_data orion5x_eth_shared_data = { .dram = &orion5x_mbus_dram_info, - .t_clk = ORION5X_TCLK, }; static struct resource orion5x_eth_shared_resources[] = { @@ -153,6 +154,10 @@ static struct resource orion5x_eth_shared_resources[] = { .start = ORION5X_ETH_PHYS_BASE + 0x2000, .end = ORION5X_ETH_PHYS_BASE + 0x3fff, .flags = IORESOURCE_MEM, + }, { + .start = IRQ_ORION5X_ETH_ERR, + .end = IRQ_ORION5X_ETH_ERR, + .flags = IORESOURCE_IRQ, }, }; @@ -162,7 +167,7 @@ static struct platform_device orion5x_eth_shared = { .dev = { .platform_data = &orion5x_eth_shared_data, }, - .num_resources = 1, + .num_resources = ARRAY_SIZE(orion5x_eth_shared_resources), .resource = orion5x_eth_shared_resources, }; @@ -267,6 +272,38 @@ void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data) /***************************************************************************** + * SPI + ****************************************************************************/ +static struct orion_spi_info orion5x_spi_plat_data = { + .tclk = 0, +}; + +static struct resource orion5x_spi_resources[] = { + { + .name = "spi base", + .start = SPI_PHYS_BASE, + .end = SPI_PHYS_BASE + 0x1f, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device orion5x_spi = { + .name = "orion_spi", + .id = 0, + .dev = { + .platform_data = &orion5x_spi_plat_data, + }, + .num_resources = ARRAY_SIZE(orion5x_spi_resources), + .resource = orion5x_spi_resources, +}; + +void __init orion5x_spi_init() +{ + platform_device_register(&orion5x_spi); +} + + +/***************************************************************************** * UART0 ****************************************************************************/ static struct plat_serial8250_port orion5x_uart0_data[] = { @@ -277,7 +314,7 @@ static struct plat_serial8250_port orion5x_uart0_data[] = { .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, .iotype = UPIO_MEM, .regshift = 2, - .uartclk = ORION5X_TCLK, + .uartclk = 0, }, { }, }; @@ -321,7 +358,7 @@ static struct plat_serial8250_port orion5x_uart1_data[] = { .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, .iotype = UPIO_MEM, .regshift = 2, - .uartclk = ORION5X_TCLK, + .uartclk = 0, }, { }, }; @@ -355,11 +392,123 @@ void __init orion5x_uart1_init(void) /***************************************************************************** + * XOR engine + ****************************************************************************/ +static struct resource orion5x_xor_shared_resources[] = { + { + .name = "xor low", + .start = ORION5X_XOR_PHYS_BASE, + .end = ORION5X_XOR_PHYS_BASE + 0xff, + .flags = IORESOURCE_MEM, + }, { + .name = "xor high", + .start = ORION5X_XOR_PHYS_BASE + 0x200, + .end = ORION5X_XOR_PHYS_BASE + 0x2ff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device orion5x_xor_shared = { + .name = MV_XOR_SHARED_NAME, + .id = 0, + .num_resources = ARRAY_SIZE(orion5x_xor_shared_resources), + .resource = orion5x_xor_shared_resources, +}; + +static u64 orion5x_xor_dmamask = DMA_32BIT_MASK; + +static struct resource orion5x_xor0_resources[] = { + [0] = { + .start = IRQ_ORION5X_XOR0, + .end = IRQ_ORION5X_XOR0, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct mv_xor_platform_data orion5x_xor0_data = { + .shared = &orion5x_xor_shared, + .hw_id = 0, + .pool_size = PAGE_SIZE, +}; + +static struct platform_device orion5x_xor0_channel = { + .name = MV_XOR_NAME, + .id = 0, + .num_resources = ARRAY_SIZE(orion5x_xor0_resources), + .resource = orion5x_xor0_resources, + .dev = { + .dma_mask = &orion5x_xor_dmamask, + .coherent_dma_mask = DMA_64BIT_MASK, + .platform_data = (void *)&orion5x_xor0_data, + }, +}; + +static struct resource orion5x_xor1_resources[] = { + [0] = { + .start = IRQ_ORION5X_XOR1, + .end = IRQ_ORION5X_XOR1, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct mv_xor_platform_data orion5x_xor1_data = { + .shared = &orion5x_xor_shared, + .hw_id = 1, + .pool_size = PAGE_SIZE, +}; + +static struct platform_device orion5x_xor1_channel = { + .name = MV_XOR_NAME, + .id = 1, + .num_resources = ARRAY_SIZE(orion5x_xor1_resources), + .resource = orion5x_xor1_resources, + .dev = { + .dma_mask = &orion5x_xor_dmamask, + .coherent_dma_mask = DMA_64BIT_MASK, + .platform_data = (void *)&orion5x_xor1_data, + }, +}; + +void __init orion5x_xor_init(void) +{ + platform_device_register(&orion5x_xor_shared); + + /* + * two engines can't do memset simultaneously, this limitation + * satisfied by removing memset support from one of the engines. + */ + dma_cap_set(DMA_MEMCPY, orion5x_xor0_data.cap_mask); + dma_cap_set(DMA_XOR, orion5x_xor0_data.cap_mask); + platform_device_register(&orion5x_xor0_channel); + + dma_cap_set(DMA_MEMCPY, orion5x_xor1_data.cap_mask); + dma_cap_set(DMA_MEMSET, orion5x_xor1_data.cap_mask); + dma_cap_set(DMA_XOR, orion5x_xor1_data.cap_mask); + platform_device_register(&orion5x_xor1_channel); +} + + +/***************************************************************************** * Time handling ****************************************************************************/ +int orion5x_tclk; + +int __init orion5x_find_tclk(void) +{ + u32 dev, rev; + + orion5x_pcie_id(&dev, &rev); + if (dev == MV88F6183_DEV_ID && + (readl(MPP_RESET_SAMPLE) & 0x00000200) == 0) + return 133333333; + + return 166666667; +} + static void orion5x_timer_init(void) { - orion_time_init(IRQ_ORION5X_BRIDGE, ORION5X_TCLK); + orion5x_tclk = orion5x_find_tclk(); + orion_time_init(IRQ_ORION5X_BRIDGE, orion5x_tclk); } struct sys_timer orion5x_timer = { @@ -382,6 +531,8 @@ static void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name) *dev_name = "MV88F5281-D2"; } else if (*rev == MV88F5281_REV_D1) { *dev_name = "MV88F5281-D1"; + } else if (*rev == MV88F5281_REV_D0) { + *dev_name = "MV88F5281-D0"; } else { *dev_name = "MV88F5281-Rev-Unsupported"; } @@ -399,6 +550,12 @@ static void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name) } else { *dev_name = "MV88F5181(L)-Rev-Unsupported"; } + } else if (*dev == MV88F6183_DEV_ID) { + if (*rev == MV88F6183_REV_B0) { + *dev_name = "MV88F6183-Rev-B0"; + } else { + *dev_name = "MV88F6183-Rev-Unsupported"; + } } else { *dev_name = "Device-Unknown"; } @@ -410,12 +567,26 @@ void __init orion5x_init(void) u32 dev, rev; orion5x_id(&dev, &rev, &dev_name); - printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, ORION5X_TCLK); + printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, orion5x_tclk); + + orion5x_eth_shared_data.t_clk = orion5x_tclk; + orion5x_spi_plat_data.tclk = orion5x_tclk; + orion5x_uart0_data[0].uartclk = orion5x_tclk; + orion5x_uart1_data[0].uartclk = orion5x_tclk; /* * Setup Orion address map */ orion5x_setup_cpu_mbus_bridge(); + + /* + * Don't issue "Wait for Interrupt" instruction if we are + * running on D0 5281 silicon. + */ + if (dev == MV88F5281_DEV_ID && rev == MV88F5281_REV_D0) { + printk(KERN_INFO "Orion: Applying 5281 D0 WFI workaround.\n"); + disable_hlt(); + } } /* diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h index f72cf0e77544..1f8b2da676a5 100644 --- a/arch/arm/mach-orion5x/common.h +++ b/arch/arm/mach-orion5x/common.h @@ -10,6 +10,7 @@ struct mv_sata_platform_data; void orion5x_map_io(void); void orion5x_init_irq(void); void orion5x_init(void); +extern int orion5x_tclk; extern struct sys_timer orion5x_timer; /* @@ -30,8 +31,10 @@ void orion5x_ehci1_init(void); void orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data); void orion5x_i2c_init(void); void orion5x_sata_init(struct mv_sata_platform_data *sata_data); +void orion5x_spi_init(void); void orion5x_uart0_init(void); void orion5x_uart1_init(void); +void orion5x_xor_init(void); /* * PCIe/PCI functions. @@ -40,6 +43,7 @@ struct pci_bus; struct pci_sys_data; void orion5x_pcie_id(u32 *dev, u32 *rev); +void orion5x_pci_disable(void); void orion5x_pci_set_cardbus_mode(void); int orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys); struct pci_bus *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys); diff --git a/arch/arm/mach-orion5x/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c index 88405e74e5e3..d318bea2af91 100644 --- a/arch/arm/mach-orion5x/db88f5281-setup.c +++ b/arch/arm/mach-orion5x/db88f5281-setup.c @@ -24,8 +24,8 @@ #include <asm/gpio.h> #include <asm/mach/arch.h> #include <asm/mach/pci.h> -#include <asm/arch/orion5x.h> -#include <asm/plat-orion/orion_nand.h> +#include <mach/orion5x.h> +#include <plat/orion_nand.h> #include "common.h" #include "mpp.h" @@ -213,7 +213,7 @@ void __init db88f5281_pci_preinit(void) pin = DB88F5281_PCI_SLOT0_IRQ_PIN; if (gpio_request(pin, "PCI Int1") == 0) { if (gpio_direction_input(pin) == 0) { - set_irq_type(gpio_to_irq(pin), IRQT_LOW); + set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); } else { printk(KERN_ERR "db88f5281_pci_preinit faield to " "set_irq_type pin %d\n", pin); @@ -226,7 +226,7 @@ void __init db88f5281_pci_preinit(void) pin = DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN; if (gpio_request(pin, "PCI Int2") == 0) { if (gpio_direction_input(pin) == 0) { - set_irq_type(gpio_to_irq(pin), IRQT_LOW); + set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); } else { printk(KERN_ERR "db88f5281_pci_preinit faield " "to set_irq_type pin %d\n", pin); @@ -285,7 +285,7 @@ subsys_initcall(db88f5281_pci_init); * Ethernet ****************************************************************************/ static struct mv643xx_eth_platform_data db88f5281_eth_data = { - .phy_addr = 8, + .phy_addr = MV643XX_ETH_PHY_ADDR(8), }; /***************************************************************************** diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c index 3791ca6f001a..3e66098340a5 100644 --- a/arch/arm/mach-orion5x/dns323-setup.c +++ b/arch/arm/mach-orion5x/dns323-setup.c @@ -25,7 +25,7 @@ #include <asm/gpio.h> #include <asm/mach/arch.h> #include <asm/mach/pci.h> -#include <asm/arch/orion5x.h> +#include <mach/orion5x.h> #include "common.h" #include "mpp.h" @@ -79,7 +79,7 @@ subsys_initcall(dns323_pci_init); */ static struct mv643xx_eth_platform_data dns323_eth_data = { - .phy_addr = 8, + .phy_addr = MV643XX_ETH_PHY_ADDR(8), }; /**************************************************************************** @@ -245,12 +245,8 @@ static struct orion5x_mpp_mode dns323_mpp_modes[] __initdata = { static struct i2c_board_info __initdata dns323_i2c_devices[] = { { I2C_BOARD_INFO("g760a", 0x3e), -#if 0 - /* this entry requires the new-style driver model lm75 driver, - * for the meantime "insmod lm75.ko force_lm75=0,0x48" is needed */ }, { - I2C_BOARD_INFO("g751", 0x48), -#endif + I2C_BOARD_INFO("lm75", 0x48), }, { I2C_BOARD_INFO("m41t80", 0x68), }, diff --git a/arch/arm/mach-orion5x/edmini_v2-setup.c b/arch/arm/mach-orion5x/edmini_v2-setup.c new file mode 100644 index 000000000000..b24ee0c2cd61 --- /dev/null +++ b/arch/arm/mach-orion5x/edmini_v2-setup.c @@ -0,0 +1,262 @@ +/* + * arch/arm/mach-orion5x/edmini_v2-setup.c + * + * LaCie Ethernet Disk mini V2 Setup + * + * Copyright (C) 2008 Christopher Moore <moore@free.fr> + * Copyright (C) 2008 Albert Aribaud <albert.aribaud@free.fr> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/* + * TODO: add Orion USB device port init when kernel.org support is added. + * TODO: add flash write support: see below. + * TODO: add power-off support. + * TODO: add I2C EEPROM support. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/pci.h> +#include <linux/irq.h> +#include <linux/mtd/physmap.h> +#include <linux/mv643xx_eth.h> +#include <linux/leds.h> +#include <linux/gpio_keys.h> +#include <linux/input.h> +#include <linux/i2c.h> +#include <linux/ata_platform.h> +#include <linux/gpio.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/pci.h> +#include <mach/orion5x.h> +#include "common.h" +#include "mpp.h" + +/***************************************************************************** + * EDMINI_V2 Info + ****************************************************************************/ + +/* + * 512KB NOR flash Device bus boot chip select + */ + +#define EDMINI_V2_NOR_BOOT_BASE 0xfff80000 +#define EDMINI_V2_NOR_BOOT_SIZE SZ_512K + +/***************************************************************************** + * 512KB NOR Flash on BOOT Device + ****************************************************************************/ + +/* + * Currently the MTD code does not recognize the MX29LV400CBCT as a bottom + * -type device. This could cause risks of accidentally erasing critical + * flash sectors. We thus define a single, write-protected partition covering + * the whole flash. + * TODO: once the flash part TOP/BOTTOM detection issue is sorted out in the MTD + * code, break this into at least three partitions: 'u-boot code', 'u-boot + * environment' and 'whatever is left'. + */ + +static struct mtd_partition edmini_v2_partitions[] = { + { + .name = "Full512kb", + .size = 0x00080000, + .offset = 0x00000000, + .mask_flags = MTD_WRITEABLE, + }, +}; + +static struct physmap_flash_data edmini_v2_nor_flash_data = { + .width = 1, + .parts = edmini_v2_partitions, + .nr_parts = ARRAY_SIZE(edmini_v2_partitions), +}; + +static struct resource edmini_v2_nor_flash_resource = { + .flags = IORESOURCE_MEM, + .start = EDMINI_V2_NOR_BOOT_BASE, + .end = EDMINI_V2_NOR_BOOT_BASE + + EDMINI_V2_NOR_BOOT_SIZE - 1, +}; + +static struct platform_device edmini_v2_nor_flash = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &edmini_v2_nor_flash_data, + }, + .num_resources = 1, + .resource = &edmini_v2_nor_flash_resource, +}; + +/***************************************************************************** + * Ethernet + ****************************************************************************/ + +static struct mv643xx_eth_platform_data edmini_v2_eth_data = { + .phy_addr = 8, +}; + +/***************************************************************************** + * RTC 5C372a on I2C bus + ****************************************************************************/ + +#define EDMINIV2_RTC_GPIO 3 + +static struct i2c_board_info __initdata edmini_v2_i2c_rtc = { + I2C_BOARD_INFO("rs5c372a", 0x32), + .irq = 0, +}; + +/***************************************************************************** + * Sata + ****************************************************************************/ + +static struct mv_sata_platform_data edmini_v2_sata_data = { + .n_ports = 2, +}; + +/***************************************************************************** + * GPIO LED (simple - doesn't use hardware blinking support) + ****************************************************************************/ + +#define EDMINI_V2_GPIO_LED_POWER 16 + +static struct gpio_led edmini_v2_leds[] = { + { + .name = "power:blue", + .gpio = EDMINI_V2_GPIO_LED_POWER, + .active_low = 1, + }, +}; + +static struct gpio_led_platform_data edmini_v2_led_data = { + .num_leds = ARRAY_SIZE(edmini_v2_leds), + .leds = edmini_v2_leds, +}; + +static struct platform_device edmini_v2_gpio_leds = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &edmini_v2_led_data, + }, +}; + +/**************************************************************************** + * GPIO key + ****************************************************************************/ + +#define EDMINI_V2_GPIO_KEY_POWER 18 + +static struct gpio_keys_button edmini_v2_buttons[] = { + { + .code = KEY_POWER, + .gpio = EDMINI_V2_GPIO_KEY_POWER, + .desc = "Power Button", + .active_low = 0, + }, +}; + +static struct gpio_keys_platform_data edmini_v2_button_data = { + .buttons = edmini_v2_buttons, + .nbuttons = ARRAY_SIZE(edmini_v2_buttons), +}; + +static struct platform_device edmini_v2_gpio_buttons = { + .name = "gpio-keys", + .id = -1, + .dev = { + .platform_data = &edmini_v2_button_data, + }, +}; + +/***************************************************************************** + * General Setup + ****************************************************************************/ +static struct orion5x_mpp_mode edminiv2_mpp_modes[] __initdata = { + { 0, MPP_UNUSED }, + { 1, MPP_UNUSED }, + { 2, MPP_UNUSED }, + { 3, MPP_GPIO }, /* RTC interrupt */ + { 4, MPP_UNUSED }, + { 5, MPP_UNUSED }, + { 6, MPP_UNUSED }, + { 7, MPP_UNUSED }, + { 8, MPP_UNUSED }, + { 9, MPP_UNUSED }, + { 10, MPP_UNUSED }, + { 11, MPP_UNUSED }, + { 12, MPP_SATA_LED }, /* SATA 0 presence */ + { 13, MPP_SATA_LED }, /* SATA 1 presence */ + { 14, MPP_SATA_LED }, /* SATA 0 active */ + { 15, MPP_SATA_LED }, /* SATA 1 active */ + /* 16: Power LED control (0 = On, 1 = Off) */ + { 16, MPP_GPIO }, + /* 17: Power LED control select (0 = CPLD, 1 = GPIO16) */ + { 17, MPP_GPIO }, + /* 18: Power button status (0 = Released, 1 = Pressed) */ + { 18, MPP_GPIO }, + { 19, MPP_UNUSED }, + { -1 } +}; + +static void __init edmini_v2_init(void) +{ + /* + * Setup basic Orion functions. Need to be called early. + */ + orion5x_init(); + + orion5x_mpp_conf(edminiv2_mpp_modes); + + /* + * Configure peripherals. + */ + orion5x_ehci0_init(); + orion5x_eth_init(&edmini_v2_eth_data); + orion5x_i2c_init(); + orion5x_sata_init(&edmini_v2_sata_data); + orion5x_uart0_init(); + + orion5x_setup_dev_boot_win(EDMINI_V2_NOR_BOOT_BASE, + EDMINI_V2_NOR_BOOT_SIZE); + platform_device_register(&edmini_v2_nor_flash); + platform_device_register(&edmini_v2_gpio_leds); + platform_device_register(&edmini_v2_gpio_buttons); + + pr_notice("edmini_v2: USB device port, flash write and power-off " + "are not yet supported.\n"); + + /* Get RTC IRQ and register the chip */ + if (gpio_request(EDMINIV2_RTC_GPIO, "rtc") == 0) { + if (gpio_direction_input(EDMINIV2_RTC_GPIO) == 0) + edmini_v2_i2c_rtc.irq = gpio_to_irq(EDMINIV2_RTC_GPIO); + else + gpio_free(EDMINIV2_RTC_GPIO); + } + + if (edmini_v2_i2c_rtc.irq == 0) + pr_warning("edmini_v2: failed to get RTC IRQ\n"); + + i2c_register_board_info(0, &edmini_v2_i2c_rtc, 1); +} + +/* Warning: LaCie use a wrong mach-type (0x20e=526) in their bootloader. */ +MACHINE_START(EDMINI_V2, "LaCie Ethernet Disk mini V2") + /* Maintainer: Christopher Moore <moore@free.fr> */ + .phys_io = ORION5X_REGS_PHYS_BASE, + .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC, + .boot_params = 0x00000100, + .init_machine = edmini_v2_init, + .map_io = orion5x_map_io, + .init_irq = orion5x_init_irq, + .timer = &orion5x_timer, + .fixup = tag_fixup_mem32, +MACHINE_END diff --git a/arch/arm/mach-orion5x/gpio.c b/arch/arm/mach-orion5x/gpio.c index d09797990f41..fc419868e39f 100644 --- a/arch/arm/mach-orion5x/gpio.c +++ b/arch/arm/mach-orion5x/gpio.c @@ -15,9 +15,9 @@ #include <linux/module.h> #include <linux/spinlock.h> #include <linux/bitops.h> +#include <linux/io.h> #include <asm/gpio.h> -#include <asm/io.h> -#include <asm/arch/orion5x.h> +#include <mach/orion5x.h> #include "common.h" static DEFINE_SPINLOCK(gpio_lock); diff --git a/arch/arm/mach-orion5x/include/mach/debug-macro.S b/arch/arm/mach-orion5x/include/mach/debug-macro.S new file mode 100644 index 000000000000..c7f808bfe272 --- /dev/null +++ b/arch/arm/mach-orion5x/include/mach/debug-macro.S @@ -0,0 +1,22 @@ +/* + * arch/arm/mach-orion5x/include/mach/debug-macro.S + * + * Debugging macro include header + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <mach/orion5x.h> + + .macro addruart,rx + mrc p15, 0, \rx, c1, c0 + tst \rx, #1 @ MMU enabled? + ldreq \rx, =ORION5X_REGS_PHYS_BASE + ldrne \rx, =ORION5X_REGS_VIRT_BASE + orr \rx, \rx, #0x00012000 + .endm + +#define UART_SHIFT 2 +#include <asm/hardware/debug-8250.S> diff --git a/arch/arm/mach-orion5x/include/mach/dma.h b/arch/arm/mach-orion5x/include/mach/dma.h new file mode 100644 index 000000000000..40a8c178f10d --- /dev/null +++ b/arch/arm/mach-orion5x/include/mach/dma.h @@ -0,0 +1 @@ +/* empty */ diff --git a/arch/arm/mach-orion5x/include/mach/entry-macro.S b/arch/arm/mach-orion5x/include/mach/entry-macro.S new file mode 100644 index 000000000000..4351937035cd --- /dev/null +++ b/arch/arm/mach-orion5x/include/mach/entry-macro.S @@ -0,0 +1,31 @@ +/* + * arch/arm/mach-orion5x/include/mach/entry-macro.S + * + * Low-level IRQ helper macros for Orion platforms + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <mach/orion5x.h> + + .macro disable_fiq + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + + .macro get_irqnr_preamble, base, tmp + ldr \base, =MAIN_IRQ_CAUSE + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + ldr \irqstat, [\base, #0] @ main cause + ldr \tmp, [\base, #(MAIN_IRQ_MASK - MAIN_IRQ_CAUSE)] @ main mask + mov \irqnr, #0 @ default irqnr + @ find cause bits that are unmasked + ands \irqstat, \irqstat, \tmp @ clear Z flag if any + clzne \irqnr, \irqstat @ calc irqnr + rsbne \irqnr, \irqnr, #31 + .endm diff --git a/arch/arm/mach-orion5x/include/mach/gpio.h b/arch/arm/mach-orion5x/include/mach/gpio.h new file mode 100644 index 000000000000..65dc136a86f7 --- /dev/null +++ b/arch/arm/mach-orion5x/include/mach/gpio.h @@ -0,0 +1,28 @@ +/* + * arch/arm/mach-orion5x/include/mach/gpio.h + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +extern int gpio_request(unsigned pin, const char *label); +extern void gpio_free(unsigned pin); +extern int gpio_direction_input(unsigned pin); +extern int gpio_direction_output(unsigned pin, int value); +extern int gpio_get_value(unsigned pin); +extern void gpio_set_value(unsigned pin, int value); +extern void orion5x_gpio_set_blink(unsigned pin, int blink); +extern void gpio_display(void); /* debug */ + +static inline int gpio_to_irq(int pin) +{ + return pin + IRQ_ORION5X_GPIO_START; +} + +static inline int irq_to_gpio(int irq) +{ + return irq - IRQ_ORION5X_GPIO_START; +} + +#include <asm-generic/gpio.h> /* cansleep wrappers */ diff --git a/arch/arm/mach-orion5x/include/mach/hardware.h b/arch/arm/mach-orion5x/include/mach/hardware.h new file mode 100644 index 000000000000..e51aaf4bf2b5 --- /dev/null +++ b/arch/arm/mach-orion5x/include/mach/hardware.h @@ -0,0 +1,21 @@ +/* + * arch/arm/mach-orion5x/include/mach/hardware.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +#include "orion5x.h" + +#define pcibios_assign_all_busses() 1 + +#define PCIBIOS_MIN_IO 0x00001000 +#define PCIBIOS_MIN_MEM 0x01000000 +#define PCIMEM_BASE ORION5X_PCIE_MEM_PHYS_BASE + + +#endif diff --git a/arch/arm/mach-orion5x/include/mach/io.h b/arch/arm/mach-orion5x/include/mach/io.h new file mode 100644 index 000000000000..f24b2513f7f3 --- /dev/null +++ b/arch/arm/mach-orion5x/include/mach/io.h @@ -0,0 +1,63 @@ +/* + * arch/arm/mach-orion5x/include/mach/io.h + * + * Tzachi Perelstein <tzachi@marvell.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_IO_H +#define __ASM_ARCH_IO_H + +#include "orion5x.h" + +#define IO_SPACE_LIMIT 0xffffffff + +static inline void __iomem * +__arch_ioremap(unsigned long paddr, size_t size, unsigned int mtype) +{ + void __iomem *retval; + unsigned long offs = paddr - ORION5X_REGS_PHYS_BASE; + if (mtype == MT_DEVICE && size && offs < ORION5X_REGS_SIZE && + size <= ORION5X_REGS_SIZE && offs + size <= ORION5X_REGS_SIZE) { + retval = (void __iomem *)ORION5X_REGS_VIRT_BASE + offs; + } else { + retval = __arm_ioremap(paddr, size, mtype); + } + + return retval; +} + +static inline void +__arch_iounmap(void __iomem *addr) +{ + if (addr < (void __iomem *)ORION5X_REGS_VIRT_BASE || + addr >= (void __iomem *)(ORION5X_REGS_VIRT_BASE + ORION5X_REGS_SIZE)) + __iounmap(addr); +} + +static inline void __iomem *__io(unsigned long addr) +{ + return (void __iomem *)addr; +} + +#define __arch_ioremap(p, s, m) __arch_ioremap(p, s, m) +#define __arch_iounmap(a) __arch_iounmap(a) +#define __io(a) __io(a) +#define __mem_pci(a) (a) + + +/***************************************************************************** + * Helpers to access Orion registers + ****************************************************************************/ +/* + * These are not preempt-safe. Locks, if needed, must be taken + * care of by the caller. + */ +#define orion5x_setbits(r, mask) writel(readl(r) | (mask), (r)) +#define orion5x_clrbits(r, mask) writel(readl(r) & ~(mask), (r)) + + +#endif diff --git a/arch/arm/mach-orion5x/include/mach/irqs.h b/arch/arm/mach-orion5x/include/mach/irqs.h new file mode 100644 index 000000000000..d5b0fbf6b965 --- /dev/null +++ b/arch/arm/mach-orion5x/include/mach/irqs.h @@ -0,0 +1,62 @@ +/* + * arch/arm/mach-orion5x/include/mach/irqs.h + * + * IRQ definitions for Orion SoC + * + * Maintainer: Tzachi Perelstein <tzachi@marvell.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_IRQS_H +#define __ASM_ARCH_IRQS_H + +#include "orion5x.h" /* need GPIO_MAX */ + +/* + * Orion Main Interrupt Controller + */ +#define IRQ_ORION5X_BRIDGE 0 +#define IRQ_ORION5X_DOORBELL_H2C 1 +#define IRQ_ORION5X_DOORBELL_C2H 2 +#define IRQ_ORION5X_UART0 3 +#define IRQ_ORION5X_UART1 4 +#define IRQ_ORION5X_I2C 5 +#define IRQ_ORION5X_GPIO_0_7 6 +#define IRQ_ORION5X_GPIO_8_15 7 +#define IRQ_ORION5X_GPIO_16_23 8 +#define IRQ_ORION5X_GPIO_24_31 9 +#define IRQ_ORION5X_PCIE0_ERR 10 +#define IRQ_ORION5X_PCIE0_INT 11 +#define IRQ_ORION5X_USB1_CTRL 12 +#define IRQ_ORION5X_DEV_BUS_ERR 14 +#define IRQ_ORION5X_PCI_ERR 15 +#define IRQ_ORION5X_USB_BR_ERR 16 +#define IRQ_ORION5X_USB0_CTRL 17 +#define IRQ_ORION5X_ETH_RX 18 +#define IRQ_ORION5X_ETH_TX 19 +#define IRQ_ORION5X_ETH_MISC 20 +#define IRQ_ORION5X_ETH_SUM 21 +#define IRQ_ORION5X_ETH_ERR 22 +#define IRQ_ORION5X_IDMA_ERR 23 +#define IRQ_ORION5X_IDMA_0 24 +#define IRQ_ORION5X_IDMA_1 25 +#define IRQ_ORION5X_IDMA_2 26 +#define IRQ_ORION5X_IDMA_3 27 +#define IRQ_ORION5X_CESA 28 +#define IRQ_ORION5X_SATA 29 +#define IRQ_ORION5X_XOR0 30 +#define IRQ_ORION5X_XOR1 31 + +/* + * Orion General Purpose Pins + */ +#define IRQ_ORION5X_GPIO_START 32 +#define NR_GPIO_IRQS GPIO_MAX + +#define NR_IRQS (IRQ_ORION5X_GPIO_START + NR_GPIO_IRQS) + + +#endif diff --git a/arch/arm/mach-orion5x/include/mach/memory.h b/arch/arm/mach-orion5x/include/mach/memory.h new file mode 100644 index 000000000000..54dd76b013f2 --- /dev/null +++ b/arch/arm/mach-orion5x/include/mach/memory.h @@ -0,0 +1,16 @@ +/* + * arch/arm/mach-orion5x/include/mach/memory.h + * + * Marvell Orion memory definitions + */ + +#ifndef __ASM_ARCH_MEMORY_H +#define __ASM_ARCH_MEMORY_H + +#define PHYS_OFFSET UL(0x00000000) + +#define __virt_to_bus(x) __virt_to_phys(x) +#define __bus_to_virt(x) __phys_to_virt(x) + + +#endif diff --git a/arch/arm/mach-orion5x/include/mach/orion5x.h b/arch/arm/mach-orion5x/include/mach/orion5x.h new file mode 100644 index 000000000000..9f5ce1ce5840 --- /dev/null +++ b/arch/arm/mach-orion5x/include/mach/orion5x.h @@ -0,0 +1,173 @@ +/* + * arch/arm/mach-orion5x/include/mach/orion5x.h + * + * Generic definitions of Orion SoC flavors: + * Orion-1, Orion-VoIP, Orion-NAS, Orion-2, and Orion-1-90. + * + * Maintainer: Tzachi Perelstein <tzachi@marvell.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_ORION5X_H +#define __ASM_ARCH_ORION5X_H + +/***************************************************************************** + * Orion Address Maps + * + * phys + * e0000000 PCIe MEM space + * e8000000 PCI MEM space + * f0000000 PCIe WA space (Orion-1/Orion-NAS only) + * f1000000 on-chip peripheral registers + * f2000000 PCIe I/O space + * f2100000 PCI I/O space + * f4000000 device bus mappings (boot) + * fa000000 device bus mappings (cs0) + * fa800000 device bus mappings (cs2) + * fc000000 device bus mappings (cs0/cs1) + * + * virt phys size + * fdd00000 f1000000 1M on-chip peripheral registers + * fde00000 f2000000 1M PCIe I/O space + * fdf00000 f2100000 1M PCI I/O space + * fe000000 f0000000 16M PCIe WA space (Orion-1/Orion-NAS only) + ****************************************************************************/ +#define ORION5X_REGS_PHYS_BASE 0xf1000000 +#define ORION5X_REGS_VIRT_BASE 0xfdd00000 +#define ORION5X_REGS_SIZE SZ_1M + +#define ORION5X_PCIE_IO_PHYS_BASE 0xf2000000 +#define ORION5X_PCIE_IO_VIRT_BASE 0xfde00000 +#define ORION5X_PCIE_IO_BUS_BASE 0x00000000 +#define ORION5X_PCIE_IO_SIZE SZ_1M + +#define ORION5X_PCI_IO_PHYS_BASE 0xf2100000 +#define ORION5X_PCI_IO_VIRT_BASE 0xfdf00000 +#define ORION5X_PCI_IO_BUS_BASE 0x00100000 +#define ORION5X_PCI_IO_SIZE SZ_1M + +/* Relevant only for Orion-1/Orion-NAS */ +#define ORION5X_PCIE_WA_PHYS_BASE 0xf0000000 +#define ORION5X_PCIE_WA_VIRT_BASE 0xfe000000 +#define ORION5X_PCIE_WA_SIZE SZ_16M + +#define ORION5X_PCIE_MEM_PHYS_BASE 0xe0000000 +#define ORION5X_PCIE_MEM_SIZE SZ_128M + +#define ORION5X_PCI_MEM_PHYS_BASE 0xe8000000 +#define ORION5X_PCI_MEM_SIZE SZ_128M + +/******************************************************************************* + * Supported Devices & Revisions + ******************************************************************************/ +/* Orion-1 (88F5181) and Orion-VoIP (88F5181L) */ +#define MV88F5181_DEV_ID 0x5181 +#define MV88F5181_REV_B1 3 +#define MV88F5181L_REV_A0 8 +#define MV88F5181L_REV_A1 9 +/* Orion-NAS (88F5182) */ +#define MV88F5182_DEV_ID 0x5182 +#define MV88F5182_REV_A2 2 +/* Orion-2 (88F5281) */ +#define MV88F5281_DEV_ID 0x5281 +#define MV88F5281_REV_D0 4 +#define MV88F5281_REV_D1 5 +#define MV88F5281_REV_D2 6 +/* Orion-1-90 (88F6183) */ +#define MV88F6183_DEV_ID 0x6183 +#define MV88F6183_REV_B0 3 + +/******************************************************************************* + * Orion Registers Map + ******************************************************************************/ +#define ORION5X_DDR_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x00000) +#define ORION5X_DDR_REG(x) (ORION5X_DDR_VIRT_BASE | (x)) + +#define ORION5X_DEV_BUS_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x10000) +#define ORION5X_DEV_BUS_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x10000) +#define ORION5X_DEV_BUS_REG(x) (ORION5X_DEV_BUS_VIRT_BASE | (x)) +#define SPI_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x0600) +#define I2C_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x1000) +#define UART0_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x2000) +#define UART0_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE | 0x2000) +#define UART1_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x2100) +#define UART1_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE | 0x2100) + +#define ORION5X_BRIDGE_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x20000) +#define ORION5X_BRIDGE_REG(x) (ORION5X_BRIDGE_VIRT_BASE | (x)) +#define TIMER_VIRT_BASE (ORION5X_BRIDGE_VIRT_BASE | 0x300) + +#define ORION5X_PCI_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x30000) +#define ORION5X_PCI_REG(x) (ORION5X_PCI_VIRT_BASE | (x)) + +#define ORION5X_PCIE_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x40000) +#define ORION5X_PCIE_REG(x) (ORION5X_PCIE_VIRT_BASE | (x)) + +#define ORION5X_USB0_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x50000) +#define ORION5X_USB0_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x50000) +#define ORION5X_USB0_REG(x) (ORION5X_USB0_VIRT_BASE | (x)) + +#define ORION5X_XOR_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x60900) +#define ORION5X_XOR_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x60900) +#define ORION5X_XOR_REG(x) (ORION5X_XOR_VIRT_BASE | (x)) + +#define ORION5X_ETH_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x70000) +#define ORION5X_ETH_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x70000) +#define ORION5X_ETH_REG(x) (ORION5X_ETH_VIRT_BASE | (x)) + +#define ORION5X_SATA_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x80000) +#define ORION5X_SATA_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x80000) +#define ORION5X_SATA_REG(x) (ORION5X_SATA_VIRT_BASE | (x)) + +#define ORION5X_USB1_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0xa0000) +#define ORION5X_USB1_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0xa0000) +#define ORION5X_USB1_REG(x) (ORION5X_USB1_VIRT_BASE | (x)) + +/******************************************************************************* + * Device Bus Registers + ******************************************************************************/ +#define MPP_0_7_CTRL ORION5X_DEV_BUS_REG(0x000) +#define MPP_8_15_CTRL ORION5X_DEV_BUS_REG(0x004) +#define MPP_16_19_CTRL ORION5X_DEV_BUS_REG(0x050) +#define MPP_DEV_CTRL ORION5X_DEV_BUS_REG(0x008) +#define MPP_RESET_SAMPLE ORION5X_DEV_BUS_REG(0x010) +#define GPIO_OUT ORION5X_DEV_BUS_REG(0x100) +#define GPIO_IO_CONF ORION5X_DEV_BUS_REG(0x104) +#define GPIO_BLINK_EN ORION5X_DEV_BUS_REG(0x108) +#define GPIO_IN_POL ORION5X_DEV_BUS_REG(0x10c) +#define GPIO_DATA_IN ORION5X_DEV_BUS_REG(0x110) +#define GPIO_EDGE_CAUSE ORION5X_DEV_BUS_REG(0x114) +#define GPIO_EDGE_MASK ORION5X_DEV_BUS_REG(0x118) +#define GPIO_LEVEL_MASK ORION5X_DEV_BUS_REG(0x11c) +#define DEV_BANK_0_PARAM ORION5X_DEV_BUS_REG(0x45c) +#define DEV_BANK_1_PARAM ORION5X_DEV_BUS_REG(0x460) +#define DEV_BANK_2_PARAM ORION5X_DEV_BUS_REG(0x464) +#define DEV_BANK_BOOT_PARAM ORION5X_DEV_BUS_REG(0x46c) +#define DEV_BUS_CTRL ORION5X_DEV_BUS_REG(0x4c0) +#define DEV_BUS_INT_CAUSE ORION5X_DEV_BUS_REG(0x4d0) +#define DEV_BUS_INT_MASK ORION5X_DEV_BUS_REG(0x4d4) +#define GPIO_MAX 32 + +/*************************************************************************** + * Orion CPU Bridge Registers + **************************************************************************/ +#define CPU_CONF ORION5X_BRIDGE_REG(0x100) +#define CPU_CTRL ORION5X_BRIDGE_REG(0x104) +#define CPU_RESET_MASK ORION5X_BRIDGE_REG(0x108) +#define WDT_RESET 0x0002 +#define CPU_SOFT_RESET ORION5X_BRIDGE_REG(0x10c) +#define POWER_MNG_CTRL_REG ORION5X_BRIDGE_REG(0x11C) +#define BRIDGE_CAUSE ORION5X_BRIDGE_REG(0x110) +#define WDT_INT_REQ 0x0008 +#define BRIDGE_MASK ORION5X_BRIDGE_REG(0x114) +#define BRIDGE_INT_TIMER0 0x0002 +#define BRIDGE_INT_TIMER1 0x0004 +#define BRIDGE_INT_TIMER1_CLR (~0x0004) +#define MAIN_IRQ_CAUSE ORION5X_BRIDGE_REG(0x200) +#define MAIN_IRQ_MASK ORION5X_BRIDGE_REG(0x204) + + +#endif diff --git a/arch/arm/mach-orion5x/include/mach/system.h b/arch/arm/mach-orion5x/include/mach/system.h new file mode 100644 index 000000000000..08e430757890 --- /dev/null +++ b/arch/arm/mach-orion5x/include/mach/system.h @@ -0,0 +1,32 @@ +/* + * arch/arm/mach-orion5x/include/mach/system.h + * + * Tzachi Perelstein <tzachi@marvell.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_SYSTEM_H +#define __ASM_ARCH_SYSTEM_H + +#include <mach/hardware.h> +#include <mach/orion5x.h> + +static inline void arch_idle(void) +{ + cpu_do_idle(); +} + +static inline void arch_reset(char mode) +{ + /* + * Enable and issue soft reset + */ + orion5x_setbits(CPU_RESET_MASK, (1 << 2)); + orion5x_setbits(CPU_SOFT_RESET, 1); +} + + +#endif diff --git a/arch/arm/mach-orion5x/include/mach/timex.h b/arch/arm/mach-orion5x/include/mach/timex.h new file mode 100644 index 000000000000..4c69820e0810 --- /dev/null +++ b/arch/arm/mach-orion5x/include/mach/timex.h @@ -0,0 +1,11 @@ +/* + * arch/arm/mach-orion5x/include/mach/timex.h + * + * Tzachi Perelstein <tzachi@marvell.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#define CLOCK_TICK_RATE (100 * HZ) diff --git a/arch/arm/mach-orion5x/include/mach/uncompress.h b/arch/arm/mach-orion5x/include/mach/uncompress.h new file mode 100644 index 000000000000..4322dba468a4 --- /dev/null +++ b/arch/arm/mach-orion5x/include/mach/uncompress.h @@ -0,0 +1,49 @@ +/* + * arch/arm/mach-orion5x/include/mach/uncompress.h + * + * Tzachi Perelstein <tzachi@marvell.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/serial_reg.h> +#include <mach/orion5x.h> + +#define SERIAL_BASE ((unsigned char *)UART0_PHYS_BASE) + +static void putc(const char c) +{ + unsigned char *base = SERIAL_BASE; + int i; + + for (i = 0; i < 0x1000; i++) { + if (base[UART_LSR << 2] & UART_LSR_THRE) + break; + barrier(); + } + + base[UART_TX << 2] = c; +} + +static void flush(void) +{ + unsigned char *base = SERIAL_BASE; + unsigned char mask; + int i; + + mask = UART_LSR_TEMT | UART_LSR_THRE; + + for (i = 0; i < 0x1000; i++) { + if ((base[UART_LSR << 2] & mask) == mask) + break; + barrier(); + } +} + +/* + * nothing to do + */ +#define arch_decomp_setup() +#define arch_decomp_wdog() diff --git a/arch/arm/mach-orion5x/include/mach/vmalloc.h b/arch/arm/mach-orion5x/include/mach/vmalloc.h new file mode 100644 index 000000000000..7147a297e97f --- /dev/null +++ b/arch/arm/mach-orion5x/include/mach/vmalloc.h @@ -0,0 +1,5 @@ +/* + * arch/arm/mach-orion5x/include/mach/vmalloc.h + */ + +#define VMALLOC_END 0xfd800000 diff --git a/arch/arm/mach-orion5x/irq.c b/arch/arm/mach-orion5x/irq.c index e2a0084ab4a3..632a36f5cf14 100644 --- a/arch/arm/mach-orion5x/irq.c +++ b/arch/arm/mach-orion5x/irq.c @@ -13,10 +13,10 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/irq.h> +#include <linux/io.h> #include <asm/gpio.h> -#include <asm/io.h> -#include <asm/arch/orion5x.h> -#include <asm/plat-orion/irq.h> +#include <mach/orion5x.h> +#include <plat/irq.h> #include "common.h" /***************************************************************************** @@ -91,27 +91,27 @@ static int orion5x_gpio_set_irq_type(u32 irq, u32 type) desc = irq_desc + irq; switch (type) { - case IRQT_HIGH: + case IRQ_TYPE_LEVEL_HIGH: desc->handle_irq = handle_level_irq; desc->status |= IRQ_LEVEL; orion5x_clrbits(GPIO_IN_POL, (1 << pin)); break; - case IRQT_LOW: + case IRQ_TYPE_LEVEL_LOW: desc->handle_irq = handle_level_irq; desc->status |= IRQ_LEVEL; orion5x_setbits(GPIO_IN_POL, (1 << pin)); break; - case IRQT_RISING: + case IRQ_TYPE_EDGE_RISING: desc->handle_irq = handle_edge_irq; desc->status &= ~IRQ_LEVEL; orion5x_clrbits(GPIO_IN_POL, (1 << pin)); break; - case IRQT_FALLING: + case IRQ_TYPE_EDGE_FALLING: desc->handle_irq = handle_edge_irq; desc->status &= ~IRQ_LEVEL; orion5x_setbits(GPIO_IN_POL, (1 << pin)); break; - case IRQT_BOTHEDGE: + case IRQ_TYPE_EDGE_BOTH: desc->handle_irq = handle_edge_irq; desc->status &= ~IRQ_LEVEL; /* @@ -156,13 +156,13 @@ static void orion5x_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) if (cause & (1 << pin)) { irq = gpio_to_irq(pin); desc = irq_desc + irq; - if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQT_BOTHEDGE) { + if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { /* Swap polarity (race with GPIO line) */ u32 polarity = readl(GPIO_IN_POL); polarity ^= 1 << pin; writel(polarity, GPIO_IN_POL); } - desc_handle_irq(irq, desc); + generic_handle_irq(irq); } } } diff --git a/arch/arm/mach-orion5x/kurobox_pro-setup.c b/arch/arm/mach-orion5x/kurobox_pro-setup.c index 84feac4a1fe2..dfbb68df7b09 100644 --- a/arch/arm/mach-orion5x/kurobox_pro-setup.c +++ b/arch/arm/mach-orion5x/kurobox_pro-setup.c @@ -24,8 +24,8 @@ #include <asm/gpio.h> #include <asm/mach/arch.h> #include <asm/mach/pci.h> -#include <asm/arch/orion5x.h> -#include <asm/plat-orion/orion_nand.h> +#include <mach/orion5x.h> +#include <plat/orion_nand.h> #include "common.h" #include "mpp.h" @@ -146,8 +146,10 @@ static struct hw_pci kurobox_pro_pci __initdata = { static int __init kurobox_pro_pci_init(void) { - if (machine_is_kurobox_pro()) + if (machine_is_kurobox_pro()) { + orion5x_pci_disable(); pci_common_init(&kurobox_pro_pci); + } return 0; } @@ -159,7 +161,7 @@ subsys_initcall(kurobox_pro_pci_init); ****************************************************************************/ static struct mv643xx_eth_platform_data kurobox_pro_eth_data = { - .phy_addr = 8, + .phy_addr = MV643XX_ETH_PHY_ADDR(8), }; /***************************************************************************** @@ -291,7 +293,7 @@ static void kurobox_pro_power_off(void) const unsigned char shutdownwait[] = {0x00, 0x0c}; const unsigned char poweroff[] = {0x00, 0x06}; /* 38400 baud divisor */ - const unsigned divisor = ((ORION5X_TCLK + (8 * 38400)) / (16 * 38400)); + const unsigned divisor = ((orion5x_tclk + (8 * 38400)) / (16 * 38400)); pr_info("%s: triggering power-off...\n", __func__); @@ -356,6 +358,7 @@ static void __init kurobox_pro_init(void) orion5x_sata_init(&kurobox_pro_sata_data); orion5x_uart0_init(); orion5x_uart1_init(); + orion5x_xor_init(); orion5x_setup_dev_boot_win(KUROBOX_PRO_NOR_BOOT_BASE, KUROBOX_PRO_NOR_BOOT_SIZE); diff --git a/arch/arm/mach-orion5x/lsmini-setup.c b/arch/arm/mach-orion5x/lsmini-setup.c new file mode 100644 index 000000000000..e0c43b8beb72 --- /dev/null +++ b/arch/arm/mach-orion5x/lsmini-setup.c @@ -0,0 +1,279 @@ +/* + * arch/arm/mach-orion5x/lsmini-setup.c + * + * Maintainer: Alexey Kopytko <alexey@kopytko.ru> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/pci.h> +#include <linux/mtd/physmap.h> +#include <linux/mv643xx_eth.h> +#include <linux/leds.h> +#include <linux/gpio_keys.h> +#include <linux/input.h> +#include <linux/i2c.h> +#include <linux/ata_platform.h> +#include <asm/mach-types.h> +#include <linux/gpio.h> +#include <asm/mach/arch.h> +#include "common.h" +#include "mpp.h" +#include "include/mach/system.h" + +/***************************************************************************** + * Linkstation Mini Info + ****************************************************************************/ + +/* + * 256K NOR flash Device bus boot chip select + */ + +#define LSMINI_NOR_BOOT_BASE 0xf4000000 +#define LSMINI_NOR_BOOT_SIZE SZ_256K + +/***************************************************************************** + * 256KB NOR Flash on BOOT Device + ****************************************************************************/ + +static struct physmap_flash_data lsmini_nor_flash_data = { + .width = 1, +}; + +static struct resource lsmini_nor_flash_resource = { + .flags = IORESOURCE_MEM, + .start = LSMINI_NOR_BOOT_BASE, + .end = LSMINI_NOR_BOOT_BASE + LSMINI_NOR_BOOT_SIZE - 1, +}; + +static struct platform_device lsmini_nor_flash = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &lsmini_nor_flash_data, + }, + .num_resources = 1, + .resource = &lsmini_nor_flash_resource, +}; + +/***************************************************************************** + * Ethernet + ****************************************************************************/ + +static struct mv643xx_eth_platform_data lsmini_eth_data = { + .phy_addr = 8, +}; + +/***************************************************************************** + * RTC 5C372a on I2C bus + ****************************************************************************/ + +static struct i2c_board_info __initdata lsmini_i2c_rtc = { + I2C_BOARD_INFO("rs5c372a", 0x32), +}; + +/***************************************************************************** + * LEDs attached to GPIO + ****************************************************************************/ + +#define LSMINI_GPIO_LED_ALARM 2 +#define LSMINI_GPIO_LED_INFO 3 +#define LSMINI_GPIO_LED_FUNC 9 +#define LSMINI_GPIO_LED_PWR 14 + +static struct gpio_led lsmini_led_pins[] = { + { + .name = "alarm:red", + .gpio = LSMINI_GPIO_LED_ALARM, + .active_low = 1, + }, { + .name = "info:amber", + .gpio = LSMINI_GPIO_LED_INFO, + .active_low = 1, + }, { + .name = "func:blue:top", + .gpio = LSMINI_GPIO_LED_FUNC, + .active_low = 1, + }, { + .name = "power:blue:bottom", + .gpio = LSMINI_GPIO_LED_PWR, + }, +}; + +static struct gpio_led_platform_data lsmini_led_data = { + .leds = lsmini_led_pins, + .num_leds = ARRAY_SIZE(lsmini_led_pins), +}; + +static struct platform_device lsmini_leds = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &lsmini_led_data, + }, +}; + +/**************************************************************************** + * GPIO Attached Keys + ****************************************************************************/ + +#define LSMINI_GPIO_KEY_FUNC 15 +#define LSMINI_GPIO_KEY_POWER 18 +#define LSMINI_GPIO_KEY_AUTOPOWER 17 + +#define LSMINI_SW_POWER 0x00 +#define LSMINI_SW_AUTOPOWER 0x01 + +static struct gpio_keys_button lsmini_buttons[] = { + { + .code = KEY_OPTION, + .gpio = LSMINI_GPIO_KEY_FUNC, + .desc = "Function Button", + .active_low = 1, + }, { + .type = EV_SW, + .code = LSMINI_SW_POWER, + .gpio = LSMINI_GPIO_KEY_POWER, + .desc = "Power-on Switch", + .active_low = 1, + }, { + .type = EV_SW, + .code = LSMINI_SW_AUTOPOWER, + .gpio = LSMINI_GPIO_KEY_AUTOPOWER, + .desc = "Power-auto Switch", + .active_low = 1, + }, +}; + +static struct gpio_keys_platform_data lsmini_button_data = { + .buttons = lsmini_buttons, + .nbuttons = ARRAY_SIZE(lsmini_buttons), +}; + +static struct platform_device lsmini_button_device = { + .name = "gpio-keys", + .id = -1, + .num_resources = 0, + .dev = { + .platform_data = &lsmini_button_data, + }, +}; + + +/***************************************************************************** + * SATA + ****************************************************************************/ +static struct mv_sata_platform_data lsmini_sata_data = { + .n_ports = 2, +}; + + +/***************************************************************************** + * Linkstation Mini specific power off method: reboot + ****************************************************************************/ +/* + * On the Linkstation Mini, the shutdown process is following: + * - Userland monitors key events until the power switch goes to off position + * - The board reboots + * - U-boot starts and goes into an idle mode waiting for the user + * to move the switch to ON position + */ + +static void lsmini_power_off(void) +{ + arch_reset(0); +} + + +/***************************************************************************** + * General Setup + ****************************************************************************/ + +#define LSMINI_GPIO_USB_POWER 16 +#define LSMINI_GPIO_AUTO_POWER 17 +#define LSMINI_GPIO_POWER 18 + +#define LSMINI_GPIO_HDD_POWER0 1 +#define LSMINI_GPIO_HDD_POWER1 19 + +static struct orion5x_mpp_mode lsmini_mpp_modes[] __initdata = { + { 0, MPP_UNUSED }, /* LED_RESERVE1 (unused) */ + { 1, MPP_GPIO }, /* HDD_PWR */ + { 2, MPP_GPIO }, /* LED_ALARM */ + { 3, MPP_GPIO }, /* LED_INFO */ + { 4, MPP_UNUSED }, + { 5, MPP_UNUSED }, + { 6, MPP_UNUSED }, + { 7, MPP_UNUSED }, + { 8, MPP_UNUSED }, + { 9, MPP_GPIO }, /* LED_FUNC */ + { 10, MPP_UNUSED }, + { 11, MPP_UNUSED }, /* LED_ETH (dummy) */ + { 12, MPP_UNUSED }, + { 13, MPP_UNUSED }, + { 14, MPP_GPIO }, /* LED_PWR */ + { 15, MPP_GPIO }, /* FUNC */ + { 16, MPP_GPIO }, /* USB_PWR */ + { 17, MPP_GPIO }, /* AUTO_POWER */ + { 18, MPP_GPIO }, /* POWER */ + { 19, MPP_GPIO }, /* HDD_PWR1 */ + { -1 }, +}; + +static void __init lsmini_init(void) +{ + /* + * Setup basic Orion functions. Need to be called early. + */ + orion5x_init(); + + orion5x_mpp_conf(lsmini_mpp_modes); + + /* + * Configure peripherals. + */ + orion5x_ehci0_init(); + orion5x_ehci1_init(); + orion5x_eth_init(&lsmini_eth_data); + orion5x_i2c_init(); + orion5x_sata_init(&lsmini_sata_data); + orion5x_uart0_init(); + orion5x_xor_init(); + + orion5x_setup_dev_boot_win(LSMINI_NOR_BOOT_BASE, + LSMINI_NOR_BOOT_SIZE); + platform_device_register(&lsmini_nor_flash); + + platform_device_register(&lsmini_button_device); + + platform_device_register(&lsmini_leds); + + i2c_register_board_info(0, &lsmini_i2c_rtc, 1); + + /* enable USB power */ + gpio_set_value(LSMINI_GPIO_USB_POWER, 1); + + /* register power-off method */ + pm_power_off = lsmini_power_off; + + pr_info("%s: finished\n", __func__); +} + +#ifdef CONFIG_MACH_LINKSTATION_MINI +MACHINE_START(LINKSTATION_MINI, "Buffalo Linkstation Mini") + /* Maintainer: Alexey Kopytko <alexey@kopytko.ru> */ + .phys_io = ORION5X_REGS_PHYS_BASE, + .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC, + .boot_params = 0x00000100, + .init_machine = lsmini_init, + .map_io = orion5x_map_io, + .init_irq = orion5x_init_irq, + .timer = &orion5x_timer, + .fixup = tag_fixup_mem32, +MACHINE_END +#endif diff --git a/arch/arm/mach-orion5x/mpp.c b/arch/arm/mach-orion5x/mpp.c index a48cadb01590..640ea2a3fc6c 100644 --- a/arch/arm/mach-orion5x/mpp.c +++ b/arch/arm/mach-orion5x/mpp.c @@ -11,8 +11,8 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/mbus.h> -#include <asm/hardware.h> -#include <asm/io.h> +#include <linux/io.h> +#include <mach/hardware.h> #include "common.h" #include "mpp.h" diff --git a/arch/arm/mach-orion5x/mss2-setup.c b/arch/arm/mach-orion5x/mss2-setup.c index 7ce9e407d9d1..68acca98e638 100644 --- a/arch/arm/mach-orion5x/mss2-setup.c +++ b/arch/arm/mach-orion5x/mss2-setup.c @@ -25,7 +25,7 @@ #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/pci.h> -#include <asm/arch/orion5x.h> +#include <mach/orion5x.h> #include "common.h" #include "mpp.h" @@ -109,7 +109,7 @@ subsys_initcall(mss2_pci_init); ****************************************************************************/ static struct mv643xx_eth_platform_data mss2_eth_data = { - .phy_addr = 8, + .phy_addr = MV643XX_ETH_PHY_ADDR(8), }; /***************************************************************************** @@ -239,6 +239,7 @@ static void __init mss2_init(void) orion5x_i2c_init(); orion5x_sata_init(&mss2_sata_data); orion5x_uart0_init(); + orion5x_xor_init(); orion5x_setup_dev_boot_win(MSS2_NOR_BOOT_BASE, MSS2_NOR_BOOT_SIZE); platform_device_register(&mss2_nor_flash); diff --git a/arch/arm/mach-orion5x/mv2120-setup.c b/arch/arm/mach-orion5x/mv2120-setup.c index 55f3b0fdef8b..97c9ccb2ac60 100644 --- a/arch/arm/mach-orion5x/mv2120-setup.c +++ b/arch/arm/mach-orion5x/mv2120-setup.c @@ -22,7 +22,7 @@ #include <asm/mach-types.h> #include <asm/gpio.h> #include <asm/mach/arch.h> -#include <asm/arch/orion5x.h> +#include <mach/orion5x.h> #include "common.h" #include "mpp.h" @@ -39,7 +39,7 @@ * Ethernet ****************************************************************************/ static struct mv643xx_eth_platform_data mv2120_eth_data = { - .phy_addr = 8, + .phy_addr = MV643XX_ETH_PHY_ADDR(8), }; static struct mv_sata_platform_data mv2120_sata_data = { @@ -203,6 +203,7 @@ static void __init mv2120_init(void) orion5x_i2c_init(); orion5x_sata_init(&mv2120_sata_data); orion5x_uart0_init(); + orion5x_xor_init(); orion5x_setup_dev_boot_win(MV2120_NOR_BOOT_BASE, MV2120_NOR_BOOT_SIZE); platform_device_register(&mv2120_nor_flash); diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c index 256a4f680935..a7b7d77b1b09 100644 --- a/arch/arm/mach-orion5x/pci.c +++ b/arch/arm/mach-orion5x/pci.c @@ -14,7 +14,7 @@ #include <linux/pci.h> #include <linux/mbus.h> #include <asm/mach/pci.h> -#include <asm/plat-orion/pcie.h> +#include <plat/pcie.h> #include "common.h" /***************************************************************************** @@ -541,6 +541,13 @@ static void __devinit rc_pci_fixup(struct pci_dev *dev) } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup); +static int orion5x_pci_disabled __initdata; + +void __init orion5x_pci_disable(void) +{ + orion5x_pci_disabled = 1; +} + void __init orion5x_pci_set_cardbus_mode(void) { orion5x_pci_cardbus_mode = 1; @@ -553,7 +560,7 @@ int __init orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys) if (nr == 0) { orion_pcie_set_local_bus_nr(PCIE_BASE, sys->busnr); ret = pcie_setup(sys); - } else if (nr == 1) { + } else if (nr == 1 && !orion5x_pci_disabled) { orion5x_pci_set_bus_nr(sys->busnr); ret = pci_setup(sys); } @@ -567,7 +574,7 @@ struct pci_bus __init *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys if (nr == 0) { bus = pci_scan_bus(sys->busnr, &pcie_ops, sys); - } else if (nr == 1) { + } else if (nr == 1 && !orion5x_pci_disabled) { bus = pci_scan_bus(sys->busnr, &pci_ops, sys); } else { bus = NULL; @@ -584,7 +591,7 @@ int __init orion5x_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) /* * PCIe endpoint? */ - if (bus < orion5x_pci_local_bus_nr()) + if (orion5x_pci_disabled || bus < orion5x_pci_local_bus_nr()) return IRQ_ORION5X_PCIE0_INT; return -1; diff --git a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c index d50e3650a09e..500cdadaf09c 100644 --- a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c +++ b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c @@ -15,12 +15,13 @@ #include <linux/irq.h> #include <linux/mtd/physmap.h> #include <linux/mv643xx_eth.h> +#include <linux/ethtool.h> #include <asm/mach-types.h> #include <asm/gpio.h> #include <asm/leds.h> #include <asm/mach/arch.h> #include <asm/mach/pci.h> -#include <asm/arch/orion5x.h> +#include <mach/orion5x.h> #include "common.h" #include "mpp.h" @@ -87,7 +88,9 @@ static struct orion5x_mpp_mode rd88f5181l_fxo_mpp_modes[] __initdata = { }; static struct mv643xx_eth_platform_data rd88f5181l_fxo_eth_data = { - .phy_addr = -1, + .phy_addr = MV643XX_ETH_PHY_NONE, + .speed = SPEED_1000, + .duplex = DUPLEX_FULL, }; static void __init rd88f5181l_fxo_init(void) diff --git a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c index b56447d32e17..ebde81416499 100644 --- a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c +++ b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c @@ -15,13 +15,14 @@ #include <linux/irq.h> #include <linux/mtd/physmap.h> #include <linux/mv643xx_eth.h> +#include <linux/ethtool.h> #include <linux/i2c.h> #include <asm/mach-types.h> #include <asm/gpio.h> #include <asm/leds.h> #include <asm/mach/arch.h> #include <asm/mach/pci.h> -#include <asm/arch/orion5x.h> +#include <mach/orion5x.h> #include "common.h" #include "mpp.h" @@ -88,7 +89,9 @@ static struct orion5x_mpp_mode rd88f5181l_ge_mpp_modes[] __initdata = { }; static struct mv643xx_eth_platform_data rd88f5181l_ge_eth_data = { - .phy_addr = -1, + .phy_addr = MV643XX_ETH_PHY_NONE, + .speed = SPEED_1000, + .duplex = DUPLEX_FULL, }; static struct i2c_board_info __initdata rd88f5181l_ge_i2c_rtc = { diff --git a/arch/arm/mach-orion5x/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c index 10ae62864269..a04f9e4b633a 100644 --- a/arch/arm/mach-orion5x/rd88f5182-setup.c +++ b/arch/arm/mach-orion5x/rd88f5182-setup.c @@ -24,7 +24,7 @@ #include <asm/leds.h> #include <asm/mach/arch.h> #include <asm/mach/pci.h> -#include <asm/arch/orion5x.h> +#include <mach/orion5x.h> #include "common.h" #include "mpp.h" @@ -148,7 +148,7 @@ void __init rd88f5182_pci_preinit(void) pin = RD88F5182_PCI_SLOT0_IRQ_A_PIN; if (gpio_request(pin, "PCI IntA") == 0) { if (gpio_direction_input(pin) == 0) { - set_irq_type(gpio_to_irq(pin), IRQT_LOW); + set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); } else { printk(KERN_ERR "rd88f5182_pci_preinit faield to " "set_irq_type pin %d\n", pin); @@ -161,7 +161,7 @@ void __init rd88f5182_pci_preinit(void) pin = RD88F5182_PCI_SLOT0_IRQ_B_PIN; if (gpio_request(pin, "PCI IntB") == 0) { if (gpio_direction_input(pin) == 0) { - set_irq_type(gpio_to_irq(pin), IRQT_LOW); + set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); } else { printk(KERN_ERR "rd88f5182_pci_preinit faield to " "set_irq_type pin %d\n", pin); @@ -221,7 +221,7 @@ subsys_initcall(rd88f5182_pci_init); ****************************************************************************/ static struct mv643xx_eth_platform_data rd88f5182_eth_data = { - .phy_addr = 8, + .phy_addr = MV643XX_ETH_PHY_ADDR(8), }; /***************************************************************************** @@ -292,6 +292,7 @@ static void __init rd88f5182_init(void) orion5x_i2c_init(); orion5x_sata_init(&rd88f5182_sata_data); orion5x_uart0_init(); + orion5x_xor_init(); orion5x_setup_dev_boot_win(RD88F5182_NOR_BOOT_BASE, RD88F5182_NOR_BOOT_SIZE); diff --git a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c new file mode 100644 index 000000000000..40e049539091 --- /dev/null +++ b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c @@ -0,0 +1,117 @@ +/* + * arch/arm/mach-orion5x/rd88f6183-ap-ge-setup.c + * + * Marvell Orion-1-90 AP GE Reference Design Setup + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/pci.h> +#include <linux/irq.h> +#include <linux/mtd/physmap.h> +#include <linux/mv643xx_eth.h> +#include <linux/spi/spi.h> +#include <linux/spi/orion_spi.h> +#include <linux/spi/flash.h> +#include <linux/ethtool.h> +#include <asm/mach-types.h> +#include <asm/gpio.h> +#include <asm/leds.h> +#include <asm/mach/arch.h> +#include <asm/mach/pci.h> +#include <mach/orion5x.h> +#include "common.h" +#include "mpp.h" + +static struct mv643xx_eth_platform_data rd88f6183ap_ge_eth_data = { + .phy_addr = -1, + .speed = SPEED_1000, + .duplex = DUPLEX_FULL, +}; + +static struct mtd_partition rd88f6183ap_ge_partitions[] = { + { + .name = "kernel", + .offset = 0x00000000, + .size = 0x00200000, + }, { + .name = "rootfs", + .offset = 0x00200000, + .size = 0x00500000, + }, { + .name = "nvram", + .offset = 0x00700000, + .size = 0x00080000, + }, +}; + +static struct flash_platform_data rd88f6183ap_ge_spi_slave_data = { + .type = "m25p64", + .nr_parts = ARRAY_SIZE(rd88f6183ap_ge_partitions), + .parts = rd88f6183ap_ge_partitions, +}; + +static struct spi_board_info __initdata rd88f6183ap_ge_spi_slave_info[] = { + { + .modalias = "m25p80", + .platform_data = &rd88f6183ap_ge_spi_slave_data, + .irq = NO_IRQ, + .max_speed_hz = 20000000, + .bus_num = 0, + .chip_select = 0, + }, +}; + +static void __init rd88f6183ap_ge_init(void) +{ + /* + * Setup basic Orion functions. Need to be called early. + */ + orion5x_init(); + + /* + * Configure peripherals. + */ + orion5x_ehci0_init(); + orion5x_eth_init(&rd88f6183ap_ge_eth_data); + spi_register_board_info(rd88f6183ap_ge_spi_slave_info, + ARRAY_SIZE(rd88f6183ap_ge_spi_slave_info)); + orion5x_spi_init(); + orion5x_uart0_init(); +} + +static struct hw_pci rd88f6183ap_ge_pci __initdata = { + .nr_controllers = 2, + .swizzle = pci_std_swizzle, + .setup = orion5x_pci_sys_setup, + .scan = orion5x_pci_sys_scan_bus, + .map_irq = orion5x_pci_map_irq, +}; + +static int __init rd88f6183ap_ge_pci_init(void) +{ + if (machine_is_rd88f6183ap_ge()) { + orion5x_pci_disable(); + pci_common_init(&rd88f6183ap_ge_pci); + } + + return 0; +} +subsys_initcall(rd88f6183ap_ge_pci_init); + +MACHINE_START(RD88F6183AP_GE, "Marvell Orion-1-90 AP GE Reference Design") + /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */ + .phys_io = ORION5X_REGS_PHYS_BASE, + .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC, + .boot_params = 0x00000100, + .init_machine = rd88f6183ap_ge_init, + .map_io = orion5x_map_io, + .init_irq = orion5x_init_irq, + .timer = &orion5x_timer, + .fixup = tag_fixup_mem32, +MACHINE_END diff --git a/arch/arm/mach-orion5x/terastation_pro2-setup.c b/arch/arm/mach-orion5x/terastation_pro2-setup.c new file mode 100644 index 000000000000..0b101d7d41c2 --- /dev/null +++ b/arch/arm/mach-orion5x/terastation_pro2-setup.c @@ -0,0 +1,369 @@ +/* + * Buffalo Terastation Pro II/Live Board Setup + * + * Maintainer: Sylver Bruneau <sylver.bruneau@googlemail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/pci.h> +#include <linux/irq.h> +#include <linux/delay.h> +#include <linux/mtd/physmap.h> +#include <linux/mv643xx_eth.h> +#include <linux/i2c.h> +#include <linux/serial_reg.h> +#include <asm/mach-types.h> +#include <asm/gpio.h> +#include <asm/mach/arch.h> +#include <asm/mach/pci.h> +#include <mach/orion5x.h> +#include "common.h" +#include "mpp.h" + +/***************************************************************************** + * Terastation Pro 2/Live Info + ****************************************************************************/ + +/* + * Terastation Pro 2 hardware : + * - Marvell 88F5281-D0 + * - Marvell 88SX6042 SATA controller (PCI) + * - Marvell 88E1118 Gigabit Ethernet PHY + * - 256KB NOR flash + * - 128MB of DDR RAM + * - PCIe port (not equipped) + */ + +/* + * 256K NOR flash Device bus boot chip select + */ + +#define TSP2_NOR_BOOT_BASE 0xf4000000 +#define TSP2_NOR_BOOT_SIZE SZ_256K + +/***************************************************************************** + * 256KB NOR Flash on BOOT Device + ****************************************************************************/ + +static struct physmap_flash_data tsp2_nor_flash_data = { + .width = 1, +}; + +static struct resource tsp2_nor_flash_resource = { + .flags = IORESOURCE_MEM, + .start = TSP2_NOR_BOOT_BASE, + .end = TSP2_NOR_BOOT_BASE + TSP2_NOR_BOOT_SIZE - 1, +}; + +static struct platform_device tsp2_nor_flash = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &tsp2_nor_flash_data, + }, + .num_resources = 1, + .resource = &tsp2_nor_flash_resource, +}; + +/***************************************************************************** + * PCI + ****************************************************************************/ +#define TSP2_PCI_SLOT0_OFFS 7 +#define TSP2_PCI_SLOT0_IRQ_PIN 11 + +void __init tsp2_pci_preinit(void) +{ + int pin; + + /* + * Configure PCI GPIO IRQ pins + */ + pin = TSP2_PCI_SLOT0_IRQ_PIN; + if (gpio_request(pin, "PCI Int1") == 0) { + if (gpio_direction_input(pin) == 0) { + set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); + } else { + printk(KERN_ERR "tsp2_pci_preinit failed " + "to set_irq_type pin %d\n", pin); + gpio_free(pin); + } + } else { + printk(KERN_ERR "tsp2_pci_preinit failed to " + "gpio_request %d\n", pin); + } +} + +static int __init tsp2_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +{ + int irq; + + /* + * Check for devices with hard-wired IRQs. + */ + irq = orion5x_pci_map_irq(dev, slot, pin); + if (irq != -1) + return irq; + + /* + * PCI IRQs are connected via GPIOs. + */ + if (slot == TSP2_PCI_SLOT0_OFFS) + return gpio_to_irq(TSP2_PCI_SLOT0_IRQ_PIN); + + return -1; +} + +static struct hw_pci tsp2_pci __initdata = { + .nr_controllers = 2, + .preinit = tsp2_pci_preinit, + .swizzle = pci_std_swizzle, + .setup = orion5x_pci_sys_setup, + .scan = orion5x_pci_sys_scan_bus, + .map_irq = tsp2_pci_map_irq, +}; + +static int __init tsp2_pci_init(void) +{ + if (machine_is_terastation_pro2()) + pci_common_init(&tsp2_pci); + + return 0; +} + +subsys_initcall(tsp2_pci_init); + +/***************************************************************************** + * Ethernet + ****************************************************************************/ + +static struct mv643xx_eth_platform_data tsp2_eth_data = { + .phy_addr = 0, +}; + +/***************************************************************************** + * RTC 5C372a on I2C bus + ****************************************************************************/ + +#define TSP2_RTC_GPIO 9 + +static struct i2c_board_info __initdata tsp2_i2c_rtc = { + I2C_BOARD_INFO("rs5c372a", 0x32), +}; + +/***************************************************************************** + * Terastation Pro II specific power off method via UART1-attached + * microcontroller + ****************************************************************************/ + +#define UART1_REG(x) (UART1_VIRT_BASE + ((UART_##x) << 2)) + +static int tsp2_miconread(unsigned char *buf, int count) +{ + int i; + int timeout; + + for (i = 0; i < count; i++) { + timeout = 10; + + while (!(readl(UART1_REG(LSR)) & UART_LSR_DR)) { + if (--timeout == 0) + break; + udelay(1000); + } + + if (timeout == 0) + break; + buf[i] = readl(UART1_REG(RX)); + } + + /* return read bytes */ + return i; +} + +static int tsp2_miconwrite(const unsigned char *buf, int count) +{ + int i = 0; + + while (count--) { + while (!(readl(UART1_REG(LSR)) & UART_LSR_THRE)) + barrier(); + writel(buf[i++], UART1_REG(TX)); + } + + return 0; +} + +static int tsp2_miconsend(const unsigned char *data, int count) +{ + int i; + unsigned char checksum = 0; + unsigned char recv_buf[40]; + unsigned char send_buf[40]; + unsigned char correct_ack[3]; + int retry = 2; + + /* Generate checksum */ + for (i = 0; i < count; i++) + checksum -= data[i]; + + do { + /* Send data */ + tsp2_miconwrite(data, count); + + /* send checksum */ + tsp2_miconwrite(&checksum, 1); + + if (tsp2_miconread(recv_buf, sizeof(recv_buf)) <= 3) { + printk(KERN_ERR ">%s: receive failed.\n", __func__); + + /* send preamble to clear the receive buffer */ + memset(&send_buf, 0xff, sizeof(send_buf)); + tsp2_miconwrite(send_buf, sizeof(send_buf)); + + /* make dummy reads */ + mdelay(100); + tsp2_miconread(recv_buf, sizeof(recv_buf)); + } else { + /* Generate expected ack */ + correct_ack[0] = 0x01; + correct_ack[1] = data[1]; + correct_ack[2] = 0x00; + + /* checksum Check */ + if ((recv_buf[0] + recv_buf[1] + recv_buf[2] + + recv_buf[3]) & 0xFF) { + printk(KERN_ERR ">%s: Checksum Error : " + "Received data[%02x, %02x, %02x, %02x]" + "\n", __func__, recv_buf[0], + recv_buf[1], recv_buf[2], recv_buf[3]); + } else { + /* Check Received Data */ + if (correct_ack[0] == recv_buf[0] && + correct_ack[1] == recv_buf[1] && + correct_ack[2] == recv_buf[2]) { + /* Interval for next command */ + mdelay(10); + + /* Receive ACK */ + return 0; + } + } + /* Received NAK or illegal Data */ + printk(KERN_ERR ">%s: Error : NAK or Illegal Data " + "Received\n", __func__); + } + } while (retry--); + + /* Interval for next command */ + mdelay(10); + + return -1; +} + +static void tsp2_power_off(void) +{ + const unsigned char watchdogkill[] = {0x01, 0x35, 0x00}; + const unsigned char shutdownwait[] = {0x00, 0x0c}; + const unsigned char poweroff[] = {0x00, 0x06}; + /* 38400 baud divisor */ + const unsigned divisor = ((orion5x_tclk + (8 * 38400)) / (16 * 38400)); + + pr_info("%s: triggering power-off...\n", __func__); + + /* hijack uart1 and reset into sane state (38400,8n1,even parity) */ + writel(0x83, UART1_REG(LCR)); + writel(divisor & 0xff, UART1_REG(DLL)); + writel((divisor >> 8) & 0xff, UART1_REG(DLM)); + writel(0x1b, UART1_REG(LCR)); + writel(0x00, UART1_REG(IER)); + writel(0x07, UART1_REG(FCR)); + writel(0x00, UART1_REG(MCR)); + + /* Send the commands to shutdown the Terastation Pro II */ + tsp2_miconsend(watchdogkill, sizeof(watchdogkill)) ; + tsp2_miconsend(shutdownwait, sizeof(shutdownwait)) ; + tsp2_miconsend(poweroff, sizeof(poweroff)); +} + +/***************************************************************************** + * General Setup + ****************************************************************************/ +static struct orion5x_mpp_mode tsp2_mpp_modes[] __initdata = { + { 0, MPP_PCIE_RST_OUTn }, + { 1, MPP_UNUSED }, + { 2, MPP_UNUSED }, + { 3, MPP_UNUSED }, + { 4, MPP_NAND }, /* BOOT NAND Flash REn */ + { 5, MPP_NAND }, /* BOOT NAND Flash WEn */ + { 6, MPP_NAND }, /* BOOT NAND Flash HREn[0] */ + { 7, MPP_NAND }, /* BOOT NAND Flash WEn[0] */ + { 8, MPP_GPIO }, /* MICON int */ + { 9, MPP_GPIO }, /* RTC int */ + { 10, MPP_UNUSED }, + { 11, MPP_GPIO }, /* PCI Int A */ + { 12, MPP_UNUSED }, + { 13, MPP_GPIO }, /* UPS on UART0 enable */ + { 14, MPP_GPIO }, /* UPS low battery detection */ + { 15, MPP_UNUSED }, + { 16, MPP_UART }, /* UART1 RXD */ + { 17, MPP_UART }, /* UART1 TXD */ + { 18, MPP_UART }, /* UART1 CTSn */ + { 19, MPP_UART }, /* UART1 RTSn */ + { -1 }, +}; + +static void __init tsp2_init(void) +{ + /* + * Setup basic Orion functions. Need to be called early. + */ + orion5x_init(); + + orion5x_mpp_conf(tsp2_mpp_modes); + + /* + * Configure peripherals. + */ + orion5x_setup_dev_boot_win(TSP2_NOR_BOOT_BASE, + TSP2_NOR_BOOT_SIZE); + platform_device_register(&tsp2_nor_flash); + + orion5x_ehci0_init(); + orion5x_eth_init(&tsp2_eth_data); + orion5x_i2c_init(); + orion5x_uart0_init(); + orion5x_uart1_init(); + + /* Get RTC IRQ and register the chip */ + if (gpio_request(TSP2_RTC_GPIO, "rtc") == 0) { + if (gpio_direction_input(TSP2_RTC_GPIO) == 0) + tsp2_i2c_rtc.irq = gpio_to_irq(TSP2_RTC_GPIO); + else + gpio_free(TSP2_RTC_GPIO); + } + if (tsp2_i2c_rtc.irq == 0) + pr_warning("tsp2_init: failed to get RTC IRQ\n"); + i2c_register_board_info(0, &tsp2_i2c_rtc, 1); + + /* register Terastation Pro II specific power-off method */ + pm_power_off = tsp2_power_off; +} + +MACHINE_START(TERASTATION_PRO2, "Buffalo Terastation Pro II/Live") + /* Maintainer: Sylver Bruneau <sylver.bruneau@googlemail.com> */ + .phys_io = ORION5X_REGS_PHYS_BASE, + .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC, + .boot_params = 0x00000100, + .init_machine = tsp2_init, + .map_io = orion5x_map_io, + .init_irq = orion5x_init_irq, + .timer = &orion5x_timer, + .fixup = tag_fixup_mem32, +MACHINE_END diff --git a/arch/arm/mach-orion5x/ts209-setup.c b/arch/arm/mach-orion5x/ts209-setup.c index a9cef9703d5b..9d6890514199 100644 --- a/arch/arm/mach-orion5x/ts209-setup.c +++ b/arch/arm/mach-orion5x/ts209-setup.c @@ -26,7 +26,7 @@ #include <asm/gpio.h> #include <asm/mach/arch.h> #include <asm/mach/pci.h> -#include <asm/arch/orion5x.h> +#include <mach/orion5x.h> #include "common.h" #include "mpp.h" #include "tsx09-common.h" @@ -117,7 +117,7 @@ void __init qnap_ts209_pci_preinit(void) pin = QNAP_TS209_PCI_SLOT0_IRQ_PIN; if (gpio_request(pin, "PCI Int1") == 0) { if (gpio_direction_input(pin) == 0) { - set_irq_type(gpio_to_irq(pin), IRQT_LOW); + set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); } else { printk(KERN_ERR "qnap_ts209_pci_preinit failed to " "set_irq_type pin %d\n", pin); @@ -131,7 +131,7 @@ void __init qnap_ts209_pci_preinit(void) pin = QNAP_TS209_PCI_SLOT1_IRQ_PIN; if (gpio_request(pin, "PCI Int2") == 0) { if (gpio_direction_input(pin) == 0) { - set_irq_type(gpio_to_irq(pin), IRQT_LOW); + set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); } else { printk(KERN_ERR "qnap_ts209_pci_preinit failed " "to set_irq_type pin %d\n", pin); @@ -207,12 +207,12 @@ static struct i2c_board_info __initdata qnap_ts209_i2c_rtc = { static struct gpio_keys_button qnap_ts209_buttons[] = { { - .code = KEY_RESTART, + .code = KEY_COPY, .gpio = QNAP_TS209_GPIO_KEY_MEDIA, .desc = "USB Copy Button", .active_low = 1, }, { - .code = KEY_POWER, + .code = KEY_RESTART, .gpio = QNAP_TS209_GPIO_KEY_RESET, .desc = "Reset Button", .active_low = 1, @@ -287,6 +287,10 @@ static void __init qnap_ts209_init(void) /* * Configure peripherals. */ + orion5x_setup_dev_boot_win(QNAP_TS209_NOR_BOOT_BASE, + QNAP_TS209_NOR_BOOT_SIZE); + platform_device_register(&qnap_ts209_nor_flash); + orion5x_ehci0_init(); orion5x_ehci1_init(); qnap_tsx09_find_mac_addr(QNAP_TS209_NOR_BOOT_BASE + @@ -296,10 +300,8 @@ static void __init qnap_ts209_init(void) orion5x_i2c_init(); orion5x_sata_init(&qnap_ts209_sata_data); orion5x_uart0_init(); - - orion5x_setup_dev_boot_win(QNAP_TS209_NOR_BOOT_BASE, - QNAP_TS209_NOR_BOOT_SIZE); - platform_device_register(&qnap_ts209_nor_flash); + orion5x_uart1_init(); + orion5x_xor_init(); platform_device_register(&qnap_ts209_button_device); diff --git a/arch/arm/mach-orion5x/ts409-setup.c b/arch/arm/mach-orion5x/ts409-setup.c index 32f0ff073b7e..d85588ac7ef8 100644 --- a/arch/arm/mach-orion5x/ts409-setup.c +++ b/arch/arm/mach-orion5x/ts409-setup.c @@ -3,6 +3,9 @@ * * Maintainer: Sylver Bruneau <sylver.bruneau@gmail.com> * + * Copyright (C) 2008 Sylver Bruneau <sylver.bruneau@gmail.com> + * Copyright (C) 2008 Martin Michlmayr <tbm@cyrius.com> + * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation; either version @@ -16,6 +19,7 @@ #include <linux/irq.h> #include <linux/mtd/physmap.h> #include <linux/mv643xx_eth.h> +#include <linux/leds.h> #include <linux/gpio_keys.h> #include <linux/input.h> #include <linux/i2c.h> @@ -24,7 +28,7 @@ #include <asm/gpio.h> #include <asm/mach/arch.h> #include <asm/mach/pci.h> -#include <asm/arch/orion5x.h> +#include <mach/orion5x.h> #include "common.h" #include "mpp.h" #include "tsx09-common.h" @@ -162,16 +166,59 @@ static struct i2c_board_info __initdata qnap_ts409_i2c_rtc = { I2C_BOARD_INFO("s35390a", 0x30), }; +/***************************************************************************** + * LEDs attached to GPIO + ****************************************************************************/ + +static struct gpio_led ts409_led_pins[] = { + { + .name = "ts409:red:sata1", + .gpio = 4, + .active_low = 1, + }, { + .name = "ts409:red:sata2", + .gpio = 5, + .active_low = 1, + }, { + .name = "ts409:red:sata3", + .gpio = 6, + .active_low = 1, + }, { + .name = "ts409:red:sata4", + .gpio = 7, + .active_low = 1, + }, +}; + +static struct gpio_led_platform_data ts409_led_data = { + .leds = ts409_led_pins, + .num_leds = ARRAY_SIZE(ts409_led_pins), +}; + +static struct platform_device ts409_leds = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &ts409_led_data, + }, +}; + /**************************************************************************** * GPIO Attached Keys * Power button is attached to the PIC microcontroller ****************************************************************************/ +#define QNAP_TS409_GPIO_KEY_RESET 14 #define QNAP_TS409_GPIO_KEY_MEDIA 15 static struct gpio_keys_button qnap_ts409_buttons[] = { { .code = KEY_RESTART, + .gpio = QNAP_TS409_GPIO_KEY_RESET, + .desc = "Reset Button", + .active_low = 1, + }, { + .code = KEY_COPY, .gpio = QNAP_TS409_GPIO_KEY_MEDIA, .desc = "USB Copy Button", .active_low = 1, @@ -231,6 +278,10 @@ static void __init qnap_ts409_init(void) /* * Configure peripherals. */ + orion5x_setup_dev_boot_win(QNAP_TS409_NOR_BOOT_BASE, + QNAP_TS409_NOR_BOOT_SIZE); + platform_device_register(&qnap_ts409_nor_flash); + orion5x_ehci0_init(); qnap_tsx09_find_mac_addr(QNAP_TS409_NOR_BOOT_BASE + qnap_ts409_partitions[5].offset, @@ -238,10 +289,7 @@ static void __init qnap_ts409_init(void) orion5x_eth_init(&qnap_tsx09_eth_data); orion5x_i2c_init(); orion5x_uart0_init(); - - orion5x_setup_dev_boot_win(QNAP_TS409_NOR_BOOT_BASE, - QNAP_TS409_NOR_BOOT_SIZE); - platform_device_register(&qnap_ts409_nor_flash); + orion5x_uart1_init(); platform_device_register(&qnap_ts409_button_device); @@ -255,6 +303,7 @@ static void __init qnap_ts409_init(void) if (qnap_ts409_i2c_rtc.irq == 0) pr_warning("qnap_ts409_init: failed to get RTC IRQ\n"); i2c_register_board_info(0, &qnap_ts409_i2c_rtc, 1); + platform_device_register(&ts409_leds); /* register tsx09 specific power-off method */ pm_power_off = qnap_tsx09_power_off; diff --git a/arch/arm/mach-orion5x/ts78xx-setup.c b/arch/arm/mach-orion5x/ts78xx-setup.c index 77e9f351f07a..1368e9fd1a06 100644 --- a/arch/arm/mach-orion5x/ts78xx-setup.c +++ b/arch/arm/mach-orion5x/ts78xx-setup.c @@ -18,7 +18,7 @@ #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <asm/arch/orion5x.h> +#include <mach/orion5x.h> #include "common.h" #include "mpp.h" @@ -103,8 +103,7 @@ static struct platform_device ts78xx_nor_boot_flash = { * Ethernet ****************************************************************************/ static struct mv643xx_eth_platform_data ts78xx_eth_data = { - .phy_addr = 0, - .force_phy_addr = 1, + .phy_addr = MV643XX_ETH_PHY_ADDR(0), }; /***************************************************************************** @@ -256,6 +255,7 @@ static void __init ts78xx_init(void) orion5x_sata_init(&ts78xx_sata_data); orion5x_uart0_init(); orion5x_uart1_init(); + orion5x_xor_init(); orion5x_setup_dev_boot_win(TS78XX_NOR_BOOT_BASE, TS78XX_NOR_BOOT_SIZE); diff --git a/arch/arm/mach-orion5x/tsx09-common.c b/arch/arm/mach-orion5x/tsx09-common.c index 83feac3147a6..c9abb8fbfa70 100644 --- a/arch/arm/mach-orion5x/tsx09-common.c +++ b/arch/arm/mach-orion5x/tsx09-common.c @@ -16,6 +16,7 @@ #include <linux/timex.h> #include <linux/serial_reg.h> #include "tsx09-common.h" +#include "common.h" /***************************************************************************** * QNAP TS-x09 specific power off method via UART1-attached PIC @@ -26,7 +27,7 @@ void qnap_tsx09_power_off(void) { /* 19200 baud divisor */ - const unsigned divisor = ((ORION5X_TCLK + (8 * 19200)) / (16 * 19200)); + const unsigned divisor = ((orion5x_tclk + (8 * 19200)) / (16 * 19200)); pr_info("%s: triggering power-off...\n", __func__); @@ -48,7 +49,7 @@ void qnap_tsx09_power_off(void) ****************************************************************************/ struct mv643xx_eth_platform_data qnap_tsx09_eth_data = { - .phy_addr = 8, + .phy_addr = MV643XX_ETH_PHY_ADDR(8), }; static int __init qnap_tsx09_parse_hex_nibble(char n) diff --git a/arch/arm/mach-orion5x/wnr854t-setup.c b/arch/arm/mach-orion5x/wnr854t-setup.c index 1af093ff8cf3..7ddc22c2bb54 100644 --- a/arch/arm/mach-orion5x/wnr854t-setup.c +++ b/arch/arm/mach-orion5x/wnr854t-setup.c @@ -14,11 +14,12 @@ #include <linux/delay.h> #include <linux/mtd/physmap.h> #include <linux/mv643xx_eth.h> +#include <linux/ethtool.h> #include <asm/mach-types.h> #include <asm/gpio.h> #include <asm/mach/arch.h> #include <asm/mach/pci.h> -#include <asm/arch/orion5x.h> +#include <mach/orion5x.h> #include "common.h" #include "mpp.h" @@ -91,7 +92,9 @@ static struct platform_device wnr854t_nor_flash = { }; static struct mv643xx_eth_platform_data wnr854t_eth_data = { - .phy_addr = -1, + .phy_addr = MV643XX_ETH_PHY_NONE, + .speed = SPEED_1000, + .duplex = DUPLEX_FULL, }; static void __init wnr854t_init(void) diff --git a/arch/arm/mach-orion5x/wrt350n-v2-setup.c b/arch/arm/mach-orion5x/wrt350n-v2-setup.c index aeab55c6a82d..9a4fd5256462 100644 --- a/arch/arm/mach-orion5x/wrt350n-v2-setup.c +++ b/arch/arm/mach-orion5x/wrt350n-v2-setup.c @@ -14,11 +14,12 @@ #include <linux/delay.h> #include <linux/mtd/physmap.h> #include <linux/mv643xx_eth.h> +#include <linux/ethtool.h> #include <asm/mach-types.h> #include <asm/gpio.h> #include <asm/mach/arch.h> #include <asm/mach/pci.h> -#include <asm/arch/orion5x.h> +#include <mach/orion5x.h> #include "common.h" #include "mpp.h" @@ -99,7 +100,9 @@ static struct platform_device wrt350n_v2_nor_flash = { }; static struct mv643xx_eth_platform_data wrt350n_v2_eth_data = { - .phy_addr = -1, + .phy_addr = MV643XX_ETH_PHY_NONE, + .speed = SPEED_1000, + .duplex = DUPLEX_FULL, }; static void __init wrt350n_v2_init(void) |