diff options
Diffstat (limited to 'arch/arm/mach-omap2/mcbsp.c')
-rw-r--r-- | arch/arm/mach-omap2/mcbsp.c | 613 |
1 files changed, 495 insertions, 118 deletions
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c index 0526b758bdcc..765ebe7da723 100644 --- a/arch/arm/mach-omap2/mcbsp.c +++ b/arch/arm/mach-omap2/mcbsp.c @@ -105,173 +105,542 @@ EXPORT_SYMBOL(omap2_mcbsp_set_clks_src); /* Platform data */ #ifdef CONFIG_SOC_OMAP2420 -static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = { +struct resource omap2420_mcbsp_res[][6] = { { - .phys_base = OMAP24XX_MCBSP1_BASE, - .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX, - .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX, - .rx_irq = INT_24XX_MCBSP1_IRQ_RX, - .tx_irq = INT_24XX_MCBSP1_IRQ_TX, + { + .start = OMAP24XX_MCBSP1_BASE, + .end = OMAP24XX_MCBSP1_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "rx", + .start = INT_24XX_MCBSP1_IRQ_RX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "tx", + .start = INT_24XX_MCBSP1_IRQ_TX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "rx", + .start = OMAP24XX_DMA_MCBSP1_RX, + .flags = IORESOURCE_DMA, + }, + { + .name = "tx", + .start = OMAP24XX_DMA_MCBSP1_TX, + .flags = IORESOURCE_DMA, + }, }, { - .phys_base = OMAP24XX_MCBSP2_BASE, - .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX, - .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX, - .rx_irq = INT_24XX_MCBSP2_IRQ_RX, - .tx_irq = INT_24XX_MCBSP2_IRQ_TX, + { + .start = OMAP24XX_MCBSP2_BASE, + .end = OMAP24XX_MCBSP2_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "rx", + .start = INT_24XX_MCBSP2_IRQ_RX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "tx", + .start = INT_24XX_MCBSP2_IRQ_TX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "rx", + .start = OMAP24XX_DMA_MCBSP2_RX, + .flags = IORESOURCE_DMA, + }, + { + .name = "tx", + .start = OMAP24XX_DMA_MCBSP2_TX, + .flags = IORESOURCE_DMA, + }, }, }; -#define OMAP2420_MCBSP_PDATA_SZ ARRAY_SIZE(omap2420_mcbsp_pdata) -#define OMAP2420_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1) +#define OMAP2420_MCBSP_RES_SZ ARRAY_SIZE(omap2420_mcbsp_res[1]) +#define OMAP2420_MCBSP_COUNT ARRAY_SIZE(omap2420_mcbsp_res) #else -#define omap2420_mcbsp_pdata NULL -#define OMAP2420_MCBSP_PDATA_SZ 0 -#define OMAP2420_MCBSP_REG_NUM 0 +#define omap2420_mcbsp_res NULL +#define OMAP2420_MCBSP_RES_SZ 0 +#define OMAP2420_MCBSP_COUNT 0 #endif +#define omap2420_mcbsp_pdata NULL + #ifdef CONFIG_SOC_OMAP2430 -static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = { +struct resource omap2430_mcbsp_res[][6] = { { - .phys_base = OMAP24XX_MCBSP1_BASE, - .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX, - .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX, - .rx_irq = INT_24XX_MCBSP1_IRQ_RX, - .tx_irq = INT_24XX_MCBSP1_IRQ_TX, + { + .start = OMAP24XX_MCBSP1_BASE, + .end = OMAP24XX_MCBSP1_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "rx", + .start = INT_24XX_MCBSP1_IRQ_RX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "tx", + .start = INT_24XX_MCBSP1_IRQ_TX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "rx", + .start = OMAP24XX_DMA_MCBSP1_RX, + .flags = IORESOURCE_DMA, + }, + { + .name = "tx", + .start = OMAP24XX_DMA_MCBSP1_TX, + .flags = IORESOURCE_DMA, + }, }, { - .phys_base = OMAP24XX_MCBSP2_BASE, - .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX, - .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX, - .rx_irq = INT_24XX_MCBSP2_IRQ_RX, - .tx_irq = INT_24XX_MCBSP2_IRQ_TX, + { + .start = OMAP24XX_MCBSP2_BASE, + .end = OMAP24XX_MCBSP2_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "rx", + .start = INT_24XX_MCBSP2_IRQ_RX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "tx", + .start = INT_24XX_MCBSP2_IRQ_TX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "rx", + .start = OMAP24XX_DMA_MCBSP2_RX, + .flags = IORESOURCE_DMA, + }, + { + .name = "tx", + .start = OMAP24XX_DMA_MCBSP2_TX, + .flags = IORESOURCE_DMA, + }, }, { - .phys_base = OMAP2430_MCBSP3_BASE, - .dma_rx_sync = OMAP24XX_DMA_MCBSP3_RX, - .dma_tx_sync = OMAP24XX_DMA_MCBSP3_TX, - .rx_irq = INT_24XX_MCBSP3_IRQ_RX, - .tx_irq = INT_24XX_MCBSP3_IRQ_TX, + { + .start = OMAP2430_MCBSP3_BASE, + .end = OMAP2430_MCBSP3_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "rx", + .start = INT_24XX_MCBSP3_IRQ_RX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "tx", + .start = INT_24XX_MCBSP3_IRQ_TX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "rx", + .start = OMAP24XX_DMA_MCBSP3_RX, + .flags = IORESOURCE_DMA, + }, + { + .name = "tx", + .start = OMAP24XX_DMA_MCBSP3_TX, + .flags = IORESOURCE_DMA, + }, }, { - .phys_base = OMAP2430_MCBSP4_BASE, - .dma_rx_sync = OMAP24XX_DMA_MCBSP4_RX, - .dma_tx_sync = OMAP24XX_DMA_MCBSP4_TX, - .rx_irq = INT_24XX_MCBSP4_IRQ_RX, - .tx_irq = INT_24XX_MCBSP4_IRQ_TX, + { + .start = OMAP2430_MCBSP4_BASE, + .end = OMAP2430_MCBSP4_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "rx", + .start = INT_24XX_MCBSP4_IRQ_RX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "tx", + .start = INT_24XX_MCBSP4_IRQ_TX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "rx", + .start = OMAP24XX_DMA_MCBSP4_RX, + .flags = IORESOURCE_DMA, + }, + { + .name = "tx", + .start = OMAP24XX_DMA_MCBSP4_TX, + .flags = IORESOURCE_DMA, + }, }, { - .phys_base = OMAP2430_MCBSP5_BASE, - .dma_rx_sync = OMAP24XX_DMA_MCBSP5_RX, - .dma_tx_sync = OMAP24XX_DMA_MCBSP5_TX, - .rx_irq = INT_24XX_MCBSP5_IRQ_RX, - .tx_irq = INT_24XX_MCBSP5_IRQ_TX, + { + .start = OMAP2430_MCBSP5_BASE, + .end = OMAP2430_MCBSP5_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "rx", + .start = INT_24XX_MCBSP5_IRQ_RX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "tx", + .start = INT_24XX_MCBSP5_IRQ_TX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "rx", + .start = OMAP24XX_DMA_MCBSP5_RX, + .flags = IORESOURCE_DMA, + }, + { + .name = "tx", + .start = OMAP24XX_DMA_MCBSP5_TX, + .flags = IORESOURCE_DMA, + }, }, }; -#define OMAP2430_MCBSP_PDATA_SZ ARRAY_SIZE(omap2430_mcbsp_pdata) -#define OMAP2430_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1) +#define OMAP2430_MCBSP_RES_SZ ARRAY_SIZE(omap2430_mcbsp_res[1]) +#define OMAP2430_MCBSP_COUNT ARRAY_SIZE(omap2430_mcbsp_res) #else -#define omap2430_mcbsp_pdata NULL -#define OMAP2430_MCBSP_PDATA_SZ 0 -#define OMAP2430_MCBSP_REG_NUM 0 +#define omap2430_mcbsp_res NULL +#define OMAP2430_MCBSP_RES_SZ 0 +#define OMAP2430_MCBSP_COUNT 0 #endif +#define omap2430_mcbsp_pdata NULL + #ifdef CONFIG_ARCH_OMAP3 +struct resource omap34xx_mcbsp_res[][7] = { + { + { + .start = OMAP34XX_MCBSP1_BASE, + .end = OMAP34XX_MCBSP1_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "rx", + .start = INT_24XX_MCBSP1_IRQ_RX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "tx", + .start = INT_24XX_MCBSP1_IRQ_TX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "rx", + .start = OMAP24XX_DMA_MCBSP1_RX, + .flags = IORESOURCE_DMA, + }, + { + .name = "tx", + .start = OMAP24XX_DMA_MCBSP1_TX, + .flags = IORESOURCE_DMA, + }, + }, + { + { + .start = OMAP34XX_MCBSP2_BASE, + .end = OMAP34XX_MCBSP2_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "sidetone", + .start = OMAP34XX_MCBSP2_ST_BASE, + .end = OMAP34XX_MCBSP2_ST_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "rx", + .start = INT_24XX_MCBSP2_IRQ_RX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "tx", + .start = INT_24XX_MCBSP2_IRQ_TX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "rx", + .start = OMAP24XX_DMA_MCBSP2_RX, + .flags = IORESOURCE_DMA, + }, + { + .name = "tx", + .start = OMAP24XX_DMA_MCBSP2_TX, + .flags = IORESOURCE_DMA, + }, + }, + { + { + .start = OMAP34XX_MCBSP3_BASE, + .end = OMAP34XX_MCBSP3_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "sidetone", + .start = OMAP34XX_MCBSP3_ST_BASE, + .end = OMAP34XX_MCBSP3_ST_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "rx", + .start = INT_24XX_MCBSP3_IRQ_RX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "tx", + .start = INT_24XX_MCBSP3_IRQ_TX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "rx", + .start = OMAP24XX_DMA_MCBSP3_RX, + .flags = IORESOURCE_DMA, + }, + { + .name = "tx", + .start = OMAP24XX_DMA_MCBSP3_TX, + .flags = IORESOURCE_DMA, + }, + }, + { + { + .start = OMAP34XX_MCBSP4_BASE, + .end = OMAP34XX_MCBSP4_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "rx", + .start = INT_24XX_MCBSP4_IRQ_RX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "tx", + .start = INT_24XX_MCBSP4_IRQ_TX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "rx", + .start = OMAP24XX_DMA_MCBSP4_RX, + .flags = IORESOURCE_DMA, + }, + { + .name = "tx", + .start = OMAP24XX_DMA_MCBSP4_TX, + .flags = IORESOURCE_DMA, + }, + }, + { + { + .start = OMAP34XX_MCBSP5_BASE, + .end = OMAP34XX_MCBSP5_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "rx", + .start = INT_24XX_MCBSP5_IRQ_RX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "tx", + .start = INT_24XX_MCBSP5_IRQ_TX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "rx", + .start = OMAP24XX_DMA_MCBSP5_RX, + .flags = IORESOURCE_DMA, + }, + { + .name = "tx", + .start = OMAP24XX_DMA_MCBSP5_TX, + .flags = IORESOURCE_DMA, + }, + }, +}; + static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { { - .phys_base = OMAP34XX_MCBSP1_BASE, - .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX, - .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX, - .rx_irq = INT_24XX_MCBSP1_IRQ_RX, - .tx_irq = INT_24XX_MCBSP1_IRQ_TX, .buffer_size = 0x80, /* The FIFO has 128 locations */ }, { - .phys_base = OMAP34XX_MCBSP2_BASE, - .phys_base_st = OMAP34XX_MCBSP2_ST_BASE, - .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX, - .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX, - .rx_irq = INT_24XX_MCBSP2_IRQ_RX, - .tx_irq = INT_24XX_MCBSP2_IRQ_TX, .buffer_size = 0x500, /* The FIFO has 1024 + 256 locations */ }, { - .phys_base = OMAP34XX_MCBSP3_BASE, - .phys_base_st = OMAP34XX_MCBSP3_ST_BASE, - .dma_rx_sync = OMAP24XX_DMA_MCBSP3_RX, - .dma_tx_sync = OMAP24XX_DMA_MCBSP3_TX, - .rx_irq = INT_24XX_MCBSP3_IRQ_RX, - .tx_irq = INT_24XX_MCBSP3_IRQ_TX, .buffer_size = 0x80, /* The FIFO has 128 locations */ }, { - .phys_base = OMAP34XX_MCBSP4_BASE, - .dma_rx_sync = OMAP24XX_DMA_MCBSP4_RX, - .dma_tx_sync = OMAP24XX_DMA_MCBSP4_TX, - .rx_irq = INT_24XX_MCBSP4_IRQ_RX, - .tx_irq = INT_24XX_MCBSP4_IRQ_TX, .buffer_size = 0x80, /* The FIFO has 128 locations */ }, { - .phys_base = OMAP34XX_MCBSP5_BASE, - .dma_rx_sync = OMAP24XX_DMA_MCBSP5_RX, - .dma_tx_sync = OMAP24XX_DMA_MCBSP5_TX, - .rx_irq = INT_24XX_MCBSP5_IRQ_RX, - .tx_irq = INT_24XX_MCBSP5_IRQ_TX, .buffer_size = 0x80, /* The FIFO has 128 locations */ }, }; -#define OMAP34XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap34xx_mcbsp_pdata) -#define OMAP34XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1) +#define OMAP34XX_MCBSP_RES_SZ ARRAY_SIZE(omap34xx_mcbsp_res[1]) +#define OMAP34XX_MCBSP_COUNT ARRAY_SIZE(omap34xx_mcbsp_res) #else #define omap34xx_mcbsp_pdata NULL -#define OMAP34XX_MCBSP_PDATA_SZ 0 -#define OMAP34XX_MCBSP_REG_NUM 0 +#define omap34XX_mcbsp_res NULL +#define OMAP34XX_MCBSP_RES_SZ 0 +#define OMAP34XX_MCBSP_COUNT 0 #endif -static struct omap_mcbsp_platform_data omap44xx_mcbsp_pdata[] = { +struct resource omap44xx_mcbsp_res[][6] = { { - .phys_base = OMAP44XX_MCBSP1_BASE, - .dma_rx_sync = OMAP44XX_DMA_MCBSP1_RX, - .dma_tx_sync = OMAP44XX_DMA_MCBSP1_TX, - .tx_irq = OMAP44XX_IRQ_MCBSP1, + { + .name = "mpu", + .start = OMAP44XX_MCBSP1_BASE, + .end = OMAP44XX_MCBSP1_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "dma", + .start = OMAP44XX_MCBSP1_DMA_BASE, + .end = OMAP44XX_MCBSP1_DMA_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "rx", + .start = 0, + .flags = IORESOURCE_IRQ, + }, + { + .name = "tx", + .start = OMAP44XX_IRQ_MCBSP1, + .flags = IORESOURCE_IRQ, + }, + { + .name = "rx", + .start = OMAP44XX_DMA_MCBSP1_RX, + .flags = IORESOURCE_DMA, + }, + { + .name = "tx", + .start = OMAP44XX_DMA_MCBSP1_TX, + .flags = IORESOURCE_DMA, + }, }, { - .phys_base = OMAP44XX_MCBSP2_BASE, - .dma_rx_sync = OMAP44XX_DMA_MCBSP2_RX, - .dma_tx_sync = OMAP44XX_DMA_MCBSP2_TX, - .tx_irq = OMAP44XX_IRQ_MCBSP2, + { + .name = "mpu", + .start = OMAP44XX_MCBSP2_BASE, + .end = OMAP44XX_MCBSP2_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "dma", + .start = OMAP44XX_MCBSP2_DMA_BASE, + .end = OMAP44XX_MCBSP2_DMA_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "rx", + .start = 0, + .flags = IORESOURCE_IRQ, + }, + { + .name = "tx", + .start = OMAP44XX_IRQ_MCBSP2, + .flags = IORESOURCE_IRQ, + }, + { + .name = "rx", + .start = OMAP44XX_DMA_MCBSP2_RX, + .flags = IORESOURCE_DMA, + }, + { + .name = "tx", + .start = OMAP44XX_DMA_MCBSP2_TX, + .flags = IORESOURCE_DMA, + }, }, { - .phys_base = OMAP44XX_MCBSP3_BASE, - .dma_rx_sync = OMAP44XX_DMA_MCBSP3_RX, - .dma_tx_sync = OMAP44XX_DMA_MCBSP3_TX, - .tx_irq = OMAP44XX_IRQ_MCBSP3, + { + .name = "mpu", + .start = OMAP44XX_MCBSP3_BASE, + .end = OMAP44XX_MCBSP3_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "dma", + .start = OMAP44XX_MCBSP3_DMA_BASE, + .end = OMAP44XX_MCBSP3_DMA_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "rx", + .start = 0, + .flags = IORESOURCE_IRQ, + }, + { + .name = "tx", + .start = OMAP44XX_IRQ_MCBSP3, + .flags = IORESOURCE_IRQ, + }, + { + .name = "rx", + .start = OMAP44XX_DMA_MCBSP3_RX, + .flags = IORESOURCE_DMA, + }, + { + .name = "tx", + .start = OMAP44XX_DMA_MCBSP3_TX, + .flags = IORESOURCE_DMA, + }, }, { - .phys_base = OMAP44XX_MCBSP4_BASE, - .dma_rx_sync = OMAP44XX_DMA_MCBSP4_RX, - .dma_tx_sync = OMAP44XX_DMA_MCBSP4_TX, - .tx_irq = OMAP44XX_IRQ_MCBSP4, + { + .start = OMAP44XX_MCBSP4_BASE, + .end = OMAP44XX_MCBSP4_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "rx", + .start = 0, + .flags = IORESOURCE_IRQ, + }, + { + .name = "tx", + .start = OMAP44XX_IRQ_MCBSP4, + .flags = IORESOURCE_IRQ, + }, + { + .name = "rx", + .start = OMAP44XX_DMA_MCBSP4_RX, + .flags = IORESOURCE_DMA, + }, + { + .name = "tx", + .start = OMAP44XX_DMA_MCBSP4_TX, + .flags = IORESOURCE_DMA, + }, }, }; -#define OMAP44XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap44xx_mcbsp_pdata) -#define OMAP44XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1) +#define omap44xx_mcbsp_pdata NULL +#define OMAP44XX_MCBSP_RES_SZ ARRAY_SIZE(omap44xx_mcbsp_res[1]) +#define OMAP44XX_MCBSP_COUNT ARRAY_SIZE(omap44xx_mcbsp_res) static int __init omap2_mcbsp_init(void) { - if (cpu_is_omap2420()) { - omap_mcbsp_count = OMAP2420_MCBSP_PDATA_SZ; - omap_mcbsp_cache_size = OMAP2420_MCBSP_REG_NUM * sizeof(u16); - } else if (cpu_is_omap2430()) { - omap_mcbsp_count = OMAP2430_MCBSP_PDATA_SZ; - omap_mcbsp_cache_size = OMAP2430_MCBSP_REG_NUM * sizeof(u32); - } else if (cpu_is_omap34xx()) { - omap_mcbsp_count = OMAP34XX_MCBSP_PDATA_SZ; - omap_mcbsp_cache_size = OMAP34XX_MCBSP_REG_NUM * sizeof(u32); - } else if (cpu_is_omap44xx()) { - omap_mcbsp_count = OMAP44XX_MCBSP_PDATA_SZ; - omap_mcbsp_cache_size = OMAP44XX_MCBSP_REG_NUM * sizeof(u32); - } + if (cpu_is_omap2420()) + omap_mcbsp_count = OMAP2420_MCBSP_COUNT; + else if (cpu_is_omap2430()) + omap_mcbsp_count = OMAP2430_MCBSP_COUNT; + else if (cpu_is_omap34xx()) + omap_mcbsp_count = OMAP34XX_MCBSP_COUNT; + else if (cpu_is_omap44xx()) + omap_mcbsp_count = OMAP44XX_MCBSP_COUNT; mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *), GFP_KERNEL); @@ -279,17 +648,25 @@ static int __init omap2_mcbsp_init(void) return -ENOMEM; if (cpu_is_omap2420()) - omap_mcbsp_register_board_cfg(omap2420_mcbsp_pdata, - OMAP2420_MCBSP_PDATA_SZ); + omap_mcbsp_register_board_cfg(omap2420_mcbsp_res[0], + OMAP2420_MCBSP_RES_SZ, + omap2420_mcbsp_pdata, + OMAP2420_MCBSP_COUNT); if (cpu_is_omap2430()) - omap_mcbsp_register_board_cfg(omap2430_mcbsp_pdata, - OMAP2430_MCBSP_PDATA_SZ); + omap_mcbsp_register_board_cfg(omap2430_mcbsp_res[0], + OMAP2420_MCBSP_RES_SZ, + omap2430_mcbsp_pdata, + OMAP2430_MCBSP_COUNT); if (cpu_is_omap34xx()) - omap_mcbsp_register_board_cfg(omap34xx_mcbsp_pdata, - OMAP34XX_MCBSP_PDATA_SZ); + omap_mcbsp_register_board_cfg(omap34xx_mcbsp_res[0], + OMAP34XX_MCBSP_RES_SZ, + omap34xx_mcbsp_pdata, + OMAP34XX_MCBSP_COUNT); if (cpu_is_omap44xx()) - omap_mcbsp_register_board_cfg(omap44xx_mcbsp_pdata, - OMAP44XX_MCBSP_PDATA_SZ); + omap_mcbsp_register_board_cfg(omap44xx_mcbsp_res[0], + OMAP44XX_MCBSP_RES_SZ, + omap44xx_mcbsp_pdata, + OMAP44XX_MCBSP_COUNT); return omap_mcbsp_init(); } |