diff options
Diffstat (limited to 'arch/arm/mach-omap1')
| -rw-r--r-- | arch/arm/mach-omap1/Kconfig | 10 | ||||
| -rw-r--r-- | arch/arm/mach-omap1/Makefile | 1 | ||||
| -rw-r--r-- | arch/arm/mach-omap1/ams-delta-fiq-handler.S | 278 | ||||
| -rw-r--r-- | arch/arm/mach-omap1/ams-delta-fiq.c | 155 | ||||
| -rw-r--r-- | arch/arm/mach-omap1/board-ams-delta.c | 18 | ||||
| -rw-r--r-- | arch/arm/mach-omap1/clock.c | 2 | ||||
| -rw-r--r-- | arch/arm/mach-omap1/clock.h | 2 | ||||
| -rw-r--r-- | arch/arm/mach-omap1/include/mach/ams-delta-fiq.h | 79 | ||||
| -rw-r--r-- | arch/arm/mach-omap1/include/mach/debug-macro.S | 21 |
9 files changed, 548 insertions, 18 deletions
diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig index 27f489747bbd..b18d7c28ab7a 100644 --- a/arch/arm/mach-omap1/Kconfig +++ b/arch/arm/mach-omap1/Kconfig @@ -152,6 +152,16 @@ config MACH_AMS_DELTA Support for the Amstrad E3 (codename Delta) videophone. Say Y here if you have such a device. +config AMS_DELTA_FIQ + bool "Fast Interrupt Request (FIQ) support for the E3" + depends on MACH_AMS_DELTA + select FIQ + help + Provide a FIQ handler for the E3. + This allows for fast handling of interrupts generated + by the clock line of the E3 mailboard (or a PS/2 keyboard) + connected to the GPIO based external keyboard port. + config MACH_OMAP_GENERIC bool "Generic OMAP board" depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX) diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile index b6a537c875b8..ea231c7a550a 100644 --- a/arch/arm/mach-omap1/Makefile +++ b/arch/arm/mach-omap1/Makefile @@ -37,6 +37,7 @@ obj-$(CONFIG_MACH_OMAP_PALMZ71) += board-palmz71.o obj-$(CONFIG_MACH_OMAP_PALMTT) += board-palmtt.o obj-$(CONFIG_MACH_NOKIA770) += board-nokia770.o obj-$(CONFIG_MACH_AMS_DELTA) += board-ams-delta.o +obj-$(CONFIG_AMS_DELTA_FIQ) += ams-delta-fiq.o ams-delta-fiq-handler.o obj-$(CONFIG_MACH_SX1) += board-sx1.o board-sx1-mmc.o obj-$(CONFIG_MACH_HERALD) += board-htcherald.o diff --git a/arch/arm/mach-omap1/ams-delta-fiq-handler.S b/arch/arm/mach-omap1/ams-delta-fiq-handler.S new file mode 100644 index 000000000000..927d5a181760 --- /dev/null +++ b/arch/arm/mach-omap1/ams-delta-fiq-handler.S @@ -0,0 +1,278 @@ +/* + * linux/arch/arm/mach-omap1/ams-delta-fiq-handler.S + * + * Based on linux/arch/arm/lib/floppydma.S + * Renamed and modified to work with 2.6 kernel by Matt Callow + * Copyright (C) 1995, 1996 Russell King + * Copyright (C) 2004 Pete Trapps + * Copyright (C) 2006 Matt Callow + * Copyright (C) 2010 Janusz Krzysztofik + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + */ + +#include <linux/linkage.h> + +#include <plat/io.h> +#include <plat/board-ams-delta.h> + +#include <mach/ams-delta-fiq.h> + +/* + * GPIO related definitions, copied from arch/arm/plat-omap/gpio.c. + * Unfortunately, those were not placed in a separate header file. + */ +#define OMAP1510_GPIO_BASE 0xFFFCE000 +#define OMAP1510_GPIO_DATA_INPUT 0x00 +#define OMAP1510_GPIO_DATA_OUTPUT 0x04 +#define OMAP1510_GPIO_DIR_CONTROL 0x08 +#define OMAP1510_GPIO_INT_CONTROL 0x0c +#define OMAP1510_GPIO_INT_MASK 0x10 +#define OMAP1510_GPIO_INT_STATUS 0x14 +#define OMAP1510_GPIO_PIN_CONTROL 0x18 + +/* GPIO register bitmasks */ +#define KEYBRD_DATA_MASK (0x1 << AMS_DELTA_GPIO_PIN_KEYBRD_DATA) +#define KEYBRD_CLK_MASK (0x1 << AMS_DELTA_GPIO_PIN_KEYBRD_CLK) +#define MODEM_IRQ_MASK (0x1 << AMS_DELTA_GPIO_PIN_MODEM_IRQ) +#define HOOK_SWITCH_MASK (0x1 << AMS_DELTA_GPIO_PIN_HOOK_SWITCH) +#define OTHERS_MASK (MODEM_IRQ_MASK | HOOK_SWITCH_MASK) + +/* IRQ handler register bitmasks */ +#define DEFERRED_FIQ_MASK (0x1 << (INT_DEFERRED_FIQ % IH2_BASE)) +#define GPIO_BANK1_MASK (0x1 << INT_GPIO_BANK1) + +/* Driver buffer byte offsets */ +#define BUF_MASK (FIQ_MASK * 4) +#define BUF_STATE (FIQ_STATE * 4) +#define BUF_KEYS_CNT (FIQ_KEYS_CNT * 4) +#define BUF_TAIL_OFFSET (FIQ_TAIL_OFFSET * 4) +#define BUF_HEAD_OFFSET (FIQ_HEAD_OFFSET * 4) +#define BUF_BUF_LEN (FIQ_BUF_LEN * 4) +#define BUF_KEY (FIQ_KEY * 4) +#define BUF_MISSED_KEYS (FIQ_MISSED_KEYS * 4) +#define BUF_BUFFER_START (FIQ_BUFFER_START * 4) +#define BUF_GPIO_INT_MASK (FIQ_GPIO_INT_MASK * 4) +#define BUF_KEYS_HICNT (FIQ_KEYS_HICNT * 4) +#define BUF_IRQ_PEND (FIQ_IRQ_PEND * 4) +#define BUF_SIR_CODE_L1 (FIQ_SIR_CODE_L1 * 4) +#define BUF_SIR_CODE_L2 (IRQ_SIR_CODE_L2 * 4) +#define BUF_CNT_INT_00 (FIQ_CNT_INT_00 * 4) +#define BUF_CNT_INT_KEY (FIQ_CNT_INT_KEY * 4) +#define BUF_CNT_INT_MDM (FIQ_CNT_INT_MDM * 4) +#define BUF_CNT_INT_03 (FIQ_CNT_INT_03 * 4) +#define BUF_CNT_INT_HSW (FIQ_CNT_INT_HSW * 4) +#define BUF_CNT_INT_05 (FIQ_CNT_INT_05 * 4) +#define BUF_CNT_INT_06 (FIQ_CNT_INT_06 * 4) +#define BUF_CNT_INT_07 (FIQ_CNT_INT_07 * 4) +#define BUF_CNT_INT_08 (FIQ_CNT_INT_08 * 4) +#define BUF_CNT_INT_09 (FIQ_CNT_INT_09 * 4) +#define BUF_CNT_INT_10 (FIQ_CNT_INT_10 * 4) +#define BUF_CNT_INT_11 (FIQ_CNT_INT_11 * 4) +#define BUF_CNT_INT_12 (FIQ_CNT_INT_12 * 4) +#define BUF_CNT_INT_13 (FIQ_CNT_INT_13 * 4) +#define BUF_CNT_INT_14 (FIQ_CNT_INT_14 * 4) +#define BUF_CNT_INT_15 (FIQ_CNT_INT_15 * 4) +#define BUF_CIRC_BUFF (FIQ_CIRC_BUFF * 4) + + +/* + * Register useage + * r8 - temporary + * r9 - the driver buffer + * r10 - temporary + * r11 - interrupts mask + * r12 - base pointers + * r13 - interrupts status + */ + + .text + + .global qwerty_fiqin_end + +ENTRY(qwerty_fiqin_start) + @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ + @ FIQ intrrupt handler + ldr r12, omap_ih1_base @ set pointer to level1 handler + + ldr r11, [r12, #IRQ_MIR_REG_OFFSET] @ fetch interrupts mask + + ldr r13, [r12, #IRQ_ITR_REG_OFFSET] @ fetch interrupts status + bics r13, r13, r11 @ clear masked - any left? + beq exit @ none - spurious FIQ? exit + + ldr r10, [r12, #IRQ_SIR_FIQ_REG_OFFSET] @ get requested interrupt number + + mov r8, #2 @ reset FIQ agreement + str r8, [r12, #IRQ_CONTROL_REG_OFFSET] + + cmp r10, #INT_GPIO_BANK1 @ is it GPIO bank interrupt? + beq gpio @ yes - process it + + mov r8, #1 + orr r8, r11, r8, lsl r10 @ mask spurious interrupt + str r8, [r12, #IRQ_MIR_REG_OFFSET] +exit: + subs pc, lr, #4 @ return from FIQ + @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ + + + @@@@@@@@@@@@@@@@@@@@@@@@@@@ +gpio: @ GPIO bank interrupt handler + ldr r12, omap1510_gpio_base @ set base pointer to GPIO bank + + ldr r11, [r12, #OMAP1510_GPIO_INT_MASK] @ fetch GPIO interrupts mask +restart: + ldr r13, [r12, #OMAP1510_GPIO_INT_STATUS] @ fetch status bits + bics r13, r13, r11 @ clear masked - any left? + beq exit @ no - spurious interrupt? exit + + orr r11, r11, r13 @ mask all requested interrupts + str r11, [r12, #OMAP1510_GPIO_INT_MASK] + + ands r10, r13, #KEYBRD_CLK_MASK @ extract keyboard status - set? + beq hksw @ no - try next source + + + @@@@@@@@@@@@@@@@@@@@@@ + @ Keyboard clock FIQ mode interrupt handler + @ r10 now contains KEYBRD_CLK_MASK, use it + str r10, [r12, #OMAP1510_GPIO_INT_STATUS] @ ack the interrupt + bic r11, r11, r10 @ unmask it + str r11, [r12, #OMAP1510_GPIO_INT_MASK] + + @ Process keyboard data + ldr r8, [r12, #OMAP1510_GPIO_DATA_INPUT] @ fetch GPIO input + + ldr r10, [r9, #BUF_STATE] @ fetch kbd interface state + cmp r10, #0 @ are we expecting start bit? + bne data @ no - go to data processing + + ands r8, r8, #KEYBRD_DATA_MASK @ check start bit - detected? + beq hksw @ no - try next source + + @ r8 contains KEYBRD_DATA_MASK, use it + str r8, [r9, #BUF_STATE] @ enter data processing state + @ r10 already contains 0, reuse it + str r10, [r9, #BUF_KEY] @ clear keycode + mov r10, #2 @ reset input bit mask + str r10, [r9, #BUF_MASK] + + @ Mask other GPIO line interrupts till key done + str r11, [r9, #BUF_GPIO_INT_MASK] @ save mask for later restore + mvn r11, #KEYBRD_CLK_MASK @ prepare all except kbd mask + str r11, [r12, #OMAP1510_GPIO_INT_MASK] @ store into the mask register + + b restart @ restart + +data: ldr r10, [r9, #BUF_MASK] @ fetch current input bit mask + + @ r8 still contains GPIO input bits + ands r8, r8, #KEYBRD_DATA_MASK @ is keyboard data line low? + ldreq r8, [r9, #BUF_KEY] @ yes - fetch collected so far, + orreq r8, r8, r10 @ set 1 at current mask position + streq r8, [r9, #BUF_KEY] @ and save back + + mov r10, r10, lsl #1 @ shift mask left + bics r10, r10, #0x800 @ have we got all the bits? + strne r10, [r9, #BUF_MASK] @ not yet - store the mask + bne restart @ and restart + + @ r10 already contains 0, reuse it + str r10, [r9, #BUF_STATE] @ reset state to start + + @ Key done - restore interrupt mask + ldr r10, [r9, #BUF_GPIO_INT_MASK] @ fetch saved mask + and r11, r11, r10 @ unmask all saved as unmasked + str r11, [r12, #OMAP1510_GPIO_INT_MASK] @ restore into the mask register + + @ Try appending the keycode to the circular buffer + ldr r10, [r9, #BUF_KEYS_CNT] @ get saved keystrokes count + ldr r8, [r9, #BUF_BUF_LEN] @ get buffer size + cmp r10, r8 @ is buffer full? + beq hksw @ yes - key lost, next source + + add r10, r10, #1 @ incremet keystrokes counter + str r10, [r9, #BUF_KEYS_CNT] + + ldr r10, [r9, #BUF_TAIL_OFFSET] @ get buffer tail offset + @ r8 already contains buffer size + cmp r10, r8 @ end of buffer? + moveq r10, #0 @ yes - rewind to buffer start + + ldr r12, [r9, #BUF_BUFFER_START] @ get buffer start address + add r12, r12, r10, LSL #2 @ calculate buffer tail address + ldr r8, [r9, #BUF_KEY] @ get last keycode + str r8, [r12] @ append it to the buffer tail + + add r10, r10, #1 @ increment buffer tail offset + str r10, [r9, #BUF_TAIL_OFFSET] + + ldr r10, [r9, #BUF_CNT_INT_KEY] @ increment interrupts counter + add r10, r10, #1 + str r10, [r9, #BUF_CNT_INT_KEY] + @@@@@@@@@@@@@@@@@@@@@@@@ + + +hksw: @Is hook switch interrupt requested? + tst r13, #HOOK_SWITCH_MASK @ is hook switch status bit set? + beq mdm @ no - try next source + + + @@@@@@@@@@@@@@@@@@@@@@@@ + @ Hook switch interrupt FIQ mode simple handler + + @ Don't toggle active edge, the switch always bounces + + @ Increment hook switch interrupt counter + ldr r10, [r9, #BUF_CNT_INT_HSW] + add r10, r10, #1 + str r10, [r9, #BUF_CNT_INT_HSW] + @@@@@@@@@@@@@@@@@@@@@@@@ + + +mdm: @Is it a modem interrupt? + tst r13, #MODEM_IRQ_MASK @ is modem status bit set? + beq irq @ no - check for next interrupt + + + @@@@@@@@@@@@@@@@@@@@@@@@ + @ Modem FIQ mode interrupt handler stub + + @ Increment modem interrupt counter + ldr r10, [r9, #BUF_CNT_INT_MDM] + add r10, r10, #1 + str r10, [r9, #BUF_CNT_INT_MDM] + @@@@@@@@@@@@@@@@@@@@@@@@ + + +irq: @ Place deferred_fiq interrupt request + ldr r12, deferred_fiq_ih_base @ set pointer to IRQ handler + mov r10, #DEFERRED_FIQ_MASK @ set deferred_fiq bit + str r10, [r12, #IRQ_ISR_REG_OFFSET] @ place it in the ISR register + + ldr r12, omap1510_gpio_base @ set pointer back to GPIO bank + b restart @ check for next GPIO interrupt + @@@@@@@@@@@@@@@@@@@@@@@@@@@ + + +/* + * Virtual addresses for IO + */ +omap_ih1_base: + .word OMAP1_IO_ADDRESS(OMAP_IH1_BASE) +deferred_fiq_ih_base: + .word OMAP1_IO_ADDRESS(DEFERRED_FIQ_IH_BASE) +omap1510_gpio_base: + .word OMAP1_IO_ADDRESS(OMAP1510_GPIO_BASE) +qwerty_fiqin_end: + +/* + * Check the size of the FIQ, + * it cannot go beyond 0xffff0200, and is copied to 0xffff001c + */ +.if (qwerty_fiqin_end - qwerty_fiqin_start) > (0x200 - 0x1c) + .err +.endif diff --git a/arch/arm/mach-omap1/ams-delta-fiq.c b/arch/arm/mach-omap1/ams-delta-fiq.c new file mode 100644 index 000000000000..6c994e2d8879 --- /dev/null +++ b/arch/arm/mach-omap1/ams-delta-fiq.c @@ -0,0 +1,155 @@ +/* + * Amstrad E3 FIQ handling + * + * Copyright (C) 2009 Janusz Krzysztofik + * Copyright (c) 2006 Matt Callow + * Copyright (c) 2004 Amstrad Plc + * Copyright (C) 2001 RidgeRun, Inc. + * + * Parts of this code are taken from linux/arch/arm/mach-omap/irq.c + * in the MontaVista 2.4 kernel (and the Amstrad changes therein) + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + */ +#include <linux/gpio.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/module.h> +#include <linux/io.h> + +#include <plat/board-ams-delta.h> + +#include <asm/fiq.h> +#include <mach/ams-delta-fiq.h> + +static struct fiq_handler fh = { + .name = "ams-delta-fiq" +}; + +/* + * This buffer is shared between FIQ and IRQ contexts. + * The FIQ and IRQ isrs can both read and write it. + * It is structured as a header section several 32bit slots, + * followed by the circular buffer where the FIQ isr stores + * keystrokes received from the qwerty keyboard. + * See ams-delta-fiq.h for details of offsets. + */ +unsigned int fiq_buffer[1024]; +EXPORT_SYMBOL(fiq_buffer); + +static unsigned int irq_counter[16]; + +static irqreturn_t deferred_fiq(int irq, void *dev_id) +{ + struct irq_desc *irq_desc; + struct irq_chip *irq_chip = NULL; + int gpio, irq_num, fiq_count; + + irq_desc = irq_to_desc(IH_GPIO_BASE); + if (irq_desc) + irq_chip = irq_desc->chip; + + /* + * For each handled GPIO interrupt, keep calling its interrupt handler + * until the IRQ counter catches the FIQ incremented interrupt counter. + */ + for (gpio = AMS_DELTA_GPIO_PIN_KEYBRD_CLK; + gpio <= AMS_DELTA_GPIO_PIN_HOOK_SWITCH; gpio++) { + irq_num = gpio_to_irq(gpio); + fiq_count = fiq_buffer[FIQ_CNT_INT_00 + gpio]; + + while (irq_counter[gpio] < fiq_count) { + if (gpio != AMS_DELTA_GPIO_PIN_KEYBRD_CLK) { + /* + * It looks like handle_edge_irq() that + * OMAP GPIO edge interrupts default to, + * expects interrupt already unmasked. + */ + if (irq_chip && irq_chip->unmask) + irq_chip->unmask(irq_num); + } + generic_handle_irq(irq_num); + + irq_counter[gpio]++; + } + } + return IRQ_HANDLED; +} + +void __init ams_delta_init_fiq(void) +{ + void *fiqhandler_start; + unsigned int fiqhandler_length; + struct pt_regs FIQ_regs; + unsigned long val, offset; + int i, retval; + + fiqhandler_start = &qwerty_fiqin_start; + fiqhandler_length = &qwerty_fiqin_end - &qwerty_fiqin_start; + pr_info("Installing fiq handler from %p, length 0x%x\n", + fiqhandler_start, fiqhandler_length); + + retval = claim_fiq(&fh); + if (retval) { + pr_err("ams_delta_init_fiq(): couldn't claim FIQ, ret=%d\n", + retval); + return; + } + + retval = request_irq(INT_DEFERRED_FIQ, deferred_fiq, + IRQ_TYPE_EDGE_RISING, "deferred_fiq", 0); + if (retval < 0) { + pr_err("Failed to get deferred_fiq IRQ, ret=%d\n", retval); + release_fiq(&fh); + return; + } + /* + * Since no set_type() method is provided by OMAP irq chip, + * switch to edge triggered interrupt type manually. + */ + offset = IRQ_ILR0_REG_OFFSET + INT_DEFERRED_FIQ * 0x4; + val = omap_readl(DEFERRED_FIQ_IH_BASE + offset) & ~(1 << 1); + omap_writel(val, DEFERRED_FIQ_IH_BASE + offset); + + set_fiq_handler(fiqhandler_start, fiqhandler_length); + + /* + * Initialise the buffer which is shared + * between FIQ mode and IRQ mode + */ + fiq_buffer[FIQ_GPIO_INT_MASK] = 0; + fiq_buffer[FIQ_MASK] = 0; + fiq_buffer[FIQ_STATE] = 0; + fiq_buffer[FIQ_KEY] = 0; + fiq_buffer[FIQ_KEYS_CNT] = 0; + fiq_buffer[FIQ_KEYS_HICNT] = 0; + fiq_buffer[FIQ_TAIL_OFFSET] = 0; + fiq_buffer[FIQ_HEAD_OFFSET] = 0; + fiq_buffer[FIQ_BUF_LEN] = 256; + fiq_buffer[FIQ_MISSED_KEYS] = 0; + fiq_buffer[FIQ_BUFFER_START] = + (unsigned int) &fiq_buffer[FIQ_CIRC_BUFF]; + + for (i = FIQ_CNT_INT_00; i <= FIQ_CNT_INT_15; i++) + fiq_buffer[i] = 0; + + /* + * FIQ mode r9 always points to the fiq_buffer, becauses the FIQ isr + * will run in an unpredictable context. The fiq_buffer is the FIQ isr's + * only means of communication with the IRQ level and other kernel + * context code. + */ + FIQ_regs.ARM_r9 = (unsigned int)fiq_buffer; + set_fiq_regs(&FIQ_regs); + + pr_info("request_fiq(): fiq_buffer = %p\n", fiq_buffer); + + /* + * Redirect GPIO interrupts to FIQ + */ + offset = IRQ_ILR0_REG_OFFSET + INT_GPIO_BANK1 * 0x4; + val = omap_readl(OMAP_IH1_BASE + offset) | 1; + omap_writel(val, OMAP_IH1_BASE + offset); +} diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c index 7fc11c34b696..fdd1dd53fa9c 100644 --- a/arch/arm/mach-omap1/board-ams-delta.c +++ b/arch/arm/mach-omap1/board-ams-delta.c @@ -33,6 +33,8 @@ #include <plat/board.h> #include <plat/common.h> +#include <mach/ams-delta-fiq.h> + static u8 ams_delta_latch1_reg; static u16 ams_delta_latch2_reg; @@ -236,6 +238,10 @@ static void __init ams_delta_init(void) omap_usb_init(&ams_delta_usb_config); platform_add_devices(ams_delta_devices, ARRAY_SIZE(ams_delta_devices)); +#ifdef CONFIG_AMS_DELTA_FIQ + ams_delta_init_fiq(); +#endif + omap_writew(omap_readw(ARM_RSTCT1) | 0x0004, ARM_RSTCT1); } @@ -263,8 +269,18 @@ static struct platform_device ams_delta_modem_device = { static int __init ams_delta_modem_init(void) { + int err; + omap_cfg_reg(M14_1510_GPIO2); - ams_delta_modem_ports[0].irq = gpio_to_irq(2); + ams_delta_modem_ports[0].irq = + gpio_to_irq(AMS_DELTA_GPIO_PIN_MODEM_IRQ); + + err = gpio_request(AMS_DELTA_GPIO_PIN_MODEM_IRQ, "modem"); + if (err) { + pr_err("Couldn't request gpio pin for modem\n"); + return err; + } + gpio_direction_input(AMS_DELTA_GPIO_PIN_MODEM_IRQ); ams_delta_latch2_write( AMS_DELTA_LATCH2_MODEM_NRESET | AMS_DELTA_LATCH2_MODEM_CODEC, diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c index e0aec1007a0d..6bbb1b8b8294 100644 --- a/arch/arm/mach-omap1/clock.c +++ b/arch/arm/mach-omap1/clock.c @@ -578,7 +578,7 @@ int omap1_clk_set_rate(struct clk *clk, unsigned long rate) #ifdef CONFIG_OMAP_RESET_CLOCKS -void __init omap1_clk_disable_unused(struct clk *clk) +void omap1_clk_disable_unused(struct clk *clk) { __u32 regval32; diff --git a/arch/arm/mach-omap1/clock.h b/arch/arm/mach-omap1/clock.h index a4190afb8614..75d0d7d90bff 100644 --- a/arch/arm/mach-omap1/clock.h +++ b/arch/arm/mach-omap1/clock.h @@ -39,7 +39,7 @@ extern long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate); extern unsigned long omap1_watchdog_recalc(struct clk *clk); #ifdef CONFIG_OMAP_RESET_CLOCKS -extern void __init omap1_clk_disable_unused(struct clk *clk); +extern void omap1_clk_disable_unused(struct clk *clk); #else #define omap1_clk_disable_unused NULL #endif diff --git a/arch/arm/mach-omap1/include/mach/ams-delta-fiq.h b/arch/arm/mach-omap1/include/mach/ams-delta-fiq.h new file mode 100644 index 000000000000..7a2df29400ca --- /dev/null +++ b/arch/arm/mach-omap1/include/mach/ams-delta-fiq.h @@ -0,0 +1,79 @@ +/* + * arch/arm/mach-omap1/include/ams-delta-fiq.h + * + * Taken from the original Amstrad modifications to fiq.h + * + * Copyright (c) 2004 Amstrad Plc + * Copyright (c) 2006 Matt Callow + * Copyright (c) 2010 Janusz Krzysztofik + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __AMS_DELTA_FIQ_H +#define __AMS_DELTA_FIQ_H + +#include <plat/irqs.h> + +/* + * Interrupt number used for passing control from FIQ to IRQ. + * IRQ12, described as reserved, has been selected. + */ +#define INT_DEFERRED_FIQ INT_1510_RES12 +/* + * Base address of an interrupt handler that the INT_DEFERRED_FIQ belongs to. + */ +#if (INT_DEFERRED_FIQ < IH2_BASE) +#define DEFERRED_FIQ_IH_BASE OMAP_IH1_BASE +#else +#define DEFERRED_FIQ_IH_BASE OMAP_IH2_BASE +#endif + +/* + * These are the offsets from the begining of the fiq_buffer. They are put here + * since the buffer and header need to be accessed by drivers servicing devices + * which generate GPIO interrupts - e.g. keyboard, modem, hook switch. + */ +#define FIQ_MASK 0 +#define FIQ_STATE 1 +#define FIQ_KEYS_CNT 2 +#define FIQ_TAIL_OFFSET 3 +#define FIQ_HEAD_OFFSET 4 +#define FIQ_BUF_LEN 5 +#define FIQ_KEY 6 +#define FIQ_MISSED_KEYS 7 +#define FIQ_BUFFER_START 8 +#define FIQ_GPIO_INT_MASK 9 +#define FIQ_KEYS_HICNT 10 +#define FIQ_IRQ_PEND 11 +#define FIQ_SIR_CODE_L1 12 +#define IRQ_SIR_CODE_L2 13 + +#define FIQ_CNT_INT_00 14 +#define FIQ_CNT_INT_KEY 15 +#define FIQ_CNT_INT_MDM 16 +#define FIQ_CNT_INT_03 17 +#define FIQ_CNT_INT_HSW 18 +#define FIQ_CNT_INT_05 19 +#define FIQ_CNT_INT_06 20 +#define FIQ_CNT_INT_07 21 +#define FIQ_CNT_INT_08 22 +#define FIQ_CNT_INT_09 23 +#define FIQ_CNT_INT_10 24 +#define FIQ_CNT_INT_11 25 +#define FIQ_CNT_INT_12 26 +#define FIQ_CNT_INT_13 27 +#define FIQ_CNT_INT_14 28 +#define FIQ_CNT_INT_15 29 + +#define FIQ_CIRC_BUFF 30 /*Start of circular buffer */ + +#ifndef __ASSEMBLER__ +extern unsigned int fiq_buffer[]; +extern unsigned char qwerty_fiqin_start, qwerty_fiqin_end; + +extern void __init ams_delta_init_fiq(void); +#endif + +#endif diff --git a/arch/arm/mach-omap1/include/mach/debug-macro.S b/arch/arm/mach-omap1/include/mach/debug-macro.S index b6d9584544b4..e8a8cf36b7f0 100644 --- a/arch/arm/mach-omap1/include/mach/debug-macro.S +++ b/arch/arm/mach-omap1/include/mach/debug-macro.S @@ -13,6 +13,8 @@ #include <linux/serial_reg.h> +#include <asm/memory.h> + #include <plat/serial.h> .pushsection .data @@ -37,23 +39,12 @@ omap_uart_virt: .word 0x0 cmp \rx, #0 @ is port configured? bne 99f @ already configured - /* Check 7XX UART1 scratchpad register for uart to use */ + /* Check the debug UART configuration set in uncompress.h */ mrc p15, 0, \rx, c1, c0 tst \rx, #1 @ MMU enabled? - moveq \rx, #0xff000000 @ physical base address - movne \rx, #0xfe000000 @ virtual base - orr \rx, \rx, #0x00fb0000 @ OMAP1UART1 - ldrb \rx, [\rx, #(UART_SCR << OMAP7XX_PORT_SHIFT)] - cmp \rx, #0 @ anything in 7XX scratchpad? - bne 10f @ found 7XX uart - - /* Check 15xx/16xx UART1 scratchpad register for uart to use */ - mrc p15, 0, \rx, c1, c0 - tst \rx, #1 @ MMU enabled? - moveq \rx, #0xff000000 @ physical base address - movne \rx, #0xfe000000 @ virtual base - orr \rx, \rx, #0x00fb0000 @ OMAP1UART1 - ldrb \rx, [\rx, #(UART_SCR << OMAP_PORT_SHIFT)] + ldreq \rx, =OMAP_UART_INFO + ldrne \rx, =__phys_to_virt(OMAP_UART_INFO) + ldr \rx, [\rx, #0] /* Select the UART to use based on the UART1 scratchpad value */ 10: cmp \rx, #0 @ no port configured? |