diff options
Diffstat (limited to 'arch/arm/mach-exynos')
| -rw-r--r-- | arch/arm/mach-exynos/Kconfig | 7 | ||||
| -rw-r--r-- | arch/arm/mach-exynos/clock-exynos4.c | 67 | ||||
| -rw-r--r-- | arch/arm/mach-exynos/clock-exynos5.c | 95 | ||||
| -rw-r--r-- | arch/arm/mach-exynos/common.c | 28 | ||||
| -rw-r--r-- | arch/arm/mach-exynos/include/mach/irqs.h | 4 | ||||
| -rw-r--r-- | arch/arm/mach-exynos/include/mach/map.h | 3 | ||||
| -rw-r--r-- | arch/arm/mach-exynos/include/mach/regs-pmu.h | 5 | ||||
| -rw-r--r-- | arch/arm/mach-exynos/include/mach/regs-usb-phy.h | 20 | ||||
| -rw-r--r-- | arch/arm/mach-exynos/include/mach/spi-clocks.h | 16 | ||||
| -rw-r--r-- | arch/arm/mach-exynos/mach-exynos4-dt.c | 6 | ||||
| -rw-r--r-- | arch/arm/mach-exynos/mach-exynos5-dt.c | 6 | ||||
| -rw-r--r-- | arch/arm/mach-exynos/mach-nuri.c | 4 | ||||
| -rw-r--r-- | arch/arm/mach-exynos/mach-origen.c | 40 | ||||
| -rw-r--r-- | arch/arm/mach-exynos/mach-smdk4x12.c | 83 | ||||
| -rw-r--r-- | arch/arm/mach-exynos/mach-smdkv310.c | 18 | ||||
| -rw-r--r-- | arch/arm/mach-exynos/mach-universal_c210.c | 4 | ||||
| -rw-r--r-- | arch/arm/mach-exynos/pmu.c | 18 | ||||
| -rw-r--r-- | arch/arm/mach-exynos/setup-spi.c | 33 | ||||
| -rw-r--r-- | arch/arm/mach-exynos/setup-usb-phy.c | 60 |
19 files changed, 385 insertions, 132 deletions
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 6f6d13f91e4c..b5b4c8c9db11 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -207,6 +207,7 @@ config MACH_SMDKV310 select S3C_DEV_HSMMC1 select S3C_DEV_HSMMC2 select S3C_DEV_HSMMC3 + select S3C_DEV_USB_HSOTG select SAMSUNG_DEV_BACKLIGHT select EXYNOS_DEV_DRM select EXYNOS_DEV_SYSMMU @@ -326,6 +327,7 @@ config MACH_ORIGEN select S3C_DEV_WDT select S3C_DEV_HSMMC select S3C_DEV_HSMMC2 + select S3C_DEV_USB_HSOTG select S5P_DEV_FIMC0 select S5P_DEV_FIMC1 select S5P_DEV_FIMC2 @@ -360,22 +362,27 @@ config MACH_SMDK4212 select S3C_DEV_I2C3 select S3C_DEV_I2C7 select S3C_DEV_RTC + select S3C_DEV_USB_HSOTG select S3C_DEV_WDT select S5P_DEV_FIMC0 select S5P_DEV_FIMC1 select S5P_DEV_FIMC2 select S5P_DEV_FIMC3 + select S5P_DEV_FIMD0 select S5P_DEV_MFC select SAMSUNG_DEV_BACKLIGHT select SAMSUNG_DEV_KEYPAD select SAMSUNG_DEV_PWM select EXYNOS_DEV_SYSMMU select EXYNOS_DEV_DMA + select EXYNOS_DEV_DRM + select EXYNOS4_SETUP_FIMD0 select EXYNOS4_SETUP_I2C1 select EXYNOS4_SETUP_I2C3 select EXYNOS4_SETUP_I2C7 select EXYNOS4_SETUP_KEYPAD select EXYNOS4_SETUP_SDHCI + select EXYNOS4_SETUP_USB_PHY help Machine support for Samsung SMDK4212 diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c index bcb7db453145..26fe9de35ecb 100644 --- a/arch/arm/mach-exynos/clock-exynos4.c +++ b/arch/arm/mach-exynos/clock-exynos4.c @@ -586,17 +586,17 @@ static struct clk exynos4_init_clocks_off[] = { .ctrlbit = (1 << 13), }, { .name = "spi", - .devname = "s3c64xx-spi.0", + .devname = "exynos4210-spi.0", .enable = exynos4_clk_ip_peril_ctrl, .ctrlbit = (1 << 16), }, { .name = "spi", - .devname = "s3c64xx-spi.1", + .devname = "exynos4210-spi.1", .enable = exynos4_clk_ip_peril_ctrl, .ctrlbit = (1 << 17), }, { .name = "spi", - .devname = "s3c64xx-spi.2", + .devname = "exynos4210-spi.2", .enable = exynos4_clk_ip_peril_ctrl, .ctrlbit = (1 << 18), }, { @@ -1242,40 +1242,67 @@ static struct clksrc_clk exynos4_clk_sclk_mmc3 = { .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 24, .size = 8 }, }; +static struct clksrc_clk exynos4_clk_mdout_spi0 = { + .clk = { + .name = "mdout_spi", + .devname = "exynos4210-spi.0", + }, + .sources = &exynos4_clkset_group, + .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 16, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 0, .size = 4 }, +}; + +static struct clksrc_clk exynos4_clk_mdout_spi1 = { + .clk = { + .name = "mdout_spi", + .devname = "exynos4210-spi.1", + }, + .sources = &exynos4_clkset_group, + .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 20, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 16, .size = 4 }, +}; + +static struct clksrc_clk exynos4_clk_mdout_spi2 = { + .clk = { + .name = "mdout_spi", + .devname = "exynos4210-spi.2", + }, + .sources = &exynos4_clkset_group, + .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 24, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 0, .size = 4 }, +}; + static struct clksrc_clk exynos4_clk_sclk_spi0 = { .clk = { .name = "sclk_spi", - .devname = "s3c64xx-spi.0", + .devname = "exynos4210-spi.0", + .parent = &exynos4_clk_mdout_spi0.clk, .enable = exynos4_clksrc_mask_peril1_ctrl, .ctrlbit = (1 << 16), }, - .sources = &exynos4_clkset_group, - .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 16, .size = 4 }, - .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 0, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 8, .size = 8 }, }; static struct clksrc_clk exynos4_clk_sclk_spi1 = { .clk = { .name = "sclk_spi", - .devname = "s3c64xx-spi.1", + .devname = "exynos4210-spi.1", + .parent = &exynos4_clk_mdout_spi1.clk, .enable = exynos4_clksrc_mask_peril1_ctrl, .ctrlbit = (1 << 20), }, - .sources = &exynos4_clkset_group, - .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 20, .size = 4 }, - .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 16, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 24, .size = 8 }, }; static struct clksrc_clk exynos4_clk_sclk_spi2 = { .clk = { .name = "sclk_spi", - .devname = "s3c64xx-spi.2", + .devname = "exynos4210-spi.2", + .parent = &exynos4_clk_mdout_spi2.clk, .enable = exynos4_clksrc_mask_peril1_ctrl, .ctrlbit = (1 << 24), }, - .sources = &exynos4_clkset_group, - .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 24, .size = 4 }, - .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 0, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 8, .size = 8 }, }; /* Clock initialization code */ @@ -1331,7 +1358,9 @@ static struct clksrc_clk *exynos4_clksrc_cdev[] = { &exynos4_clk_sclk_spi0, &exynos4_clk_sclk_spi1, &exynos4_clk_sclk_spi2, - + &exynos4_clk_mdout_spi0, + &exynos4_clk_mdout_spi1, + &exynos4_clk_mdout_spi2, }; static struct clk_lookup exynos4_clk_lookup[] = { @@ -1347,9 +1376,9 @@ static struct clk_lookup exynos4_clk_lookup[] = { CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0), CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1), CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos4_clk_mdma1), - CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk), - CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk), - CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk), + CLKDEV_INIT("exynos4210-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk), + CLKDEV_INIT("exynos4210-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk), + CLKDEV_INIT("exynos4210-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk), }; static int xtal_rate; diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c index fefa336be2b4..774533c67066 100644 --- a/arch/arm/mach-exynos/clock-exynos5.c +++ b/arch/arm/mach-exynos/clock-exynos5.c @@ -131,6 +131,11 @@ static int exynos5_clksrc_mask_peric0_ctrl(struct clk *clk, int enable) return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC0, clk, enable); } +static int exynos5_clksrc_mask_peric1_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC1, clk, enable); +} + static int exynos5_clk_ip_acp_ctrl(struct clk *clk, int enable) { return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ACP, clk, enable); @@ -741,6 +746,24 @@ static struct clk exynos5_init_clocks_off[] = { .enable = exynos5_clk_ip_peric_ctrl, .ctrlbit = (1 << 14), }, { + .name = "spi", + .devname = "exynos4210-spi.0", + .parent = &exynos5_clk_aclk_66.clk, + .enable = exynos5_clk_ip_peric_ctrl, + .ctrlbit = (1 << 16), + }, { + .name = "spi", + .devname = "exynos4210-spi.1", + .parent = &exynos5_clk_aclk_66.clk, + .enable = exynos5_clk_ip_peric_ctrl, + .ctrlbit = (1 << 17), + }, { + .name = "spi", + .devname = "exynos4210-spi.2", + .parent = &exynos5_clk_aclk_66.clk, + .enable = exynos5_clk_ip_peric_ctrl, + .ctrlbit = (1 << 18), + }, { .name = SYSMMU_CLOCK_NAME, .devname = SYSMMU_CLOCK_DEVNAME(mfc_l, 0), .enable = &exynos5_clk_ip_mfc_ctrl, @@ -1034,6 +1057,69 @@ static struct clksrc_clk exynos5_clk_sclk_mmc3 = { .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 24, .size = 8 }, }; +static struct clksrc_clk exynos5_clk_mdout_spi0 = { + .clk = { + .name = "mdout_spi", + .devname = "exynos4210-spi.0", + }, + .sources = &exynos5_clkset_group, + .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 16, .size = 4 }, + .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 0, .size = 4 }, +}; + +static struct clksrc_clk exynos5_clk_mdout_spi1 = { + .clk = { + .name = "mdout_spi", + .devname = "exynos4210-spi.1", + }, + .sources = &exynos5_clkset_group, + .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 20, .size = 4 }, + .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 16, .size = 4 }, +}; + +static struct clksrc_clk exynos5_clk_mdout_spi2 = { + .clk = { + .name = "mdout_spi", + .devname = "exynos4210-spi.2", + }, + .sources = &exynos5_clkset_group, + .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 24, .size = 4 }, + .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 0, .size = 4 }, +}; + +static struct clksrc_clk exynos5_clk_sclk_spi0 = { + .clk = { + .name = "sclk_spi", + .devname = "exynos4210-spi.0", + .parent = &exynos5_clk_mdout_spi0.clk, + .enable = exynos5_clksrc_mask_peric1_ctrl, + .ctrlbit = (1 << 16), + }, + .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 8, .size = 8 }, +}; + +static struct clksrc_clk exynos5_clk_sclk_spi1 = { + .clk = { + .name = "sclk_spi", + .devname = "exynos4210-spi.1", + .parent = &exynos5_clk_mdout_spi1.clk, + .enable = exynos5_clksrc_mask_peric1_ctrl, + .ctrlbit = (1 << 20), + }, + .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 24, .size = 8 }, +}; + +static struct clksrc_clk exynos5_clk_sclk_spi2 = { + .clk = { + .name = "sclk_spi", + .devname = "exynos4210-spi.2", + .parent = &exynos5_clk_mdout_spi2.clk, + .enable = exynos5_clksrc_mask_peric1_ctrl, + .ctrlbit = (1 << 24), + }, + .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 8, .size = 8 }, +}; + static struct clksrc_clk exynos5_clksrcs[] = { { .clk = { @@ -1148,6 +1234,12 @@ static struct clksrc_clk *exynos5_sysclks[] = { &exynos5_clk_dout_mmc4, &exynos5_clk_aclk_acp, &exynos5_clk_pclk_acp, + &exynos5_clk_sclk_spi0, + &exynos5_clk_sclk_spi1, + &exynos5_clk_sclk_spi2, + &exynos5_clk_mdout_spi0, + &exynos5_clk_mdout_spi1, + &exynos5_clk_mdout_spi2, }; static struct clk *exynos5_clk_cdev[] = { @@ -1176,6 +1268,9 @@ static struct clk_lookup exynos5_clk_lookup[] = { CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk), CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk), CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk), + CLKDEV_INIT("exynos4210-spi.0", "spi_busclk0", &exynos5_clk_sclk_spi0.clk), + CLKDEV_INIT("exynos4210-spi.1", "spi_busclk0", &exynos5_clk_sclk_spi1.clk), + CLKDEV_INIT("exynos4210-spi.2", "spi_busclk0", &exynos5_clk_sclk_spi2.clk), CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0), CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1), CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1), diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c index 742edd3bbec3..4eb39cdf75ea 100644 --- a/arch/arm/mach-exynos/common.c +++ b/arch/arm/mach-exynos/common.c @@ -540,7 +540,8 @@ static struct irq_domain_ops combiner_irq_domain_ops = { .map = combiner_irq_domain_map, }; -void __init combiner_init(void __iomem *combiner_base, struct device_node *np) +static void __init combiner_init(void __iomem *combiner_base, + struct device_node *np) { int i, irq, irq_base; unsigned int max_nr, nr_irq; @@ -712,31 +713,6 @@ static int __init exynos4_l2x0_cache_init(void) early_initcall(exynos4_l2x0_cache_init); #endif -static int __init exynos5_l2_cache_init(void) -{ - unsigned int val; - - if (!soc_is_exynos5250()) - return 0; - - asm volatile("mrc p15, 0, %0, c1, c0, 0\n" - "bic %0, %0, #(1 << 2)\n" /* cache disable */ - "mcr p15, 0, %0, c1, c0, 0\n" - "mrc p15, 1, %0, c9, c0, 2\n" - : "=r"(val)); - - val |= (1 << 9) | (1 << 5) | (2 << 6) | (2 << 0); - - asm volatile("mcr p15, 1, %0, c9, c0, 2\n" : : "r"(val)); - asm volatile("mrc p15, 0, %0, c1, c0, 0\n" - "orr %0, %0, #(1 << 2)\n" /* cache enable */ - "mcr p15, 0, %0, c1, c0, 0\n" - : : "r"(val)); - - return 0; -} -early_initcall(exynos5_l2_cache_init); - static int __init exynos_init(void) { printk(KERN_INFO "EXYNOS: Initializing architecture\n"); diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h index 7a4b4789eb72..35bced6f9092 100644 --- a/arch/arm/mach-exynos/include/mach/irqs.h +++ b/arch/arm/mach-exynos/include/mach/irqs.h @@ -195,6 +195,10 @@ #define IRQ_IIC6 EXYNOS4_IRQ_IIC6 #define IRQ_IIC7 EXYNOS4_IRQ_IIC7 +#define IRQ_SPI0 EXYNOS4_IRQ_SPI0 +#define IRQ_SPI1 EXYNOS4_IRQ_SPI1 +#define IRQ_SPI2 EXYNOS4_IRQ_SPI2 + #define IRQ_USB_HOST EXYNOS4_IRQ_USB_HOST #define IRQ_OTG EXYNOS4_IRQ_USB_HSOTG diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h index ca4aa89aa46b..c72b675b3e4b 100644 --- a/arch/arm/mach-exynos/include/mach/map.h +++ b/arch/arm/mach-exynos/include/mach/map.h @@ -154,6 +154,9 @@ #define EXYNOS4_PA_SPI0 0x13920000 #define EXYNOS4_PA_SPI1 0x13930000 #define EXYNOS4_PA_SPI2 0x13940000 +#define EXYNOS5_PA_SPI0 0x12D20000 +#define EXYNOS5_PA_SPI1 0x12D30000 +#define EXYNOS5_PA_SPI2 0x12D40000 #define EXYNOS4_PA_GPIO1 0x11400000 #define EXYNOS4_PA_GPIO2 0x11000000 diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/include/mach/regs-pmu.h index 43a99e6f56ab..d4e392b811a3 100644 --- a/arch/arm/mach-exynos/include/mach/regs-pmu.h +++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h @@ -232,6 +232,11 @@ #define EXYNOS5_USB_CFG S5P_PMUREG(0x0230) +#define EXYNOS5_AUTO_WDTRESET_DISABLE S5P_PMUREG(0x0408) +#define EXYNOS5_MASK_WDTRESET_REQUEST S5P_PMUREG(0x040C) + +#define EXYNOS5_SYS_WDTRESET (1 << 20) + #define EXYNOS5_ARM_CORE0_SYS_PWR_REG S5P_PMUREG(0x1000) #define EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1004) #define EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1008) diff --git a/arch/arm/mach-exynos/include/mach/regs-usb-phy.h b/arch/arm/mach-exynos/include/mach/regs-usb-phy.h index c337cf3a71bf..07277735252e 100644 --- a/arch/arm/mach-exynos/include/mach/regs-usb-phy.h +++ b/arch/arm/mach-exynos/include/mach/regs-usb-phy.h @@ -35,11 +35,21 @@ #define PHY1_COMMON_ON_N (1 << 7) #define PHY0_COMMON_ON_N (1 << 4) #define PHY0_ID_PULLUP (1 << 2) -#define CLKSEL_MASK (0x3 << 0) -#define CLKSEL_SHIFT (0) -#define CLKSEL_48M (0x0 << 0) -#define CLKSEL_12M (0x2 << 0) -#define CLKSEL_24M (0x3 << 0) + +#define EXYNOS4_CLKSEL_SHIFT (0) + +#define EXYNOS4210_CLKSEL_MASK (0x3 << 0) +#define EXYNOS4210_CLKSEL_48M (0x0 << 0) +#define EXYNOS4210_CLKSEL_12M (0x2 << 0) +#define EXYNOS4210_CLKSEL_24M (0x3 << 0) + +#define EXYNOS4X12_CLKSEL_MASK (0x7 << 0) +#define EXYNOS4X12_CLKSEL_9600K (0x0 << 0) +#define EXYNOS4X12_CLKSEL_10M (0x1 << 0) +#define EXYNOS4X12_CLKSEL_12M (0x2 << 0) +#define EXYNOS4X12_CLKSEL_19200K (0x3 << 0) +#define EXYNOS4X12_CLKSEL_20M (0x4 << 0) +#define EXYNOS4X12_CLKSEL_24M (0x5 << 0) #define EXYNOS4_RSTCON EXYNOS4_HSOTG_PHYREG(0x08) #define HOST_LINK_PORT_SWRST_MASK (0xf << 6) diff --git a/arch/arm/mach-exynos/include/mach/spi-clocks.h b/arch/arm/mach-exynos/include/mach/spi-clocks.h deleted file mode 100644 index c71a5fba6a84..000000000000 --- a/arch/arm/mach-exynos/include/mach/spi-clocks.h +++ /dev/null @@ -1,16 +0,0 @@ -/* linux/arch/arm/mach-exynos4/include/mach/spi-clocks.h - * - * Copyright (C) 2011 Samsung Electronics Co. Ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARCH_SPI_CLKS_H -#define __ASM_ARCH_SPI_CLKS_H __FILE__ - -/* Must source from SCLK_SPI */ -#define EXYNOS_SPI_SRCCLK_SCLK 0 - -#endif /* __ASM_ARCH_SPI_CLKS_H */ diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c index e7e9743543ac..b2b5d5faa748 100644 --- a/arch/arm/mach-exynos/mach-exynos4-dt.c +++ b/arch/arm/mach-exynos/mach-exynos4-dt.c @@ -55,6 +55,12 @@ static const struct of_dev_auxdata exynos4210_auxdata_lookup[] __initconst = { "exynos4-sdhci.3", NULL), OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(0), "s3c2440-i2c.0", NULL), + OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI0, + "exynos4210-spi.0", NULL), + OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI1, + "exynos4210-spi.1", NULL), + OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI2, + "exynos4210-spi.2", NULL), OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA0, "dma-pl330.0", NULL), OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA1, "dma-pl330.1", NULL), {}, diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c index 7b1e11a228cc..ef770bc2318f 100644 --- a/arch/arm/mach-exynos/mach-exynos5-dt.c +++ b/arch/arm/mach-exynos/mach-exynos5-dt.c @@ -47,6 +47,12 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = { "s3c2440-i2c.0", NULL), OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(1), "s3c2440-i2c.1", NULL), + OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI0, + "exynos4210-spi.0", NULL), + OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI1, + "exynos4210-spi.1", NULL), + OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI2, + "exynos4210-spi.2", NULL), OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL), OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL), OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL), diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c index 656f8fc9addd..f98a83a81ce7 100644 --- a/arch/arm/mach-exynos/mach-nuri.c +++ b/arch/arm/mach-exynos/mach-nuri.c @@ -50,7 +50,6 @@ #include <plat/gpio-cfg.h> #include <plat/iic.h> #include <plat/mfc.h> -#include <plat/pd.h> #include <plat/fimc-core.h> #include <plat/camport.h> #include <plat/mipi_csis.h> @@ -1342,9 +1341,8 @@ static struct platform_device *nuri_devices[] __initdata = { static void __init nuri_map_io(void) { - clk_xusbxti.rate = 24000000; exynos_init_io(NULL, 0); - s3c24xx_init_clocks(24000000); + s3c24xx_init_clocks(clk_xusbxti.rate); s3c24xx_init_uarts(nuri_uartcfgs, ARRAY_SIZE(nuri_uartcfgs)); } diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c index f5572be9d7bf..5a12dc26f496 100644 --- a/arch/arm/mach-exynos/mach-origen.c +++ b/arch/arm/mach-exynos/mach-origen.c @@ -9,6 +9,7 @@ */ #include <linux/serial_core.h> +#include <linux/leds.h> #include <linux/gpio.h> #include <linux/mmc/host.h> #include <linux/platform_device.h> @@ -21,6 +22,7 @@ #include <linux/mfd/max8997.h> #include <linux/lcd.h> #include <linux/rfkill-gpio.h> +#include <linux/platform_data/s3c-hsotg.h> #include <asm/mach/arch.h> #include <asm/hardware/gic.h> @@ -38,7 +40,6 @@ #include <plat/clock.h> #include <plat/gpio-cfg.h> #include <plat/backlight.h> -#include <plat/pd.h> #include <plat/fb.h> #include <plat/mfc.h> @@ -499,6 +500,37 @@ static void __init origen_ohci_init(void) exynos4_ohci_set_platdata(pdata); } +/* USB OTG */ +static struct s3c_hsotg_plat origen_hsotg_pdata; + +static struct gpio_led origen_gpio_leds[] = { + { + .name = "origen::status1", + .default_trigger = "heartbeat", + .gpio = EXYNOS4_GPX1(3), + .active_low = 1, + }, + { + .name = "origen::status2", + .default_trigger = "mmc0", + .gpio = EXYNOS4_GPX1(4), + .active_low = 1, + }, +}; + +static struct gpio_led_platform_data origen_gpio_led_info = { + .leds = origen_gpio_leds, + .num_leds = ARRAY_SIZE(origen_gpio_leds), +}; + +static struct platform_device origen_leds_gpio = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &origen_gpio_led_info, + }, +}; + static struct gpio_keys_button origen_gpio_keys_table[] = { { .code = KEY_MENU, @@ -655,6 +687,7 @@ static struct platform_device *origen_devices[] __initdata = { &s3c_device_hsmmc0, &s3c_device_i2c0, &s3c_device_rtc, + &s3c_device_usb_hsotg, &s3c_device_wdt, &s5p_device_ehci, &s5p_device_fimc0, @@ -677,6 +710,7 @@ static struct platform_device *origen_devices[] __initdata = { &exynos4_device_ohci, &origen_device_gpiokeys, &origen_lcd_hv070wsa, + &origen_leds_gpio, &origen_device_bluetooth, }; @@ -712,7 +746,7 @@ static void s5p_tv_setup(void) static void __init origen_map_io(void) { exynos_init_io(NULL, 0); - s3c24xx_init_clocks(24000000); + s3c24xx_init_clocks(clk_xusbxti.rate); s3c24xx_init_uarts(origen_uartcfgs, ARRAY_SIZE(origen_uartcfgs)); } @@ -744,7 +778,7 @@ static void __init origen_machine_init(void) origen_ehci_init(); origen_ohci_init(); - clk_xusbxti.rate = 24000000; + s3c_hsotg_set_platdata(&origen_hsotg_pdata); s5p_tv_setup(); s5p_i2c_hdmiphy_set_platdata(NULL); diff --git a/arch/arm/mach-exynos/mach-smdk4x12.c b/arch/arm/mach-exynos/mach-smdk4x12.c index fb09c70e195a..b26beb13ebef 100644 --- a/arch/arm/mach-exynos/mach-smdk4x12.c +++ b/arch/arm/mach-exynos/mach-smdk4x12.c @@ -13,12 +13,14 @@ #include <linux/i2c.h> #include <linux/input.h> #include <linux/io.h> +#include <linux/lcd.h> #include <linux/mfd/max8997.h> #include <linux/mmc/host.h> #include <linux/platform_device.h> #include <linux/pwm_backlight.h> #include <linux/regulator/machine.h> #include <linux/serial_core.h> +#include <linux/platform_data/s3c-hsotg.h> #include <asm/mach/arch.h> #include <asm/hardware/gic.h> @@ -28,15 +30,18 @@ #include <plat/clock.h> #include <plat/cpu.h> #include <plat/devs.h> +#include <plat/fb.h> #include <plat/gpio-cfg.h> #include <plat/iic.h> #include <plat/keypad.h> #include <plat/mfc.h> +#include <plat/regs-fb.h> #include <plat/regs-serial.h> #include <plat/sdhci.h> #include <mach/map.h> +#include <drm/exynos_drm.h> #include "common.h" /* Following are default values for UCON, ULCON and UFCON UART registers */ @@ -219,8 +224,10 @@ static struct platform_pwm_backlight_data smdk4x12_bl_data = { static uint32_t smdk4x12_keymap[] __initdata = { /* KEY(row, col, keycode) */ - KEY(1, 0, KEY_D), KEY(1, 1, KEY_A), KEY(1, 2, KEY_B), - KEY(1, 3, KEY_E), KEY(1, 4, KEY_C) + KEY(1, 3, KEY_1), KEY(1, 4, KEY_2), KEY(1, 5, KEY_3), + KEY(1, 6, KEY_4), KEY(1, 7, KEY_5), + KEY(2, 5, KEY_D), KEY(2, 6, KEY_A), KEY(2, 7, KEY_B), + KEY(0, 7, KEY_E), KEY(0, 5, KEY_C) }; static struct matrix_keymap_data smdk4x12_keymap_data __initdata = { @@ -230,10 +237,62 @@ static struct matrix_keymap_data smdk4x12_keymap_data __initdata = { static struct samsung_keypad_platdata smdk4x12_keypad_data __initdata = { .keymap_data = &smdk4x12_keymap_data, - .rows = 2, - .cols = 5, + .rows = 3, + .cols = 8, }; +#ifdef CONFIG_DRM_EXYNOS +static struct exynos_drm_fimd_pdata drm_fimd_pdata = { + .panel = { + .timing = { + .left_margin = 8, + .right_margin = 8, + .upper_margin = 6, + .lower_margin = 6, + .hsync_len = 6, + .vsync_len = 4, + .xres = 480, + .yres = 800, + }, + }, + .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB, + .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, + .default_win = 0, + .bpp = 32, +}; +#else +static struct s3c_fb_pd_win smdk4x12_fb_win0 = { + .xres = 480, + .yres = 800, + .virtual_x = 480, + .virtual_y = 800 * 2, + .max_bpp = 32, + .default_bpp = 24, +}; + +static struct fb_videomode smdk4x12_lcd_timing = { + .left_margin = 8, + .right_margin = 8, + .upper_margin = 6, + .lower_margin = 6, + .hsync_len = 6, + .vsync_len = 4, + .xres = 480, + .yres = 800, +}; + +static struct s3c_fb_platdata smdk4x12_lcd_pdata __initdata = { + .win[0] = &smdk4x12_fb_win0, + .vtiming = &smdk4x12_lcd_timing, + .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB, + .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, + .setup_gpio = exynos4_fimd0_gpio_setup_24bpp, +}; +#endif + +/* USB OTG */ +static struct s3c_hsotg_plat smdk4x12_hsotg_pdata; + static struct platform_device *smdk4x12_devices[] __initdata = { &s3c_device_hsmmc2, &s3c_device_hsmmc3, @@ -242,22 +301,25 @@ static struct platform_device *smdk4x12_devices[] __initdata = { &s3c_device_i2c3, &s3c_device_i2c7, &s3c_device_rtc, + &s3c_device_usb_hsotg, &s3c_device_wdt, &s5p_device_fimc0, &s5p_device_fimc1, &s5p_device_fimc2, &s5p_device_fimc3, &s5p_device_fimc_md, + &s5p_device_fimd0, &s5p_device_mfc, &s5p_device_mfc_l, &s5p_device_mfc_r, +#ifdef CONFIG_DRM_EXYNOS + &exynos_device_drm, +#endif &samsung_device_keypad, }; static void __init smdk4x12_map_io(void) { - clk_xusbxti.rate = 24000000; - exynos_init_io(NULL, 0); s3c24xx_init_clocks(clk_xusbxti.rate); s3c24xx_init_uarts(smdk4x12_uartcfgs, ARRAY_SIZE(smdk4x12_uartcfgs)); @@ -293,6 +355,15 @@ static void __init smdk4x12_machine_init(void) s3c_sdhci2_set_platdata(&smdk4x12_hsmmc2_pdata); s3c_sdhci3_set_platdata(&smdk4x12_hsmmc3_pdata); + s3c_hsotg_set_platdata(&smdk4x12_hsotg_pdata); + +#ifdef CONFIG_DRM_EXYNOS + s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata; + exynos4_fimd0_gpio_setup_24bpp(); +#else + s5p_fimd0_set_platdata(&smdk4x12_lcd_pdata); +#endif + platform_add_devices(smdk4x12_devices, ARRAY_SIZE(smdk4x12_devices)); } diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c index 262e9e446a96..3cfa688d274a 100644 --- a/arch/arm/mach-exynos/mach-smdkv310.c +++ b/arch/arm/mach-exynos/mach-smdkv310.c @@ -19,6 +19,7 @@ #include <linux/i2c.h> #include <linux/input.h> #include <linux/pwm_backlight.h> +#include <linux/platform_data/s3c-hsotg.h> #include <asm/mach/arch.h> #include <asm/hardware/gic.h> @@ -34,7 +35,6 @@ #include <plat/keypad.h> #include <plat/sdhci.h> #include <plat/iic.h> -#include <plat/pd.h> #include <plat/gpio-cfg.h> #include <plat/backlight.h> #include <plat/mfc.h> @@ -271,6 +271,15 @@ static void __init smdkv310_ohci_init(void) exynos4_ohci_set_platdata(pdata); } +/* USB OTG */ +static struct s3c_hsotg_plat smdkv310_hsotg_pdata; + +/* Audio device */ +static struct platform_device smdkv310_device_audio = { + .name = "smdk-audio", + .id = -1, +}; + static struct platform_device *smdkv310_devices[] __initdata = { &s3c_device_hsmmc0, &s3c_device_hsmmc1, @@ -279,6 +288,7 @@ static struct platform_device *smdkv310_devices[] __initdata = { &s3c_device_i2c1, &s5p_device_i2c_hdmiphy, &s3c_device_rtc, + &s3c_device_usb_hsotg, &s3c_device_wdt, &s5p_device_ehci, &s5p_device_fimc0, @@ -302,6 +312,7 @@ static struct platform_device *smdkv310_devices[] __initdata = { &samsung_asoc_dma, &samsung_asoc_idma, &s5p_device_fimd0, + &smdkv310_device_audio, &smdkv310_lcd_lte480wv, &smdkv310_smsc911x, &exynos4_device_ahci, @@ -354,7 +365,7 @@ static void s5p_tv_setup(void) static void __init smdkv310_map_io(void) { exynos_init_io(NULL, 0); - s3c24xx_init_clocks(24000000); + s3c24xx_init_clocks(clk_xusbxti.rate); s3c24xx_init_uarts(smdkv310_uartcfgs, ARRAY_SIZE(smdkv310_uartcfgs)); } @@ -390,7 +401,7 @@ static void __init smdkv310_machine_init(void) smdkv310_ehci_init(); smdkv310_ohci_init(); - clk_xusbxti.rate = 24000000; + s3c_hsotg_set_platdata(&smdkv310_hsotg_pdata); platform_add_devices(smdkv310_devices, ARRAY_SIZE(smdkv310_devices)); } @@ -417,5 +428,6 @@ MACHINE_START(SMDKC210, "SMDKC210") .init_machine = smdkv310_machine_init, .init_late = exynos_init_late, .timer = &exynos4_timer, + .reserve = &smdkv310_reserve, .restart = exynos4_restart, MACHINE_END diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c index cd92fa86ba41..4d1f40d44ed1 100644 --- a/arch/arm/mach-exynos/mach-universal_c210.c +++ b/arch/arm/mach-exynos/mach-universal_c210.c @@ -39,7 +39,6 @@ #include <plat/fb.h> #include <plat/mfc.h> #include <plat/sdhci.h> -#include <plat/pd.h> #include <plat/regs-fb-v4.h> #include <plat/fimc-core.h> #include <plat/s5p-time.h> @@ -1100,9 +1099,8 @@ static struct platform_device *universal_devices[] __initdata = { static void __init universal_map_io(void) { - clk_xusbxti.rate = 24000000; exynos_init_io(NULL, 0); - s3c24xx_init_clocks(24000000); + s3c24xx_init_clocks(clk_xusbxti.rate); s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs)); s5p_set_timer_source(S5P_PWM2, S5P_PWM4); } diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c index 4aacb66f7161..3a48c852be6c 100644 --- a/arch/arm/mach-exynos/pmu.c +++ b/arch/arm/mach-exynos/pmu.c @@ -315,7 +315,7 @@ static struct exynos_pmu_conf exynos5250_pmu_config[] = { { PMU_TABLE_END,}, }; -void __iomem *exynos5_list_both_cnt_feed[] = { +static void __iomem *exynos5_list_both_cnt_feed[] = { EXYNOS5_ARM_CORE0_OPTION, EXYNOS5_ARM_CORE1_OPTION, EXYNOS5_ARM_COMMON_OPTION, @@ -329,7 +329,7 @@ void __iomem *exynos5_list_both_cnt_feed[] = { EXYNOS5_TOP_PWR_SYSMEM_OPTION, }; -void __iomem *exynos5_list_diable_wfi_wfe[] = { +static void __iomem *exynos5_list_diable_wfi_wfe[] = { EXYNOS5_ARM_CORE1_OPTION, EXYNOS5_FSYS_ARM_OPTION, EXYNOS5_ISP_ARM_OPTION, @@ -390,6 +390,8 @@ void exynos_sys_powerdown_conf(enum sys_powerdown mode) static int __init exynos_pmu_init(void) { + unsigned int value; + exynos_pmu_config = exynos4210_pmu_config; if (soc_is_exynos4210()) { @@ -399,6 +401,18 @@ static int __init exynos_pmu_init(void) exynos_pmu_config = exynos4x12_pmu_config; pr_info("EXYNOS4x12 PMU Initialize\n"); } else if (soc_is_exynos5250()) { + /* + * When SYS_WDTRESET is set, watchdog timer reset request + * is ignored by power management unit. + */ + value = __raw_readl(EXYNOS5_AUTO_WDTRESET_DISABLE); + value &= ~EXYNOS5_SYS_WDTRESET; + __raw_writel(value, EXYNOS5_AUTO_WDTRESET_DISABLE); + + value = __raw_readl(EXYNOS5_MASK_WDTRESET_REQUEST); + value &= ~EXYNOS5_SYS_WDTRESET; + __raw_writel(value, EXYNOS5_MASK_WDTRESET_REQUEST); + exynos_pmu_config = exynos5250_pmu_config; pr_info("EXYNOS5250 PMU Initialize\n"); } else { diff --git a/arch/arm/mach-exynos/setup-spi.c b/arch/arm/mach-exynos/setup-spi.c index 833ff40ee0e8..4999829d1c6e 100644 --- a/arch/arm/mach-exynos/setup-spi.c +++ b/arch/arm/mach-exynos/setup-spi.c @@ -9,21 +9,10 @@ */ #include <linux/gpio.h> -#include <linux/platform_device.h> - #include <plat/gpio-cfg.h> -#include <plat/s3c64xx-spi.h> #ifdef CONFIG_S3C64XX_DEV_SPI0 -struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = { - .fifo_lvl_mask = 0x1ff, - .rx_lvl_offset = 15, - .high_speed = 1, - .clk_from_cmu = true, - .tx_st_done = 25, -}; - -int s3c64xx_spi0_cfg_gpio(struct platform_device *dev) +int s3c64xx_spi0_cfg_gpio(void) { s3c_gpio_cfgpin(EXYNOS4_GPB(0), S3C_GPIO_SFN(2)); s3c_gpio_setpull(EXYNOS4_GPB(0), S3C_GPIO_PULL_UP); @@ -34,15 +23,7 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev) #endif #ifdef CONFIG_S3C64XX_DEV_SPI1 -struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = { - .fifo_lvl_mask = 0x7f, - .rx_lvl_offset = 15, - .high_speed = 1, - .clk_from_cmu = true, - .tx_st_done = 25, -}; - -int s3c64xx_spi1_cfg_gpio(struct platform_device *dev) +int s3c64xx_spi1_cfg_gpio(void) { s3c_gpio_cfgpin(EXYNOS4_GPB(4), S3C_GPIO_SFN(2)); s3c_gpio_setpull(EXYNOS4_GPB(4), S3C_GPIO_PULL_UP); @@ -53,15 +34,7 @@ int s3c64xx_spi1_cfg_gpio(struct platform_device *dev) #endif #ifdef CONFIG_S3C64XX_DEV_SPI2 -struct s3c64xx_spi_info s3c64xx_spi2_pdata __initdata = { - .fifo_lvl_mask = 0x7f, - .rx_lvl_offset = 15, - .high_speed = 1, - .clk_from_cmu = true, - .tx_st_done = 25, -}; - -int s3c64xx_spi2_cfg_gpio(struct platform_device *dev) +int s3c64xx_spi2_cfg_gpio(void) { s3c_gpio_cfgpin(EXYNOS4_GPC1(1), S3C_GPIO_SFN(5)); s3c_gpio_setpull(EXYNOS4_GPC1(1), S3C_GPIO_PULL_UP); diff --git a/arch/arm/mach-exynos/setup-usb-phy.c b/arch/arm/mach-exynos/setup-usb-phy.c index 1af0a7f44e00..b81cc569a8dd 100644 --- a/arch/arm/mach-exynos/setup-usb-phy.c +++ b/arch/arm/mach-exynos/setup-usb-phy.c @@ -31,27 +31,55 @@ static void exynos4210_usb_phy_clkset(struct platform_device *pdev) struct clk *xusbxti_clk; u32 phyclk; - /* set clock frequency for PLL */ - phyclk = readl(EXYNOS4_PHYCLK) & ~CLKSEL_MASK; - xusbxti_clk = clk_get(&pdev->dev, "xusbxti"); if (xusbxti_clk && !IS_ERR(xusbxti_clk)) { - switch (clk_get_rate(xusbxti_clk)) { - case 12 * MHZ: - phyclk |= CLKSEL_12M; - break; - case 24 * MHZ: - phyclk |= CLKSEL_24M; - break; - default: - case 48 * MHZ: - /* default reference clock */ - break; + if (soc_is_exynos4210()) { + /* set clock frequency for PLL */ + phyclk = readl(EXYNOS4_PHYCLK) & ~EXYNOS4210_CLKSEL_MASK; + + switch (clk_get_rate(xusbxti_clk)) { + case 12 * MHZ: + phyclk |= EXYNOS4210_CLKSEL_12M; + break; + case 48 * MHZ: + phyclk |= EXYNOS4210_CLKSEL_48M; + break; + default: + case 24 * MHZ: + phyclk |= EXYNOS4210_CLKSEL_24M; + break; + } + writel(phyclk, EXYNOS4_PHYCLK); + } else if (soc_is_exynos4212() || soc_is_exynos4412()) { + /* set clock frequency for PLL */ + phyclk = readl(EXYNOS4_PHYCLK) & ~EXYNOS4X12_CLKSEL_MASK; + + switch (clk_get_rate(xusbxti_clk)) { + case 9600 * KHZ: + phyclk |= EXYNOS4X12_CLKSEL_9600K; + break; + case 10 * MHZ: + phyclk |= EXYNOS4X12_CLKSEL_10M; + break; + case 12 * MHZ: + phyclk |= EXYNOS4X12_CLKSEL_12M; + break; + case 19200 * KHZ: + phyclk |= EXYNOS4X12_CLKSEL_19200K; + break; + case 20 * MHZ: + phyclk |= EXYNOS4X12_CLKSEL_20M; + break; + default: + case 24 * MHZ: + /* default reference clock */ + phyclk |= EXYNOS4X12_CLKSEL_24M; + break; + } + writel(phyclk, EXYNOS4_PHYCLK); } clk_put(xusbxti_clk); } - - writel(phyclk, EXYNOS4_PHYCLK); } static int exynos4210_usb_phy0_init(struct platform_device *pdev) |