diff options
Diffstat (limited to 'arch/arm/boot/dts/uniphier-common32.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/uniphier-common32.dtsi | 63 |
1 files changed, 56 insertions, 7 deletions
diff --git a/arch/arm/boot/dts/uniphier-common32.dtsi b/arch/arm/boot/dts/uniphier-common32.dtsi index 03f60ec340b5..8c8a85176b64 100644 --- a/arch/arm/boot/dts/uniphier-common32.dtsi +++ b/arch/arm/boot/dts/uniphier-common32.dtsi @@ -1,7 +1,8 @@ /* * Device Tree Source commonly used by UniPhier ARM SoCs * - * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -45,6 +46,11 @@ /include/ "skeleton.dtsi" / { + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + clocks { refclk: ref { #clock-cells = <0>; @@ -66,7 +72,7 @@ interrupts = <0 33 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; - clocks = <&uart_clk>; + clocks = <&peri_clk 0>; }; serial1: serial@54006900 { @@ -76,7 +82,7 @@ interrupts = <0 35 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; - clocks = <&uart_clk>; + clocks = <&peri_clk 1>; }; serial2: serial@54006a00 { @@ -86,7 +92,7 @@ interrupts = <0 37 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; - clocks = <&uart_clk>; + clocks = <&peri_clk 2>; }; serial3: serial@54006b00 { @@ -96,7 +102,7 @@ interrupts = <0 177 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; - clocks = <&uart_clk>; + clocks = <&peri_clk 3>; }; system_bus: system-bus@58c00000 { @@ -114,6 +120,34 @@ reg = <0x59801000 0x400>; }; + mioctrl@59810000 { + compatible = "socionext,uniphier-mioctrl", + "simple-mfd", "syscon"; + reg = <0x59810000 0x800>; + + mio_clk: clock { + #clock-cells = <1>; + }; + + mio_rst: reset { + #reset-cells = <1>; + }; + }; + + perictrl@59820000 { + compatible = "socionext,uniphier-perictrl", + "simple-mfd", "syscon"; + reg = <0x59820000 0x200>; + + peri_clk: clock { + #clock-cells = <1>; + }; + + peri_rst: reset { + #reset-cells = <1>; + }; + }; + timer@60000200 { compatible = "arm,cortex-a9-global-timer"; reg = <0x60000200 0x20>; @@ -137,11 +171,26 @@ }; soc-glue@5f800000 { - compatible = "simple-mfd", "syscon"; + compatible = "socionext,uniphier-soc-glue", + "simple-mfd", "syscon"; reg = <0x5f800000 0x2000>; pinctrl: pinctrl { - /* specify compatible in each SoC DTSI */ + /* specify compatible in each SoC DTSI */ + }; + }; + + sysctrl@61840000 { + compatible = "socionext,uniphier-sysctrl", + "simple-mfd", "syscon"; + reg = <0x61840000 0x4000>; + + sys_clk: clock { + #clock-cells = <1>; + }; + + sys_rst: reset { + #reset-cells = <1>; }; }; }; |