diff options
Diffstat (limited to 'arch/arm/boot/dts/qcom-msm8660.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/qcom-msm8660.dtsi | 25 |
1 files changed, 16 insertions, 9 deletions
diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi index 70698941f64c..993107ed1476 100644 --- a/arch/arm/boot/dts/qcom-msm8660.dtsi +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi @@ -1,14 +1,14 @@ // SPDX-License-Identifier: GPL-2.0 /dts-v1/; -/include/ "skeleton.dtsi" - #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/qcom,gcc-msm8660.h> #include <dt-bindings/soc/qcom,gsbi.h> / { + #address-cells = <1>; + #size-cells = <1>; model = "Qualcomm MSM8660"; compatible = "qcom,msm8660"; interrupt-parent = <&intc>; @@ -39,6 +39,11 @@ }; }; + memory { + device_type = "memory"; + reg = <0x0 0x0>; + }; + cpu-pmu { compatible = "qcom,scorpion-mp-pmu"; interrupts = <1 9 0x304>; @@ -133,6 +138,7 @@ #address-cells = <1>; #size-cells = <1>; ranges; + status = "disabled"; syscon-tcsr = <&tcsr>; @@ -140,7 +146,7 @@ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; reg = <0x16540000 0x1000>, <0x16500000 0x1000>; - interrupts = <GIC_SPI 156 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>; clock-names = "core", "iface"; status = "disabled"; @@ -149,7 +155,7 @@ gsbi6_i2c: i2c@16580000 { compatible = "qcom,i2c-qup-v1.1.1"; reg = <0x16580000 0x1000>; - interrupts = <GIC_SPI 157 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>; clock-names = "core", "iface"; #address-cells = <1>; @@ -167,6 +173,7 @@ #address-cells = <1>; #size-cells = <1>; ranges; + status = "disabled"; syscon-tcsr = <&tcsr>; @@ -174,7 +181,7 @@ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; reg = <0x16640000 0x1000>, <0x16600000 0x1000>; - interrupts = <GIC_SPI 158 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>; clock-names = "core", "iface"; status = "disabled"; @@ -183,7 +190,7 @@ gsbi7_i2c: i2c@16680000 { compatible = "qcom,i2c-qup-v1.1.1"; reg = <0x16680000 0x1000>; - interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>; clock-names = "core", "iface"; #address-cells = <1>; @@ -207,7 +214,7 @@ gsbi8_i2c: i2c@19880000 { compatible = "qcom,i2c-qup-v1.1.1"; reg = <0x19880000 0x1000>; - interrupts = <GIC_SPI 161 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GSBI8_QUP_CLK>, <&gcc GSBI8_H_CLK>; clock-names = "core", "iface"; #address-cells = <1>; @@ -232,7 +239,7 @@ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; reg = <0x19c40000 0x1000>, <0x19c00000 0x1000>; - interrupts = <0 195 IRQ_TYPE_NONE>; + interrupts = <0 195 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>; clock-names = "core", "iface"; status = "disabled"; @@ -241,7 +248,7 @@ gsbi12_i2c: i2c@19c80000 { compatible = "qcom,i2c-qup-v1.1.1"; reg = <0x19c80000 0x1000>; - interrupts = <0 196 IRQ_TYPE_NONE>; + interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GSBI12_QUP_CLK>, <&gcc GSBI12_H_CLK>; clock-names = "core", "iface"; #address-cells = <1>; |