diff options
Diffstat (limited to 'arch/arm/boot/dts/imx6sl.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx6sl.dtsi | 64 |
1 files changed, 56 insertions, 8 deletions
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index 994e48dc1df0..7a4f5dace902 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -60,6 +60,7 @@ 396000 1175000 >; clock-latency = <61036>; /* two CLK32 periods */ + #cooling-cells = <2>; clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>, <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>, <&clks IMX6SL_CLK_PLL1_SYS>; @@ -523,8 +524,8 @@ regulator-1p1 { compatible = "fsl,anatop-regulator"; regulator-name = "vdd1p1"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1375000>; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; regulator-always-on; anatop-reg-offset = <0x110>; anatop-vol-bit-shift = <8>; @@ -553,8 +554,8 @@ regulator-2p5 { compatible = "fsl,anatop-regulator"; regulator-name = "vdd2p5"; - regulator-min-microvolt = <2100000>; - regulator-max-microvolt = <2850000>; + regulator-min-microvolt = <2250000>; + regulator-max-microvolt = <2750000>; regulator-always-on; anatop-reg-offset = <0x130>; anatop-vol-bit-shift = <8>; @@ -680,10 +681,36 @@ #interrupt-cells = <3>; interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&intc>; - pu-supply = <®_pu>; - clocks = <&clks IMX6SL_CLK_GPU2D_OVG>, - <&clks IMX6SL_CLK_GPU2D_PODF>; - #power-domain-cells = <1>; + clocks = <&clks IMX6SL_CLK_IPG>; + clock-names = "ipg"; + + pgc { + #address-cells = <1>; + #size-cells = <0>; + + power-domain@0 { + reg = <0>; + #power-domain-cells = <0>; + }; + + pd_pu: power-domain@1 { + reg = <1>; + #power-domain-cells = <0>; + power-supply = <®_pu>; + clocks = <&clks IMX6SL_CLK_GPU2D_OVG>, + <&clks IMX6SL_CLK_GPU2D_PODF>; + }; + + pd_disp: power-domain@2 { + reg = <2>; + #power-domain-cells = <0>; + clocks = <&clks IMX6SL_CLK_LCDIF_AXI>, + <&clks IMX6SL_CLK_LCDIF_PIX>, + <&clks IMX6SL_CLK_EPDC_AXI>, + <&clks IMX6SL_CLK_EPDC_PIX>, + <&clks IMX6SL_CLK_PXP_AXI>; + }; + }; }; gpr: iomuxc-gpr@20e0000 { @@ -738,6 +765,7 @@ <&clks IMX6SL_CLK_DUMMY>; clock-names = "pix", "axi", "disp_axi"; status = "disabled"; + power-domains = <&pd_disp>; }; dcp: dcp@20fc000 { @@ -921,5 +949,25 @@ status = "disabled"; }; }; + + gpu_2d: gpu@2200000 { + compatible = "vivante,gc"; + reg = <0x02200000 0x4000>; + interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SL_CLK_MMDC_ROOT>, + <&clks IMX6SL_CLK_GPU2D_OVG>; + clock-names = "bus", "core"; + power-domains = <&pd_pu>; + }; + + gpu_vg: gpu@2204000 { + compatible = "vivante,gc"; + reg = <0x02204000 0x4000>; + interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SL_CLK_MMDC_ROOT>, + <&clks IMX6SL_CLK_GPU2D_OVG>; + clock-names = "bus", "core"; + power-domains = <&pd_pu>; + }; }; }; |