diff options
Diffstat (limited to 'arch/arm/boot/dts/dra7.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/dra7.dtsi | 249 |
1 files changed, 222 insertions, 27 deletions
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index ab01f2d0e590..c29945e07c5a 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -33,33 +33,6 @@ serial5 = &uart6; }; - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - - operating-points = < - /* kHz uV */ - 1000000 1060000 - 1176000 1160000 - >; - - clocks = <&dpll_mpu_ck>; - clock-names = "cpu"; - - clock-latency = <300000>; /* From omap-cpufreq driver */ - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <1>; - }; - }; - timer { compatible = "arm,armv7-timer"; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, @@ -789,6 +762,228 @@ dma-names = "tx0", "rx0"; status = "disabled"; }; + + qspi: qspi@4b300000 { + compatible = "ti,dra7xxx-qspi"; + reg = <0x4b300000 0x100>; + reg-names = "qspi_base"; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "qspi"; + clocks = <&qspi_gfclk_div>; + clock-names = "fck"; + num-cs = <4>; + interrupts = <0 343 0x4>; + status = "disabled"; + }; + + omap_control_sata: control-phy@4a002374 { + compatible = "ti,control-phy-pipe3"; + reg = <0x4a002374 0x4>; + reg-names = "power"; + clocks = <&sys_clkin1>; + clock-names = "sysclk"; + }; + + /* OCP2SCP3 */ + ocp2scp@4a090000 { + compatible = "ti,omap-ocp2scp"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + reg = <0x4a090000 0x20>; + ti,hwmods = "ocp2scp3"; + sata_phy: phy@4A096000 { + compatible = "ti,phy-pipe3-sata"; + reg = <0x4A096000 0x80>, /* phy_rx */ + <0x4A096400 0x64>, /* phy_tx */ + <0x4A096800 0x40>; /* pll_ctrl */ + reg-names = "phy_rx", "phy_tx", "pll_ctrl"; + ctrl-module = <&omap_control_sata>; + clocks = <&sys_clkin1>; + clock-names = "sysclk"; + #phy-cells = <0>; + }; + }; + + sata: sata@4a141100 { + compatible = "snps,dwc-ahci"; + reg = <0x4a140000 0x1100>, <0x4a141100 0x7>; + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; + phys = <&sata_phy>; + phy-names = "sata-phy"; + clocks = <&sata_ref_clk>; + ti,hwmods = "sata"; + }; + + omap_control_usb2phy1: control-phy@4a002300 { + compatible = "ti,control-phy-usb2"; + reg = <0x4a002300 0x4>; + reg-names = "power"; + }; + + omap_control_usb3phy1: control-phy@4a002370 { + compatible = "ti,control-phy-pipe3"; + reg = <0x4a002370 0x4>; + reg-names = "power"; + }; + + omap_control_usb2phy2: control-phy@0x4a002e74 { + compatible = "ti,control-phy-usb2-dra7"; + reg = <0x4a002e74 0x4>; + reg-names = "power"; + }; + + /* OCP2SCP1 */ + ocp2scp@4a080000 { + compatible = "ti,omap-ocp2scp"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + reg = <0x4a080000 0x20>; + ti,hwmods = "ocp2scp1"; + + usb2_phy1: phy@4a084000 { + compatible = "ti,omap-usb2"; + reg = <0x4a084000 0x400>; + ctrl-module = <&omap_control_usb2phy1>; + clocks = <&usb_phy1_always_on_clk32k>, + <&usb_otg_ss1_refclk960m>; + clock-names = "wkupclk", + "refclk"; + #phy-cells = <0>; + }; + + usb2_phy2: phy@4a085000 { + compatible = "ti,omap-usb2"; + reg = <0x4a085000 0x400>; + ctrl-module = <&omap_control_usb2phy2>; + clocks = <&usb_phy2_always_on_clk32k>, + <&usb_otg_ss2_refclk960m>; + clock-names = "wkupclk", + "refclk"; + #phy-cells = <0>; + }; + + usb3_phy1: phy@4a084400 { + compatible = "ti,omap-usb3"; + reg = <0x4a084400 0x80>, + <0x4a084800 0x64>, + <0x4a084c00 0x40>; + reg-names = "phy_rx", "phy_tx", "pll_ctrl"; + ctrl-module = <&omap_control_usb3phy1>; + clocks = <&usb_phy3_always_on_clk32k>, + <&sys_clkin1>, + <&usb_otg_ss1_refclk960m>; + clock-names = "wkupclk", + "sysclk", + "refclk"; + #phy-cells = <0>; + }; + }; + + omap_dwc3_1@48880000 { + compatible = "ti,dwc3"; + ti,hwmods = "usb_otg_ss1"; + reg = <0x48880000 0x10000>; + interrupts = <0 77 4>; + #address-cells = <1>; + #size-cells = <1>; + utmi-mode = <2>; + ranges; + usb1: usb@48890000 { + compatible = "snps,dwc3"; + reg = <0x48890000 0x17000>; + interrupts = <0 76 4>; + phys = <&usb2_phy1>, <&usb3_phy1>; + phy-names = "usb2-phy", "usb3-phy"; + tx-fifo-resize; + maximum-speed = "super-speed"; + dr_mode = "otg"; + }; + }; + + omap_dwc3_2@488c0000 { + compatible = "ti,dwc3"; + ti,hwmods = "usb_otg_ss2"; + reg = <0x488c0000 0x10000>; + interrupts = <0 92 4>; + #address-cells = <1>; + #size-cells = <1>; + utmi-mode = <2>; + ranges; + usb2: usb@488d0000 { + compatible = "snps,dwc3"; + reg = <0x488d0000 0x17000>; + interrupts = <0 78 4>; + phys = <&usb2_phy2>; + phy-names = "usb2-phy"; + tx-fifo-resize; + maximum-speed = "high-speed"; + dr_mode = "otg"; + }; + }; + + /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */ + omap_dwc3_3@48900000 { + compatible = "ti,dwc3"; + ti,hwmods = "usb_otg_ss3"; + reg = <0x48900000 0x10000>; + /* interrupts = <0 TBD 4>; */ + #address-cells = <1>; + #size-cells = <1>; + utmi-mode = <2>; + ranges; + status = "disabled"; + usb3: usb@48910000 { + compatible = "snps,dwc3"; + reg = <0x48910000 0x17000>; + /* interrupts = <0 93 4>; */ + tx-fifo-resize; + maximum-speed = "high-speed"; + dr_mode = "otg"; + }; + }; + + omap_dwc3_4@48940000 { + compatible = "ti,dwc3"; + ti,hwmods = "usb_otg_ss4"; + reg = <0x48940000 0x10000>; + /* interrupts = <0 TBD 4>; */ + #address-cells = <1>; + #size-cells = <1>; + utmi-mode = <2>; + ranges; + status = "disabled"; + usb4: usb@48950000 { + compatible = "snps,dwc3"; + reg = <0x48950000 0x17000>; + /* interrupts = <0 TBD 4>; */ + tx-fifo-resize; + maximum-speed = "high-speed"; + dr_mode = "otg"; + }; + }; + + elm: elm@48078000 { + compatible = "ti,am3352-elm"; + reg = <0x48078000 0xfc0>; /* device IO registers */ + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + ti,hwmods = "elm"; + status = "disabled"; + }; + + gpmc: gpmc@50000000 { + compatible = "ti,am3352-gpmc"; + ti,hwmods = "gpmc"; + reg = <0x50000000 0x37c>; /* device IO registers */ + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + gpmc,num-cs = <8>; + gpmc,num-waitpins = <2>; + #address-cells = <2>; + #size-cells = <1>; + status = "disabled"; + }; }; }; |