diff options
Diffstat (limited to 'Documentation')
28 files changed, 505 insertions, 162 deletions
diff --git a/Documentation/devicetree/bindings/net/brcm,amac.txt b/Documentation/devicetree/bindings/net/brcm,amac.txt index ba5ecc1041a5..2fefa1a44afd 100644 --- a/Documentation/devicetree/bindings/net/brcm,amac.txt +++ b/Documentation/devicetree/bindings/net/brcm,amac.txt @@ -2,11 +2,17 @@ Broadcom AMAC Ethernet Controller Device Tree Bindings ------------------------------------------------------------- Required properties: - - compatible: "brcm,amac" or "brcm,nsp-amac" - - reg: Address and length of the GMAC registers, - Address and length of the GMAC IDM registers - - reg-names: Names of the registers. Must have both "amac_base" and - "idm_base" + - compatible: "brcm,amac" + "brcm,nsp-amac" + "brcm,ns2-amac" + - reg: Address and length of the register set for the device. It + contains the information of registers in the same order as + described by reg-names + - reg-names: Names of the registers. + "amac_base": Address and length of the GMAC registers + "idm_base": Address and length of the GMAC IDM registers + "nicpm_base": Address and length of the NIC Port Manager + registers (required for Northstar2) - interrupts: Interrupt number Optional properties: diff --git a/Documentation/devicetree/bindings/net/can/rcar_can.txt b/Documentation/devicetree/bindings/net/can/rcar_can.txt index 8d40ab27bc8c..06bb7cc334c8 100644 --- a/Documentation/devicetree/bindings/net/can/rcar_can.txt +++ b/Documentation/devicetree/bindings/net/can/rcar_can.txt @@ -10,6 +10,7 @@ Required properties: "renesas,can-r8a7793" if CAN controller is a part of R8A7793 SoC. "renesas,can-r8a7794" if CAN controller is a part of R8A7794 SoC. "renesas,can-r8a7795" if CAN controller is a part of R8A7795 SoC. + "renesas,can-r8a7796" if CAN controller is a part of R8A7796 SoC. "renesas,rcar-gen1-can" for a generic R-Car Gen1 compatible device. "renesas,rcar-gen2-can" for a generic R-Car Gen2 compatible device. "renesas,rcar-gen3-can" for a generic R-Car Gen3 compatible device. @@ -24,11 +25,12 @@ Required properties: - pinctrl-0: pin control group to be used for this controller. - pinctrl-names: must be "default". -Required properties for "renesas,can-r8a7795" compatible: -In R8A7795 SoC, "clkp2" can be CANFD clock. This is a div6 clock and can be -used by both CAN and CAN FD controller at the same time. It needs to be scaled -to maximum frequency if any of these controllers use it. This is done using -the below properties. +Required properties for "renesas,can-r8a7795" and "renesas,can-r8a7796" +compatible: +In R8A7795 and R8A7796 SoCs, "clkp2" can be CANFD clock. This is a div6 clock +and can be used by both CAN and CAN FD controller at the same time. It needs to +be scaled to maximum frequency if any of these controllers use it. This is done +using the below properties: - assigned-clocks: phandle of clkp2(CANFD) clock. - assigned-clock-rates: maximum frequency of this clock. diff --git a/Documentation/devicetree/bindings/net/can/rcar_canfd.txt b/Documentation/devicetree/bindings/net/can/rcar_canfd.txt index 22a6f10bab05..93c3a6ae32f9 100644 --- a/Documentation/devicetree/bindings/net/can/rcar_canfd.txt +++ b/Documentation/devicetree/bindings/net/can/rcar_canfd.txt @@ -5,13 +5,14 @@ Required properties: - compatible: Must contain one or more of the following: - "renesas,rcar-gen3-canfd" for R-Car Gen3 compatible controller. - "renesas,r8a7795-canfd" for R8A7795 (R-Car H3) compatible controller. + - "renesas,r8a7796-canfd" for R8A7796 (R-Car M3) compatible controller. When compatible with the generic version, nodes must list the SoC-specific version corresponding to the platform first, followed by the family-specific and/or generic versions. - reg: physical base address and size of the R-Car CAN FD register map. -- interrupts: interrupt specifier for the Global & Channel interrupts +- interrupts: interrupt specifiers for the Channel & Global interrupts - clocks: phandles and clock specifiers for 3 clock inputs. - clock-names: 3 clock input name strings: "fck", "canfd", "can_clk". - pinctrl-0: pin control group to be used for this controller. @@ -23,11 +24,12 @@ The name of the child nodes are "channel0" and "channel1" respectively. Each child node supports the "status" property only, which is used to enable/disable the respective channel. -Required properties for "renesas,r8a7795-canfd" compatible: -In R8A7795 SoC, canfd clock is a div6 clock and can be used by both CAN -and CAN FD controller at the same time. It needs to be scaled to maximum -frequency if any of these controllers use it. This is done using the -below properties. +Required properties for "renesas,r8a7795-canfd" and "renesas,r8a7796-canfd" +compatible: +In R8A7795 and R8A7796 SoCs, canfd clock is a div6 clock and can be used by both +CAN and CAN FD controller at the same time. It needs to be scaled to maximum +frequency if any of these controllers use it. This is done using the below +properties: - assigned-clocks: phandle of canfd clock. - assigned-clock-rates: maximum frequency of this clock. diff --git a/Documentation/devicetree/bindings/net/cpsw.txt b/Documentation/devicetree/bindings/net/cpsw.txt index 5ad439f30135..ebda7c93453a 100644 --- a/Documentation/devicetree/bindings/net/cpsw.txt +++ b/Documentation/devicetree/bindings/net/cpsw.txt @@ -20,8 +20,6 @@ Required properties: - slaves : Specifies number for slaves - active_slave : Specifies the slave to use for time stamping, ethtool and SIOCGMIIPHY -- cpts_clock_mult : Numerator to convert input clock ticks into nanoseconds -- cpts_clock_shift : Denominator to convert input clock ticks into nanoseconds Optional properties: - ti,hwmods : Must be "cpgmac0" @@ -35,7 +33,11 @@ Optional properties: For example in dra72x-evm, pcf gpio has to be driven low so that cpsw slave 0 and phy data lines are connected via mux. - +- cpts_clock_mult : Numerator to convert input clock ticks into nanoseconds +- cpts_clock_shift : Denominator to convert input clock ticks into nanoseconds + Mult and shift will be calculated basing on CPTS + rftclk frequency if both cpts_clock_shift and + cpts_clock_mult properties are not provided. Slave Properties: Required properties: diff --git a/Documentation/devicetree/bindings/net/dsa/marvell.txt b/Documentation/devicetree/bindings/net/dsa/marvell.txt index 7629189398aa..b3dd6b40e0de 100644 --- a/Documentation/devicetree/bindings/net/dsa/marvell.txt +++ b/Documentation/devicetree/bindings/net/dsa/marvell.txt @@ -14,22 +14,42 @@ The properties described here are those specific to Marvell devices. Additional required and optional properties can be found in dsa.txt. Required properties: -- compatible : Should be one of "marvell,mv88e6085", +- compatible : Should be one of "marvell,mv88e6085" or + "marvell,mv88e6190" - reg : Address on the MII bus for the switch. Optional properties: - reset-gpios : Should be a gpio specifier for a reset line - +- interrupt-parent : Parent interrupt controller +- interrupts : Interrupt from the switch +- interrupt-controller : Indicates the switch is itself an interrupt + controller. This is used for the PHY interrupts. +#interrupt-cells = <2> : Controller uses two cells, number and flag +- mdio : container of PHY and devices on the switches MDIO + bus Example: mdio { #address-cells = <1>; #size-cells = <0>; + interrupt-parent = <&gpio0>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; switch0: switch@0 { compatible = "marvell,mv88e6085"; reg = <0>; reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; }; + mdio { + #address-cells = <1>; + #size-cells = <0>; + switch1phy0: switch1phy0@0 { + reg = <0>; + interrupt-parent = <&switch0>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + }; + }; }; diff --git a/Documentation/devicetree/bindings/net/hisilicon-hix5hd2-gmac.txt b/Documentation/devicetree/bindings/net/hisilicon-hix5hd2-gmac.txt index 75d398bb1fbb..063c02da018a 100644 --- a/Documentation/devicetree/bindings/net/hisilicon-hix5hd2-gmac.txt +++ b/Documentation/devicetree/bindings/net/hisilicon-hix5hd2-gmac.txt @@ -1,7 +1,12 @@ Hisilicon hix5hd2 gmac controller Required properties: -- compatible: should be "hisilicon,hix5hd2-gmac". +- compatible: should contain one of the following SoC strings: + * "hisilicon,hix5hd2-gemac" + * "hisilicon,hi3798cv200-gemac" + and one of the following version string: + * "hisilicon,hisi-gemac-v1" + * "hisilicon,hisi-gemac-v2" - reg: specifies base physical address(s) and size of the device registers. The first region is the MAC register base and size. The second region is external interface control register. @@ -12,6 +17,16 @@ Required properties: - phy-handle: see ethernet.txt [1]. - mac-address: see ethernet.txt [1]. - clocks: clock phandle and specifier pair. +- clock-names: contain the clock name "mac_core"(required) and "mac_ifc"(optional). +- resets: should contain the phandle to the MAC core reset signal(optional), + the MAC interface reset signal(optional) + and the PHY reset signal(optional). +- reset-names: contain the reset signal name "mac_core"(optional), + "mac_ifc"(optional) and "phy"(optional). +- hisilicon,phy-reset-delays-us: triplet of delays if PHY reset signal given. + The 1st cell is reset pre-delay in micro seconds. + The 2nd cell is reset pulse in micro seconds. + The 3rd cell is reset post-delay in micro seconds. - PHY subnode: inherits from phy binding [2] @@ -20,15 +35,19 @@ Required properties: Example: gmac0: ethernet@f9840000 { - compatible = "hisilicon,hix5hd2-gmac"; + compatible = "hisilicon,hi3798cv200-gemac", "hisilicon,hisi-gemac-v2"; reg = <0xf9840000 0x1000>,<0xf984300c 0x4>; interrupts = <0 71 4>; #address-cells = <1>; #size-cells = <0>; - phy-mode = "mii"; + phy-mode = "rgmii"; phy-handle = <&phy2>; mac-address = [00 00 00 00 00 00]; - clocks = <&clock HIX5HD2_MAC0_CLK>; + clocks = <&crg HISTB_ETH0_MAC_CLK>, <&crg HISTB_ETH0_MACIF_CLK>; + clock-names = "mac_core", "mac_ifc"; + resets = <&crg 0xcc 8>, <&crg 0xcc 10>, <&crg 0xcc 12>; + reset-names = "mac_core", "mac_ifc", "phy"; + hisilicon,phy-reset-delays-us = <10000 10000 30000>; phy2: ethernet-phy@2 { reg = <2>; diff --git a/Documentation/devicetree/bindings/net/hisilicon-hns-dsaf.txt b/Documentation/devicetree/bindings/net/hisilicon-hns-dsaf.txt index d4b7f2e49984..abfbeecbcf39 100644 --- a/Documentation/devicetree/bindings/net/hisilicon-hns-dsaf.txt +++ b/Documentation/devicetree/bindings/net/hisilicon-hns-dsaf.txt @@ -45,6 +45,12 @@ Required properties: depends on the hardware user manual. - port-mode-offset: is offset of port mode field for each port in dsaf. Its value depends on the hardware user manual. +- mc-mac-mask: mask of multicast address, determines bit in multicast address + to set: + 1 stands for this bit will be precisely matched, TCAM will check this bit of + MAC address. + 0 stands for this bit will be fuzzy matched, TCAM won't care about this bit + of MAC address. [1] Documentation/devicetree/bindings/net/phy.txt @@ -74,10 +80,12 @@ dsaf0: dsa@c7000000 { reg = 0; phy-handle = <&phy0>; serdes-syscon = <&serdes>; + mc-mac-mask = [ff f0 00 00 00 00]; }; port@1 { reg = 1; serdes-syscon = <&serdes>; + mc-mac-mask = [ff f0 00 00 00 00]; }; }; diff --git a/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt b/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt index 73be8970815e..7aa840c8768d 100644 --- a/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt +++ b/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt @@ -1,7 +1,10 @@ -* Marvell Armada 370 / Armada XP Ethernet Controller (NETA) +* Marvell Armada 370 / Armada XP / Armada 3700 Ethernet Controller (NETA) Required properties: -- compatible: "marvell,armada-370-neta" or "marvell,armada-xp-neta". +- compatible: could be one of the followings + "marvell,armada-370-neta" + "marvell,armada-xp-neta" + "marvell,armada-3700-neta" - reg: address and length of the register set for the device. - interrupts: interrupt for the device - phy: See ethernet.txt file in the same directory. diff --git a/Documentation/devicetree/bindings/net/mdio-mux-mmioreg.txt b/Documentation/devicetree/bindings/net/mdio-mux-mmioreg.txt index 8516929c7251..065e8bdb957d 100644 --- a/Documentation/devicetree/bindings/net/mdio-mux-mmioreg.txt +++ b/Documentation/devicetree/bindings/net/mdio-mux-mmioreg.txt @@ -3,7 +3,7 @@ Properties for an MDIO bus multiplexer controlled by a memory-mapped device This is a special case of a MDIO bus multiplexer. A memory-mapped device, like an FPGA, is used to control which child bus is connected. The mdio-mux node must be a child of the memory-mapped device. The driver currently only -supports devices with eight-bit registers. +supports devices with 8, 16 or 32-bit registers. Required properties in addition to the generic multiplexer properties: @@ -11,7 +11,7 @@ Required properties in addition to the generic multiplexer properties: - reg : integer, contains the offset of the register that controls the bus multiplexer. The size field in the 'reg' property is the size of - register, and must therefore be 1. + register, and must therefore be 1, 2, or 4. - mux-mask : integer, contains an eight-bit mask that specifies which bits in the register control the actual bus multiplexer. The diff --git a/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt b/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt index 99c7eb0a00c8..bdefefc66594 100644 --- a/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt +++ b/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt @@ -6,22 +6,27 @@ Required properties: Documentation/devicetree/bindings/net/phy.txt Optional properties: -- vsc8531,vddmac : The vddmac in mV. +- vsc8531,vddmac : The vddmac in mV. Allowed values is listed + in the first row of Table 1 (below). + This property is only used in combination + with the 'edge-slowdown' property. + Default value is 3300. - vsc8531,edge-slowdown : % the edge should be slowed down relative to - the fastest possible edge time. Native sign - need not enter. + the fastest possible edge time. Edge rate sets the drive strength of the MAC - interface output signals. Changing the drive - strength will affect the edge rate of the output - signal. The goal of this setting is to help - reduce electrical emission (EMI) by being able - to reprogram drive strength and in effect slow - down the edge rate if desired. Table 1 shows the - impact to the edge rate per VDDMAC supply for each - drive strength setting. - Ref: Table:1 - Edge rate change below. - -Note: see dt-bindings/net/mscc-phy-vsc8531.h for applicable values + interface output signals. Changing the + drive strength will affect the edge rate of + the output signal. The goal of this setting + is to help reduce electrical emission (EMI) + by being able to reprogram drive strength + and in effect slow down the edge rate if + desired. + To adjust the edge-slowdown, the 'vddmac' + must be specified. Table 1 lists the + supported edge-slowdown values for a given + 'vddmac'. + Default value is 0%. + Ref: Table:1 - Edge rate change (below). Table: 1 - Edge rate change ----------------------------------------------------------------| @@ -29,23 +34,23 @@ Table: 1 - Edge rate change | | | 3300 mV 2500 mV 1800 mV 1500 mV | |---------------------------------------------------------------| -| Default Deafult Default Default | +| 0% 0% 0% 0% | | (Fastest) (recommended) (recommended) | |---------------------------------------------------------------| -| -2% -3% -5% -6% | +| 2% 3% 5% 6% | |---------------------------------------------------------------| -| -4% -6% -9% -14% | +| 4% 6% 9% 14% | |---------------------------------------------------------------| -| -7% -10% -16% -21% | +| 7% 10% 16% 21% | |(recommended) (recommended) | |---------------------------------------------------------------| -| -10% -14% -23% -29% | +| 10% 14% 23% 29% | |---------------------------------------------------------------| -| -17% -23% -35% -42% | +| 17% 23% 35% 42% | |---------------------------------------------------------------| -| -29% -37% -52% -58% | +| 29% 37% 52% 58% | |---------------------------------------------------------------| -| -53% -63% -76% -77% | +| 53% 63% 76% 77% | | (slowest) | |---------------------------------------------------------------| @@ -54,5 +59,5 @@ Example: vsc8531_0: ethernet-phy@0 { compatible = "ethernet-phy-id0007.0570"; vsc8531,vddmac = <3300>; - vsc8531,edge-slowdown = <21>; + vsc8531,edge-slowdown = <7>; }; diff --git a/Documentation/devicetree/bindings/net/oxnas-dwmac.txt b/Documentation/devicetree/bindings/net/oxnas-dwmac.txt new file mode 100644 index 000000000000..df0534e2eda1 --- /dev/null +++ b/Documentation/devicetree/bindings/net/oxnas-dwmac.txt @@ -0,0 +1,39 @@ +* Oxford Semiconductor OXNAS DWMAC Ethernet controller + +The device inherits all the properties of the dwmac/stmmac devices +described in the file stmmac.txt in the current directory with the +following changes. + +Required properties on all platforms: + +- compatible: For the OX820 SoC, it should be : + - "oxsemi,ox820-dwmac" to select glue + - "snps,dwmac-3.512" to select IP version. + +- clocks: Should contain phandles to the following clocks +- clock-names: Should contain the following: + - "stmmaceth" for the host clock - see stmmac.txt + - "gmac" for the peripheral gate clock + +- oxsemi,sys-ctrl: a phandle to the system controller syscon node + +Example : + +etha: ethernet@40400000 { + compatible = "oxsemi,ox820-dwmac", "snps,dwmac-3.512"; + reg = <0x40400000 0x2000>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq", "eth_wake_irq"; + mac-address = [000000000000]; /* Filled in by U-Boot */ + phy-mode = "rgmii"; + + clocks = <&stdclk CLK_820_ETHA>, <&gmacclk>; + clock-names = "gmac", "stmmaceth"; + resets = <&reset RESET_MAC>; + + /* Regmap for sys registers */ + oxsemi,sys-ctrl = <&sys>; + + status = "disabled"; +}; diff --git a/Documentation/devicetree/bindings/net/phy.txt b/Documentation/devicetree/bindings/net/phy.txt index bc1c3c8bf8fa..54749b60a466 100644 --- a/Documentation/devicetree/bindings/net/phy.txt +++ b/Documentation/devicetree/bindings/net/phy.txt @@ -35,6 +35,12 @@ Optional Properties: - broken-turn-around: If set, indicates the PHY device does not correctly release the turn around line low at the end of a MDIO transaction. +- enet-phy-lane-swap: If set, indicates the PHY will swap the TX/RX lanes to + compensate for the board being designed with the lanes swapped. + +- eee-broken-modes: Bits to clear in the MDIO_AN_EEE_ADV register to + disable EEE broken modes. + Example: ethernet-phy@0 { diff --git a/Documentation/devicetree/bindings/net/smsc-lan91c111.txt b/Documentation/devicetree/bindings/net/smsc-lan91c111.txt index e77e167593db..309e37eb7c7c 100644 --- a/Documentation/devicetree/bindings/net/smsc-lan91c111.txt +++ b/Documentation/devicetree/bindings/net/smsc-lan91c111.txt @@ -13,3 +13,5 @@ Optional properties: 16-bit access only. - power-gpios: GPIO to control the PWRDWN pin - reset-gpios: GPIO to control the RESET pin +- pxa-u16-align4 : Boolean, put in place the workaround the force all + u16 writes to be 32 bits aligned diff --git a/Documentation/devicetree/bindings/net/stmmac.txt b/Documentation/devicetree/bindings/net/stmmac.txt index 41b49e6075f5..128da752fec9 100644 --- a/Documentation/devicetree/bindings/net/stmmac.txt +++ b/Documentation/devicetree/bindings/net/stmmac.txt @@ -1,7 +1,7 @@ * STMicroelectronics 10/100/1000 Ethernet driver (GMAC) Required properties: -- compatible: Should be "snps,dwmac-<ip_version>" "snps,dwmac" +- compatible: Should be "snps,dwmac-<ip_version>", "snps,dwmac" For backwards compatibility: "st,spear600-gmac" is also supported. - reg: Address and length of the register set for the device - interrupt-parent: Should be the phandle for the interrupt controller @@ -34,7 +34,13 @@ Optional properties: platforms. - tx-fifo-depth: See ethernet.txt file in the same directory - rx-fifo-depth: See ethernet.txt file in the same directory -- snps,pbl Programmable Burst Length +- snps,pbl Programmable Burst Length (tx and rx) +- snps,txpbl Tx Programmable Burst Length. Only for GMAC and newer. + If set, DMA tx will use this value rather than snps,pbl. +- snps,rxpbl Rx Programmable Burst Length. Only for GMAC and newer. + If set, DMA rx will use this value rather than snps,pbl. +- snps,no-pbl-x8 Don't multiply the pbl/txpbl/rxpbl values by 8. + For core rev < 3.50, don't multiply the values by 4. - snps,aal Address-Aligned Beats - snps,fixed-burst Program the DMA to use the fixed burst mode - snps,mixed-burst Program the DMA to use the mixed burst mode @@ -50,6 +56,8 @@ Optional properties: - snps,ps-speed: port selection speed that can be passed to the core when PCS is supported. For example, this is used in case of SGMII and MAC2MAC connection. +- snps,tso: this enables the TSO feature otherwise it will be managed by + MAC HW capability register. Only for GMAC4 and newer. - AXI BUS Mode parameters: below the list of all the parameters to program the AXI register inside the DMA module: - snps,lpi_en: enable Low Power Interface @@ -62,8 +70,6 @@ Optional properties: - snps,fb: fixed-burst - snps,mb: mixed-burst - snps,rb: rebuild INCRx Burst - - snps,tso: this enables the TSO feature otherwise it will be managed by - MAC HW capability register. - mdio: with compatible = "snps,dwmac-mdio", create and register mdio bus. Examples: diff --git a/Documentation/devicetree/bindings/net/ti,dp83867.txt b/Documentation/devicetree/bindings/net/ti,dp83867.txt index 5d21141a68b5..85bf945b898f 100644 --- a/Documentation/devicetree/bindings/net/ti,dp83867.txt +++ b/Documentation/devicetree/bindings/net/ti,dp83867.txt @@ -9,6 +9,18 @@ Required properties: - ti,fifo-depth - Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h for applicable values +Optional property: + - ti,min-output-impedance - MAC Interface Impedance control to set + the programmable output impedance to + minimum value (35 ohms). + - ti,max-output-impedance - MAC Interface Impedance control to set + the programmable output impedance to + maximum value (70 ohms). + +Note: ti,min-output-impedance and ti,max-output-impedance are mutually + exclusive. When both properties are present ti,max-output-impedance + takes precedence. + Default child nodes are standard Ethernet PHY device nodes as described in Documentation/devicetree/bindings/net/phy.txt diff --git a/Documentation/devicetree/bindings/net/wireless/marvell-sd8xxx.txt b/Documentation/devicetree/bindings/net/wireless/marvell-8xxx.txt index c421aba0a5bc..980b16df74c3 100644 --- a/Documentation/devicetree/bindings/net/wireless/marvell-sd8xxx.txt +++ b/Documentation/devicetree/bindings/net/wireless/marvell-8xxx.txt @@ -1,8 +1,8 @@ -Marvell 8897/8997 (sd8897/sd8997) SDIO devices +Marvell 8897/8997 (sd8897/sd8997/pcie8997) SDIO/PCIE devices ------ -This node provides properties for controlling the marvell sdio wireless device. -The node is expected to be specified as a child node to the SDIO controller that +This node provides properties for controlling the Marvell SDIO/PCIE wireless device. +The node is expected to be specified as a child node to the SDIO/PCIE controller that connects the device to the system. Required properties: @@ -10,6 +10,8 @@ Required properties: - compatible : should be one of the following: * "marvell,sd8897" * "marvell,sd8997" + * "pci11ab,2b42" + * "pci1b4b,2b42" Optional properties: diff --git a/Documentation/devicetree/bindings/net/wireless/qca,ath9k.txt b/Documentation/devicetree/bindings/net/wireless/qca,ath9k.txt new file mode 100644 index 000000000000..b7396c8c271c --- /dev/null +++ b/Documentation/devicetree/bindings/net/wireless/qca,ath9k.txt @@ -0,0 +1,48 @@ +* Qualcomm Atheros ath9k wireless devices + +This node provides properties for configuring the ath9k wireless device. The +node is expected to be specified as a child node of the PCI controller to +which the wireless chip is connected. + +Required properties: +- compatible: For PCI and PCIe devices this should be an identifier following + the format as defined in "PCI Bus Binding to Open Firmware" + Revision 2.1. One of the possible formats is "pciVVVV,DDDD" + where VVVV is the PCI vendor ID and DDDD is PCI device ID. + Typically QCA's PCI vendor ID 168c is used while the PCI device + ID depends on the chipset - see the following (possibly + incomplete) list: + - 0023 for AR5416 + - 0024 for AR5418 + - 0027 for AR9160 + - 0029 for AR9220 and AR9223 + - 002a for AR9280 and AR9283 + - 002b for AR9285 + - 002c for AR2427 + - 002d for AR9227 + - 002e for AR9287 + - 0030 for AR9380, AR9381 and AR9382 + - 0032 for AR9485 + - 0033 for AR9580 and AR9590 + - 0034 for AR9462 + - 0036 for AR9565 + - 0037 for AR9485 +- reg: Address and length of the register set for the device. + +Optional properties: +- qca,no-eeprom: Indicates that there is no physical EEPROM connected to the + ath9k wireless chip (in this case the calibration / + EEPROM data will be loaded from userspace using the + kernel firmware loader). +- mac-address: See ethernet.txt in the parent directory +- local-mac-address: See ethernet.txt in the parent directory + + +In this example, the node is defined as child node of the PCI controller: +&pci0 { + wifi@168c,002d { + compatible = "pci168c,002d"; + reg = <0x7000 0 0 0 0x1000>; + qca,no-eeprom; + }; +}; diff --git a/Documentation/driver-model/devres.txt b/Documentation/driver-model/devres.txt index 167070895498..ca9d1eb46bc0 100644 --- a/Documentation/driver-model/devres.txt +++ b/Documentation/driver-model/devres.txt @@ -332,6 +332,10 @@ MEM MFD devm_mfd_add_devices() +PER-CPU MEM + devm_alloc_percpu() + devm_free_percpu() + PCI pcim_enable_device() : after success, all PCI ops become managed pcim_pin_device() : keep PCI device enabled after release diff --git a/Documentation/networking/batman-adv.txt b/Documentation/networking/batman-adv.txt index 8a8d3d96f6c6..ccf94677b240 100644 --- a/Documentation/networking/batman-adv.txt +++ b/Documentation/networking/batman-adv.txt @@ -32,7 +32,7 @@ compatible interfaces. Once found, it will create subfolders in the /sys directories of each supported interface, e.g. # ls /sys/class/net/eth0/batman_adv/ -# iface_status mesh_iface +# elp_interval iface_status mesh_iface throughput_override If an interface does not have the "batman_adv" subfolder it prob- ably is not supported. Not supported interfaces are: loopback, @@ -71,17 +71,19 @@ All mesh wide settings can be found in batman's own interface folder: # ls /sys/class/net/bat0/mesh/ -#aggregated_ogms distributed_arp_table gw_sel_class orig_interval -#ap_isolation fragmentation hop_penalty routing_algo -#bonding gw_bandwidth isolation_mark vlan0 -#bridge_loop_avoidance gw_mode log_level +# aggregated_ogms fragmentation isolation_mark routing_algo +# ap_isolation gw_bandwidth log_level vlan0 +# bonding gw_mode multicast_mode +# bridge_loop_avoidance gw_sel_class network_coding +# distributed_arp_table hop_penalty orig_interval There is a special folder for debugging information: # ls /sys/kernel/debug/batman_adv/bat0/ -# bla_backbone_table log transtable_global -# bla_claim_table originators transtable_local -# gateways socket +# bla_backbone_table log neighbors transtable_local +# bla_claim_table mcast_flags originators +# dat_cache nc socket +# gateways nc_nodes transtable_global Some of the files contain all sort of status information regard- ing the mesh network. For example, you can view the table of @@ -159,13 +161,16 @@ file in debugfs The additional debug output is by default disabled. It can be en- abled during run time. Following log_levels are defined: -0 - All debug output disabled -1 - Enable messages related to routing / flooding / broadcasting -2 - Enable messages related to route added / changed / deleted -4 - Enable messages related to translation table operations -8 - Enable messages related to bridge loop avoidance -16 - Enable messaged related to DAT, ARP snooping and parsing -31 - Enable all messages + 0 - All debug output disabled + 1 - Enable messages related to routing / flooding / broadcasting + 2 - Enable messages related to route added / changed / deleted + 4 - Enable messages related to translation table operations + 8 - Enable messages related to bridge loop avoidance + 16 - Enable messages related to DAT, ARP snooping and parsing + 32 - Enable messages related to network coding + 64 - Enable messages related to multicast +128 - Enable messages related to throughput meter +255 - Enable all messages The debug output can be changed at runtime using the file /sys/class/net/bat0/mesh/log_level. e.g. diff --git a/Documentation/networking/ieee802154.txt b/Documentation/networking/ieee802154.txt index aa69ccc481db..c4114346f054 100644 --- a/Documentation/networking/ieee802154.txt +++ b/Documentation/networking/ieee802154.txt @@ -4,20 +4,20 @@ Introduction ============ -The IEEE 802.15.4 working group focuses on standardization of bottom -two layers: Medium Access Control (MAC) and Physical (PHY). And there +The IEEE 802.15.4 working group focuses on standardization of the bottom +two layers: Medium Access Control (MAC) and Physical access (PHY). And there are mainly two options available for upper layers: - ZigBee - proprietary protocol from the ZigBee Alliance - 6LoWPAN - IPv6 networking over low rate personal area networks -The linux-wpan project goal is to provide a complete implementation +The goal of the Linux-wpan is to provide a complete implementation of the IEEE 802.15.4 and 6LoWPAN protocols. IEEE 802.15.4 is a stack of protocols for organizing Low-Rate Wireless Personal Area Networks. The stack is composed of three main parts: - IEEE 802.15.4 layer; We have chosen to use plain Berkeley socket API, - the generic Linux networking stack to transfer IEEE 802.15.4 messages - and a special protocol over genetlink for configuration/management + the generic Linux networking stack to transfer IEEE 802.15.4 data + messages and a special protocol over netlink for configuration/management - MAC - provides access to shared channel and reliable data delivery - PHY - represents device drivers @@ -33,15 +33,13 @@ include/net/af_ieee802154.h header or in the special header in the userspace package (see either http://wpan.cakelab.org/ or the git tree at https://github.com/linux-wpan/wpan-tools). -One can use SOCK_RAW for passing raw data towards device xmit function. YMMV. - Kernel side ============= Like with WiFi, there are several types of devices implementing IEEE 802.15.4. 1) 'HardMAC'. The MAC layer is implemented in the device itself, the device - exports MLME and data API. + exports a management (e.g. MLME) and data API. 2) 'SoftMAC' or just radio. These types of devices are just radio transceivers possibly with some kinds of acceleration like automatic CRC computation and comparation, automagic ACK handling, address matching, etc. @@ -106,7 +104,7 @@ Fake drivers In addition there is a driver available which simulates a real device with SoftMAC (fakelb - IEEE 802.15.4 loopback driver) interface. This option -provides possibility to test and debug stack without usage of real hardware. +provides a possibility to test and debug the stack without usage of real hardware. See sources in drivers/net/ieee802154 folder for more details. @@ -125,17 +123,15 @@ to support the IPv6 minimum MTU requirement [RFC2460], and stateless header compression for IPv6 datagrams (LOWPAN_HC1 and LOWPAN_HC2) to reduce the relatively large IPv6 and UDP headers down to (in the best case) several bytes. -In Semptember 2011 the standard update was published - [RFC6282]. +In September 2011 the standard update was published - [RFC6282]. It deprecates HC1 and HC2 compression and defines IPHC encoding format which is used in this Linux implementation. All the code related to 6lowpan you may find in files: net/6lowpan/* and net/ieee802154/6lowpan/* -To setup 6lowpan interface you need (busybox release > 1.17.0): -1. Add IEEE802.15.4 interface and initialize PANid; +To setup a 6LoWPAN interface you need: +1. Add IEEE802.15.4 interface and set channel and PAN ID; 2. Add 6lowpan interface by command like: # ip link add link wpan0 name lowpan0 type lowpan -3. Set MAC (if needs): - # ip link set lowpan0 address de:ad:be:ef:ca:fe:ba:be -4. Bring up 'lowpan0' interface +3. Bring up 'lowpan0' interface diff --git a/Documentation/networking/ip-sysctl.txt b/Documentation/networking/ip-sysctl.txt index 3db8c67d2c8d..7dd65c9cf707 100644 --- a/Documentation/networking/ip-sysctl.txt +++ b/Documentation/networking/ip-sysctl.txt @@ -610,8 +610,13 @@ tcp_syn_retries - INTEGER with the current initial RTO of 1second. With this the final timeout for an active TCP connection attempt will happen after 127seconds. -tcp_timestamps - BOOLEAN - Enable timestamps as defined in RFC1323. +tcp_timestamps - INTEGER +Enable timestamps as defined in RFC1323. + 0: Disabled. + 1: Enable timestamps as defined in RFC1323 and use random offset for + each connection rather than only using the current time. + 2: Like 1, but without random offsets. + Default: 1 tcp_min_tso_segs - INTEGER Minimal number of segments per TSO frame. @@ -967,6 +972,21 @@ igmp_qrv - INTEGER Default: 2 (as specified by RFC2236 8.1) Minimum: 1 (as specified by RFC6636 4.5) +force_igmp_version - INTEGER + 0 - (default) No enforcement of a IGMP version, IGMPv1/v2 fallback + allowed. Will back to IGMPv3 mode again if all IGMPv1/v2 Querier + Present timer expires. + 1 - Enforce to use IGMP version 1. Will also reply IGMPv1 report if + receive IGMPv2/v3 query. + 2 - Enforce to use IGMP version 2. Will fallback to IGMPv1 if receive + IGMPv1 query message. Will reply report if receive IGMPv3 query. + 3 - Enforce to use IGMP version 3. The same react with default 0. + + Note: this is not the same with force_mld_version because IGMPv3 RFC3376 + Security Considerations does not have clear description that we could + ignore other version messages completely as MLDv2 RFC3810. So make + this value as default 0 is recommended. + conf/interface/* changes special settings per interface (where "interface" is the name of your network interface) @@ -1714,6 +1734,15 @@ drop_unsolicited_na - BOOLEAN By default this is turned off. +enhanced_dad - BOOLEAN + Include a nonce option in the IPv6 neighbor solicitation messages used for + duplicate address detection per RFC7527. A received DAD NS will only signal + a duplicate address if the nonce is different. This avoids any false + detection of duplicates due to loopback of the NS messages that we send. + The nonce option will be sent on an interface unless both of + conf/{all,interface}/enhanced_dad are set to FALSE. + Default: TRUE + icmp/*: ratelimit - INTEGER Limit the maximal rates for sending ICMPv6 packets. diff --git a/Documentation/networking/l2tp.txt b/Documentation/networking/l2tp.txt index 4650a00ed012..9bc271cdc9a8 100644 --- a/Documentation/networking/l2tp.txt +++ b/Documentation/networking/l2tp.txt @@ -177,10 +177,10 @@ setsockopt on the PPPoX socket to set a debug mask. The following debug mask bits are available: -PPPOL2TP_MSG_DEBUG verbose debug (if compiled in) -PPPOL2TP_MSG_CONTROL userspace - kernel interface -PPPOL2TP_MSG_SEQ sequence numbers handling -PPPOL2TP_MSG_DATA data packets +L2TP_MSG_DEBUG verbose debug (if compiled in) +L2TP_MSG_CONTROL userspace - kernel interface +L2TP_MSG_SEQ sequence numbers handling +L2TP_MSG_DATA data packets If enabled, files under a l2tp debugfs directory can be used to dump kernel state about L2TP tunnels and sessions. To access it, the diff --git a/Documentation/networking/mac80211_hwsim/README b/Documentation/networking/mac80211_hwsim/README index 24ac91d56698..3566a725d19c 100644 --- a/Documentation/networking/mac80211_hwsim/README +++ b/Documentation/networking/mac80211_hwsim/README @@ -60,7 +60,7 @@ modprobe mac80211_hwsim hostapd hostapd.conf # Run wpa_supplicant (station) for wlan1 -wpa_supplicant -Dwext -iwlan1 -c wpa_supplicant.conf +wpa_supplicant -Dnl80211 -iwlan1 -c wpa_supplicant.conf More test cases are available in hostap.git: diff --git a/Documentation/networking/nf_conntrack-sysctl.txt b/Documentation/networking/nf_conntrack-sysctl.txt index 433b6724797a..497d668288f9 100644 --- a/Documentation/networking/nf_conntrack-sysctl.txt +++ b/Documentation/networking/nf_conntrack-sysctl.txt @@ -96,6 +96,17 @@ nf_conntrack_max - INTEGER Size of connection tracking table. Default value is nf_conntrack_buckets value * 4. +nf_conntrack_default_on - BOOLEAN + 0 - don't register conntrack in new net namespaces + 1 - register conntrack in new net namespaces (default) + + This controls wheter newly created network namespaces have connection + tracking enabled by default. It will be enabled automatically + regardless of this setting if the new net namespace requires + connection tracking, e.g. when NAT rules are created. + This setting is only visible in initial user namespace, it has no + effect on existing namespaces. + nf_conntrack_tcp_be_liberal - BOOLEAN 0 - disabled (default) not 0 - enabled diff --git a/Documentation/networking/phy.txt b/Documentation/networking/phy.txt index 7ab9404a8412..16f90d817224 100644 --- a/Documentation/networking/phy.txt +++ b/Documentation/networking/phy.txt @@ -65,6 +65,83 @@ The MDIO bus drivers/net/ethernet/freescale/fsl_pq_mdio.c and an associated DTS file for one of the users. (e.g. "git grep fsl,.*-mdio arch/powerpc/boot/dts/") +(RG)MII/electrical interface considerations + + The Reduced Gigabit Medium Independent Interface (RGMII) is a 12-pin + electrical signal interface using a synchronous 125Mhz clock signal and several + data lines. Due to this design decision, a 1.5ns to 2ns delay must be added + between the clock line (RXC or TXC) and the data lines to let the PHY (clock + sink) have enough setup and hold times to sample the data lines correctly. The + PHY library offers different types of PHY_INTERFACE_MODE_RGMII* values to let + the PHY driver and optionally the MAC driver, implement the required delay. The + values of phy_interface_t must be understood from the perspective of the PHY + device itself, leading to the following: + + * PHY_INTERFACE_MODE_RGMII: the PHY is not responsible for inserting any + internal delay by itself, it assumes that either the Ethernet MAC (if capable + or the PCB traces) insert the correct 1.5-2ns delay + + * PHY_INTERFACE_MODE_RGMII_TXID: the PHY should insert an internal delay + for the transmit data lines (TXD[3:0]) processed by the PHY device + + * PHY_INTERFACE_MODE_RGMII_RXID: the PHY should insert an internal delay + for the receive data lines (RXD[3:0]) processed by the PHY device + + * PHY_INTERFACE_MODE_RGMII_ID: the PHY should insert internal delays for + both transmit AND receive data lines from/to the PHY device + + Whenever possible, use the PHY side RGMII delay for these reasons: + + * PHY devices may offer sub-nanosecond granularity in how they allow a + receiver/transmitter side delay (e.g: 0.5, 1.0, 1.5ns) to be specified. Such + precision may be required to account for differences in PCB trace lengths + + * PHY devices are typically qualified for a large range of applications + (industrial, medical, automotive...), and they provide a constant and + reliable delay across temperature/pressure/voltage ranges + + * PHY device drivers in PHYLIB being reusable by nature, being able to + configure correctly a specified delay enables more designs with similar delay + requirements to be operate correctly + + For cases where the PHY is not capable of providing this delay, but the + Ethernet MAC driver is capable of doing so, the correct phy_interface_t value + should be PHY_INTERFACE_MODE_RGMII, and the Ethernet MAC driver should be + configured correctly in order to provide the required transmit and/or receive + side delay from the perspective of the PHY device. Conversely, if the Ethernet + MAC driver looks at the phy_interface_t value, for any other mode but + PHY_INTERFACE_MODE_RGMII, it should make sure that the MAC-level delays are + disabled. + + In case neither the Ethernet MAC, nor the PHY are capable of providing the + required delays, as defined per the RGMII standard, several options may be + available: + + * Some SoCs may offer a pin pad/mux/controller capable of configuring a given + set of pins'strength, delays, and voltage; and it may be a suitable + option to insert the expected 2ns RGMII delay. + + * Modifying the PCB design to include a fixed delay (e.g: using a specifically + designed serpentine), which may not require software configuration at all. + +Common problems with RGMII delay mismatch + + When there is a RGMII delay mismatch between the Ethernet MAC and the PHY, this + will most likely result in the clock and data line signals to be unstable when + the PHY or MAC take a snapshot of these signals to translate them into logical + 1 or 0 states and reconstruct the data being transmitted/received. Typical + symptoms include: + + * Transmission/reception partially works, and there is frequent or occasional + packet loss observed + + * Ethernet MAC may report some or all packets ingressing with a FCS/CRC error, + or just discard them all + + * Switching to lower speeds such as 10/100Mbits/sec makes the problem go away + (since there is enough setup/hold time in that case) + + Connecting to a PHY Sometime during startup, the network driver needs to establish a connection @@ -127,8 +204,9 @@ Letting the PHY Abstraction Layer do Everything values pruned from them which don't make sense for your controller (a 10/100 controller may be connected to a gigabit capable PHY, so you would need to mask off SUPPORTED_1000baseT*). See include/linux/ethtool.h for definitions - for these bitfields. Note that you should not SET any bits, or the PHY may - get put into an unsupported state. + for these bitfields. Note that you should not SET any bits, except the + SUPPORTED_Pause and SUPPORTED_AsymPause bits (see below), or the PHY may get + put into an unsupported state. Lastly, once the controller is ready to handle network traffic, you call phy_start(phydev). This tells the PAL that you are ready, and configures the @@ -139,6 +217,19 @@ Letting the PHY Abstraction Layer do Everything When you want to disconnect from the network (even if just briefly), you call phy_stop(phydev). +Pause frames / flow control + + The PHY does not participate directly in flow control/pause frames except by + making sure that the SUPPORTED_Pause and SUPPORTED_AsymPause bits are set in + MII_ADVERTISE to indicate towards the link partner that the Ethernet MAC + controller supports such a thing. Since flow control/pause frames generation + involves the Ethernet MAC driver, it is recommended that this driver takes care + of properly indicating advertisement and support for such features by setting + the SUPPORTED_Pause and SUPPORTED_AsymPause bits accordingly. This can be done + either before or after phy_connect() and/or as a result of implementing the + ethtool::set_pauseparam feature. + + Keeping Close Tabs on the PAL It is possible that the PAL's built-in state machine needs a little help to @@ -251,39 +342,8 @@ Writing a PHY driver PHY_BASIC_FEATURES, but you can look in include/mii.h for other features. - Each driver consists of a number of function pointers: - - soft_reset: perform a PHY software reset - config_init: configures PHY into a sane state after a reset. - For instance, a Davicom PHY requires descrambling disabled. - probe: Allocate phy->priv, optionally refuse to bind. - PHY may not have been reset or had fixups run yet. - suspend/resume: power management - config_aneg: Changes the speed/duplex/negotiation settings - aneg_done: Determines the auto-negotiation result - read_status: Reads the current speed/duplex/negotiation settings - ack_interrupt: Clear a pending interrupt - did_interrupt: Checks if the PHY generated an interrupt - config_intr: Enable or disable interrupts - remove: Does any driver take-down - ts_info: Queries about the HW timestamping status - match_phy_device: used for Clause 45 capable PHYs to match devices - in package and ensure they are compatible - hwtstamp: Set the PHY HW timestamping configuration - rxtstamp: Requests a receive timestamp at the PHY level for a 'skb' - txtsamp: Requests a transmit timestamp at the PHY level for a 'skb' - set_wol: Enable Wake-on-LAN at the PHY level - get_wol: Get the Wake-on-LAN status at the PHY level - link_change_notify: called to inform the core is about to change the - link state, can be used to work around bogus PHY between state changes - read_mmd_indirect: Read PHY MMD indirect register - write_mmd_indirect: Write PHY MMD indirect register - module_info: Get the size and type of an EEPROM contained in an plug-in - module - module_eeprom: Get EEPROM information of a plug-in module - get_sset_count: Get number of strings sets that get_strings will count - get_strings: Get strings from requested objects (statistics) - get_stats: Get the extended statistics from the PHY device + Each driver consists of a number of function pointers, documented + in include/linux/phy.h under the phy_driver structure. Of these, only config_aneg and read_status are required to be assigned by the driver code. The rest are optional. Also, it is @@ -347,3 +407,22 @@ Board Fixups The stubs set one of the two matching criteria, and set the other one to match anything. + When phy_register_fixup() or *_for_uid()/*_for_id() is called at module, + unregister fixup and free allocate memory are required. + + Call one of following function before unloading module. + + int phy_unregister_fixup(const char *phy_id, u32 phy_uid, u32 phy_uid_mask); + int phy_unregister_fixup_for_uid(u32 phy_uid, u32 phy_uid_mask); + int phy_register_fixup_for_id(const char *phy_id); + +Standards + + IEEE Standard 802.3: CSMA/CD Access Method and Physical Layer Specifications, Section Two: + http://standards.ieee.org/getieee802/download/802.3-2008_section2.pdf + + RGMII v1.3: + http://web.archive.org/web/20160303212629/http://www.hp.com/rnd/pdfs/RGMIIv1_3.pdf + + RGMII v2.0: + http://web.archive.org/web/20160303171328/http://www.hp.com/rnd/pdfs/RGMIIv2_0_final_hp.pdf diff --git a/Documentation/networking/seg6-sysctl.txt b/Documentation/networking/seg6-sysctl.txt new file mode 100644 index 000000000000..bdbde23b19cb --- /dev/null +++ b/Documentation/networking/seg6-sysctl.txt @@ -0,0 +1,18 @@ +/proc/sys/net/conf/<iface>/seg6_* variables: + +seg6_enabled - BOOL + Accept or drop SR-enabled IPv6 packets on this interface. + + Relevant packets are those with SRH present and DA = local. + + 0 - disabled (default) + not 0 - enabled + +seg6_require_hmac - INTEGER + Define HMAC policy for ingress SR-enabled packets on this interface. + + -1 - Ignore HMAC field + 0 - Accept SR packets without HMAC, validate SR packets with HMAC + 1 - Drop SR packets without HMAC, validate SR packets with HMAC + + Default is 0. diff --git a/Documentation/networking/stmmac.txt b/Documentation/networking/stmmac.txt index e226f8925c9e..2bb07078f535 100644 --- a/Documentation/networking/stmmac.txt +++ b/Documentation/networking/stmmac.txt @@ -28,8 +28,6 @@ CONFIG_STMMAC_PCI: is to enable the pci driver. 2) Driver parameters list: debug: message level (0: no output, 16: all); phyaddr: to manually provide the physical address to the PHY device; - dma_rxsize: DMA rx ring size; - dma_txsize: DMA tx ring size; buf_sz: DMA buffer size; tc: control the HW FIFO threshold; watchdog: transmit timeout (in milliseconds); @@ -40,31 +38,31 @@ CONFIG_STMMAC_PCI: is to enable the pci driver. 3) Command line options Driver parameters can be also passed in command line by using: - stmmaceth=dma_rxsize:128,dma_txsize:512 + stmmaceth=watchdog:100,chain_mode=1 4) Driver information and notes 4.1) Transmit process The xmit method is invoked when the kernel needs to transmit a packet; it sets -the descriptors in the ring and informs the DMA engine that there is a packet +the descriptors in the ring and informs the DMA engine, that there is a packet ready to be transmitted. By default, the driver sets the NETIF_F_SG bit in the features field of the -net_device structure enabling the scatter-gather feature. This is true on +net_device structure, enabling the scatter-gather feature. This is true on chips and configurations where the checksum can be done in hardware. -Once the controller has finished transmitting the packet, napi will be +Once the controller has finished transmitting the packet, timer will be scheduled to release the transmit resources. 4.2) Receive process When one or more packets are received, an interrupt happens. The interrupts -are not queued so the driver has to scan all the descriptors in the ring during +are not queued, so the driver has to scan all the descriptors in the ring during the receive process. -This is based on NAPI so the interrupt handler signals only if there is work +This is based on NAPI, so the interrupt handler signals only if there is work to be done, and it exits. Then the poll method will be scheduled at some future point. The incoming packets are stored, by the DMA, in a list of pre-allocated socket buffers in order to avoid the memcpy (zero-copy). -4.3) Interrupt Mitigation +4.3) Interrupt mitigation The driver is able to mitigate the number of its DMA interrupts using NAPI for the reception on chips older than the 3.50. New chips have an HW RX-Watchdog used for this mitigation. @@ -88,19 +86,20 @@ the list, hence creating the explicit chaining in the descriptor itself, whereas such explicit chaining is not possible in RING mode. 4.5.1) Extended descriptors - The extended descriptors give us information about the Ethernet payload - when it is carrying PTP packets or TCP/UDP/ICMP over IP. - These are not available on GMAC Synopsys chips older than the 3.50. - At probe time the driver will decide if these can be actually used. - This support also is mandatory for PTPv2 because the extra descriptors - are used for saving the hardware timestamps and Extended Status. +The extended descriptors give us information about the Ethernet payload +when it is carrying PTP packets or TCP/UDP/ICMP over IP. +These are not available on GMAC Synopsys chips older than the 3.50. +At probe time the driver will decide if these can be actually used. +This support also is mandatory for PTPv2 because the extra descriptors +are used for saving the hardware timestamps and Extended Status. 4.6) Ethtool support Ethtool is supported. For example, driver statistics (including RMON), internal errors can be taken using: - # ethtool -S ethX command + # ethtool -S ethX +command 4.7) Jumbo and Segmentation Offloading Jumbo frames are supported and tested for the GMAC. @@ -153,8 +152,10 @@ Where: o dma_cfg: internal DMA parameters o pbl: the Programmable Burst Length is maximum number of beats to be transferred in one DMA transaction. - GMAC also enables the 4xPBL by default. - o fixed_burst/mixed_burst/burst_len + GMAC also enables the 4xPBL by default. (8xPBL for GMAC 3.50 and newer) + o txpbl/rxpbl: GMAC and newer supports independent DMA pbl for tx/rx. + o pblx8: Enable 8xPBL (4xPBL for core rev < 3.50). Enabled by default. + o fixed_burst/mixed_burst/aal o clk_csr: fixed CSR Clock range selection. o has_gmac: uses the GMAC core. o enh_desc: if sets the MAC will use the enhanced descriptor structure. @@ -206,16 +207,24 @@ tuned according to the HW capabilities. struct stmmac_dma_cfg { int pbl; + int txpbl; + int rxpbl; + bool pblx8; int fixed_burst; - int burst_len_supported; + int mixed_burst; + bool aal; }; Where: - o pbl: Programmable Burst Length + o pbl: Programmable Burst Length (tx and rx) + o txpbl: Transmit Programmable Burst Length. Only for GMAC and newer. + If set, DMA tx will use this value rather than pbl. + o rxpbl: Receive Programmable Burst Length. Only for GMAC and newer. + If set, DMA rx will use this value rather than pbl. + o pblx8: Enable 8xPBL (4xPBL for core rev < 3.50). Enabled by default. o fixed_burst: program the DMA to use the fixed burst mode - o burst_len: this is the value we put in the register - supported values are provided as macros in - linux/stmmac.h header file. + o mixed_burst: program the DMA to use the mixed burst mode + o aal: Address-Aligned Beats --- @@ -275,11 +284,11 @@ Please see the following document: Documentation/devicetree/bindings/net/stmmac.txt 4.11) This is a summary of the content of some relevant files: - o stmmac_main.c: to implement the main network device driver; - o stmmac_mdio.c: to provide mdio functions; - o stmmac_pci: this the PCI driver; - o stmmac_platform.c: this the platform driver (OF supported) - o stmmac_ethtool.c: to implement the ethtool support; + o stmmac_main.c: implements the main network device driver; + o stmmac_mdio.c: provides MDIO functions; + o stmmac_pci: this is the PCI driver; + o stmmac_platform.c: this the platform driver (OF supported); + o stmmac_ethtool.c: implements the ethtool support; o stmmac.h: private driver structure; o common.h: common definitions and VFTs; o mmc_core.c/mmc.h: Management MAC Counters; @@ -381,12 +390,12 @@ In addition to the basic timestamp features mentioned in IEEE 1588-2002 Timestamps, new GMAC cores support the advanced timestamp features. IEEE 1588-2008 that can be enabled when configure the Kernel. -8) SGMII/RGMII supports +8) SGMII/RGMII support New GMAC devices provide own way to manage RGMII/SGMII. This information is available at run-time by looking at the HW capability register. This means that the stmmac can manage -auto-negotiation and link status w/o using the PHYLIB stuff +auto-negotiation and link status w/o using the PHYLIB stuff. In fact, the HW provides a subset of extended registers to restart the ANE, verify Full/Half duplex mode and Speed. -Also thanks to these registers it is possible to look at the +Thanks to these registers, it is possible to look at the Auto-negotiated Link Parter Ability. diff --git a/Documentation/networking/timestamping.txt b/Documentation/networking/timestamping.txt index 671cccf0dcd2..96f50694a748 100644 --- a/Documentation/networking/timestamping.txt +++ b/Documentation/networking/timestamping.txt @@ -182,6 +182,16 @@ SOF_TIMESTAMPING_OPT_TSONLY: the timestamp even if sysctl net.core.tstamp_allow_data is 0. This option disables SOF_TIMESTAMPING_OPT_CMSG. +SOF_TIMESTAMPING_OPT_STATS: + + Optional stats that are obtained along with the transmit timestamps. + It must be used together with SOF_TIMESTAMPING_OPT_TSONLY. When the + transmit timestamp is available, the stats are available in a + separate control message of type SCM_TIMESTAMPING_OPT_STATS, as a + list of TLVs (struct nlattr) of types. These stats allow the + application to associate various transport layer stats with + the transmit timestamps, such as how long a certain block of + data was limited by peer's receiver window. New applications are encouraged to pass SOF_TIMESTAMPING_OPT_ID to disambiguate timestamps and SOF_TIMESTAMPING_OPT_TSONLY to operate |