diff options
Diffstat (limited to 'Documentation/devicetree')
1090 files changed, 34625 insertions, 11337 deletions
diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/arm/altera.yaml index 8c7575455422..30c44a0e6407 100644 --- a/Documentation/devicetree/bindings/arm/altera.yaml +++ b/Documentation/devicetree/bindings/arm/altera.yaml @@ -47,6 +47,7 @@ properties: - novtech,chameleon96 - samtec,vining - terasic,de0-atlas + - terasic,de10-nano - terasic,socfpga-cyclone5-sockit - const: altr,socfpga-cyclone5 - const: altr,socfpga diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-clk-manager.yaml b/Documentation/devicetree/bindings/arm/altera/socfpga-clk-manager.yaml index 572381306681..a758f4bb2bb3 100644 --- a/Documentation/devicetree/bindings/arm/altera/socfpga-clk-manager.yaml +++ b/Documentation/devicetree/bindings/arm/altera/socfpga-clk-manager.yaml @@ -9,20 +9,120 @@ title: Altera SOCFPGA Clock Manager maintainers: - Dinh Nguyen <dinguyen@kernel.org> -description: test +description: + This binding describes the Altera SOCFGPA Clock Manager and its associated + tree of clocks, pll's, and clock gates for the Cyclone5, Arria5 and Arria10 + chip families. properties: compatible: items: - const: altr,clk-mgr + reg: maxItems: 1 + clocks: + type: object + additionalProperties: false + + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + patternProperties: + "^osc[0-9]$": + type: object + + "^[a-z0-9,_]+(clk|pll|clk_gate|clk_divided)(@[a-f0-9]+)?$": + type: object + $ref: '#/$defs/clock-props' + unevaluatedProperties: false + + properties: + compatible: + enum: + - altr,socfpga-pll-clock + - altr,socfpga-perip-clk + - altr,socfpga-gate-clk + - altr,socfpga-a10-pll-clock + - altr,socfpga-a10-perip-clk + - altr,socfpga-a10-gate-clk + - fixed-clock + + clocks: + description: one or more phandles to input clock + minItems: 1 + maxItems: 5 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + patternProperties: + "^[a-z0-9,_]+(clk|pll)(@[a-f0-9]+)?$": + type: object + $ref: '#/$defs/clock-props' + unevaluatedProperties: false + + properties: + compatible: + enum: + - altr,socfpga-perip-clk + - altr,socfpga-gate-clk + - altr,socfpga-a10-perip-clk + - altr,socfpga-a10-gate-clk + + clocks: + description: one or more phandles to input clock + minItems: 1 + maxItems: 4 + + required: + - compatible + - clocks + - "#clock-cells" + + required: + - compatible + - "#clock-cells" + required: - compatible + - reg additionalProperties: false +$defs: + clock-props: + properties: + reg: + maxItems: 1 + + "#clock-cells": + const: 0 + + clk-gate: + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - description: gating register offset + - description: bit index + + div-reg: + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - description: divider register offset + - description: bit shift + - description: bit width + + fixed-divider: + $ref: /schemas/types.yaml#/definitions/uint32 + examples: - | clkmgr@ffd04000 { diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml b/Documentation/devicetree/bindings/arm/amlogic.yaml index 0647851ae1f5..05edf22e6c30 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.yaml +++ b/Documentation/devicetree/bindings/arm/amlogic.yaml @@ -27,6 +27,7 @@ properties: items: - enum: - minix,neo-x8 + - tcu,fernsehfee3 - const: amlogic,meson8 - description: Boards with the Amlogic Meson8m2 SoC @@ -73,6 +74,13 @@ properties: - const: amlogic,s805x - const: amlogic,meson-gxl + - description: Boards with the Amlogic Meson GXL S805Y SoC + items: + - enum: + - xiaomi,aquaman + - const: amlogic,s805y + - const: amlogic,meson-gxl + - description: Boards with the Amlogic Meson GXL S905W SoC items: - enum: @@ -237,6 +245,24 @@ properties: - amlogic,aq222 - const: amlogic,s4 + - description: Boards with the Amlogic S6 S905X5 SoC + items: + - enum: + - amlogic,bl209 + - const: amlogic,s6 + + - description: Boards with the Amlogic S7 S805X3 SoC + items: + - enum: + - amlogic,bp201 + - const: amlogic,s7 + + - description: Boards with the Amlogic S7D S905X5M SoC + items: + - enum: + - amlogic,bm202 + - const: amlogic,s7d + - description: Boards with the Amlogic T7 A311D2 SoC items: - enum: diff --git a/Documentation/devicetree/bindings/arm/apple.yaml b/Documentation/devicetree/bindings/arm/apple.yaml index dc9aab19ff11..da60e9de1cfb 100644 --- a/Documentation/devicetree/bindings/arm/apple.yaml +++ b/Documentation/devicetree/bindings/arm/apple.yaml @@ -57,6 +57,25 @@ description: | - iPad Pro (2nd Generation) (10.5 Inch) - iPad Pro (2nd Generation) (12.9 Inch) + Devices based on the "T2" SoC: + + - Apple T2 MacBookPro15,2 (j132) + - Apple T2 iMacPro1,1 (j137) + - Apple T2 MacBookAir8,2 (j140a) + - Apple T2 MacBookAir8,1 (j140k) + - Apple T2 MacBookPro16,1 (j152f) + - Apple T2 MacPro7,1 (j160) + - Apple T2 Macmini8,1 (j174) + - Apple T2 iMac20,1 (j185) + - Apple T2 iMac20,2 (j185f) + - Apple T2 MacBookPro15,4 (j213) + - Apple T2 MacBookPro16,2 (j214k) + - Apple T2 MacBookPro16,4 (j215) + - Apple T2 MacBookPro16,3 (j223) + - Apple T2 MacBookAir9,1 (j230k) + - Apple T2 MacBookPro15,1 (j680) + - Apple T2 MacBookPro15,3 (j780) + Devices based on the "A11" SoC: - iPhone 8 @@ -211,6 +230,28 @@ properties: - const: apple,t8011 - const: apple,arm-platform + - description: Apple T2 SoC based platforms + items: + - enum: + - apple,j132 # Apple T2 MacBookPro15,2 (j132) + - apple,j137 # Apple T2 iMacPro1,1 (j137) + - apple,j140a # Apple T2 MacBookAir8,2 (j140a) + - apple,j140k # Apple T2 MacBookAir8,1 (j140k) + - apple,j152f # Apple T2 MacBookPro16,1 (j152f) + - apple,j160 # Apple T2 MacPro7,1 (j160) + - apple,j174 # Apple T2 Macmini8,1 (j174) + - apple,j185 # Apple T2 iMac20,1 (j185) + - apple,j185f # Apple T2 iMac20,2 (j185f) + - apple,j213 # Apple T2 MacBookPro15,4 (j213) + - apple,j214k # Apple T2 MacBookPro16,2 (j214k) + - apple,j215 # Apple T2 MacBookPro16,4 (j215) + - apple,j223 # Apple T2 MacBookPro16,3 (j223) + - apple,j230k # Apple T2 MacBookAir9,1 (j230k) + - apple,j680 # Apple T2 MacBookPro15,1 (j680) + - apple,j780 # Apple T2 MacBookPro15,3 (j780) + - const: apple,t8012 + - const: apple,arm-platform + - description: Apple A11 SoC based platforms items: - enum: diff --git a/Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml b/Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml index 673277a7a224..5001f4d5a0dc 100644 --- a/Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml +++ b/Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml @@ -22,6 +22,11 @@ properties: compatible: items: - enum: + - apple,s5l8960x-pmgr + - apple,t7000-pmgr + - apple,s8000-pmgr + - apple,t8010-pmgr + - apple,t8015-pmgr - apple,t8103-pmgr - apple,t8112-pmgr - apple,t6000-pmgr diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-static-replicator.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-static-replicator.yaml index a6f793ea03b6..0c1017affbad 100644 --- a/Documentation/devicetree/bindings/arm/arm,coresight-static-replicator.yaml +++ b/Documentation/devicetree/bindings/arm/arm,coresight-static-replicator.yaml @@ -30,6 +30,19 @@ properties: power-domains: maxItems: 1 + clocks: + minItems: 1 + maxItems: 3 + + clock-names: + oneOf: + - items: + - enum: [apb_pclk, atclk] + - items: # Zynq-700 + - const: apb_pclk + - const: dbg_trc + - const: dbg_apb + in-ports: $ref: /schemas/graph.yaml#/properties/ports additionalProperties: false diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml index cb8dceaca70e..4787d7c6bac2 100644 --- a/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml +++ b/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml @@ -101,6 +101,29 @@ properties: and ETF configurations. $ref: /schemas/graph.yaml#/properties/port + memory-region: + items: + - description: Reserved trace buffer memory for ETR and ETF sinks. + For ETR, this reserved memory region is used for trace data capture. + Same region is used for trace data retention as well after a panic + or watchdog reset. + This reserved memory region is used as trace buffer or used for trace + data retention only if specifically selected by the user in sysfs + interface. + The default memory usage models for ETR in sysfs/perf modes are + otherwise unaltered. + + For ETF, this reserved memory region is used by default for + retention of trace data synced from internal SRAM after a panic + or watchdog reset. + - description: Reserved meta data memory. Used for ETR and ETF sinks + for storing metadata. + + memory-region-names: + items: + - const: tracedata + - const: metadata + required: - compatible - reg @@ -115,6 +138,9 @@ examples: etr@20070000 { compatible = "arm,coresight-tmc", "arm,primecell"; reg = <0x20070000 0x1000>; + memory-region = <&etr_trace_mem_reserved>, + <&etr_mdata_mem_reserved>; + memory-region-names = "tracedata", "metadata"; clocks = <&oscclk6a>; clock-names = "apb_pclk"; diff --git a/Documentation/devicetree/bindings/arm/arm,morello.yaml b/Documentation/devicetree/bindings/arm/arm,morello.yaml new file mode 100644 index 000000000000..e843b97fa485 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,morello.yaml @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,morello.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM Morello Platforms + +maintainers: + - Vincenzo Frascino <vincenzo.frascino@arm.com> + +description: |+ + The Morello architecture is an experimental extension to Armv8.2-A, + which extends the AArch64 state with the principles proposed in + version 7 of the Capability Hardware Enhanced RISC Instructions + (CHERI) ISA. + + ARM's Morello Platforms are built as a research project to explore + capability architectures based on arm. + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: Arm Morello System Platforms + items: + - enum: + - arm,morello-sdp + - arm,morello-fvp + - const: arm,morello + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/arm/atmel,sama5d2-secumod.yaml b/Documentation/devicetree/bindings/arm/atmel,sama5d2-secumod.yaml new file mode 100644 index 000000000000..ad4a98a4ee67 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/atmel,sama5d2-secumod.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/atmel,sama5d2-secumod.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip AT91 Security Module (SECUMOD) + +maintainers: + - Nicolas Ferre <nicolas.ferre@microchip.com> + +description: + The Security Module also offers the PIOBU pins which can be used as GPIO pins. + Note that they maintain their voltage during Backup/Self-refresh. + +properties: + compatible: + oneOf: + - items: + - const: atmel,sama5d2-secumod + - const: syscon + - items: + - enum: + - microchip,sama7d65-secumod + - microchip,sama7g5-secumod + - const: atmel,sama5d2-secumod + - const: syscon + reg: + maxItems: 1 + + gpio-controller: true + + "#gpio-cells": + const: 2 + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + security-module@fc040000 { + compatible = "atmel,sama5d2-secumod", "syscon"; + reg = <0xfc040000 0x100>; + gpio-controller; + #gpio-cells = <2>; + }; diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.yaml b/Documentation/devicetree/bindings/arm/atmel-at91.yaml index 0ec29366e6c2..3a34b7a2e8d4 100644 --- a/Documentation/devicetree/bindings/arm/atmel-at91.yaml +++ b/Documentation/devicetree/bindings/arm/atmel-at91.yaml @@ -23,8 +23,6 @@ properties: - const: atmel,at91rm9200 - items: - enum: - - olimex,sam9-l9260 - - enum: - atmel,at91sam9260 - atmel,at91sam9261 - atmel,at91sam9263 @@ -36,6 +34,37 @@ properties: - atmel,at91sam9x60 - const: atmel,at91sam9 + - description: Olimex SAM9-L9260 + items: + - const: olimex,sam9-l9260 + - const: atmel,at91sam9260 + - const: atmel,at91sam9 + + - description: Calao USB A9260 + items: + - const: calao,usb-a9260 + - const: atmel,at91sam9260 + - const: atmel,at91sam9 + + - description: Calao USB A9263 + items: + - const: calao,usb-a9263 + - const: atmel,at91sam9263 + - const: atmel,at91sam9 + + - description: Calao USB A9G20 + items: + - const: calao,usb-a9g20 + - const: atmel,at91sam9g20 + - const: atmel,at91sam9 + + - description: Calao USB A9G20-LPW + items: + - const: calao,usb-a9g20-lpw + - const: calao,usb-a9g20 + - const: atmel,at91sam9g20 + - const: atmel,at91sam9 + - items: - enum: - overkiz,kizboxmini-base # Overkiz kizbox Mini Base Board diff --git a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt index 1a173e92bb13..5ce54f9befe6 100644 --- a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt +++ b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt @@ -2,6 +2,7 @@ Atmel system registers Chipid required properties: - compatible: Should be "atmel,sama5d2-chipid" or "microchip,sama7g5-chipid" + "microchip,sama7d65-chipid" - reg : Should contain registers location and length PIT Timer required properties: @@ -45,28 +46,3 @@ Examples: reg = <0xffffe800 0x200>; }; -Security Module (SECUMOD) - -The Security Module macrocell provides all necessary secure functions to avoid -voltage, temperature, frequency and mechanical attacks on the chip. It also -embeds secure memories that can be scrambled. - -The Security Module also offers the PIOBU pins which can be used as GPIO pins. -Note that they maintain their voltage during Backup/Self-refresh. - -required properties: -- compatible: Should be "atmel,<chip>-secumod", "syscon". - <chip> can be "sama5d2". -- reg: Should contain registers location and length -- gpio-controller: Marks the port as GPIO controller. -- #gpio-cells: There are 2. The pin number is the - first, the second represents additional - parameters such as GPIO_ACTIVE_HIGH/LOW. - - - secumod@fc040000 { - compatible = "atmel,sama5d2-secumod", "syscon"; - reg = <0xfc040000 0x100>; - gpio-controller; - #gpio-cells = <2>; - }; diff --git a/Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml b/Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml index e4ff71f006b8..2729a542c4f3 100644 --- a/Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml +++ b/Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml @@ -52,6 +52,7 @@ properties: - description: BCM2837 based Boards items: - enum: + - raspberrypi,2-model-b-rev2 - raspberrypi,3-model-a-plus - raspberrypi,3-model-b - raspberrypi,3-model-b-plus diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index 73dd73d2d4fa..2e9ab9583005 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -10,9 +10,9 @@ maintainers: - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> description: |+ - The device tree allows to describe the layout of CPUs in a system through - the "cpus" node, which in turn contains a number of subnodes (ie "cpu") - defining properties for every cpu. + The device tree allows to describe the layout of CPUs in a system through the + "cpus" node, which in turn contains a number of subnodes (ie "cpu") defining + properties for every cpu. Bindings for CPU nodes follow the Devicetree Specification, available from: @@ -41,45 +41,40 @@ description: |+ properties: reg: maxItems: 1 - description: | - Usage and definition depend on ARM architecture version and - configuration: + description: > + Usage and definition depend on ARM architecture version and configuration: - On uniprocessor ARM architectures previous to v7 - this property is required and must be set to 0. + On uniprocessor ARM architectures previous to v7 this property is required + and must be set to 0. - On ARM 11 MPcore based systems this property is - required and matches the CPUID[11:0] register bits. + On ARM 11 MPcore based systems this property is required and matches the + CPUID[11:0] register bits. - Bits [11:0] in the reg cell must be set to - bits [11:0] in CPU ID register. + Bits [11:0] in the reg cell must be set to bits [11:0] in CPU ID register. All other bits in the reg cell must be set to 0. - On 32-bit ARM v7 or later systems this property is - required and matches the CPU MPIDR[23:0] register - bits. + On 32-bit ARM v7 or later systems this property is required and matches + the CPU MPIDR[23:0] register bits. - Bits [23:0] in the reg cell must be set to - bits [23:0] in MPIDR. + Bits [23:0] in the reg cell must be set to bits [23:0] in MPIDR. All other bits in the reg cell must be set to 0. - On ARM v8 64-bit systems this property is required - and matches the MPIDR_EL1 register affinity bits. + On ARM v8 64-bit systems this property is required and matches the + MPIDR_EL1 register affinity bits. * If cpus node's #address-cells property is set to 2 - The first reg cell bits [7:0] must be set to - bits [39:32] of MPIDR_EL1. + The first reg cell bits [7:0] must be set to bits [39:32] of + MPIDR_EL1. - The second reg cell bits [23:0] must be set to - bits [23:0] of MPIDR_EL1. + The second reg cell bits [23:0] must be set to bits [23:0] of + MPIDR_EL1. * If cpus node's #address-cells property is set to 1 - The reg cell bits [23:0] must be set to bits [23:0] - of MPIDR_EL1. + The reg cell bits [23:0] must be set to bits [23:0] of MPIDR_EL1. All other bits in the reg cells must be set to 0. @@ -177,6 +172,7 @@ properties: - arm,neoverse-v2 - arm,neoverse-v3 - arm,neoverse-v3ae + - arm,rainier - brcm,brahma-b15 - brcm,brahma-b53 - brcm,vulcan @@ -272,103 +268,122 @@ properties: description: The DT specification defines this as 64-bit always, but some 32-bit Arm systems have used a 32-bit value which must be supported. - Required for systems that have an "enable-method" - property value of "spin-table". cpu-idle-states: $ref: /schemas/types.yaml#/definitions/phandle-array items: maxItems: 1 - description: | - List of phandles to idle state nodes supported - by this cpu (see ./idle-states.yaml). + description: + List of phandles to idle state nodes supported by this cpu (see + ./idle-states.yaml). capacity-dmips-mhz: description: u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in - DMIPS/MHz, relative to highest capacity-dmips-mhz - in the system. + DMIPS/MHz, relative to highest capacity-dmips-mhz in the system. cci-control-port: true dynamic-power-coefficient: $ref: /schemas/types.yaml#/definitions/uint32 - description: - A u32 value that represents the running time dynamic - power coefficient in units of uW/MHz/V^2. The - coefficient can either be calculated from power + description: > + A u32 value that represents the running time dynamic power coefficient in + units of uW/MHz/V^2. The coefficient can either be calculated from power measurements or derived by analysis. - The dynamic power consumption of the CPU is - proportional to the square of the Voltage (V) and - the clock frequency (f). The coefficient is used to + The dynamic power consumption of the CPU is proportional to the square of + the Voltage (V) and the clock frequency (f). The coefficient is used to calculate the dynamic power as below - Pdyn = dynamic-power-coefficient * V^2 * f where voltage is in V, frequency is in MHz. + interconnects: + minItems: 1 + maxItems: 3 + + nvmem-cells: + maxItems: 1 + + nvmem-cell-names: + const: speed_grade + performance-domains: maxItems: 1 - description: - List of phandles and performance domain specifiers, as defined by - bindings of the performance domain provider. See also - dvfs/performance-domain.yaml. power-domains: - description: - List of phandles and PM domain specifiers, as defined by bindings of the - PM domain provider (see also ../power_domain.txt). + minItems: 1 + maxItems: 2 power-domain-names: description: - A list of power domain name strings sorted in the same order as the - power-domains property. - For PSCI based platforms, the name corresponding to the index of the PSCI PM domain provider, must be "psci". For SCMI based platforms, the name corresponding to the index of an SCMI performance domain provider, must be "perf". + minItems: 1 + maxItems: 2 + items: + enum: [ psci, perf, cpr ] - qcom,saw: - $ref: /schemas/types.yaml#/definitions/phandle - description: | - Specifies the SAW* node associated with this CPU. + resets: + maxItems: 1 - Required for systems that have an "enable-method" property - value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2" + arm-supply: + deprecated: true + description: Use 'cpu-supply' instead - * arm/msm/qcom,saw2.txt + cpu0-supply: + deprecated: true + description: Use 'cpu-supply' instead - qcom,acc: + mem-supply: true + + proc-supply: + deprecated: true + description: Use 'cpu-supply' instead + + sram-supply: + deprecated: true + description: Use 'mem-supply' instead + + mediatek,cci: $ref: /schemas/types.yaml#/definitions/phandle - description: | - Specifies the ACC* node associated with this CPU. + description: Link to Mediatek Cache Coherent Interconnect - Required for systems that have an "enable-method" property - value of "qcom,kpss-acc-v1", "qcom,kpss-acc-v2", "qcom,msm8226-smp" or - "qcom,msm8916-smp". + qcom,saw: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Specifies the SAW node associated with this CPU. - * arm/msm/qcom,kpss-acc.txt + qcom,acc: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Specifies the ACC node associated with this CPU. + + qcom,freq-domain: + description: Specifies the QCom CPUFREQ HW associated with the CPU. + $ref: /schemas/types.yaml#/definitions/phandle-array + maxItems: 1 rockchip,pmu: $ref: /schemas/types.yaml#/definitions/phandle - description: | + description: > Specifies the syscon node controlling the cpu core power domains. - Optional for systems that have an "enable-method" - property value of "rockchip,rk3066-smp" - While optional, it is the preferred way to get access to - the cpu-core power-domains. + Optional for systems that have an "enable-method" property value of + "rockchip,rk3066-smp". While optional, it is the preferred way to get + access to the cpu-core power-domains. secondary-boot-reg: $ref: /schemas/types.yaml#/definitions/uint32 - description: | + description: > Required for systems that have an "enable-method" property value of "brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp". - This includes the following SoCs: | - BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550 + This includes the following SoCs: + BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550, BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312 The secondary-boot-reg property is a u32 value that specifies the @@ -377,22 +392,66 @@ properties: formed by encoding the target CPU id into the low bits of the physical start address it should jump to. -if: - # If the enable-method property contains one of those values - properties: - enable-method: - contains: - enum: - - brcm,bcm11351-cpu-method - - brcm,bcm23550 - - brcm,bcm-nsp-smp - # and if enable-method is present - required: - - enable-method - -then: - required: - - secondary-boot-reg + thermal-idle: + type: object + +allOf: + - $ref: /schemas/cpu.yaml# + - $ref: /schemas/opp/opp-v1.yaml# + - if: + # If the enable-method property contains one of those values + properties: + enable-method: + contains: + enum: + - brcm,bcm11351-cpu-method + - brcm,bcm23550 + - brcm,bcm-nsp-smp + # and if enable-method is present + required: + - enable-method + then: + required: + - secondary-boot-reg + - if: + properties: + enable-method: + enum: + - spin-table + - renesas,r9a06g032-smp + required: + - enable-method + then: + required: + - cpu-release-addr + - if: + properties: + enable-method: + enum: + - qcom,kpss-acc-v1 + - qcom,kpss-acc-v2 + - qcom,msm8226-smp + - qcom,msm8916-smp + required: + - enable-method + then: + required: + - qcom,acc + - qcom,saw + else: + if: + # 2 Qualcomm platforms bootloaders need qcom,acc and qcom,saw yet use + # "spin-table" or "psci" enable-methods. Disallowing the properties for + # all other CPUs is the best we can do as there's not any way to + # distinguish these Qualcomm platforms. + not: + properties: + compatible: + const: arm,cortex-a53 + then: + properties: + qcom,acc: false + qcom,saw: false required: - device_type @@ -402,7 +461,7 @@ required: dependencies: rockchip,pmu: [enable-method] -additionalProperties: true +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,imx51-m4if.yaml b/Documentation/devicetree/bindings/arm/freescale/fsl,imx51-m4if.yaml new file mode 100644 index 000000000000..1f515bea3959 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/freescale/fsl,imx51-m4if.yaml @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/freescale/fsl,imx51-m4if.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale Multi Master Multi Memory Interface (M4IF) and Tigerp module + +description: collect the imx devices, which only have compatible and reg property + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +properties: + compatible: + oneOf: + - enum: + - fsl,imx51-m4if + - fsl,imx51-tigerp + - fsl,imx51-aipstz + - fsl,imx53-aipstz + - fsl,imx7d-pcie-phy + - items: + - const: fsl,imx53-tigerp + - const: fsl,imx51-tigerp + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + m4if@83fd8000 { + compatible = "fsl,imx51-m4if"; + reg = <0x83fd8000 0x1000>; + }; diff --git a/Documentation/devicetree/bindings/arm/freescale/m4if.txt b/Documentation/devicetree/bindings/arm/freescale/m4if.txt deleted file mode 100644 index 93bd7b867a53..000000000000 --- a/Documentation/devicetree/bindings/arm/freescale/m4if.txt +++ /dev/null @@ -1,12 +0,0 @@ -* Freescale Multi Master Multi Memory Interface (M4IF) module - -Required properties: -- compatible : Should be "fsl,imx51-m4if" -- reg : Address and length of the register set for the device - -Example: - -m4if: m4if@83fd8000 { - compatible = "fsl,imx51-m4if"; - reg = <0x83fd8000 0x1000>; -}; diff --git a/Documentation/devicetree/bindings/arm/freescale/tigerp.txt b/Documentation/devicetree/bindings/arm/freescale/tigerp.txt deleted file mode 100644 index 19e2aad63d6e..000000000000 --- a/Documentation/devicetree/bindings/arm/freescale/tigerp.txt +++ /dev/null @@ -1,12 +0,0 @@ -* Freescale Tigerp platform module - -Required properties: -- compatible : Should be "fsl,imx51-tigerp" -- reg : Address and length of the register set for the device - -Example: - -tigerp: tigerp@83fa0000 { - compatible = "fsl,imx51-tigerp"; - reg = <0x83fa0000 0x28>; -}; diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 0db2cbd7891f..d3b5e6923e41 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -97,6 +97,7 @@ properties: - i2se,duckbill - i2se,duckbill-2 - karo,tx28 # Ka-Ro electronics TX28 module + - lwn,imx28-btt3 - lwn,imx28-xea - msr,m28cu3 # M28 SoM with custom base board - schulercontrol,imx28-sps1 @@ -296,7 +297,6 @@ properties: - technexion,imx6q-pico-pi # TechNexion i.MX6Q Pico-Pi - technologic,imx6q-ts4900 - technologic,imx6q-ts7970 - - toradex,apalis_imx6q # Apalis iMX6 Modules - udoo,imx6q-udoo # Udoo i.MX6 Quad Board - uniwest,imx6q-evi # Uniwest Evi - variscite,dt6customboard @@ -490,7 +490,6 @@ properties: - technexion,imx6dl-pico-pi # TechNexion i.MX6DL Pico-Pi - technologic,imx6dl-ts4900 - technologic,imx6dl-ts7970 - - toradex,colibri_imx6dl # Colibri iMX6 Modules - udoo,imx6dl-udoo # Udoo i.MX6 Dual-lite Board - vdl,lanmcu # Van der Laan LANMCU board - wand,imx6dl-wandboard # Wandboard i.MX6 Dual Lite Board @@ -688,6 +687,12 @@ properties: - const: phytec,imx6ul-pcl063 # PHYTEC phyCORE-i.MX 6UL - const: fsl,imx6ul + - description: i.MX6UL Variscite VAR-SOM-MX6 Boards + items: + - const: variscite,mx6ulconcerto + - const: variscite,var-som-imx6ul + - const: fsl,imx6ul + - description: Kontron BL i.MX6UL (N631X S) Board items: - const: kontron,bl-imx6ul # Kontron BL i.MX6UL Carrier Board @@ -730,9 +735,6 @@ properties: - joz,jozacp # JOZ Access Point - kontron,sl-imx6ull # Kontron SL i.MX6ULL SoM - myir,imx6ull-mys-6ulx-eval # MYiR Tech iMX6ULL Evaluation Board - - toradex,colibri-imx6ull # Colibri iMX6ULL Modules - - toradex,colibri-imx6ull-emmc # Colibri iMX6ULL 1GB (eMMC) Module - - toradex,colibri-imx6ull-wifi # Colibri iMX6ULL Wi-Fi / BT Modules - uni-t,uti260b # UNI-T UTi260B Thermal Camera - const: fsl,imx6ull @@ -891,8 +893,6 @@ properties: - technexion,imx7d-pico-hobbit # TechNexion i.MX7D Pico-Hobbit - technexion,imx7d-pico-nymph # TechNexion i.MX7D Pico-Nymph - technexion,imx7d-pico-pi # TechNexion i.MX7D Pico-Pi - - toradex,colibri-imx7d # Colibri iMX7D Module - - toradex,colibri-imx7d-emmc # Colibri iMX7D 1GB (eMMC) Module - zii,imx7d-rmu2 # ZII RMU2 Board - zii,imx7d-rpu2 # ZII RPU2 Board - const: fsl,imx7d @@ -962,9 +962,6 @@ properties: - innocomm,wb15-evk # i.MX8MM Innocomm EVK board with WB15 SoM - kontron,imx8mm-sl # i.MX8MM Kontron SL (N801X) SOM - kontron,imx8mm-osm-s # i.MX8MM Kontron OSM-S (N802X) SOM - - toradex,verdin-imx8mm # Verdin iMX8M Mini Modules - - toradex,verdin-imx8mm-nonwifi # Verdin iMX8M Mini Modules without Wi-Fi / BT - - toradex,verdin-imx8mm-wifi # Verdin iMX8M Mini Wi-Fi / BT Modules - prt,prt8mm # i.MX8MM Protonic PRT8MM Board - const: fsl,imx8mm @@ -1098,12 +1095,12 @@ properties: - gateworks,imx8mp-gw74xx # i.MX8MP Gateworks Board - gateworks,imx8mp-gw75xx-2x # i.MX8MP Gateworks Board - gateworks,imx8mp-gw82xx-2x # i.MX8MP Gateworks Board + - skov,imx8mp-skov-basic # SKOV i.MX8MP baseboard without frontplate - skov,imx8mp-skov-revb-hdmi # SKOV i.MX8MP climate control without panel - skov,imx8mp-skov-revb-lt6 # SKOV i.MX8MP climate control with 7” panel - skov,imx8mp-skov-revb-mi1010ait-1cp1 # SKOV i.MX8MP climate control with 10.1" panel - - toradex,verdin-imx8mp # Verdin iMX8M Plus Modules - - toradex,verdin-imx8mp-nonwifi # Verdin iMX8M Plus Modules without Wi-Fi / BT - - toradex,verdin-imx8mp-wifi # Verdin iMX8M Plus Wi-Fi / BT Modules + - skov,imx8mp-skov-revc-bd500 # SKOV i.MX8MP climate control with LED frontplate + - skov,imx8mp-skov-revc-tian-g07017 # SKOV i.MX8MP climate control with 7" panel - ysoft,imx8mp-iota2-lumpy # Y Soft i.MX8MP IOTA2 Lumpy Board - const: fsl,imx8mp @@ -1123,6 +1120,12 @@ properties: - const: avnet,sm2s-imx8mp # SM2S-IMX8PLUS SoM - const: fsl,imx8mp + - description: Boundary Devices Nitrogen8M Plus ENC Carrier Board + items: + - const: boundary,imx8mp-nitrogen-enc-carrier-board + - const: boundary,imx8mp-nitrogen-som + - const: fsl,imx8mp + - description: Boundary Device Nitrogen8MP Universal SMARC Carrier Board items: - const: boundary,imx8mp-nitrogen-smarc-universal-board @@ -1159,6 +1162,13 @@ properties: - const: kontron,imx8mp-osm-s # Kontron i.MX8MP OSM-S SoM - const: fsl,imx8mp + - description: PHYTEC phyCORE-i.MX8MP FPSC based boards + items: + - enum: + - phytec,imx8mp-libra-rdk-fpsc # i.MX 8M Plus Libra RDK + - const: phytec,imx8mp-phycore-fpsc # phyCORE-i.MX 8M Plus FPSC + - const: fsl,imx8mp + - description: PHYTEC phyCORE-i.MX8MP SoM based boards items: - const: phytec,imx8mp-phyboard-pollux-rdk # phyBOARD-Pollux RDK @@ -1179,6 +1189,12 @@ properties: - const: polyhex,imx8mp-debix-som-a # Polyhex Debix SOM A - const: fsl,imx8mp + - description: Toradex Boards with SMARC iMX8M Plus Modules + items: + - const: toradex,smarc-imx8mp-dev # Toradex SMARC iMX8M Plus on Toradex SMARC Development Board + - const: toradex,smarc-imx8mp # Toradex SMARC iMX8M Plus Module + - const: fsl,imx8mp + - description: Toradex Boards with Verdin iMX8M Plus Modules items: - enum: @@ -1273,8 +1289,6 @@ properties: - enum: - fsl,imx8qm-mek # i.MX8QM MEK Board - fsl,imx8qm-mek-revd # i.MX8QM MEK Rev D Board - - toradex,apalis-imx8 # Apalis iMX8 Modules - - toradex,apalis-imx8-v1.1 # Apalis iMX8 V1.1 Modules - const: fsl,imx8qm - description: i.MX8QM Boards with Toradex Apalis iMX8 Modules @@ -1338,6 +1352,22 @@ properties: - const: tq,imx8qxp-tqma8xqp # TQ-Systems GmbH TQMa8XQP SOM (with i.MX8QXP) - const: fsl,imx8qxp + - description: + TQMa8XxS is a series of SOM featuring NXP i.MX8X system-on-chip + variants. It has the SMARC-2.0 form factor and is designed to be placed on + different carrier boards. MB-SMARC-2 is a carrier reference design. + oneOf: + - items: + - enum: + - tq,imx8qxp-tqma8xqps-mb-smarc-2 # TQ-Systems GmbH TQMa8QXPS SOM on MB-SMARC-2 + - const: tq,imx8qxp-tqma8xqps # TQ-Systems GmbH TQMa8QXPS SOM + - const: fsl,imx8qxp + - items: + - enum: + - tq,imx8dxp-tqma8xdps-mb-smarc-2 # TQ-Systems GmbH TQMa8XDPS SOM on MB-SMARC-2 + - const: tq,imx8dxp-tqma8xdps # TQ-Systems GmbH TQMa8XDPS SOM + - const: fsl,imx8dxp + - description: i.MX8ULP based Boards items: - enum: @@ -1352,9 +1382,16 @@ properties: - fsl,imx93-14x14-evk # i.MX93 14x14 EVK Board - const: fsl,imx93 + - description: i.MX94 based Boards + items: + - enum: + - fsl,imx943-evk # i.MX943 EVK Board + - const: fsl,imx94 + - description: i.MX95 based Boards items: - enum: + - fsl,imx95-15x15-evk # i.MX95 15x15 EVK Board - fsl,imx95-19x19-evk # i.MX95 19x19 EVK Board - const: fsl,imx95 @@ -1378,12 +1415,16 @@ properties: All SOM and CPU variants use the same device tree hence only one compatible is needed. Bootloader disables all features not present in the assembled SOC. + MBa91xxCA mainboard can be used as starterkit for the SOM + soldered on an adapter board or for the connector variant + to evaluate RGB display support. MBa93xxCA mainboard can be used as starterkit for the SOM soldered on an adapter board or for the connector variant MBa93xxLA mainboard is a single board computer using the solderable SOM variant items: - enum: + - tq,imx93-tqma9352-mba91xxca # TQ-Systems GmbH i.MX93 TQMa93xxCA/LA SOM on MBa91xxCA - tq,imx93-tqma9352-mba93xxca # TQ-Systems GmbH i.MX93 TQMa93xxCA/LA SOM on MBa93xxCA - tq,imx93-tqma9352-mba93xxla # TQ-Systems GmbH i.MX93 TQMa93xxLA SOM on MBa93xxLA SBC - const: tq,imx93-tqma9352 # TQ-Systems GmbH i.MX93 TQMa93xxCA/LA SOM @@ -1391,8 +1432,10 @@ properties: - description: PHYTEC phyCORE-i.MX93 SoM based boards items: - - const: phytec,imx93-phyboard-segin # phyBOARD-Segin with i.MX93 - - const: phytec,imx93-phycore-som # phyCORE-i.MX93 SoM + - enum: + - phytec,imx93-phyboard-nash # phyBOARD-Nash-i.MX93 + - phytec,imx93-phyboard-segin # phyBOARD-Segin with i.MX93 + - const: phytec,imx93-phycore-som # phyCORE-i.MX93 SoM - const: fsl,imx93 - description: Variscite VAR-SOM-MX93 based boards @@ -1408,6 +1451,16 @@ properties: - const: fsl,imx93 - description: + TQMa95xxSA is a series of SOM featuring NXP i.MX95 SoC variants. + It has the SMARC form factor and is designed to be placed on + different carrier boards. MB-SMARC-2 is a carrier reference design. + items: + - enum: + - tq,imx95-tqma9596sa-mb-smarc-2 # TQ-Systems GmbH i.MX95 TQMa95xxSA SOM on MB-SMARC-2 + - const: tq,imx95-tqma9596sa # TQ-Systems GmbH i.MX95 TQMa95xxSA SOM + - const: fsl,imx95 + + - description: Freescale Vybrid Platform Device Tree Bindings For the Vybrid SoC family all variants with DDR controller are supported, @@ -1435,7 +1488,6 @@ properties: - fsl,vf610-twr # VF610 Tower Board - lwn,bk4 # Liebherr BK4 controller - phytec,vf610-cosmic # PHYTEC Cosmic/Cosmic+ Board - - toradex,vf610-colibri_vf61 # Colibri VF61 Modules - const: fsl,vf610 - description: Toradex Colibri VF61 Module on Colibri Evaluation Board diff --git a/Documentation/devicetree/bindings/arm/google.yaml b/Documentation/devicetree/bindings/arm/google.yaml index e20b5c9b16bc..99961e5282e5 100644 --- a/Documentation/devicetree/bindings/arm/google.yaml +++ b/Documentation/devicetree/bindings/arm/google.yaml @@ -34,10 +34,11 @@ properties: const: '/' compatible: oneOf: - - description: Google Pixel 6 / Oriole + - description: Google Pixel 6 or 6 Pro (Oriole or Raven) items: - enum: - google,gs101-oriole + - google,gs101-raven - const: google,gs101 # Bootloader requires empty ect node to be present diff --git a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml index 2ee0c740eb56..c75cd7d29f1a 100644 --- a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml +++ b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml @@ -25,6 +25,7 @@ properties: items: - enum: - intel,socfpga-agilex5-socdk + - intel,socfpga-agilex5-socdk-nand - const: intel,socfpga-agilex5 additionalProperties: true diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-37xx.yaml b/Documentation/devicetree/bindings/arm/marvell/armada-37xx.yaml index 6905d29f3108..51e1386f0e01 100644 --- a/Documentation/devicetree/bindings/arm/marvell/armada-37xx.yaml +++ b/Documentation/devicetree/bindings/arm/marvell/armada-37xx.yaml @@ -18,6 +18,7 @@ properties: items: - enum: - cznic,turris-mox + - glinet,gl-mv1000 - globalscale,espressobin - marvell,armada-3720-db - methode,edpu diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml b/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml index 538d91be8857..4bc7454a5d3a 100644 --- a/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml +++ b/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml @@ -23,6 +23,9 @@ properties: - description: Armada 7040 SoC items: + - enum: + - globalscale,mochabin + - marvell,armada7040-db - const: marvell,armada7040 - const: marvell,armada-ap806-quad - const: marvell,armada-ap806 @@ -35,10 +38,32 @@ properties: - description: Armada 8040 SoC items: + - enum: + - iei,puzzle-m801 + - marvell,armada8040-db + - solidrun,clearfog-gt-8k - const: marvell,armada8040 - const: marvell,armada-ap806-quad - const: marvell,armada-ap806 + - description: Armada 8040 SoC MACCHIATOBin Boards + items: + - enum: + - marvell,armada8040-mcbin-doubleshot + - marvell,armada8040-mcbin-singleshot + - const: marvell,armada8040-mcbin + - const: marvell,armada8040 + - const: marvell,armada-ap806-quad + - const: marvell,armada-ap806 + + - description: Armada 8080 SoC + items: + - enum: + - marvell,armada-8080-db + - const: marvell,armada-8080 + - const: marvell,armada-ap810-octa + - const: marvell,armada-ap810 + - description: Armada CN9130 SoC with no external CP items: - const: marvell,cn9130 diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-8kp.txt b/Documentation/devicetree/bindings/arm/marvell/armada-8kp.txt deleted file mode 100644 index f3e9624534c6..000000000000 --- a/Documentation/devicetree/bindings/arm/marvell/armada-8kp.txt +++ /dev/null @@ -1,15 +0,0 @@ -Marvell Armada 8KPlus Platforms Device Tree Bindings ----------------------------------------------------- - -Boards using a SoC of the Marvell Armada 8KP families must carry -the following root node property: - - - compatible, with one of the following values: - - - "marvell,armada-8080", "marvell,armada-ap810-octa", "marvell,armada-ap810" - when the SoC being used is the Armada 8080 - -Example: - -compatible = "marvell,armada-8080-db", "marvell,armada-8080", - "marvell,armada-ap810-octa", "marvell,armada-ap810" diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index 3ce34d68c213..a7e0a72f6e4c 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -105,6 +105,10 @@ properties: - bananapi,bpi-r4 - const: mediatek,mt7988a - items: + - const: bananapi,bpi-r4-2g5 + - const: bananapi,bpi-r4 + - const: mediatek,mt7988a + - items: - enum: - mediatek,mt8127-moose - const: mediatek,mt8127 @@ -285,6 +289,13 @@ properties: - const: google,steelix-sku393218 - const: google,steelix - const: mediatek,mt8186 + - description: Google Ponyta + items: + - enum: + - google,ponyta-sku0 + - google,ponyta-sku1 + - const: google,ponyta + - const: mediatek,mt8186 - description: Google Rusty (Lenovo 100e Chromebook Gen 4) items: - const: google,steelix-sku196609 @@ -414,6 +425,11 @@ properties: - const: mediatek,mt8365 - items: - enum: + - mediatek,mt8370-evk + - const: mediatek,mt8370 + - const: mediatek,mt8188 + - items: + - enum: - mediatek,mt8390-evk - const: mediatek,mt8390 - const: mediatek,mt8188 diff --git a/Documentation/devicetree/bindings/arm/pmu.yaml b/Documentation/devicetree/bindings/arm/pmu.yaml index a148ff54f2b8..295963a3cae7 100644 --- a/Documentation/devicetree/bindings/arm/pmu.yaml +++ b/Documentation/devicetree/bindings/arm/pmu.yaml @@ -67,6 +67,7 @@ properties: - arm,neoverse-v2-pmu - arm,neoverse-v3-pmu - arm,neoverse-v3ae-pmu + - arm,rainier-pmu - brcm,vulcan-pmu - cavium,thunder-pmu - nvidia,denver-pmu diff --git a/Documentation/devicetree/bindings/arm/psci.yaml b/Documentation/devicetree/bindings/arm/psci.yaml index cbb012e217ab..7360a2849b5b 100644 --- a/Documentation/devicetree/bindings/arm/psci.yaml +++ b/Documentation/devicetree/bindings/arm/psci.yaml @@ -191,27 +191,27 @@ examples: #size-cells = <0>; #address-cells = <1>; - CPU0: cpu@0 { + cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0>; enable-method = "psci"; - power-domains = <&CPU_PD0>; + power-domains = <&cpu_pd0>; power-domain-names = "psci"; }; - CPU1: cpu@1 { + cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x100>; enable-method = "psci"; - power-domains = <&CPU_PD1>; + power-domains = <&cpu_pd1>; power-domain-names = "psci"; }; idle-states { - CPU_PWRDN: cpu-power-down { + cpu_pwrdn: cpu-power-down { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x0000001>; entry-latency-us = <10>; @@ -222,7 +222,7 @@ examples: domain-idle-states { - CLUSTER_RET: cluster-retention { + cluster_ret: cluster-retention { compatible = "domain-idle-state"; arm,psci-suspend-param = <0x1000011>; entry-latency-us = <500>; @@ -230,7 +230,7 @@ examples: min-residency-us = <2000>; }; - CLUSTER_PWRDN: cluster-power-down { + cluster_pwrdn: cluster-power-down { compatible = "domain-idle-state"; arm,psci-suspend-param = <0x1000031>; entry-latency-us = <2000>; @@ -244,21 +244,21 @@ examples: compatible = "arm,psci-1.0"; method = "smc"; - CPU_PD0: power-domain-cpu0 { + cpu_pd0: power-domain-cpu0 { #power-domain-cells = <0>; - domain-idle-states = <&CPU_PWRDN>; - power-domains = <&CLUSTER_PD>; + domain-idle-states = <&cpu_pwrdn>; + power-domains = <&cluster_pd>; }; - CPU_PD1: power-domain-cpu1 { + cpu_pd1: power-domain-cpu1 { #power-domain-cells = <0>; - domain-idle-states = <&CPU_PWRDN>; - power-domains = <&CLUSTER_PD>; + domain-idle-states = <&cpu_pwrdn>; + power-domains = <&cluster_pd>; }; - CLUSTER_PD: power-domain-cluster { + cluster_pd: power-domain-cluster { #power-domain-cells = <0>; - domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>; + domain-idle-states = <&cluster_ret>, <&cluster_pwrdn>; }; }; ... diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml new file mode 100644 index 000000000000..843b52eaf872 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/qcom,coresight-ctcu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: CoreSight TMC Control Unit + +maintainers: + - Yuanfang Zhang <quic_yuanfang@quicinc.com> + - Mao Jinlong <quic_jinlmao@quicinc.com> + - Jie Gan <quic_jiegan@quicinc.com> + +description: | + The Trace Memory Controller(TMC) is used for Embedded Trace Buffer(ETB), + Embedded Trace FIFO(ETF) and Embedded Trace Router(ETR) configurations. + The configuration mode (ETB, ETF, ETR) is discovered at boot time when + the device is probed. + + The Coresight TMC Control unit controls various Coresight behaviors. + It works as a helper device when connected to TMC ETR device. + It is responsible for controlling the data filter function based on + the source device's Trace ID for TMC ETR device. The trace data with + that Trace id can get into ETR's buffer while other trace data gets + ignored. + +properties: + compatible: + enum: + - qcom,sa8775p-ctcu + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: apb + + in-ports: + $ref: /schemas/graph.yaml#/properties/ports + + patternProperties: + '^port(@[0-1])?$': + description: Input connections from CoreSight Trace bus + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + - reg + - in-ports + +additionalProperties: false + +examples: + - | + ctcu@1001000 { + compatible = "qcom,sa8775p-ctcu"; + reg = <0x1001000 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ctcu_in_port0: endpoint { + remote-endpoint = <&etr0_out_port>; + }; + }; + + port@1 { + reg = <1>; + ctcu_in_port1: endpoint { + remote-endpoint = <&etr1_out_port>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 618a87693ac1..56f78f0f3803 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -90,6 +90,7 @@ description: | sm6350 sm6375 sm7125 + sm7150 sm7225 sm7325 sm8150 @@ -1020,6 +1021,7 @@ properties: - items: - enum: - sony,pdx201 + - xiaomi,ginkgo - xiaomi,laurel-sprout - const: qcom,sm6125 @@ -1041,6 +1043,11 @@ properties: - items: - enum: + - google,sunfish + - const: qcom,sm7150 + + - items: + - enum: - fairphone,fp4 - const: qcom,sm7225 @@ -1123,14 +1130,18 @@ properties: - items: - enum: - - lenovo,thinkpad-t14s + - lenovo,thinkpad-t14s-lcd + - lenovo,thinkpad-t14s-oled + - const: lenovo,thinkpad-t14s - const: qcom,x1e78100 - const: qcom,x1e80100 - items: - enum: - asus,vivobook-s15 + - asus,zenbook-a14-ux3407ra - dell,xps13-9345 + - hp,elitebook-ultra-g1q - hp,omnibook-x14 - lenovo,yoga-slim7x - microsoft,romulus13 @@ -1141,6 +1152,7 @@ properties: - items: - enum: + - asus,zenbook-a14-ux3407qa - qcom,x1p42100-crd - const: qcom,x1p42100 diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 522a6f0450ea..5772d905f390 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -49,6 +49,11 @@ properties: - anbernic,rg-arc-s - const: rockchip,rk3566 + - description: Ariaboard Photonicat + items: + - const: ariaboard,photonicat + - const: rockchip,rk3568 + - description: ArmSoM Sige5 board items: - const: armsom,sige5 @@ -178,6 +183,13 @@ properties: - const: engicam,px30-core - const: rockchip,px30 + - description: Firefly iCore-3588Q-based boards + items: + - enum: + - mntre,reform2-rcore + - const: firefly,icore-3588q + - const: rockchip,rk3588 + - description: Firefly Core-3588J-based boards items: - enum: @@ -236,6 +248,11 @@ properties: - firefly,roc-rk3399-pc-plus - const: rockchip,rk3399 + - description: Firefly ROC-RK3576-PC + items: + - const: firefly,roc-rk3576-pc + - const: rockchip,rk3576 + - description: Firefly Station M2 items: - const: firefly,rk3566-roc-pc @@ -862,6 +879,11 @@ properties: - const: radxa,rock-4c-plus - const: rockchip,rk3399 + - description: Radxa ROCK 4D + items: + - const: radxa,rock-4d + - const: rockchip,rk3576 + - description: Radxa ROCK 4SE items: - const: radxa,rock-4se @@ -924,6 +946,11 @@ properties: - const: radxa,rock-5b - const: rockchip,rk3588 + - description: Radxa ROCK 5B+ + items: + - const: radxa,rock-5b-plus + - const: rockchip,rk3588 + - description: Radxa ROCK 5C items: - const: radxa,rock-5c @@ -1025,6 +1052,11 @@ properties: - const: rockchip,rk3399-evb - const: rockchip,rk3399 + - description: Rockchip RK3399 Industry Evaluation board + items: + - const: rockchip,rk3399-evb-ind + - const: rockchip,rk3399 + - description: Rockchip RK3399 Sapphire standalone items: - const: rockchip,rk3399-sapphire @@ -1035,6 +1067,11 @@ properties: - const: rockchip,rk3399-sapphire-excavator - const: rockchip,rk3399 + - description: Rockchip RK3562 Evaluation board 2 + items: + - const: rockchip,rk3562-evb2-v10 + - const: rockchip,rk3562 + - description: Rockchip RK3566 BOX Evaluation Demo board items: - const: rockchip,rk3566-box-demo @@ -1052,7 +1089,9 @@ properties: - description: Rockchip RK3588 Evaluation board items: - - const: rockchip,rk3588-evb1-v10 + - enum: + - rockchip,rk3588-evb1-v10 + - rockchip,rk3588-evb2-v10 - const: rockchip,rk3588 - description: Rockchip RK3588S Evaluation board @@ -1087,6 +1126,24 @@ properties: - rockchip,rv1126 - rockchip,rv1109 + - description: Theobroma Systems PX30-Cobra + items: + - enum: + - tsd,px30-cobra-ltk050h3146w + - tsd,px30-cobra-ltk050h3146w-a2 + - tsd,px30-cobra-ltk050h3148w + - tsd,px30-cobra-ltk500hd1829 + - const: tsd,px30-cobra + - const: rockchip,px30 + + - description: Theobroma Systems PX30-PP1516 + items: + - enum: + - tsd,px30-pp1516-ltk050h3146w-a2 + - tsd,px30-pp1516-ltk050h3148w + - const: tsd,px30-pp1516 + - const: rockchip,px30 + - description: Theobroma Systems PX30-uQ7 with Haikou baseboard items: - const: tsd,px30-ringneck-haikou @@ -1136,11 +1193,12 @@ properties: - const: xunlong,orangepi-3b - const: rockchip,rk3566 - - description: Xunlong Orange Pi 5 Max/Plus + - description: Xunlong Orange Pi 5 Max/Plus/Ultra items: - enum: - xunlong,orangepi-5-max - xunlong,orangepi-5-plus + - xunlong,orangepi-5-ultra - const: rockchip,rk3588 - description: Xunlong Orange Pi R1 Plus / LTS diff --git a/Documentation/devicetree/bindings/arm/rockchip/pmu.yaml b/Documentation/devicetree/bindings/arm/rockchip/pmu.yaml index 52016a141227..46c1af851be7 100644 --- a/Documentation/devicetree/bindings/arm/rockchip/pmu.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip/pmu.yaml @@ -25,6 +25,7 @@ select: - rockchip,rk3288-pmu - rockchip,rk3368-pmu - rockchip,rk3399-pmu + - rockchip,rk3562-pmu - rockchip,rk3568-pmu - rockchip,rk3576-pmu - rockchip,rk3588-pmu @@ -43,6 +44,7 @@ properties: - rockchip,rk3288-pmu - rockchip,rk3368-pmu - rockchip,rk3399-pmu + - rockchip,rk3562-pmu - rockchip,rk3568-pmu - rockchip,rk3576-pmu - rockchip,rk3588-pmu diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml index fab29f95d8e6..b3be184c7e56 100644 --- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml @@ -212,6 +212,14 @@ properties: - samsung,exynos7-espresso # Samsung Exynos7 Espresso - const: samsung,exynos7 + - description: Exynos7870 based boards + items: + - enum: + - samsung,a2corelte # Samsung Galaxy A2 Core + - samsung,j6lte # Samsung Galaxy J6 + - samsung,on7xelte # Samsung Galaxy J7 Prime + - const: samsung,exynos7870 + - description: Exynos7885 based boards items: - enum: diff --git a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml index d083d8ad48b7..ed97652c8492 100644 --- a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml @@ -21,6 +21,8 @@ properties: - st,stm32f4-gcan - st,stm32mp151-pwr-mcu - st,stm32mp157-syscfg + - st,stm32mp21-syscfg + - st,stm32mp23-syscfg - st,stm32mp25-syscfg - const: syscon - items: diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml index b6c56d4ce6b9..408532504a24 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -44,6 +44,10 @@ properties: - const: st,stm32h743 - items: - enum: + - st,stm32h747i-disco + - const: st,stm32h747 + - items: + - enum: - st,stm32h750i-art-pi - const: st,stm32h750 - items: @@ -51,9 +55,16 @@ properties: - st,stm32mp135f-dk - const: st,stm32mp135 + - description: ST STM32MP133 based Boards + items: + - enum: + - pri,prihmb # Priva E-Measuringbox board + - const: st,stm32mp133 + - description: ST STM32MP151 based Boards items: - enum: + - ply,plyaqm # Plymovent AQM board - prt,mecio1r0 # Protonic MECIO1r0 - prt,mect1s # Protonic MECT1S - prt,prtt1a # Protonic PRTT1A @@ -94,6 +105,8 @@ properties: - description: Octavo OSD32MP153 System-in-Package based boards items: - enum: + - lxa,stm32mp153c-fairytux2-gen1 # Linux Automation FairyTux 2 (Generation 1) + - lxa,stm32mp153c-fairytux2-gen2 # Linux Automation FairyTux 2 (Generation 2) - lxa,stm32mp153c-tac-gen3 # Linux Automation TAC (Generation 3) - const: oct,stm32mp153x-osd32 - const: st,stm32mp153 @@ -175,12 +188,30 @@ properties: - const: phytec,phycore-stm32mp157c-som - const: st,stm32mp157 + - description: Ultratronik STM32MP1 SBC based Boards + items: + - const: ultratronik,stm32mp157c-ultra-fly-sbc + - const: st,stm32mp157 + - description: ST STM32MP257 based Boards items: - enum: + - st,stm32mp257f-dk - st,stm32mp257f-ev1 - const: st,stm32mp257 + - description: ST STM32MP235 based Boards + items: + - enum: + - st,stm32mp235f-dk + - const: st,stm32mp235 + + - description: ST STM32MP215 based Boards + items: + - enum: + - st,stm32mp215f-dk + - const: st,stm32mp215 + additionalProperties: true ... diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index 046536d02706..7807ea613258 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -492,6 +492,11 @@ properties: - const: lamobo,lamobo-r1 - const: allwinner,sun7i-a20 + - description: Liontron H-A133L + items: + - const: liontron,h-a133l + - const: allwinner,sun50i-a100 + - description: HAOYU Electronics Marsboard A10 items: - const: haoyu,a10-marsboard @@ -589,6 +594,11 @@ properties: - const: emlid,neutis-n5h3 - const: allwinner,sun8i-h3 + - description: NetCube Systems Kumquat + items: + - const: netcube,kumquat + - const: allwinner,sun8i-v3s + - description: NextThing Co. CHIP items: - const: nextthing,chip @@ -840,6 +850,11 @@ properties: - const: allwinner,r7-tv-dongle - const: allwinner,sun5i-a10s + - description: Radxa Cubie A5E + items: + - const: radxa,cubie-a5e + - const: allwinner,sun55i-a527 + - description: Remix Mini PC items: - const: jide,remix-mini-pc @@ -961,6 +976,11 @@ properties: - const: hechuang,x96-mate - const: allwinner,sun50i-h616 + - description: X96Q Pro+ + items: + - const: amediatech,x96q-pro-plus + - const: allwinner,sun55i-h728 + - description: Xunlong OrangePi items: - const: xunlong,orangepi @@ -1076,4 +1096,14 @@ properties: - const: xunlong,orangepi-zero3 - const: allwinner,sun50i-h618 + - description: YuzukiHD Avaota A1 + items: + - const: yuzukihd,avaota-a1 + - const: allwinner,sun55i-t527 + + - description: YuzukiHD Chameleon + items: + - const: yuzukihd,chameleon + - const: allwinner,sun50i-h618 + additionalProperties: true diff --git a/Documentation/devicetree/bindings/arm/tegra.yaml b/Documentation/devicetree/bindings/arm/tegra.yaml index 65e0ff1fdf1e..9cae3268a827 100644 --- a/Documentation/devicetree/bindings/arm/tegra.yaml +++ b/Documentation/devicetree/bindings/arm/tegra.yaml @@ -52,17 +52,14 @@ properties: - nvidia,cardhu-a04 - const: nvidia,cardhu - const: nvidia,tegra30 - - items: - - const: asus,tf201 - - const: nvidia,tegra30 - - items: - - const: asus,tf300t - - const: nvidia,tegra30 - - items: - - const: asus,tf300tg - - const: nvidia,tegra30 - - items: - - const: asus,tf700t + - description: ASUS Transformers Device family + items: + - enum: + - asus,tf201 + - asus,tf300t + - asus,tf300tg + - asus,tf300tl + - asus,tf700t - const: nvidia,tegra30 - description: LG Optimus 4X P880 items: diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml index 18f155cd06c8..bf6003d8fb76 100644 --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml @@ -46,6 +46,7 @@ properties: - description: K3 AM625 SoC items: - enum: + - beagle,am62-pocketbeagle2 - beagle,am625-beagleplay - ti,am625-sk - ti,am62-lp-sk @@ -75,6 +76,30 @@ properties: - const: toradex,verdin-am62 # Verdin AM62 Module - const: ti,am625 + - description: K3 AM62P5 SoC Toradex Verdin Modules and Carrier Boards + items: + - enum: + - toradex,verdin-am62p-nonwifi-dahlia # Verdin AM62P Module on Dahlia + - toradex,verdin-am62p-nonwifi-dev # Verdin AM62P Module on Verdin Development Board + - toradex,verdin-am62p-nonwifi-ivy # Verdin AM62P Module on Ivy + - toradex,verdin-am62p-nonwifi-mallow # Verdin AM62P Module on Mallow + - toradex,verdin-am62p-nonwifi-yavia # Verdin AM62P Module on Yavia + - const: toradex,verdin-am62p-nonwifi # Verdin AM62P Module without Wi-Fi / BT + - const: toradex,verdin-am62p # Verdin AM62P Module + - const: ti,am62p5 + + - description: K3 AM62P5 SoC Toradex Verdin Modules and Carrier Boards with Wi-Fi / BT + items: + - enum: + - toradex,verdin-am62p-wifi-dahlia # Verdin AM62P Wi-Fi / BT Module on Dahlia + - toradex,verdin-am62p-wifi-dev # Verdin AM62P Wi-Fi / BT M. on Verdin Development B. + - toradex,verdin-am62p-wifi-ivy # Verdin AM62P Wi-Fi / BT Module on Ivy + - toradex,verdin-am62p-wifi-mallow # Verdin AM62P Wi-Fi / BT Module on Mallow + - toradex,verdin-am62p-wifi-yavia # Verdin AM62P Wi-Fi / BT Module on Yavia + - const: toradex,verdin-am62p-wifi # Verdin AM62P Wi-Fi / BT Module + - const: toradex,verdin-am62p # Verdin AM62P Module + - const: ti,am62p5 + - description: K3 AM642 SoC items: - enum: @@ -139,6 +164,13 @@ properties: - ti,j721s2-evm - const: ti,j721s2 + - description: K3 J721s2 SoC Phytec SoM based boards + items: + - enum: + - phytec,am68-phyboard-izar + - const: phytec,am68-phycore-som + - const: ti,j721s2 + - description: K3 J722S SoC and Boards items: - enum: diff --git a/Documentation/devicetree/bindings/arm/ti/omap.yaml b/Documentation/devicetree/bindings/arm/ti/omap.yaml index 93e04a109a12..3603edd7361d 100644 --- a/Documentation/devicetree/bindings/arm/ti/omap.yaml +++ b/Documentation/devicetree/bindings/arm/ti/omap.yaml @@ -141,6 +141,13 @@ properties: - const: ti,omap4430 - const: ti,omap4 + - description: OMAP4 PandaBoard Revision A4 and later + items: + - const: ti,omap4-panda-a4 + - const: ti,omap4-panda + - const: ti,omap4430 + - const: ti,omap4 + - description: OMAP4 DuoVero with Parlor expansion board/daughter board items: - const: gumstix,omap4-duovero-parlor diff --git a/Documentation/devicetree/bindings/arm/vt8500.yaml b/Documentation/devicetree/bindings/arm/vt8500.yaml index 5d5ad5a60451..fa47b8989bbf 100644 --- a/Documentation/devicetree/bindings/arm/vt8500.yaml +++ b/Documentation/devicetree/bindings/arm/vt8500.yaml @@ -7,14 +7,13 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: VIA/Wondermedia VT8500 Platforms maintainers: - - Tony Prisk <linux@prisktech.co.nz> -description: test + - Alexey Charkov <alchark@gmail.com> properties: $nodename: const: '/' compatible: - items: + oneOf: - enum: - via,vt8500 - wm,wm8505 @@ -22,4 +21,9 @@ properties: - wm,wm8750 - wm,wm8850 + - description: VIA APC Rock and Paper boards + items: + - const: via,apc-rock + - const: wm,wm8950 + additionalProperties: true diff --git a/Documentation/devicetree/bindings/ata/ahci-dm816.txt b/Documentation/devicetree/bindings/ata/ahci-dm816.txt deleted file mode 100644 index f8c535f3541f..000000000000 --- a/Documentation/devicetree/bindings/ata/ahci-dm816.txt +++ /dev/null @@ -1,21 +0,0 @@ -Device tree binding for the TI DM816 AHCI SATA Controller ---------------------------------------------------------- - -Required properties: - - compatible: must be "ti,dm816-ahci" - - reg: physical base address and size of the register region used by - the controller (as defined by the AHCI 1.1 standard) - - interrupts: interrupt specifier (refer to the interrupt binding) - - clocks: list of phandle and clock specifier pairs (or only - phandles for clock providers with '0' defined for - #clock-cells); two clocks must be specified: the functional - clock and an external reference clock - -Example: - - sata: sata@4a140000 { - compatible = "ti,dm816-ahci"; - reg = <0x4a140000 0x10000>; - interrupts = <16>; - clocks = <&sysclk5_ck>, <&sata_refclk>; - }; diff --git a/Documentation/devicetree/bindings/ata/ahci-st.txt b/Documentation/devicetree/bindings/ata/ahci-st.txt deleted file mode 100644 index 909c9935360d..000000000000 --- a/Documentation/devicetree/bindings/ata/ahci-st.txt +++ /dev/null @@ -1,35 +0,0 @@ -STMicroelectronics STi SATA controller - -This binding describes a SATA device. - -Required properties: - - compatible : Must be "st,ahci" - - reg : Physical base addresses and length of register sets - - interrupts : Interrupt associated with the SATA device - - interrupt-names : Associated name must be; "hostc" - - clocks : The phandle for the clock - - clock-names : Associated name must be; "ahci_clk" - - phys : The phandle for the PHY port - - phy-names : Associated name must be; "ahci_phy" - -Optional properties: - - resets : The power-down, soft-reset and power-reset lines of SATA IP - - reset-names : Associated names must be; "pwr-dwn", "sw-rst" and "pwr-rst" - -Example: - - /* Example for stih407 family silicon */ - sata0: sata@9b20000 { - compatible = "st,ahci"; - reg = <0x9b20000 0x1000>; - interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>; - interrupt-names = "hostc"; - phys = <&phy_port0 PHY_TYPE_SATA>; - phy-names = "ahci_phy"; - resets = <&powerdown STIH407_SATA0_POWERDOWN>, - <&softreset STIH407_SATA0_SOFTRESET>, - <&softreset STIH407_SATA0_PWR_SOFTRESET>; - reset-names = "pwr-dwn", "sw-rst", "pwr-rst"; - clocks = <&clk_s_c0_flexgen CLK_ICN_REG>; - clock-names = "ahci_clk"; - }; diff --git a/Documentation/devicetree/bindings/ata/apm,xgene-ahci.yaml b/Documentation/devicetree/bindings/ata/apm,xgene-ahci.yaml new file mode 100644 index 000000000000..7dc942808656 --- /dev/null +++ b/Documentation/devicetree/bindings/ata/apm,xgene-ahci.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ata/apm,xgene-ahci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: APM X-Gene 6.0 Gb/s SATA host controller + +maintainers: + - Rob Herring <robh@kernel.org> + +allOf: + - $ref: ahci-common.yaml# + +properties: + compatible: + enum: + - apm,xgene-ahci + - apm,xgene-ahci-pcie + + reg: + minItems: 4 + items: + - description: AHCI memory resource + - description: Host controller core + - description: Host controller diagnostic + - description: Host controller AXI + - description: Host controller MUX + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - clocks + - phys + - phy-names + +unevaluatedProperties: false + +examples: + - | + sata@1a400000 { + compatible = "apm,xgene-ahci"; + reg = <0x1a400000 0x1000>, + <0x1f220000 0x1000>, + <0x1f22d000 0x1000>, + <0x1f22e000 0x1000>, + <0x1f227000 0x1000>; + clocks = <&sataclk 0>; + dma-coherent; + interrupts = <0x0 0x87 0x4>; + phys = <&phy2 0>; + phy-names = "sata-phy"; + }; diff --git a/Documentation/devicetree/bindings/ata/apm-xgene.txt b/Documentation/devicetree/bindings/ata/apm-xgene.txt deleted file mode 100644 index 02e690a675db..000000000000 --- a/Documentation/devicetree/bindings/ata/apm-xgene.txt +++ /dev/null @@ -1,77 +0,0 @@ -* APM X-Gene 6.0 Gb/s SATA host controller nodes - -SATA host controller nodes are defined to describe on-chip Serial ATA -controllers. Each SATA controller (pair of ports) have its own node. - -Required properties: -- compatible : Shall contain: - * "apm,xgene-ahci" -- reg : First memory resource shall be the AHCI memory - resource. - Second memory resource shall be the host controller - core memory resource. - Third memory resource shall be the host controller - diagnostic memory resource. - 4th memory resource shall be the host controller - AXI memory resource. - 5th optional memory resource shall be the host - controller MUX memory resource if required. -- interrupts : Interrupt-specifier for SATA host controller IRQ. -- clocks : Reference to the clock entry. -- phys : A list of phandles + phy-specifiers, one for each - entry in phy-names. -- phy-names : Should contain: - * "sata-phy" for the SATA 6.0Gbps PHY - -Optional properties: -- dma-coherent : Present if dma operations are coherent -- status : Shall be "ok" if enabled or "disabled" if disabled. - Default is "ok". - -Example: - sataclk: sataclk { - compatible = "fixed-clock"; - #clock-cells = <1>; - clock-frequency = <100000000>; - clock-output-names = "sataclk"; - }; - - phy2: phy@1f22a000 { - compatible = "apm,xgene-phy"; - reg = <0x0 0x1f22a000 0x0 0x100>; - #phy-cells = <1>; - }; - - phy3: phy@1f23a000 { - compatible = "apm,xgene-phy"; - reg = <0x0 0x1f23a000 0x0 0x100>; - #phy-cells = <1>; - }; - - sata2: sata@1a400000 { - compatible = "apm,xgene-ahci"; - reg = <0x0 0x1a400000 0x0 0x1000>, - <0x0 0x1f220000 0x0 0x1000>, - <0x0 0x1f22d000 0x0 0x1000>, - <0x0 0x1f22e000 0x0 0x1000>, - <0x0 0x1f227000 0x0 0x1000>; - interrupts = <0x0 0x87 0x4>; - dma-coherent; - clocks = <&sataclk 0>; - phys = <&phy2 0>; - phy-names = "sata-phy"; - }; - - sata3: sata@1a800000 { - compatible = "apm,xgene-ahci-pcie"; - reg = <0x0 0x1a800000 0x0 0x1000>, - <0x0 0x1f230000 0x0 0x1000>, - <0x0 0x1f23d000 0x0 0x1000>, - <0x0 0x1f23e000 0x0 0x1000>, - <0x0 0x1f237000 0x0 0x1000>; - interrupts = <0x0 0x88 0x4>; - dma-coherent; - clocks = <&sataclk 0>; - phys = <&phy3 0>; - phy-names = "sata-phy"; - }; diff --git a/Documentation/devicetree/bindings/ata/arasan,cf-spear1340.yaml b/Documentation/devicetree/bindings/ata/arasan,cf-spear1340.yaml new file mode 100644 index 000000000000..4d7017452dda --- /dev/null +++ b/Documentation/devicetree/bindings/ata/arasan,cf-spear1340.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ata/arasan,cf-spear1340.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Arasan PATA Compact Flash Controller + +maintainers: + - Viresh Kumar <viresh.kumar@linaro.org> + +properties: + compatible: + const: arasan,cf-spear1340 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + arasan,broken-udma: + description: UDMA mode is unusable + type: boolean + + arasan,broken-mwdma: + description: MWDMA mode is unusable + type: boolean + + arasan,broken-pio: + description: PIO mode is unusable + type: boolean + + dmas: + maxItems: 1 + + dma-names: + items: + - const: data + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +allOf: + - if: + not: + required: + - arasan,broken-udma + - arasan,broken-mwdma + then: + required: + - dmas + - dma-names + +examples: + - | + cf@fc000000 { + compatible = "arasan,cf-spear1340"; + reg = <0xfc000000 0x1000>; + interrupts = <12>; + dmas = <&dma 23>; + dma-names = "data"; + }; diff --git a/Documentation/devicetree/bindings/ata/cavium,ebt3000-compact-flash.yaml b/Documentation/devicetree/bindings/ata/cavium,ebt3000-compact-flash.yaml new file mode 100644 index 000000000000..349f289b81e6 --- /dev/null +++ b/Documentation/devicetree/bindings/ata/cavium,ebt3000-compact-flash.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ata/cavium,ebt3000-compact-flash.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cavium Compact Flash + +maintainers: + - Rob Herring <robh@kernel.org> + +description: + The Cavium Compact Flash device is connected to the Octeon Boot Bus, and is + thus a child of the Boot Bus device. It can read and write industry standard + compact flash devices. + +properties: + compatible: + const: cavium,ebt3000-compact-flash + + reg: + description: The base address of the CF chip select banks. + items: + - description: CF chip select bank 0 + - description: CF chip select bank 1 + + cavium,bus-width: + description: The width of the connection to the CF devices. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [8, 16] + + cavium,true-ide: + description: True IDE mode when present. + type: boolean + + cavium,dma-engine-handle: + description: A phandle for the DMA Engine connected to this device. + $ref: /schemas/types.yaml#/definitions/phandle + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + bus { + #address-cells = <2>; + #size-cells = <1>; + + compact-flash@5,0 { + compatible = "cavium,ebt3000-compact-flash"; + reg = <5 0 0x10000>, <6 0 0x10000>; + cavium,bus-width = <16>; + cavium,true-ide; + cavium,dma-engine-handle = <&dma0>; + }; + }; diff --git a/Documentation/devicetree/bindings/ata/cavium-compact-flash.txt b/Documentation/devicetree/bindings/ata/cavium-compact-flash.txt deleted file mode 100644 index 3bacc8e0931e..000000000000 --- a/Documentation/devicetree/bindings/ata/cavium-compact-flash.txt +++ /dev/null @@ -1,30 +0,0 @@ -* Compact Flash - -The Cavium Compact Flash device is connected to the Octeon Boot Bus, -and is thus a child of the Boot Bus device. It can read and write -industry standard compact flash devices. - -Properties: -- compatible: "cavium,ebt3000-compact-flash"; - - Compatibility with many Cavium evaluation boards. - -- reg: The base address of the CF chip select banks. Depending on - the device configuration, there may be one or two banks. - -- cavium,bus-width: The width of the connection to the CF devices. Valid - values are 8 and 16. - -- cavium,true-ide: Optional, if present the CF connection is in True IDE mode. - -- cavium,dma-engine-handle: Optional, a phandle for the DMA Engine connected - to this device. - -Example: - compact-flash@5,0 { - compatible = "cavium,ebt3000-compact-flash"; - reg = <5 0 0x10000>, <6 0 0x10000>; - cavium,bus-width = <16>; - cavium,true-ide; - cavium,dma-engine-handle = <&dma0>; - }; diff --git a/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml b/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml index 9952e0ef7767..c92341888a28 100644 --- a/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml +++ b/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml @@ -7,7 +7,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Ceva AHCI SATA Controller maintainers: - - Mubin Sayyed <mubin.sayyed@amd.com> - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> description: | @@ -163,11 +162,9 @@ additionalProperties: false examples: - | - #include <dt-bindings/clock/xlnx-zynqmp-clk.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/power/xlnx-zynqmp-power.h> #include <dt-bindings/reset/xlnx-zynqmp-resets.h> - #include <dt-bindings/clock/xlnx-zynqmp-clk.h> #include <dt-bindings/phy/phy.h> sata: ahci@fd0c0000 { @@ -175,7 +172,7 @@ examples: reg = <0xfd0c0000 0x200>; interrupt-parent = <&gic>; interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&zynqmp_clk SATA_REF>; + clocks = <&zynqmp_clk 22>; ceva,p0-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>; ceva,p0-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>; ceva,p0-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>; diff --git a/Documentation/devicetree/bindings/ata/fsl,pq-sata.yaml b/Documentation/devicetree/bindings/ata/fsl,pq-sata.yaml new file mode 100644 index 000000000000..1d19ee832f0c --- /dev/null +++ b/Documentation/devicetree/bindings/ata/fsl,pq-sata.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ata/fsl,pq-sata.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale 8xxx/3.0 Gb/s SATA nodes + +maintainers: + - J. Neuschäfer <j.ne@posteo.net> + +description: + SATA nodes are defined to describe on-chip Serial ATA controllers. + Each SATA controller should have its own node. + +properties: + compatible: + oneOf: + - items: + - enum: + - fsl,mpc8377-sata + - fsl,mpc8536-sata + - fsl,mpc8315-sata + - fsl,mpc8379-sata + - const: fsl,pq-sata + - const: fsl,pq-sata-v2 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + cell-index: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2, 3, 4] + description: | + 1 for controller @ 0x18000 + 2 for controller @ 0x19000 + 3 for controller @ 0x1a000 + 4 for controller @ 0x1b000 + +required: + - compatible + - interrupts + - cell-index + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + sata@18000 { + compatible = "fsl,mpc8379-sata", "fsl,pq-sata"; + reg = <0x18000 0x1000>; + cell-index = <1>; + interrupts = <44 IRQ_TYPE_LEVEL_LOW>; + }; + +... diff --git a/Documentation/devicetree/bindings/ata/fsl-sata.txt b/Documentation/devicetree/bindings/ata/fsl-sata.txt deleted file mode 100644 index fd63bb3becc9..000000000000 --- a/Documentation/devicetree/bindings/ata/fsl-sata.txt +++ /dev/null @@ -1,28 +0,0 @@ -* Freescale 8xxx/3.0 Gb/s SATA nodes - -SATA nodes are defined to describe on-chip Serial ATA controllers. -Each SATA port should have its own node. - -Required properties: -- compatible : compatible list, contains 2 entries, first is - "fsl,CHIP-sata", where CHIP is the processor - (mpc8315, mpc8379, etc.) and the second is - "fsl,pq-sata" -- interrupts : <interrupt mapping for SATA IRQ> -- cell-index : controller index. - 1 for controller @ 0x18000 - 2 for controller @ 0x19000 - 3 for controller @ 0x1a000 - 4 for controller @ 0x1b000 - -Optional properties: -- reg : <registers mapping> - -Example: - sata@18000 { - compatible = "fsl,mpc8379-sata", "fsl,pq-sata"; - reg = <0x18000 0x1000>; - cell-index = <1>; - interrupts = <2c 8>; - interrupt-parent = < &ipic >; - }; diff --git a/Documentation/devicetree/bindings/ata/marvell,orion-sata.yaml b/Documentation/devicetree/bindings/ata/marvell,orion-sata.yaml new file mode 100644 index 000000000000..f656ea9223d6 --- /dev/null +++ b/Documentation/devicetree/bindings/ata/marvell,orion-sata.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ata/marvell,orion-sata.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Orion SATA + +maintainers: + - Andrew Lunn <andrew@lunn.ch> + - Gregory Clement <gregory.clement@bootlin.com> + +allOf: + - $ref: sata-common.yaml# + +properties: + compatible: + enum: + - marvell,orion-sata + - marvell,armada-370-sata + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 8 + + clock-names: + minItems: 1 + items: + - const: '0' + - const: '1' + - const: '2' + - const: '3' + - const: '4' + - const: '5' + - const: '6' + - const: '7' + + interrupts: + maxItems: 1 + + nr-ports: + description: + Number of SATA ports in use. + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 8 + + phys: + minItems: 1 + maxItems: 8 + + phy-names: + minItems: 1 + items: + - const: port0 + - const: port1 + - const: port2 + - const: port3 + - const: port4 + - const: port5 + - const: port6 + - const: port7 + +required: + - compatible + - reg + - interrupts + - nr-ports + +unevaluatedProperties: false + +examples: + - | + sata@80000 { + compatible = "marvell,orion-sata"; + reg = <0x80000 0x5000>; + interrupts = <21>; + phys = <&sata_phy0>, <&sata_phy1>; + phy-names = "port0", "port1"; + nr-ports = <2>; + }; diff --git a/Documentation/devicetree/bindings/ata/marvell.txt b/Documentation/devicetree/bindings/ata/marvell.txt deleted file mode 100644 index b460edd12766..000000000000 --- a/Documentation/devicetree/bindings/ata/marvell.txt +++ /dev/null @@ -1,22 +0,0 @@ -* Marvell Orion SATA - -Required Properties: -- compatibility : "marvell,orion-sata" or "marvell,armada-370-sata" -- reg : Address range of controller -- interrupts : Interrupt controller is using -- nr-ports : Number of SATA ports in use. - -Optional Properties: -- phys : List of phandles to sata phys -- phy-names : Should be "0", "1", etc, one number per phandle - -Example: - - sata@80000 { - compatible = "marvell,orion-sata"; - reg = <0x80000 0x5000>; - interrupts = <21>; - phys = <&sata_phy0>, <&sata_phy1>; - phy-names = "0", "1"; - nr-ports = <2>; - } diff --git a/Documentation/devicetree/bindings/ata/pata-arasan.txt b/Documentation/devicetree/bindings/ata/pata-arasan.txt deleted file mode 100644 index 872edc105680..000000000000 --- a/Documentation/devicetree/bindings/ata/pata-arasan.txt +++ /dev/null @@ -1,37 +0,0 @@ -* ARASAN PATA COMPACT FLASH CONTROLLER - -Required properties: -- compatible: "arasan,cf-spear1340" -- reg: Address range of the CF registers -- interrupt: Should contain the CF interrupt number -- clock-frequency: Interface clock rate, in Hz, one of - 25000000 - 33000000 - 40000000 - 50000000 - 66000000 - 75000000 - 100000000 - 125000000 - 150000000 - 166000000 - 200000000 - -Optional properties: -- arasan,broken-udma: if present, UDMA mode is unusable -- arasan,broken-mwdma: if present, MWDMA mode is unusable -- arasan,broken-pio: if present, PIO mode is unusable -- dmas: one DMA channel, as described in bindings/dma/dma.txt - required unless both UDMA and MWDMA mode are broken -- dma-names: the corresponding channel name, must be "data" - -Example: - - cf@fc000000 { - compatible = "arasan,cf-spear1340"; - reg = <0xfc000000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <12>; - dmas = <&dma-controller 23>; - dma-names = "data"; - }; diff --git a/Documentation/devicetree/bindings/ata/rockchip,dwc-ahci.yaml b/Documentation/devicetree/bindings/ata/rockchip,dwc-ahci.yaml index 13eaa8d9a16e..b5ecaabfe2e2 100644 --- a/Documentation/devicetree/bindings/ata/rockchip,dwc-ahci.yaml +++ b/Documentation/devicetree/bindings/ata/rockchip,dwc-ahci.yaml @@ -20,6 +20,7 @@ select: contains: enum: - rockchip,rk3568-dwc-ahci + - rockchip,rk3576-dwc-ahci - rockchip,rk3588-dwc-ahci required: - compatible @@ -29,6 +30,7 @@ properties: items: - enum: - rockchip,rk3568-dwc-ahci + - rockchip,rk3576-dwc-ahci - rockchip,rk3588-dwc-ahci - const: snps,dwc-ahci @@ -83,6 +85,7 @@ allOf: contains: enum: - rockchip,rk3568-dwc-ahci + - rockchip,rk3576-dwc-ahci then: properties: clocks: diff --git a/Documentation/devicetree/bindings/ata/st,ahci.yaml b/Documentation/devicetree/bindings/ata/st,ahci.yaml new file mode 100644 index 000000000000..6e8e4b4f3d6c --- /dev/null +++ b/Documentation/devicetree/bindings/ata/st,ahci.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ata/st,ahci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STi SATA controller + +maintainers: + - Patrice Chotard <patrice.chotard@foss.st.com> + +allOf: + - $ref: ahci-common.yaml# + +properties: + compatible: + const: st,ahci + + interrupt-names: + items: + - const: hostc + + clocks: + maxItems: 1 + + clock-names: + items: + - const: ahci_clk + + resets: + items: + - description: Power-down line + - description: Soft-reset line + - description: Power-reset line + + reset-names: + items: + - const: pwr-dwn + - const: sw-rst + - const: pwr-rst + +required: + - compatible + - interrupt-names + - phys + - phy-names + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/phy/phy.h> + #include <dt-bindings/reset/stih407-resets.h> + #include <dt-bindings/clock/stih407-clks.h> + + sata@9b20000 { + compatible = "st,ahci"; + reg = <0x9b20000 0x1000>; + interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>; + interrupt-names = "hostc"; + phys = <&phy_port0 PHY_TYPE_SATA>; + phy-names = "sata-phy"; + resets = <&powerdown STIH407_SATA0_POWERDOWN>, + <&softreset STIH407_SATA0_SOFTRESET>, + <&softreset STIH407_SATA0_PWR_SOFTRESET>; + reset-names = "pwr-dwn", "sw-rst", "pwr-rst"; + clocks = <&clk_s_c0_flexgen CLK_ICN_REG>; + clock-names = "ahci_clk"; + }; diff --git a/Documentation/devicetree/bindings/ata/ti,dm816-ahci.yaml b/Documentation/devicetree/bindings/ata/ti,dm816-ahci.yaml new file mode 100644 index 000000000000..d0ff9e78afe6 --- /dev/null +++ b/Documentation/devicetree/bindings/ata/ti,dm816-ahci.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ata/ti,dm816-ahci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI DM816 AHCI SATA Controller + +maintainers: + - Bartosz Golaszewski <brgl@bgdev.pl> + +allOf: + - $ref: ahci-common.yaml# + +properties: + compatible: + const: ti,dm816-ahci + + reg: + maxItems: 1 + + clocks: + items: + - description: functional clock + - description: external reference clock + + ti,hwmods: + const: sata + +required: + - compatible + - clocks + +unevaluatedProperties: false + +examples: + - | + sata@4a140000 { + compatible = "ti,dm816-ahci"; + reg = <0x4a140000 0x10000>; + interrupts = <16>; + clocks = <&sysclk5_ck>, <&sata_refclk>; + }; diff --git a/Documentation/devicetree/bindings/bus/microsoft,vmbus.yaml b/Documentation/devicetree/bindings/bus/microsoft,vmbus.yaml index a8d40c766dcd..0bea4f5287ce 100644 --- a/Documentation/devicetree/bindings/bus/microsoft,vmbus.yaml +++ b/Documentation/devicetree/bindings/bus/microsoft,vmbus.yaml @@ -10,8 +10,8 @@ maintainers: - Saurabh Sengar <ssengar@linux.microsoft.com> description: - VMBus is a software bus that implement the protocols for communication - between the root or host OS and guest OSs (virtual machines). + VMBus is a software bus that implements the protocols for communication + between the root or host OS and guest OS'es (virtual machines). properties: compatible: @@ -25,9 +25,16 @@ properties: '#size-cells': const: 1 + dma-coherent: true + + interrupts: + maxItems: 1 + description: Interrupt is used to report a message from the host. + required: - compatible - ranges + - interrupts - '#address-cells' - '#size-cells' @@ -35,6 +42,8 @@ additionalProperties: false examples: - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> soc { #address-cells = <2>; #size-cells = <1>; @@ -49,6 +58,9 @@ examples: #address-cells = <2>; #size-cells = <1>; ranges = <0x0f 0xf0000000 0x0f 0xf0000000 0x10000000>; + dma-coherent; + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 2 IRQ_TYPE_EDGE_RISING>; }; }; }; diff --git a/Documentation/devicetree/bindings/bus/nvidia,tegra210-aconnect.yaml b/Documentation/devicetree/bindings/bus/nvidia,tegra210-aconnect.yaml index 26362c9006e2..81a65e9f93f1 100644 --- a/Documentation/devicetree/bindings/bus/nvidia,tegra210-aconnect.yaml +++ b/Documentation/devicetree/bindings/bus/nvidia,tegra210-aconnect.yaml @@ -21,6 +21,7 @@ properties: - const: nvidia,tegra210-aconnect - items: - enum: + - nvidia,tegra264-aconnect - nvidia,tegra234-aconnect - nvidia,tegra186-aconnect - nvidia,tegra194-aconnect diff --git a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml index d2cbe49f4e15..4de5bb2e5f24 100644 --- a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml +++ b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml @@ -28,6 +28,9 @@ select: properties: compatible: items: + - enum: + - andestech,qilai-ax45mp-cache + - renesas,r9a07g043f-ax45mp-cache - const: andestech,ax45mp-cache - const: cache @@ -65,12 +68,27 @@ required: - cache-size - cache-unified +allOf: + - if: + properties: + compatible: + contains: + const: andestech,qilai-ax45mp-cache + + then: + properties: + cache-sets: + const: 2048 + cache-size: + const: 2097152 + examples: - | #include <dt-bindings/interrupt-controller/irq.h> cache-controller@13400000 { - compatible = "andestech,ax45mp-cache", "cache"; + compatible = "renesas,r9a07g043f-ax45mp-cache", "andestech,ax45mp-cache", + "cache"; reg = <0x13400000 0x100000>; interrupts = <508 IRQ_TYPE_LEVEL_HIGH>; cache-line-size = <64>; diff --git a/Documentation/devicetree/bindings/cache/marvell,feroceon-cache.txt b/Documentation/devicetree/bindings/cache/marvell,feroceon-cache.txt deleted file mode 100644 index 0d244b999d10..000000000000 --- a/Documentation/devicetree/bindings/cache/marvell,feroceon-cache.txt +++ /dev/null @@ -1,16 +0,0 @@ -* Marvell Feroceon Cache - -Required properties: -- compatible : Should be either "marvell,feroceon-cache" or - "marvell,kirkwood-cache". - -Optional properties: -- reg : Address of the L2 cache control register. Mandatory for - "marvell,kirkwood-cache", not used by "marvell,feroceon-cache" - - -Example: - l2: l2-cache@20128 { - compatible = "marvell,kirkwood-cache"; - reg = <0x20128 0x4>; - }; diff --git a/Documentation/devicetree/bindings/cache/marvell,kirkwood-cache.yaml b/Documentation/devicetree/bindings/cache/marvell,kirkwood-cache.yaml new file mode 100644 index 000000000000..2bfa3c29f6a6 --- /dev/null +++ b/Documentation/devicetree/bindings/cache/marvell,kirkwood-cache.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/cache/marvell,kirkwood-cache.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Feroceon/Kirkwood Cache + +maintainers: + - Andrew Lunn <andrew@lunn.ch> + - Gregory Clement <gregory.clement@bootlin.com> + +properties: + compatible: + enum: + - marvell,feroceon-cache + - marvell,kirkwood-cache + + reg: + maxItems: 1 + +allOf: + - if: + properties: + compatible: + contains: + const: marvell,kirkwood-cache + then: + required: + - reg + else: + properties: + reg: false + +required: + - compatible + +additionalProperties: false + +examples: + - | + l2-cache@20128 { + compatible = "marvell,kirkwood-cache"; + reg = <0x20128 0x4>; + }; diff --git a/Documentation/devicetree/bindings/cache/marvell,tauros2-cache.txt b/Documentation/devicetree/bindings/cache/marvell,tauros2-cache.txt deleted file mode 100644 index 31af1cbb60bd..000000000000 --- a/Documentation/devicetree/bindings/cache/marvell,tauros2-cache.txt +++ /dev/null @@ -1,17 +0,0 @@ -* Marvell Tauros2 Cache - -Required properties: -- compatible : Should be "marvell,tauros2-cache". -- marvell,tauros2-cache-features : Specify the features supported for the - tauros2 cache. - The features including - CACHE_TAUROS2_PREFETCH_ON (1 << 0) - CACHE_TAUROS2_LINEFILL_BURST8 (1 << 1) - The definition can be found at - arch/arm/include/asm/hardware/cache-tauros2.h - -Example: - L2: l2-cache { - compatible = "marvell,tauros2-cache"; - marvell,tauros2-cache-features = <0x3>; - }; diff --git a/Documentation/devicetree/bindings/cache/marvell,tauros2-cache.yaml b/Documentation/devicetree/bindings/cache/marvell,tauros2-cache.yaml new file mode 100644 index 000000000000..9f7f0d031631 --- /dev/null +++ b/Documentation/devicetree/bindings/cache/marvell,tauros2-cache.yaml @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/cache/marvell,tauros2-cache.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Tauros2 Cache + +maintainers: + - Andrew Lunn <andrew@lunn.ch> + - Gregory Clement <gregory.clement@bootlin.com> + +properties: + compatible: + const: marvell,tauros2-cache + + marvell,tauros2-cache-features: + description: > + Specify the features supported for the tauros2 cache. The features include: + + - CACHE_TAUROS2_PREFETCH_ON (1 << 0) + - CACHE_TAUROS2_LINEFILL_BURST8 (1 << 1) + + The definition can be found at arch/arm/include/asm/hardware/cache-tauros2.h + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 0x3 + +required: + - compatible + - marvell,tauros2-cache-features + +additionalProperties: false + +examples: + - | + l2-cache { + compatible = "marvell,tauros2-cache"; + marvell,tauros2-cache-features = <0x3>; + }; diff --git a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml index e5effbb4a606..37e3ebd55487 100644 --- a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml @@ -40,6 +40,7 @@ properties: - qcom,sm8450-llcc - qcom,sm8550-llcc - qcom,sm8650-llcc + - qcom,sm8750-llcc - qcom,x1e80100-llcc reg: @@ -274,6 +275,7 @@ allOf: - qcom,sm8450-llcc - qcom,sm8550-llcc - qcom,sm8650-llcc + - qcom,sm8750-llcc then: properties: reg: diff --git a/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml b/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml index 7e8cebe21584..579bacb66f34 100644 --- a/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml +++ b/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml @@ -39,6 +39,7 @@ properties: - const: cache - items: - enum: + - eswin,eic7700-l3-cache - starfive,jh7100-ccache - starfive,jh7110-ccache - const: sifive,ccache0 @@ -55,10 +56,10 @@ properties: enum: [2, 3] cache-sets: - enum: [1024, 2048] + enum: [1024, 2048, 4096] cache-size: - const: 2097152 + enum: [2097152, 4194304] cache-unified: true @@ -89,6 +90,7 @@ allOf: compatible: contains: enum: + - eswin,eic7700-l3-cache - sifive,fu740-c000-ccache - starfive,jh7100-ccache - starfive,jh7110-ccache @@ -112,6 +114,22 @@ allOf: properties: compatible: contains: + const: eswin,eic7700-l3-cache + + then: + properties: + cache-size: + const: 4194304 + + else: + properties: + cache-size: + const: 2097152 + + - if: + properties: + compatible: + contains: enum: - sifive,fu740-c000-ccache - starfive,jh7100-ccache @@ -122,7 +140,15 @@ allOf: cache-sets: const: 2048 - else: + - if: + properties: + compatible: + contains: + enum: + - microchip,mpfs-ccache + - sifive,fu540-c000-ccache + + then: properties: cache-sets: const: 1024 @@ -131,6 +157,18 @@ allOf: properties: compatible: contains: + enum: + - eswin,eic7700-l3-cache + + then: + properties: + cache-sets: + const: 4096 + + - if: + properties: + compatible: + contains: const: sifive,ccache0 then: diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun55i-a523-ccu.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun55i-a523-ccu.yaml new file mode 100644 index 000000000000..f5f62e9a10a1 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun55i-a523-ccu.yaml @@ -0,0 +1,103 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun55i-a523-ccu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A523 Clock Control Unit + +maintainers: + - Andre Przywara <andre.przywara@arm.com> + +properties: + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + + compatible: + enum: + - allwinner,sun55i-a523-ccu + - allwinner,sun55i-a523-r-ccu + + reg: + maxItems: 1 + + clocks: + minItems: 4 + maxItems: 5 + + clock-names: + minItems: 4 + maxItems: 5 + +required: + - "#clock-cells" + - "#reset-cells" + - compatible + - reg + - clocks + - clock-names + +allOf: + - if: + properties: + compatible: + enum: + - allwinner,sun55i-a523-ccu + + then: + properties: + clocks: + items: + - description: High Frequency Oscillator (usually at 24MHz) + - description: Low Frequency Oscillator (usually at 32kHz) + - description: Internal Oscillator + - description: Low Frequency Oscillator fanout + + clock-names: + items: + - const: hosc + - const: losc + - const: iosc + - const: losc-fanout + + - if: + properties: + compatible: + enum: + - allwinner,sun55i-a523-r-ccu + + then: + properties: + clocks: + items: + - description: High Frequency Oscillator (usually at 24MHz) + - description: Low Frequency Oscillator (usually at 32kHz) + - description: Internal Oscillator + - description: Peripherals PLL + - description: Audio PLL + + clock-names: + items: + - const: hosc + - const: losc + - const: iosc + - const: pll-periph + - const: pll-audio + +additionalProperties: false + +examples: + - | + clock-controller@2001000 { + compatible = "allwinner,sun55i-a523-ccu"; + reg = <0x02001000 0x1000>; + clocks = <&osc24M>, <&osc32k>, <&iosc>, <&r_ccu 1>; + clock-names = "hosc", "losc", "iosc", "losc-fanout"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml index 70369bd633e4..7fcd55d468d4 100644 --- a/Documentation/devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml +++ b/Documentation/devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml @@ -25,6 +25,7 @@ properties: - const: allwinner,sun50i-a64-de2-clk - const: allwinner,sun50i-h5-de2-clk - const: allwinner,sun50i-h6-de3-clk + - const: allwinner,sun50i-h616-de33-clk - items: - const: allwinner,sun8i-r40-de2-clk - const: allwinner,sun8i-h3-de2-clk diff --git a/Documentation/devicetree/bindings/clock/altr_socfpga.txt b/Documentation/devicetree/bindings/clock/altr_socfpga.txt deleted file mode 100644 index f72e80e0dade..000000000000 --- a/Documentation/devicetree/bindings/clock/altr_socfpga.txt +++ /dev/null @@ -1,30 +0,0 @@ -Device Tree Clock bindings for Altera's SoCFPGA platform - -This binding uses the common clock binding[1]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible : shall be one of the following: - "altr,socfpga-pll-clock" - for a PLL clock - "altr,socfpga-perip-clock" - The peripheral clock divided from the - PLL clock. - "altr,socfpga-gate-clk" - Clocks that directly feed peripherals and - can get gated. - -- reg : shall be the control register offset from CLOCK_MANAGER's base for the clock. -- clocks : shall be the input parent clock phandle for the clock. This is - either an oscillator or a pll output. -- #clock-cells : from common clock binding, shall be set to 0. - -Optional properties: -- fixed-divider : If clocks have a fixed divider value, use this property. -- clk-gate : For "socfpga-gate-clk", clk-gate contains the gating register - and the bit index. -- div-reg : For "socfpga-gate-clk" and "socfpga-periph-clock", div-reg contains - the divider register, bit shift, and width. -- clk-phase : For the sdmmc_clk, contains the value of the clock phase that controls - the SDMMC CIU clock. The first value is the clk_sample(smpsel), and the second - value is the cclk_in_drv(drvsel). The clk-phase is used to enable the correct - hold/delay times that is needed for the SD/MMC CIU clock. The values of both - can be 0-315 degrees, in 45 degree increments. diff --git a/Documentation/devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml b/Documentation/devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml index 885d47dd5724..e803a1fc3681 100644 --- a/Documentation/devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml +++ b/Documentation/devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml @@ -34,6 +34,8 @@ properties: - enum: - atmel,at91rm9200-pmc - atmel,at91sam9260-pmc + - atmel,at91sam9261-pmc + - atmel,at91sam9263-pmc - atmel,at91sam9g45-pmc - atmel,at91sam9n12-pmc - atmel,at91sam9rl-pmc @@ -111,6 +113,8 @@ allOf: enum: - atmel,at91rm9200-pmc - atmel,at91sam9260-pmc + - atmel,at91sam9261-pmc + - atmel,at91sam9263-pmc - atmel,at91sam9g20-pmc then: properties: diff --git a/Documentation/devicetree/bindings/clock/brcm,bcm2835-aux-clock.txt b/Documentation/devicetree/bindings/clock/brcm,bcm2835-aux-clock.txt deleted file mode 100644 index 4acfc8f641b6..000000000000 --- a/Documentation/devicetree/bindings/clock/brcm,bcm2835-aux-clock.txt +++ /dev/null @@ -1,31 +0,0 @@ -Broadcom BCM2835 auxiliary peripheral support - -This binding uses the common clock binding: - Documentation/devicetree/bindings/clock/clock-bindings.txt - -The auxiliary peripherals (UART, SPI1, and SPI2) have a small register -area controlling clock gating to the peripherals, and providing an IRQ -status register. - -Required properties: -- compatible: Should be "brcm,bcm2835-aux" -- #clock-cells: Should be <1>. The permitted clock-specifier values can be - found in include/dt-bindings/clock/bcm2835-aux.h -- reg: Specifies base physical address and size of the registers -- clocks: The parent clock phandle - -Example: - - clocks: cprman@7e101000 { - compatible = "brcm,bcm2835-cprman"; - #clock-cells = <1>; - reg = <0x7e101000 0x2000>; - clocks = <&clk_osc>; - }; - - aux: aux@7e215004 { - compatible = "brcm,bcm2835-aux"; - #clock-cells = <1>; - reg = <0x7e215000 0x8>; - clocks = <&clocks BCM2835_CLOCK_VPU>; - }; diff --git a/Documentation/devicetree/bindings/clock/brcm,bcm2835-aux-clock.yaml b/Documentation/devicetree/bindings/clock/brcm,bcm2835-aux-clock.yaml new file mode 100644 index 000000000000..0f4050ffa41c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/brcm,bcm2835-aux-clock.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/brcm,bcm2835-aux-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom BCM2835 auxiliary peripheral clock + +maintainers: + - Stefan Wahren <wahrenst@gmx.net> + - Raspberry Pi Kernel Maintenance <kernel-list@raspberrypi.com> + +description: + The auxiliary peripherals (UART, SPI1, and SPI2) have a small register + area controlling clock gating to the peripherals, and providing an IRQ + status register. + +properties: + compatible: + const: brcm,bcm2835-aux + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - "#clock-cells" + - clocks + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/bcm2835.h> + clock@7e215000 { + compatible = "brcm,bcm2835-aux"; + reg = <0x7e215000 0x8>; + #clock-cells = <1>; + clocks = <&clocks BCM2835_CLOCK_VPU>; + }; diff --git a/Documentation/devicetree/bindings/clock/fsl,vf610-ccm.yaml b/Documentation/devicetree/bindings/clock/fsl,vf610-ccm.yaml new file mode 100644 index 000000000000..29ae5be51acf --- /dev/null +++ b/Documentation/devicetree/bindings/clock/fsl,vf610-ccm.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/fsl,vf610-ccm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Clock for Freescale Vybrid VF610 SOC + +description: + The clock consumer should specify the desired clock by having the clock + ID in its "clocks" phandle cell. See include/dt-bindings/clock/vf610-clock.h + for the full list of VF610 clock IDs + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +properties: + compatible: + const: fsl,vf610-ccm + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + clocks: + items: + - description: external crystal oscillator 32KHz, recommended + - description: external crystal oscillator 24MHz, recommended + - description: audio + - description: enet + minItems: 2 + + clock-names: + items: + - const: sxosc + - const: fxosc + - const: enet_ext + - const: audio_ext + minItems: 2 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + clock-controller@4006b000 { + compatible = "fsl,vf610-ccm"; + reg = <0x4006b000 0x1000>; + #clock-cells = <1>; + clocks = <&sxosc>, <&fxosc>; + clock-names = "sxosc", "fxosc"; + }; + diff --git a/Documentation/devicetree/bindings/clock/imx8m-clock.yaml b/Documentation/devicetree/bindings/clock/imx8m-clock.yaml index c643d4a81478..4fec55832702 100644 --- a/Documentation/devicetree/bindings/clock/imx8m-clock.yaml +++ b/Documentation/devicetree/bindings/clock/imx8m-clock.yaml @@ -43,6 +43,13 @@ properties: ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8m-clock.h for the full list of i.MX8M clock IDs. + fsl,operating-mode: + $ref: /schemas/types.yaml#/definitions/string + enum: [nominal, overdrive] + description: + The operating mode of the SoC. This affects the maximum clock rates that + can safely be configured by the clock controller. + required: - compatible - reg @@ -109,6 +116,7 @@ examples: <&clk_ext3>, <&clk_ext4>; clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", "clk_ext3", "clk_ext4"; + fsl,operating-mode = "nominal"; }; - | diff --git a/Documentation/devicetree/bindings/clock/imx8mp-audiomix.yaml b/Documentation/devicetree/bindings/clock/imx8mp-audiomix.yaml index 6588a17a7d9a..0272c9527037 100644 --- a/Documentation/devicetree/bindings/clock/imx8mp-audiomix.yaml +++ b/Documentation/devicetree/bindings/clock/imx8mp-audiomix.yaml @@ -24,8 +24,8 @@ properties: maxItems: 1 clocks: - minItems: 7 - maxItems: 7 + minItems: 8 + maxItems: 8 clock-names: items: @@ -36,6 +36,7 @@ properties: - const: sai5 - const: sai6 - const: sai7 + - const: axi '#clock-cells': const: 1 @@ -72,10 +73,11 @@ examples: <&clk IMX8MP_CLK_SAI3>, <&clk IMX8MP_CLK_SAI5>, <&clk IMX8MP_CLK_SAI6>, - <&clk IMX8MP_CLK_SAI7>; + <&clk IMX8MP_CLK_SAI7>, + <&clk IMX8MP_CLK_AUDIO_AXI_ROOT>; clock-names = "ahb", "sai1", "sai2", "sai3", - "sai5", "sai6", "sai7"; + "sai5", "sai6", "sai7", "axi"; power-domains = <&pgc_audio>; }; diff --git a/Documentation/devicetree/bindings/clock/maxim,max77686.txt b/Documentation/devicetree/bindings/clock/maxim,max77686.txt deleted file mode 100644 index c10849efb444..000000000000 --- a/Documentation/devicetree/bindings/clock/maxim,max77686.txt +++ /dev/null @@ -1,114 +0,0 @@ -Binding for Maxim MAX77686/MAX77802/MAX77620 32k clock generator block - -This is a part of device tree bindings of MAX77686/MAX77802/MAX77620 -multi-function device. More information can be found in MFD DT binding -doc as follows: - bindings/mfd/max77686.txt for MAX77686 and - bindings/mfd/max77802.txt for MAX77802 and - bindings/mfd/max77620.txt for MAX77620. - -The MAX77686 contains three 32.768khz clock outputs that can be controlled -(gated/ungated) over I2C. Clocks are defined as preprocessor macros in -dt-bindings/clock/maxim,max77686.h. - - -The MAX77802 contains two 32.768khz clock outputs that can be controlled -(gated/ungated) over I2C. Clocks are defined as preprocessor macros in -dt-bindings/clock/maxim,max77802.h. - -The MAX77686 contains one 32.768khz clock outputs that can be controlled -(gated/ungated) over I2C. Clocks are defined as preprocessor macros in -dt-bindings/clock/maxim,max77620.h. - -Following properties should be presend in main device node of the MFD chip. - -Required properties: - -- #clock-cells: from common clock binding; shall be set to 1. - -Optional properties: -- clock-output-names: From common clock binding. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. Following indices are allowed: - - 0: 32khz_ap clock (max77686, max77802), 32khz_out0 (max77620) - - 1: 32khz_cp clock (max77686, max77802), - - 2: 32khz_pmic clock (max77686). - -Clocks are defined as preprocessor macros in above dt-binding header for -respective chips. - -Example: - -1. With MAX77686: - -#include <dt-bindings/clock/maxim,max77686.h> -/* ... */ - - Node of the MFD chip - max77686: max77686@9 { - compatible = "maxim,max77686"; - interrupt-parent = <&wakeup_eint>; - interrupts = <26 IRQ_TYPE_LEVEL_LOW>; - reg = <0x09>; - #clock-cells = <1>; - - /* ... */ - }; - - Clock consumer node - - foo@0 { - compatible = "bar,foo"; - /* ... */ - clock-names = "my-clock"; - clocks = <&max77686 MAX77686_CLK_PMIC>; - }; - -2. With MAX77802: - -#include <dt-bindings/clock/maxim,max77802.h> -/* ... */ - - Node of the MFD chip - max77802: max77802@9 { - compatible = "maxim,max77802"; - interrupt-parent = <&wakeup_eint>; - interrupts = <26 IRQ_TYPE_LEVEL_LOW>; - reg = <0x09>; - #clock-cells = <1>; - - /* ... */ - }; - - Clock consumer node - - foo@0 { - compatible = "bar,foo"; - /* ... */ - clock-names = "my-clock"; - clocks = <&max77802 MAX77802_CLK_32K_AP>; - }; - - -3. With MAX77620: - -#include <dt-bindings/clock/maxim,max77620.h> -/* ... */ - - Node of the MFD chip - max77620: max77620@3c { - compatible = "maxim,max77620"; - reg = <0x3c>; - #clock-cells = <1>; - /* ... */ - }; - - Clock consumer node - - foo@0 { - compatible = "bar,foo"; - /* ... */ - clock-names = "my-clock"; - clocks = <&max77620 MAX77620_CLK_32K_OUT0>; - }; diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml index 860570320545..5403242545ab 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml @@ -52,11 +52,35 @@ properties: '#clock-cells': const: 1 + '#reset-cells': + const: 1 + required: - compatible - reg - '#clock-cells' +allOf: + - if: + properties: + compatible: + contains: + enum: + - mediatek,mt8188-camsys-rawa + - mediatek,mt8188-camsys-rawb + - mediatek,mt8188-camsys-yuva + - mediatek,mt8188-camsys-yuvb + - mediatek,mt8188-imgsys-wpe1 + - mediatek,mt8188-imgsys-wpe2 + - mediatek,mt8188-imgsys-wpe3 + - mediatek,mt8188-imgsys1-dip-nr + - mediatek,mt8188-imgsys1-dip-top + - mediatek,mt8188-ipesys + + then: + required: + - '#reset-cells' + additionalProperties: false examples: diff --git a/Documentation/devicetree/bindings/clock/mediatek,mtmips-sysc.yaml b/Documentation/devicetree/bindings/clock/mediatek,mtmips-sysc.yaml index ba7ffc5b16a0..83c1803ffd16 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,mtmips-sysc.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,mtmips-sysc.yaml @@ -18,6 +18,12 @@ description: | These SoCs have an XTAL from where the cpu clock is provided as well as derived clocks for the bus and the peripherals. + Each clock is assigned an identifier and client nodes use this identifier + to specify the clock which they consume. + + All these identifiers could be found in: + [1]: <include/dt-bindings/clock/mediatek,mtmips-sysc.h>. + properties: compatible: items: @@ -38,7 +44,8 @@ properties: '#clock-cells': description: - The first cell indicates the clock number. + The first cell indicates the clock number, see [1] for available + clocks. const: 1 '#reset-cells': @@ -56,6 +63,8 @@ additionalProperties: false examples: - | + #include <dt-bindings/clock/mediatek,mtmips-sysc.h> + syscon@0 { compatible = "ralink,rt5350-sysc", "syscon"; reg = <0x0 0x100>; diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml new file mode 100644 index 000000000000..17252b6ea3be --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml @@ -0,0 +1,98 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,ipq9574-nsscc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Networking Sub System Clock & Reset Controller on IPQ9574 + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + - Anusha Rao <quic_anusha@quicinc.com> + +description: | + Qualcomm networking sub system clock control module provides the clocks, + resets on IPQ9574 + + See also:: + include/dt-bindings/clock/qcom,ipq9574-nsscc.h + include/dt-bindings/reset/qcom,ipq9574-nsscc.h + +properties: + compatible: + const: qcom,ipq9574-nsscc + + clocks: + items: + - description: Board XO source + - description: CMN_PLL NSS 1200MHz (Bias PLL cc) clock source + - description: CMN_PLL PPE 353MHz (Bias PLL ubi nc) clock source + - description: GCC GPLL0 OUT AUX clock source + - description: Uniphy0 NSS Rx clock source + - description: Uniphy0 NSS Tx clock source + - description: Uniphy1 NSS Rx clock source + - description: Uniphy1 NSS Tx clock source + - description: Uniphy2 NSS Rx clock source + - description: Uniphy2 NSS Tx clock source + - description: GCC NSSCC clock source + + '#interconnect-cells': + const: 1 + + clock-names: + items: + - const: xo + - const: nss_1200 + - const: ppe_353 + - const: gpll0_out + - const: uniphy0_rx + - const: uniphy0_tx + - const: uniphy1_rx + - const: uniphy1_tx + - const: uniphy2_rx + - const: uniphy2_tx + - const: bus + +required: + - compatible + - clocks + - clock-names + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,ipq9574-gcc.h> + #include <dt-bindings/clock/qcom,ipq-cmn-pll.h> + clock-controller@39b00000 { + compatible = "qcom,ipq9574-nsscc"; + reg = <0x39b00000 0x80000>; + clocks = <&xo_board_clk>, + <&cmn_pll NSS_1200MHZ_CLK>, + <&cmn_pll PPE_353MHZ_CLK>, + <&gcc GPLL0_OUT_AUX>, + <&uniphy 0>, + <&uniphy 1>, + <&uniphy 2>, + <&uniphy 3>, + <&uniphy 4>, + <&uniphy 5>, + <&gcc GCC_NSSCC_CLK>; + clock-names = "xo", + "nss_1200", + "ppe_353", + "gpll0_out", + "uniphy0_rx", + "uniphy0_tx", + "uniphy1_rx", + "uniphy1_tx", + "uniphy2_rx", + "uniphy2_tx", + "bus"; + #clock-cells = <1>; + #reset-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml b/Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml index be3835e2e043..90cd3feab5fa 100644 --- a/Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml @@ -44,6 +44,7 @@ properties: - qcom,rpmcc-msm8998 - qcom,rpmcc-qcm2290 - qcom,rpmcc-qcs404 + - qcom,rpmcc-sdm429 - qcom,rpmcc-sdm660 - qcom,rpmcc-sm6115 - qcom,rpmcc-sm6125 @@ -123,6 +124,7 @@ allOf: - qcom,rpmcc-msm8998 - qcom,rpmcc-qcm2290 - qcom,rpmcc-qcs404 + - qcom,rpmcc-sdm429 - qcom,rpmcc-sdm660 - qcom,rpmcc-sm6115 - qcom,rpmcc-sm6125 diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml index 488d63959424..99ab9106009f 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml @@ -20,6 +20,7 @@ description: | properties: compatible: enum: + - qcom,qcm6490-lpassaudiocc - qcom,sc7280-lpassaoncc - qcom,sc7280-lpassaudiocc - qcom,sc7280-lpasscorecc @@ -68,7 +69,9 @@ allOf: properties: compatible: contains: - const: qcom,sc7280-lpassaudiocc + enum: + - qcom,qcm6490-lpassaudiocc + - qcom,sc7280-lpassaudiocc then: properties: diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml index b88b6c9b399a..9e79f8fec437 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml @@ -64,7 +64,6 @@ allOf: - qcom,sc8280xp-camcc - qcom,sm8450-camcc - qcom,sm8550-camcc - - qcom,x1e80100-camcc then: required: - required-opps diff --git a/Documentation/devicetree/bindings/clock/qcom,videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,videocc.yaml index 340c7e5cf980..5f7738d6835c 100644 --- a/Documentation/devicetree/bindings/clock/qcom,videocc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,videocc.yaml @@ -14,6 +14,7 @@ description: | domains on Qualcomm SoCs. See also:: + include/dt-bindings/clock/qcom,sm6350-videocc.h include/dt-bindings/clock/qcom,videocc-sc7180.h include/dt-bindings/clock/qcom,videocc-sc7280.h include/dt-bindings/clock/qcom,videocc-sdm845.h @@ -26,6 +27,7 @@ properties: - qcom,sc7180-videocc - qcom,sc7280-videocc - qcom,sdm845-videocc + - qcom,sm6350-videocc - qcom,sm8150-videocc - qcom,sm8250-videocc @@ -91,6 +93,24 @@ allOf: properties: compatible: enum: + - qcom,sm6350-videocc + then: + properties: + clocks: + items: + - description: Video AHB clock from GCC + - description: Board XO source + - description: Sleep Clock source + clock-names: + items: + - const: iface + - const: bi_tcxo + - const: sleep_clk + + - if: + properties: + compatible: + enum: - qcom,sm8150-videocc then: properties: diff --git a/Documentation/devicetree/bindings/clock/qcom,x1e80100-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,x1e80100-camcc.yaml index 5bbbaa15a260..938a2f1ff3fc 100644 --- a/Documentation/devicetree/bindings/clock/qcom,x1e80100-camcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,x1e80100-camcc.yaml @@ -40,9 +40,9 @@ properties: - description: A phandle to the MMCX power-domain required-opps: - maxItems: 1 - description: - A phandle to an OPP node describing MMCX performance points. + items: + - description: A phandle to an OPP node describing MXC performance points + - description: A phandle to an OPP node describing MMCX performance points required: - compatible @@ -66,7 +66,8 @@ examples: <&sleep_clk>; power-domains = <&rpmhpd RPMHPD_MXC>, <&rpmhpd RPMHPD_MMCX>; - required-opps = <&rpmhpd_opp_low_svs>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; diff --git a/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml index c3fe76abd549..f261445bf341 100644 --- a/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml +++ b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml @@ -4,13 +4,13 @@ $id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Renesas RZ/{G3E,V2H(P)} Clock Pulse Generator (CPG) +title: Renesas RZ/{G3E,V2H(P),V2N} Clock Pulse Generator (CPG) maintainers: - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> description: - On Renesas RZ/{G3E,V2H(P)} SoCs, the CPG (Clock Pulse Generator) handles + On Renesas RZ/{G3E,V2H(P),V2N} SoCs, the CPG (Clock Pulse Generator) handles generation and control of clock signals for the IP modules, generation and control of resets, and control over booting, low power consumption and power supply domains. @@ -19,6 +19,7 @@ properties: compatible: enum: - renesas,r9a09g047-cpg # RZ/G3E + - renesas,r9a09g056-cpg # RZ/V2N - renesas,r9a09g057-cpg # RZ/V2H reg: diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3528-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3528-cru.yaml new file mode 100644 index 000000000000..5a3ec902351c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3528-cru.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/rockchip,rk3528-cru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip RK3528 Clock and Reset Controller + +maintainers: + - Yao Zi <ziyao@disroot.org> + +description: | + The RK3528 clock controller generates the clock and also implements a reset + controller for SoC peripherals. For example, it provides SCLK_UART0 and + PCLK_UART0 as well as SRST_P_UART0 and SRST_S_UART0 for the first UART + module. + Each clock is assigned an identifier, consumer nodes can use it to specify + the clock. All available clock and reset IDs are defined in dt-binding + headers. + +properties: + compatible: + const: rockchip,rk3528-cru + + reg: + maxItems: 1 + + clocks: + items: + - description: External 24MHz oscillator clock + - description: > + 50MHz clock generated by PHY module, for generating GMAC0 clocks only. + + clock-names: + items: + - const: xin24m + - const: gmac0 + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + clock-controller@ff4a0000 { + compatible = "rockchip,rk3528-cru"; + reg = <0xff4a0000 0x30000>; + clocks = <&xin24m>, <&gmac0_clk>; + clock-names = "xin24m", "gmac0"; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3562-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3562-cru.yaml new file mode 100644 index 000000000000..36a353f5c42a --- /dev/null +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3562-cru.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/rockchip,rk3562-cru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip rk3562 Clock and Reset Control Module + +maintainers: + - Elaine Zhang <zhangqing@rock-chips.com> + - Heiko Stuebner <heiko@sntech.de> + +description: + The RK3562 clock controller generates the clock and also implements a reset + controller for SoC peripherals. For example it provides SCLK_UART2 and + PCLK_UART2, as well as SRST_P_UART2 and SRST_S_UART2 for the second UART + module. + +properties: + compatible: + const: rockchip,rk3562-cru + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: xin24m + - const: xin32k + +required: + - compatible + - reg + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + clock-controller@ff100000 { + compatible = "rockchip,rk3562-cru"; + reg = <0xff100000 0x40000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos2200-cmu.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos2200-cmu.yaml new file mode 100644 index 000000000000..89433e6d3518 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/samsung,exynos2200-cmu.yaml @@ -0,0 +1,247 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/samsung,exynos2200-cmu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos2200 SoC clock controller + +maintainers: + - Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> + - Chanwoo Choi <cw00.choi@samsung.com> + - Krzysztof Kozlowski <krzk@kernel.org> + +description: | + Exynos2200 clock controller is comprised of several CMU units, generating + clocks for different domains. Those CMU units are modeled as separate device + tree nodes, and might depend on each other. The root clocks in that root tree + are two external clocks: XTCXO (76.8 MHz) and RTCCLK (32768 Hz). XTCXO must be + defined as a fixed-rate clock in dts, whereas RTCCLK originates from PMIC. + + CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and + dividers; all other clocks of function blocks (other CMUs) are usually + derived from CMU_TOP. + + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All clocks available for usage + in clock consumer nodes are defined as preprocessor macros in + 'include/dt-bindings/clock/samsung,exynos2200-cmu.h' header. + +properties: + compatible: + enum: + - samsung,exynos2200-cmu-alive + - samsung,exynos2200-cmu-cmgp + - samsung,exynos2200-cmu-hsi0 + - samsung,exynos2200-cmu-peric0 + - samsung,exynos2200-cmu-peric1 + - samsung,exynos2200-cmu-peric2 + - samsung,exynos2200-cmu-peris + - samsung,exynos2200-cmu-top + - samsung,exynos2200-cmu-ufs + - samsung,exynos2200-cmu-vts + + clocks: + minItems: 1 + maxItems: 6 + + clock-names: + minItems: 1 + maxItems: 6 + + "#clock-cells": + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - clocks + - clock-names + - reg + - "#clock-cells" + +allOf: + - if: + properties: + compatible: + contains: + const: samsung,exynos2200-cmu-alive + + then: + properties: + clocks: + items: + - description: External reference clock (76.8 MHz) + - description: CMU_ALIVE NOC clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: noc + + - if: + properties: + compatible: + contains: + const: samsung,exynos2200-cmu-cmgp + + then: + properties: + clocks: + items: + - description: External reference clock (76.8 MHz) + - description: CMU_CMGP NOC clock (from CMU_TOP) + - description: CMU_CMGP PERI clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: noc + - const: peri + + - if: + properties: + compatible: + contains: + const: samsung,exynos2200-cmu-hsi0 + + then: + properties: + clocks: + items: + - description: External reference clock (76.8 MHz) + - description: External RTC clock (32768 Hz) + - description: CMU_HSI0 NOC clock (from CMU_TOP) + - description: CMU_HSI0 DPGTC clock (from CMU_TOP) + - description: CMU_HSI0 DPOSC clock (from CMU_TOP) + - description: CMU_HSI0 USB32DRD clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: rtcclk + - const: noc + - const: dpgtc + - const: dposc + - const: usb + + - if: + properties: + compatible: + contains: + enum: + - samsung,exynos2200-cmu-peric0 + - samsung,exynos2200-cmu-peric1 + - samsung,exynos2200-cmu-peric2 + + then: + properties: + clocks: + items: + - description: External reference clock (76.8 MHz) + - description: CMU_PERICn NOC clock (from CMU_TOP) + - description: CMU_PERICn IP0 clock (from CMU_TOP) + - description: CMU_PERICn IP1 clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: noc + - const: ip0 + - const: ip1 + + - if: + properties: + compatible: + contains: + const: samsung,exynos2200-cmu-peris + + then: + properties: + clocks: + items: + - description: External reference clock (25.6 MHz) + - description: CMU_PERIS NOC clock (from CMU_TOP) + - description: CMU_PERIS GIC clock (from CMU_TOP) + + clock-names: + items: + - const: tcxo_div3 + - const: noc + - const: gic + + - if: + properties: + compatible: + contains: + const: samsung,exynos2200-cmu-top + + then: + properties: + clocks: + items: + - description: External reference clock (76.8 MHz) + + clock-names: + items: + - const: oscclk + + - if: + properties: + compatible: + contains: + const: samsung,exynos2200-cmu-ufs + + then: + properties: + clocks: + items: + - description: External reference clock (76.8 MHz) + - description: CMU_UFS NOC clock (from CMU_TOP) + - description: CMU_UFS MMC clock (from CMU_TOP) + - description: CMU_UFS UFS clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: noc + - const: mmc + - const: ufs + + - if: + properties: + compatible: + contains: + const: samsung,exynos2200-cmu-vts + + then: + properties: + clocks: + items: + - description: External reference clock (76.8 MHz) + - description: CMU_VTS DMIC clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dmic + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/samsung,exynos2200-cmu.h> + + cmu_vts: clock-controller@15300000 { + compatible = "samsung,exynos2200-cmu-vts"; + reg = <0x15300000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, + <&cmu_top CLK_DOUT_CMU_VTS_DMIC>; + clock-names = "oscclk", "dmic"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos7870-cmu.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos7870-cmu.yaml new file mode 100644 index 000000000000..3c58712f12b9 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/samsung,exynos7870-cmu.yaml @@ -0,0 +1,227 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/samsung,exynos7870-cmu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos7870 SoC clock controller + +maintainers: + - Kaustabh Chakraborty <kauschluss@disroot.org> + +description: | + Exynos7870 clock controller is comprised of several CMU units, generating + clocks for different domains. Those CMU units are modeled as separate device + tree nodes, and might depend on each other. The root clock in that root tree + is an external clock: OSCCLK (26 MHz). This external clock must be defined + as a fixed-rate clock in dts. + + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All clocks available for usage + in clock consumer nodes are defined as preprocessor macros in + include/dt-bindings/clock/samsung,exynos7870-cmu.h header. + +properties: + compatible: + enum: + - samsung,exynos7870-cmu-mif + - samsung,exynos7870-cmu-dispaud + - samsung,exynos7870-cmu-fsys + - samsung,exynos7870-cmu-g3d + - samsung,exynos7870-cmu-isp + - samsung,exynos7870-cmu-mfcmscl + - samsung,exynos7870-cmu-peri + + clocks: + minItems: 1 + maxItems: 10 + + clock-names: + minItems: 1 + maxItems: 10 + + "#clock-cells": + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - clocks + - clock-names + - "#clock-cells" + - reg + +allOf: + - if: + properties: + compatible: + contains: + const: samsung,exynos7870-cmu-mif + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + + clock-names: + items: + - const: oscclk + + - if: + properties: + compatible: + contains: + const: samsung,exynos7870-cmu-dispaud + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_DISPAUD bus clock (from CMU_MIF) + - description: DECON external clock (from CMU_MIF) + - description: DECON vertical clock (from CMU_MIF) + + clock-names: + items: + - const: oscclk + - const: bus + - const: decon_eclk + - const: decon_vclk + + - if: + properties: + compatible: + contains: + const: samsung,exynos7870-cmu-fsys + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_FSYS bus clock (from CMU_MIF) + - description: USB20DRD clock (from CMU_MIF) + + clock-names: + items: + - const: oscclk + - const: bus + - const: usb20drd + + - if: + properties: + compatible: + contains: + const: samsung,exynos7870-cmu-g3d + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: G3D switch clock (from CMU_MIF) + + clock-names: + items: + - const: oscclk + - const: switch + + - if: + properties: + compatible: + contains: + const: samsung,exynos7870-cmu-isp + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: ISP camera clock (from CMU_MIF) + - description: ISP clock (from CMU_MIF) + - description: ISP VRA clock (from CMU_MIF) + + clock-names: + items: + - const: oscclk + - const: cam + - const: isp + - const: vra + + - if: + properties: + compatible: + contains: + const: samsung,exynos7870-cmu-mfcmscl + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: MSCL clock (from CMU_MIF) + - description: MFC clock (from CMU_MIF) + + clock-names: + items: + - const: oscclk + - const: mfc + - const: mscl + + - if: + properties: + compatible: + contains: + const: samsung,exynos7870-cmu-peri + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_PERI bus clock (from CMU_MIF) + - description: SPI0 clock (from CMU_MIF) + - description: SPI1 clock (from CMU_MIF) + - description: SPI2 clock (from CMU_MIF) + - description: SPI3 clock (from CMU_MIF) + - description: SPI4 clock (from CMU_MIF) + - description: UART0 clock (from CMU_MIF) + - description: UART1 clock (from CMU_MIF) + - description: UART2 clock (from CMU_MIF) + + clock-names: + items: + - const: oscclk + - const: bus + - const: spi0 + - const: spi1 + - const: spi2 + - const: spi3 + - const: spi4 + - const: uart0 + - const: uart1 + - const: uart2 + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/samsung,exynos7870-cmu.h> + + cmu_peri: clock-controller@101f0000 { + compatible = "samsung,exynos7870-cmu-peri"; + reg = <0x101f0000 0x1000>; + #clock-cells = <1>; + + clock-names = "oscclk", "bus", "spi0", "spi1", "spi2", + "spi3", "spi4", "uart0", "uart1", "uart2"; + clocks = <&oscclk>, + <&cmu_mif CLK_GOUT_MIF_CMU_PERI_BUS>, + <&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI0>, + <&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI1>, + <&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI2>, + <&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI3>, + <&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI4>, + <&cmu_mif CLK_GOUT_MIF_CMU_PERI_UART0>, + <&cmu_mif CLK_GOUT_MIF_CMU_PERI_UART1>, + <&cmu_mif CLK_GOUT_MIF_CMU_PERI_UART2>; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos990-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos990-clock.yaml index 9e7944b5f13b..c15cc1752b02 100644 --- a/Documentation/devicetree/bindings/clock/samsung,exynos990-clock.yaml +++ b/Documentation/devicetree/bindings/clock/samsung,exynos990-clock.yaml @@ -31,6 +31,7 @@ properties: compatible: enum: - samsung,exynos990-cmu-hsi0 + - samsung,exynos990-cmu-peris - samsung,exynos990-cmu-top clocks: @@ -83,6 +84,24 @@ allOf: properties: compatible: contains: + const: samsung,exynos990-cmu-peris + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_PERIS BUS clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: bus + + - if: + properties: + compatible: + contains: const: samsung,exynos990-cmu-top then: diff --git a/Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml index 3330b2727474..6961a68098f4 100644 --- a/Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml +++ b/Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml @@ -8,6 +8,7 @@ title: Samsung ExynosAuto v920 SoC clock controller maintainers: - Sunyeal Hong <sunyeal.hong@samsung.com> + - Shin Son <shin.son@samsung.com> - Chanwoo Choi <cw00.choi@samsung.com> - Krzysztof Kozlowski <krzk@kernel.org> - Sylwester Nawrocki <s.nawrocki@samsung.com> @@ -32,6 +33,9 @@ properties: compatible: enum: - samsung,exynosautov920-cmu-top + - samsung,exynosautov920-cmu-cpucl0 + - samsung,exynosautov920-cmu-cpucl1 + - samsung,exynosautov920-cmu-cpucl2 - samsung,exynosautov920-cmu-peric0 - samsung,exynosautov920-cmu-peric1 - samsung,exynosautov920-cmu-misc @@ -74,6 +78,71 @@ allOf: compatible: contains: enum: + - samsung,exynosautov920-cmu-cpucl0 + + then: + properties: + clocks: + items: + - description: External reference clock (38.4 MHz) + - description: CMU_CPUCL0 SWITCH clock (from CMU_TOP) + - description: CMU_CPUCL0 CLUSTER clock (from CMU_TOP) + - description: CMU_CPUCL0 DBG clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: switch + - const: cluster + - const: dbg + + - if: + properties: + compatible: + contains: + enum: + - samsung,exynosautov920-cmu-cpucl1 + + then: + properties: + clocks: + items: + - description: External reference clock (38.4 MHz) + - description: CMU_CPUCL1 SWITCH clock (from CMU_TOP) + - description: CMU_CPUCL1 CLUSTER clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: switch + - const: cluster + + - if: + properties: + compatible: + contains: + enum: + - samsung,exynosautov920-cmu-cpucl2 + + then: + properties: + clocks: + items: + - description: External reference clock (38.4 MHz) + - description: CMU_CPUCL2 SWITCH clock (from CMU_TOP) + - description: CMU_CPUCL2 CLUSTER clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: switch + - const: cluster + + - if: + properties: + compatible: + contains: + enum: - samsung,exynosautov920-cmu-peric0 - samsung,exynosautov920-cmu-peric1 diff --git a/Documentation/devicetree/bindings/clock/sophgo,cv1800-clk.yaml b/Documentation/devicetree/bindings/clock/sophgo,cv1800-clk.yaml index 59ef41adb539..379ce3e9e391 100644 --- a/Documentation/devicetree/bindings/clock/sophgo,cv1800-clk.yaml +++ b/Documentation/devicetree/bindings/clock/sophgo,cv1800-clk.yaml @@ -11,10 +11,18 @@ maintainers: properties: compatible: - enum: - - sophgo,cv1800-clk - - sophgo,cv1810-clk - - sophgo,sg2000-clk + oneOf: + - enum: + - sophgo,cv1800b-clk + - sophgo,cv1812h-clk + - sophgo,sg2000-clk + - items: + - const: sophgo,sg2002-clk + - const: sophgo,sg2000-clk + - const: sophgo,cv1800-clk + deprecated: true + - const: sophgo,cv1810-clk + deprecated: true reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/clock/sophgo,sg2044-clk.yaml b/Documentation/devicetree/bindings/clock/sophgo,sg2044-clk.yaml new file mode 100644 index 000000000000..272e58bdb62c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/sophgo,sg2044-clk.yaml @@ -0,0 +1,99 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/sophgo,sg2044-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo SG2044 Clock Controller + +maintainers: + - Inochi Amaoto <inochiama@gmail.com> + +description: | + The Sophgo SG2044 clock controller requires an external oscillator + as input clock. + + All available clocks are defined as preprocessor macros in + include/dt-bindings/clock/sophgo,sg2044-clk.h + +properties: + compatible: + const: sophgo,sg2044-clk + + reg: + maxItems: 1 + + clocks: + items: + - description: fpll0 + - description: fpll1 + - description: fpll2 + - description: dpll0 + - description: dpll1 + - description: dpll2 + - description: dpll3 + - description: dpll4 + - description: dpll5 + - description: dpll6 + - description: dpll7 + - description: mpll0 + - description: mpll1 + - description: mpll2 + - description: mpll3 + - description: mpll4 + - description: mpll5 + + clock-names: + items: + - const: fpll0 + - const: fpll1 + - const: fpll2 + - const: dpll0 + - const: dpll1 + - const: dpll2 + - const: dpll3 + - const: dpll4 + - const: dpll5 + - const: dpll6 + - const: dpll7 + - const: mpll0 + - const: mpll1 + - const: mpll2 + - const: mpll3 + - const: mpll4 + - const: mpll5 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/sophgo,sg2044-pll.h> + + clock-controller@50002000 { + compatible = "sophgo,sg2044-clk"; + reg = <0x50002000 0x1000>; + #clock-cells = <1>; + clocks = <&syscon CLK_FPLL0>, <&syscon CLK_FPLL1>, + <&syscon CLK_FPLL2>, <&syscon CLK_DPLL0>, + <&syscon CLK_DPLL1>, <&syscon CLK_DPLL2>, + <&syscon CLK_DPLL3>, <&syscon CLK_DPLL4>, + <&syscon CLK_DPLL5>, <&syscon CLK_DPLL6>, + <&syscon CLK_DPLL7>, <&syscon CLK_MPLL0>, + <&syscon CLK_MPLL1>, <&syscon CLK_MPLL2>, + <&syscon CLK_MPLL3>, <&syscon CLK_MPLL4>, + <&syscon CLK_MPLL5>; + clock-names = "fpll0", "fpll1", "fpll2", "dpll0", + "dpll1", "dpll2", "dpll3", "dpll4", + "dpll5", "dpll6", "dpll7", "mpll0", + "mpll1", "mpll2", "mpll3", "mpll4", + "mpll5"; + }; diff --git a/Documentation/devicetree/bindings/clock/spacemit,k1-pll.yaml b/Documentation/devicetree/bindings/clock/spacemit,k1-pll.yaml new file mode 100644 index 000000000000..06bafd68c00a --- /dev/null +++ b/Documentation/devicetree/bindings/clock/spacemit,k1-pll.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/spacemit,k1-pll.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SpacemiT K1 PLL + +maintainers: + - Haylen Chu <heylenay@4d2.org> + +properties: + compatible: + const: spacemit,k1-pll + + reg: + maxItems: 1 + + clocks: + description: External 24MHz oscillator + + spacemit,mpmu: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the "Main PMU (MPMU)" syscon. It is used to check PLL + lock status. + + "#clock-cells": + const: 1 + description: + See <dt-bindings/clock/spacemit,k1-syscon.h> for valid indices. + +required: + - compatible + - reg + - clocks + - spacemit,mpmu + - "#clock-cells" + +additionalProperties: false + +examples: + - | + clock-controller@d4090000 { + compatible = "spacemit,k1-pll"; + reg = <0xd4090000 0x1000>; + clocks = <&vctcxo_24m>; + spacemit,mpmu = <&sysctl_mpmu>; + #clock-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/st,stm32h7-rcc.txt b/Documentation/devicetree/bindings/clock/st,stm32h7-rcc.txt deleted file mode 100644 index cac24ee10b72..000000000000 --- a/Documentation/devicetree/bindings/clock/st,stm32h7-rcc.txt +++ /dev/null @@ -1,71 +0,0 @@ -STMicroelectronics STM32H7 Reset and Clock Controller -===================================================== - -The RCC IP is both a reset and a clock controller. - -Please refer to clock-bindings.txt for common clock controller binding usage. -Please also refer to reset.txt for common reset controller binding usage. - -Required properties: -- compatible: Should be: - "st,stm32h743-rcc" - -- reg: should be register base and length as documented in the - datasheet - -- #reset-cells: 1, see below - -- #clock-cells : from common clock binding; shall be set to 1 - -- clocks: External oscillator clock phandle - - high speed external clock signal (HSE) - - low speed external clock signal (LSE) - - external I2S clock (I2S_CKIN) - -Optional properties: -- st,syscfg: phandle for pwrcfg, mandatory to disable/enable backup domain - write protection (RTC clock). - -Example: - - rcc: reset-clock-controller@58024400 { - compatible = "st,stm32h743-rcc", "st,stm32-rcc"; - reg = <0x58024400 0x400>; - #reset-cells = <1>; - #clock-cells = <1>; - clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s_ckin>; - - st,syscfg = <&pwrcfg>; -}; - -The peripheral clock consumer should specify the desired clock by -having the clock ID in its "clocks" phandle cell. - -Example: - - timer5: timer@40000c00 { - compatible = "st,stm32-timer"; - reg = <0x40000c00 0x400>; - interrupts = <50>; - clocks = <&rcc TIM5_CK>; - }; - -Specifying softreset control of devices -======================================= - -Device nodes should specify the reset channel required in their "resets" -property, containing a phandle to the reset device node and an index specifying -which channel to use. -The index is the bit number within the RCC registers bank, starting from RCC -base address. -It is calculated as: index = register_offset / 4 * 32 + bit_offset. -Where bit_offset is the bit offset within the register. - -For example, for CRC reset: - crc = AHB4RSTR_offset / 4 * 32 + CRCRST_bit_offset = 0x88 / 4 * 32 + 19 = 1107 - -Example: - - timer2 { - resets = <&rcc STM32H7_APB1L_RESET(TIM2)>; - }; diff --git a/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml b/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml index 0129bd0ba4b3..9d058c00ab3d 100644 --- a/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml +++ b/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml @@ -8,7 +8,8 @@ title: T-HEAD TH1520 AP sub-system clock controller description: | The T-HEAD TH1520 AP sub-system clock controller configures the - CPU, DPU, GMAC and TEE PLLs. + CPU, DPU, GMAC and TEE PLLs. Additionally the VO subsystem configures + the clock gates for the HDMI, MIPI and the GPU. SoC reference manual https://openbeagle.org/beaglev-ahead/beaglev-ahead/-/blob/main/docs/TH1520%20System%20User%20Manual.pdf @@ -20,14 +21,24 @@ maintainers: properties: compatible: - const: thead,th1520-clk-ap + enum: + - thead,th1520-clk-ap + - thead,th1520-clk-vo reg: maxItems: 1 clocks: items: - - description: main oscillator (24MHz) + - description: | + One input clock: + - For "thead,th1520-clk-ap": the clock input must be the 24 MHz + main oscillator. + - For "thead,th1520-clk-vo": the clock input must be the VIDEO_PLL, + which is configured by the AP clock controller. According to the + TH1520 manual, VIDEO_PLL is a Silicon Creations Sigma-Delta PLL + (integer PLL) typically running at 792 MHz (FOUTPOSTDIV), with + a maximum FOUTVCO of 2376 MHz. "#clock-cells": const: 1 diff --git a/Documentation/devicetree/bindings/clock/ti,clkctrl.yaml b/Documentation/devicetree/bindings/clock/ti,clkctrl.yaml new file mode 100644 index 000000000000..49787550ce45 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ti,clkctrl.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/ti,clkctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments clkctrl clock + +maintainers: + - Tony Lindgren <tony@atomide.com> + - Andreas Kemnade <andreas@kemnade.info> + +description: | + Texas Instruments SoCs can have a clkctrl clock controller for each + interconnect target module. The clkctrl clock controller manages functional + and interface clocks for each module. Each clkctrl controller can also + gate one or more optional functional clocks for a module, and can have one + or more clock muxes. There is a clkctrl clock controller typically for each + interconnect target module on omap4 and later variants. + + The clock consumers can specify the index of the clkctrl clock using + the hardware offset from the clkctrl instance register space. The optional + clocks can be specified by clkctrl hardware offset and the index of the + optional clock. + +properties: + compatible: + enum: + - ti,clkctrl + - ti,clkctrl-l4-cfg + - ti,clkctrl-l4-per + - ti,clkctrl-l4-secure + - ti,clkctrl-l4-wkup + + "#clock-cells": + const: 2 + + clock-output-names: + maxItems: 1 + + reg: + minItems: 1 + maxItems: 8 # arbitrary, should be enough + +required: + - compatible + - "#clock-cells" + - clock-output-names + - reg + +additionalProperties: false + +examples: + - | + bus { + #address-cells = <1>; + #size-cells = <1>; + + clock@20 { + compatible = "ti,clkctrl"; + clock-output-names = "l4_per"; + reg = <0x20 0x1b0>; + #clock-cells = <2>; + }; + }; diff --git a/Documentation/devicetree/bindings/clock/ti-clkctrl.txt b/Documentation/devicetree/bindings/clock/ti-clkctrl.txt deleted file mode 100644 index d20db7974a38..000000000000 --- a/Documentation/devicetree/bindings/clock/ti-clkctrl.txt +++ /dev/null @@ -1,63 +0,0 @@ -Texas Instruments clkctrl clock binding - -Texas Instruments SoCs can have a clkctrl clock controller for each -interconnect target module. The clkctrl clock controller manages functional -and interface clocks for each module. Each clkctrl controller can also -gate one or more optional functional clocks for a module, and can have one -or more clock muxes. There is a clkctrl clock controller typically for each -interconnect target module on omap4 and later variants. - -The clock consumers can specify the index of the clkctrl clock using -the hardware offset from the clkctrl instance register space. The optional -clocks can be specified by clkctrl hardware offset and the index of the -optional clock. - -For more information, please see the Linux clock framework binding at -Documentation/devicetree/bindings/clock/clock-bindings.txt. - -Required properties : -- compatible : shall be "ti,clkctrl" or a clock domain specific name: - "ti,clkctrl-l4-cfg" - "ti,clkctrl-l4-per" - "ti,clkctrl-l4-secure" - "ti,clkctrl-l4-wkup" -- clock-output-names : from common clock binding -- #clock-cells : shall contain 2 with the first entry being the instance - offset from the clock domain base and the second being the - clock index -- reg : clock registers - -Example: Clock controller node on omap 4430: - -&cm2 { - l4per: cm@1400 { - cm_l4per@0 { - cm_l4per_clkctrl: clock@20 { - compatible = "ti,clkctrl"; - clock-output-names = "l4_per"; - reg = <0x20 0x1b0>; - #clock-cells = <2>; - }; - }; - }; -}; - -Example: Preprocessor helper macros in dt-bindings/clock/ti-clkctrl.h - -#define OMAP4_CLKCTRL_OFFSET 0x20 -#define OMAP4_CLKCTRL_INDEX(offset) ((offset) - OMAP4_CLKCTRL_OFFSET) -#define MODULEMODE_HWCTRL 1 -#define MODULEMODE_SWCTRL 2 - -#define OMAP4_GPTIMER10_CLKTRL OMAP4_CLKCTRL_INDEX(0x28) -#define OMAP4_GPTIMER11_CLKTRL OMAP4_CLKCTRL_INDEX(0x30) -#define OMAP4_GPTIMER2_CLKTRL OMAP4_CLKCTRL_INDEX(0x38) -... -#define OMAP4_GPIO2_CLKCTRL OMAP_CLKCTRL_INDEX(0x60) - -Example: Clock consumer node for GPIO2: - -&gpio2 { - clocks = <&cm_l4per_clkctrl OMAP4_GPIO2_CLKCTRL 0 - &cm_l4per_clkctrl OMAP4_GPIO2_CLKCTRL 8>; -}; diff --git a/Documentation/devicetree/bindings/clock/vf610-clock.txt b/Documentation/devicetree/bindings/clock/vf610-clock.txt deleted file mode 100644 index 109ffa3a5b66..000000000000 --- a/Documentation/devicetree/bindings/clock/vf610-clock.txt +++ /dev/null @@ -1,41 +0,0 @@ -* Clock bindings for Freescale Vybrid VF610 SOC - -Required properties: -- compatible: Should be "fsl,vf610-ccm" -- reg: Address and length of the register set -- #clock-cells: Should be <1> - -Optional properties: -- clocks: list of clock identifiers which are external input clocks to the - given clock controller. Please refer the next section to find - the input clocks for a given controller. -- clock-names: list of names of clocks which are external input clocks to the - given clock controller. - -Input clocks for top clock controller: - - sxosc (external crystal oscillator 32KHz, recommended) - - fxosc (external crystal oscillator 24MHz, recommended) - - audio_ext - - enet_ext - -The clock consumer should specify the desired clock by having the clock -ID in its "clocks" phandle cell. See include/dt-bindings/clock/vf610-clock.h -for the full list of VF610 clock IDs. - -Examples: - -clks: ccm@4006b000 { - compatible = "fsl,vf610-ccm"; - reg = <0x4006b000 0x1000>; - #clock-cells = <1>; - clocks = <&sxosc>, <&fxosc>; - clock-names = "sxosc", "fxosc"; -}; - -uart1: serial@40028000 { - compatible = "fsl,vf610-uart"; - reg = <0x40028000 0x1000>; - interrupts = <0 62 0x04>; - clocks = <&clks VF610_CLK_UART1>; - clock-names = "ipg"; -}; diff --git a/Documentation/devicetree/bindings/connector/gocontroll,moduline-module-slot.yaml b/Documentation/devicetree/bindings/connector/gocontroll,moduline-module-slot.yaml new file mode 100644 index 000000000000..a16ae2762d16 --- /dev/null +++ b/Documentation/devicetree/bindings/connector/gocontroll,moduline-module-slot.yaml @@ -0,0 +1,88 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/connector/gocontroll,moduline-module-slot.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: GOcontroll Moduline Module slot + +maintainers: + - Maud Spierings <maudspierings@gocontroll.com> + +description: + The GOcontroll Moduline module slot represents a connector that fullfills the + Moduline slot specification, and can thus house any IO module that is also + built to this spec. + +properties: + compatible: + const: gocontroll,moduline-module-slot + + reg: + maxItems: 1 + + interrupts: + description: indicates readiness, high means busy. + maxItems: 1 + reset-gpios: + description: resets the module, active low. + maxItems: 1 + sync-gpios: + description: sync line between all module slots. + maxItems: 1 + + vdd-supply: + description: low power 3v3 supply generally for the microcontroller. + vddp-supply: + description: medium power 5v0 supply for on module low power peripherals. + vddhpp-supply: + description: high power 6v-8v supply for on module high power peripherals. + power-supply: + description: high power 6v-30v supply for high power module circuits. + + i2c-bus: + description: i2c bus shared between module slots and the SoC + $ref: /schemas/types.yaml#/definitions/phandle + + slot-number: + description: + The number of the module slot representing the location of on the pcb. + This enables access to the modules based on slot location. + $ref: /schemas/types.yaml#/definitions/uint32 + + spi-max-frequency: true + +required: + - compatible + - reg + - reset-gpios + - interrupts + - sync-gpios + - i2c-bus + - slot-number + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interrupt-controller/irq.h> + + spi { + #address-cells = <1>; + #size-cells = <0>; + + connector@0 { + reg = <0>; + compatible = "gocontroll,moduline-module-slot"; + reset-gpios = <&gpio5 10 GPIO_ACTIVE_LOW>; + sync-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&gpio4>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + vdd-supply = <®_3v3_per>; + vddp-supply = <®_5v0>; + vddhpp-supply = <®_6v4>; + i2c-bus = <&i2c2>; + slot-number = <1>; + }; + }; diff --git a/Documentation/devicetree/bindings/counter/fsl,ftm-quaddec.yaml b/Documentation/devicetree/bindings/counter/fsl,ftm-quaddec.yaml new file mode 100644 index 000000000000..384ca63b64d5 --- /dev/null +++ b/Documentation/devicetree/bindings/counter/fsl,ftm-quaddec.yaml @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/counter/fsl,ftm-quaddec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FlexTimer Quadrature decoder counter + +description: + Exposes a simple counter for the quadrature decoder mode. + +maintainers: + - Frank Li <Frank.li@nxp.com> + +properties: + compatible: + const: fsl,ftm-quaddec + + reg: + maxItems: 1 + + big-endian: true + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + counter@29d0000 { + compatible = "fsl,ftm-quaddec"; + reg = <0x29d0000 0x10000>; + big-endian; + }; diff --git a/Documentation/devicetree/bindings/counter/ftm-quaddec.txt b/Documentation/devicetree/bindings/counter/ftm-quaddec.txt deleted file mode 100644 index 4d18cd722074..000000000000 --- a/Documentation/devicetree/bindings/counter/ftm-quaddec.txt +++ /dev/null @@ -1,18 +0,0 @@ -FlexTimer Quadrature decoder counter - -This driver exposes a simple counter for the quadrature decoder mode. - -Required properties: -- compatible: Must be "fsl,ftm-quaddec". -- reg: Must be set to the memory region of the flextimer. - -Optional property: -- big-endian: Access the device registers in big-endian mode. - -Example: - counter0: counter@29d0000 { - compatible = "fsl,ftm-quaddec"; - reg = <0x0 0x29d0000 0x0 0x10000>; - big-endian; - status = "disabled"; - }; diff --git a/Documentation/devicetree/bindings/cpu/cpu-topology.txt b/Documentation/devicetree/bindings/cpu/cpu-topology.txt deleted file mode 100644 index 9bd530a35d14..000000000000 --- a/Documentation/devicetree/bindings/cpu/cpu-topology.txt +++ /dev/null @@ -1,553 +0,0 @@ -=========================================== -CPU topology binding description -=========================================== - -=========================================== -1 - Introduction -=========================================== - -In a SMP system, the hierarchy of CPUs is defined through three entities that -are used to describe the layout of physical CPUs in the system: - -- socket -- cluster -- core -- thread - -The bottom hierarchy level sits at core or thread level depending on whether -symmetric multi-threading (SMT) is supported or not. - -For instance in a system where CPUs support SMT, "cpu" nodes represent all -threads existing in the system and map to the hierarchy level "thread" above. -In systems where SMT is not supported "cpu" nodes represent all cores present -in the system and map to the hierarchy level "core" above. - -CPU topology bindings allow one to associate cpu nodes with hierarchical groups -corresponding to the system hierarchy; syntactically they are defined as device -tree nodes. - -Currently, only ARM/RISC-V intend to use this cpu topology binding but it may be -used for any other architecture as well. - -The cpu nodes, as per bindings defined in [4], represent the devices that -correspond to physical CPUs and are to be mapped to the hierarchy levels. - -A topology description containing phandles to cpu nodes that are not compliant -with bindings standardized in [4] is therefore considered invalid. - -=========================================== -2 - cpu-map node -=========================================== - -The ARM/RISC-V CPU topology is defined within the cpu-map node, which is a direct -child of the cpus node and provides a container where the actual topology -nodes are listed. - -- cpu-map node - - Usage: Optional - On SMP systems provide CPUs topology to the OS. - Uniprocessor systems do not require a topology - description and therefore should not define a - cpu-map node. - - Description: The cpu-map node is just a container node where its - subnodes describe the CPU topology. - - Node name must be "cpu-map". - - The cpu-map node's parent node must be the cpus node. - - The cpu-map node's child nodes can be: - - - one or more cluster nodes or - - one or more socket nodes in a multi-socket system - - Any other configuration is considered invalid. - -The cpu-map node can only contain 4 types of child nodes: - -- socket node -- cluster node -- core node -- thread node - -whose bindings are described in paragraph 3. - -The nodes describing the CPU topology (socket/cluster/core/thread) can -only be defined within the cpu-map node and every core/thread in the -system must be defined within the topology. Any other configuration is -invalid and therefore must be ignored. - -=========================================== -2.1 - cpu-map child nodes naming convention -=========================================== - -cpu-map child nodes must follow a naming convention where the node name -must be "socketN", "clusterN", "coreN", "threadN" depending on the node type -(ie socket/cluster/core/thread) (where N = {0, 1, ...} is the node number; nodes -which are siblings within a single common parent node must be given a unique and -sequential N value, starting from 0). -cpu-map child nodes which do not share a common parent node can have the same -name (ie same number N as other cpu-map child nodes at different device tree -levels) since name uniqueness will be guaranteed by the device tree hierarchy. - -=========================================== -3 - socket/cluster/core/thread node bindings -=========================================== - -Bindings for socket/cluster/cpu/thread nodes are defined as follows: - -- socket node - - Description: must be declared within a cpu-map node, one node - per physical socket in the system. A system can - contain single or multiple physical socket. - The association of sockets and NUMA nodes is beyond - the scope of this bindings, please refer [2] for - NUMA bindings. - - This node is optional for a single socket system. - - The socket node name must be "socketN" as described in 2.1 above. - A socket node can not be a leaf node. - - A socket node's child nodes must be one or more cluster nodes. - - Any other configuration is considered invalid. - -- cluster node - - Description: must be declared within a cpu-map node, one node - per cluster. A system can contain several layers of - clustering within a single physical socket and cluster - nodes can be contained in parent cluster nodes. - - The cluster node name must be "clusterN" as described in 2.1 above. - A cluster node can not be a leaf node. - - A cluster node's child nodes must be: - - - one or more cluster nodes; or - - one or more core nodes - - Any other configuration is considered invalid. - -- core node - - Description: must be declared in a cluster node, one node per core in - the cluster. If the system does not support SMT, core - nodes are leaf nodes, otherwise they become containers of - thread nodes. - - The core node name must be "coreN" as described in 2.1 above. - - A core node must be a leaf node if SMT is not supported. - - Properties for core nodes that are leaf nodes: - - - cpu - Usage: required - Value type: <phandle> - Definition: a phandle to the cpu node that corresponds to the - core node. - - If a core node is not a leaf node (CPUs supporting SMT) a core node's - child nodes can be: - - - one or more thread nodes - - Any other configuration is considered invalid. - -- thread node - - Description: must be declared in a core node, one node per thread - in the core if the system supports SMT. Thread nodes are - always leaf nodes in the device tree. - - The thread node name must be "threadN" as described in 2.1 above. - - A thread node must be a leaf node. - - A thread node must contain the following property: - - - cpu - Usage: required - Value type: <phandle> - Definition: a phandle to the cpu node that corresponds to - the thread node. - -=========================================== -4 - Example dts -=========================================== - -Example 1 (ARM 64-bit, 16-cpu system, two clusters of clusters in a single -physical socket): - -cpus { - #size-cells = <0>; - #address-cells = <2>; - - cpu-map { - socket0 { - cluster0 { - cluster0 { - core0 { - thread0 { - cpu = <&CPU0>; - }; - thread1 { - cpu = <&CPU1>; - }; - }; - - core1 { - thread0 { - cpu = <&CPU2>; - }; - thread1 { - cpu = <&CPU3>; - }; - }; - }; - - cluster1 { - core0 { - thread0 { - cpu = <&CPU4>; - }; - thread1 { - cpu = <&CPU5>; - }; - }; - - core1 { - thread0 { - cpu = <&CPU6>; - }; - thread1 { - cpu = <&CPU7>; - }; - }; - }; - }; - - cluster1 { - cluster0 { - core0 { - thread0 { - cpu = <&CPU8>; - }; - thread1 { - cpu = <&CPU9>; - }; - }; - core1 { - thread0 { - cpu = <&CPU10>; - }; - thread1 { - cpu = <&CPU11>; - }; - }; - }; - - cluster1 { - core0 { - thread0 { - cpu = <&CPU12>; - }; - thread1 { - cpu = <&CPU13>; - }; - }; - core1 { - thread0 { - cpu = <&CPU14>; - }; - thread1 { - cpu = <&CPU15>; - }; - }; - }; - }; - }; - }; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x0>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - CPU1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x1>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - CPU2: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x100>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - CPU3: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x101>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - CPU4: cpu@10000 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x10000>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - CPU5: cpu@10001 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x10001>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - CPU6: cpu@10100 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x10100>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - CPU7: cpu@10101 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x10101>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - CPU8: cpu@100000000 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x1 0x0>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - CPU9: cpu@100000001 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x1 0x1>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - CPU10: cpu@100000100 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x1 0x100>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - CPU11: cpu@100000101 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x1 0x101>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - CPU12: cpu@100010000 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x1 0x10000>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - CPU13: cpu@100010001 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x1 0x10001>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - CPU14: cpu@100010100 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x1 0x10100>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - CPU15: cpu@100010101 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x1 0x10101>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; -}; - -Example 2 (ARM 32-bit, dual-cluster, 8-cpu system, no SMT): - -cpus { - #size-cells = <0>; - #address-cells = <1>; - - cpu-map { - cluster0 { - core0 { - cpu = <&CPU0>; - }; - core1 { - cpu = <&CPU1>; - }; - core2 { - cpu = <&CPU2>; - }; - core3 { - cpu = <&CPU3>; - }; - }; - - cluster1 { - core0 { - cpu = <&CPU4>; - }; - core1 { - cpu = <&CPU5>; - }; - core2 { - cpu = <&CPU6>; - }; - core3 { - cpu = <&CPU7>; - }; - }; - }; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x0>; - }; - - CPU1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x1>; - }; - - CPU2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x2>; - }; - - CPU3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x3>; - }; - - CPU4: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x100>; - }; - - CPU5: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x101>; - }; - - CPU6: cpu@102 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x102>; - }; - - CPU7: cpu@103 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x103>; - }; -}; - -Example 3: HiFive Unleashed (RISC-V 64 bit, 4 core system) - -{ - #address-cells = <2>; - #size-cells = <2>; - compatible = "sifive,fu540g", "sifive,fu500"; - model = "sifive,hifive-unleashed-a00"; - - ... - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu-map { - socket0 { - cluster0 { - core0 { - cpu = <&CPU1>; - }; - core1 { - cpu = <&CPU2>; - }; - core2 { - cpu0 = <&CPU2>; - }; - core3 { - cpu0 = <&CPU3>; - }; - }; - }; - }; - - CPU1: cpu@1 { - device_type = "cpu"; - compatible = "sifive,rocket0", "riscv"; - reg = <0x1>; - } - - CPU2: cpu@2 { - device_type = "cpu"; - compatible = "sifive,rocket0", "riscv"; - reg = <0x2>; - } - CPU3: cpu@3 { - device_type = "cpu"; - compatible = "sifive,rocket0", "riscv"; - reg = <0x3>; - } - CPU4: cpu@4 { - device_type = "cpu"; - compatible = "sifive,rocket0", "riscv"; - reg = <0x4>; - } - } -}; -=============================================================================== -[1] ARM Linux kernel documentation - Documentation/devicetree/bindings/arm/cpus.yaml -[2] Devicetree NUMA binding description - Documentation/devicetree/bindings/numa.txt -[3] RISC-V Linux kernel documentation - Documentation/devicetree/bindings/riscv/cpus.yaml -[4] https://www.devicetree.org/specifications/ diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt deleted file mode 100644 index e0a4ba599abc..000000000000 --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt +++ /dev/null @@ -1,250 +0,0 @@ -Binding for MediaTek's CPUFreq driver -===================================== - -Required properties: -- clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names. -- clock-names: Should contain the following: - "cpu" - The multiplexer for clock input of CPU cluster. - "intermediate" - A parent of "cpu" clock which is used as "intermediate" clock - source (usually MAINPLL) when the original CPU PLL is under - transition and not stable yet. - Please refer to Documentation/devicetree/bindings/clock/clock-bindings.txt for - generic clock consumer properties. -- operating-points-v2: Please refer to Documentation/devicetree/bindings/opp/opp-v2.yaml - for detail. -- proc-supply: Regulator for Vproc of CPU cluster. - -Optional properties: -- sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver - needs to do "voltage tracking" to step by step scale up/down Vproc and - Vsram to fit SoC specific needs. When absent, the voltage scaling - flow is handled by hardware, hence no software "voltage tracking" is - needed. -- mediatek,cci: - Used to confirm the link status between cpufreq and mediatek cci. Because - cpufreq and mediatek cci could share the same regulator in some MediaTek SoCs. - To prevent the issue of high frequency and low voltage, we need to use this - property to make sure mediatek cci is ready. - For details of mediatek cci, please refer to - Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml -- #cooling-cells: - For details, please refer to - Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml - -Example 1 (MT7623 SoC): - - cpu_opp_table: opp_table { - compatible = "operating-points-v2"; - opp-shared; - - opp-598000000 { - opp-hz = /bits/ 64 <598000000>; - opp-microvolt = <1050000>; - }; - - opp-747500000 { - opp-hz = /bits/ 64 <747500000>; - opp-microvolt = <1050000>; - }; - - opp-1040000000 { - opp-hz = /bits/ 64 <1040000000>; - opp-microvolt = <1150000>; - }; - - opp-1196000000 { - opp-hz = /bits/ 64 <1196000000>; - opp-microvolt = <1200000>; - }; - - opp-1300000000 { - opp-hz = /bits/ 64 <1300000000>; - opp-microvolt = <1300000>; - }; - }; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x0>; - clocks = <&infracfg CLK_INFRA_CPUSEL>, - <&apmixedsys CLK_APMIXED_MAINPLL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cpu_opp_table>; - #cooling-cells = <2>; - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x1>; - operating-points-v2 = <&cpu_opp_table>; - }; - cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x2>; - operating-points-v2 = <&cpu_opp_table>; - }; - cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x3>; - operating-points-v2 = <&cpu_opp_table>; - }; - -Example 2 (MT8173 SoC): - cpu_opp_table_a: opp_table_a { - compatible = "operating-points-v2"; - opp-shared; - - opp-507000000 { - opp-hz = /bits/ 64 <507000000>; - opp-microvolt = <859000>; - }; - - opp-702000000 { - opp-hz = /bits/ 64 <702000000>; - opp-microvolt = <908000>; - }; - - opp-1001000000 { - opp-hz = /bits/ 64 <1001000000>; - opp-microvolt = <983000>; - }; - - opp-1105000000 { - opp-hz = /bits/ 64 <1105000000>; - opp-microvolt = <1009000>; - }; - - opp-1183000000 { - opp-hz = /bits/ 64 <1183000000>; - opp-microvolt = <1028000>; - }; - - opp-1404000000 { - opp-hz = /bits/ 64 <1404000000>; - opp-microvolt = <1083000>; - }; - - opp-1508000000 { - opp-hz = /bits/ 64 <1508000000>; - opp-microvolt = <1109000>; - }; - - opp-1573000000 { - opp-hz = /bits/ 64 <1573000000>; - opp-microvolt = <1125000>; - }; - }; - - cpu_opp_table_b: opp_table_b { - compatible = "operating-points-v2"; - opp-shared; - - opp-507000000 { - opp-hz = /bits/ 64 <507000000>; - opp-microvolt = <828000>; - }; - - opp-702000000 { - opp-hz = /bits/ 64 <702000000>; - opp-microvolt = <867000>; - }; - - opp-1001000000 { - opp-hz = /bits/ 64 <1001000000>; - opp-microvolt = <927000>; - }; - - opp-1209000000 { - opp-hz = /bits/ 64 <1209000000>; - opp-microvolt = <968000>; - }; - - opp-1404000000 { - opp-hz = /bits/ 64 <1007000000>; - opp-microvolt = <1028000>; - }; - - opp-1612000000 { - opp-hz = /bits/ 64 <1612000000>; - opp-microvolt = <1049000>; - }; - - opp-1807000000 { - opp-hz = /bits/ 64 <1807000000>; - opp-microvolt = <1089000>; - }; - - opp-1989000000 { - opp-hz = /bits/ 64 <1989000000>; - opp-microvolt = <1125000>; - }; - }; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x000>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - clocks = <&infracfg CLK_INFRA_CA53SEL>, - <&apmixedsys CLK_APMIXED_MAINPLL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cpu_opp_table_a>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x001>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - clocks = <&infracfg CLK_INFRA_CA53SEL>, - <&apmixedsys CLK_APMIXED_MAINPLL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cpu_opp_table_a>; - }; - - cpu2: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x100>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - clocks = <&infracfg CLK_INFRA_CA72SEL>, - <&apmixedsys CLK_APMIXED_MAINPLL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cpu_opp_table_b>; - }; - - cpu3: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x101>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - clocks = <&infracfg CLK_INFRA_CA72SEL>, - <&apmixedsys CLK_APMIXED_MAINPLL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cpu_opp_table_b>; - }; - - &cpu0 { - proc-supply = <&mt6397_vpca15_reg>; - }; - - &cpu1 { - proc-supply = <&mt6397_vpca15_reg>; - }; - - &cpu2 { - proc-supply = <&da9211_vcpu_reg>; - sram-supply = <&mt6397_vsramca7_reg>; - }; - - &cpu3 { - proc-supply = <&da9211_vcpu_reg>; - sram-supply = <&mt6397_vsramca7_reg>; - }; diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml index e937eb7355e7..e0242bed3342 100644 --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml @@ -34,6 +34,7 @@ properties: - description: v2 of CPUFREQ HW (EPSS) items: - enum: + - qcom,qcs8300-cpufreq-epss - qcom,qdu1000-cpufreq-epss - qcom,sa8255p-cpufreq-epss - qcom,sa8775p-cpufreq-epss @@ -111,22 +112,20 @@ allOf: enum: - qcom,qcm2290-cpufreq-hw - qcom,sar2130p-cpufreq-epss + - qcom,sdx75-cpufreq-epss then: properties: reg: - minItems: 1 maxItems: 1 reg-names: - minItems: 1 maxItems: 1 interrupts: - minItems: 1 maxItems: 1 interrupt-names: - minItems: 1 + maxItems: 1 - if: properties: @@ -135,6 +134,7 @@ allOf: enum: - qcom,qdu1000-cpufreq-epss - qcom,sa8255p-cpufreq-epss + - qcom,sa8775p-cpufreq-epss - qcom,sc7180-cpufreq-hw - qcom,sc8180x-cpufreq-hw - qcom,sc8280xp-cpufreq-epss @@ -160,12 +160,14 @@ allOf: interrupt-names: minItems: 2 + maxItems: 2 - if: properties: compatible: contains: enum: + - qcom,qcs8300-cpufreq-epss - qcom,sc7280-cpufreq-epss - qcom,sm8250-cpufreq-epss - qcom,sm8350-cpufreq-epss @@ -187,6 +189,7 @@ allOf: interrupt-names: minItems: 3 + maxItems: 3 - if: properties: @@ -211,7 +214,31 @@ allOf: interrupt-names: minItems: 2 + maxItems: 2 + - if: + properties: + compatible: + contains: + enum: + - qcom,sm8650-cpufreq-epss + then: + properties: + reg: + minItems: 4 + maxItems: 4 + + reg-names: + minItems: 4 + maxItems: 4 + + interrupts: + minItems: 4 + maxItems: 4 + + interrupt-names: + minItems: 4 + maxItems: 4 examples: - | diff --git a/Documentation/devicetree/bindings/crypto/amd,ccp-seattle-v1a.yaml b/Documentation/devicetree/bindings/crypto/amd,ccp-seattle-v1a.yaml new file mode 100644 index 000000000000..32bf3a1c3b42 --- /dev/null +++ b/Documentation/devicetree/bindings/crypto/amd,ccp-seattle-v1a.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/amd,ccp-seattle-v1a.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: AMD Cryptographic Coprocessor (ccp) + +maintainers: + - Tom Lendacky <thomas.lendacky@amd.com> + +properties: + compatible: + const: amd,ccp-seattle-v1a + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + dma-coherent: true + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + crypto@e0100000 { + compatible = "amd,ccp-seattle-v1a"; + reg = <0xe0100000 0x10000>; + interrupts = <0 3 4>; + dma-coherent; + }; diff --git a/Documentation/devicetree/bindings/crypto/amd-ccp.txt b/Documentation/devicetree/bindings/crypto/amd-ccp.txt deleted file mode 100644 index d87579d63da6..000000000000 --- a/Documentation/devicetree/bindings/crypto/amd-ccp.txt +++ /dev/null @@ -1,17 +0,0 @@ -* AMD Cryptographic Coprocessor driver (ccp) - -Required properties: -- compatible: Should be "amd,ccp-seattle-v1a" -- reg: Address and length of the register set for the device -- interrupts: Should contain the CCP interrupt - -Optional properties: -- dma-coherent: Present if dma operations are coherent - -Example: - ccp@e0100000 { - compatible = "amd,ccp-seattle-v1a"; - reg = <0 0xe0100000 0 0x10000>; - interrupt-parent = <&gic>; - interrupts = <0 3 4>; - }; diff --git a/Documentation/devicetree/bindings/crypto/artpec6-crypto.txt b/Documentation/devicetree/bindings/crypto/artpec6-crypto.txt deleted file mode 100644 index d9cca4875bd6..000000000000 --- a/Documentation/devicetree/bindings/crypto/artpec6-crypto.txt +++ /dev/null @@ -1,16 +0,0 @@ -Axis crypto engine with PDMA interface. - -Required properties: -- compatible : Should be one of the following strings: - "axis,artpec6-crypto" for the version in the Axis ARTPEC-6 SoC - "axis,artpec7-crypto" for the version in the Axis ARTPEC-7 SoC. -- reg: Base address and size for the PDMA register area. -- interrupts: Interrupt handle for the PDMA interrupt line. - -Example: - -crypto@f4264000 { - compatible = "axis,artpec6-crypto"; - reg = <0xf4264000 0x1000>; - interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; -}; diff --git a/Documentation/devicetree/bindings/crypto/axis,artpec6-crypto.yaml b/Documentation/devicetree/bindings/crypto/axis,artpec6-crypto.yaml new file mode 100644 index 000000000000..c91f81e3c39e --- /dev/null +++ b/Documentation/devicetree/bindings/crypto/axis,artpec6-crypto.yaml @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/crypto/axis,artpec6-crypto.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Axis ARTPEC6 crypto engine with PDMA interface + +maintainers: + - Lars Persson <lars.persson@axis.com> + +properties: + compatible: + enum: + - axis,artpec6-crypto + - axis,artpec7-crypto + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + crypto@f4264000 { + compatible = "axis,artpec6-crypto"; + reg = <0xf4264000 0x1000>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + }; diff --git a/Documentation/devicetree/bindings/crypto/brcm,spu-crypto.txt b/Documentation/devicetree/bindings/crypto/brcm,spu-crypto.txt deleted file mode 100644 index 29b6007568eb..000000000000 --- a/Documentation/devicetree/bindings/crypto/brcm,spu-crypto.txt +++ /dev/null @@ -1,22 +0,0 @@ -The Broadcom Secure Processing Unit (SPU) hardware supports symmetric -cryptographic offload for Broadcom SoCs. A SoC may have multiple SPU hardware -blocks. - -Required properties: -- compatible: Should be one of the following: - brcm,spum-crypto - for devices with SPU-M hardware - brcm,spu2-crypto - for devices with SPU2 hardware - brcm,spu2-v2-crypto - for devices with enhanced SPU2 hardware features like SHA3 - and Rabin Fingerprint support - brcm,spum-nsp-crypto - for the Northstar Plus variant of the SPU-M hardware - -- reg: Should contain SPU registers location and length. -- mboxes: The mailbox channel to be used to communicate with the SPU. - Mailbox channels correspond to DMA rings on the device. - -Example: - crypto@612d0000 { - compatible = "brcm,spum-crypto"; - reg = <0 0x612d0000 0 0x900>; - mboxes = <&pdc0 0>; - }; diff --git a/Documentation/devicetree/bindings/crypto/brcm,spum-crypto.yaml b/Documentation/devicetree/bindings/crypto/brcm,spum-crypto.yaml new file mode 100644 index 000000000000..9a5fb61727fa --- /dev/null +++ b/Documentation/devicetree/bindings/crypto/brcm,spum-crypto.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/brcm,spum-crypto.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom SPU Crypto Offload + +maintainers: + - Rob Rice <rob.rice@broadcom.com> + +description: + The Broadcom Secure Processing Unit (SPU) hardware supports symmetric + cryptographic offload for Broadcom SoCs. A SoC may have multiple SPU hardware + blocks. + +properties: + compatible: + enum: + - brcm,spum-crypto + - brcm,spu2-crypto + - brcm,spu2-v2-crypto # enhanced SPU2 hardware features like SHA3 and Rabin Fingerprint support + - brcm,spum-nsp-crypto # Northstar Plus variant of the SPU-M hardware + + reg: + maxItems: 1 + + mboxes: + maxItems: 1 + +required: + - compatible + - reg + - mboxes + +additionalProperties: false + +examples: + - | + crypto@612d0000 { + compatible = "brcm,spum-crypto"; + reg = <0x612d0000 0x900>; + mboxes = <&pdc0 0>; + }; diff --git a/Documentation/devicetree/bindings/crypto/fsl,sec-v4.0-mon.yaml b/Documentation/devicetree/bindings/crypto/fsl,sec-v4.0-mon.yaml index e879bc0be8e2..9f8e6689cd94 100644 --- a/Documentation/devicetree/bindings/crypto/fsl,sec-v4.0-mon.yaml +++ b/Documentation/devicetree/bindings/crypto/fsl,sec-v4.0-mon.yaml @@ -83,6 +83,8 @@ properties: by SNVS ONOFF, the driver can report the status of POWER key and wakeup system if pressed after system suspend. + $ref: /schemas/input/input.yaml + properties: compatible: const: fsl,sec-v4.0-pwrkey @@ -111,6 +113,9 @@ properties: maxItems: 1 default: 116 + power-off-time-sec: + enum: [0, 5, 10, 15] + required: - compatible - interrupts diff --git a/Documentation/devicetree/bindings/crypto/fsl,sec-v4.0.yaml b/Documentation/devicetree/bindings/crypto/fsl,sec-v4.0.yaml index f0c4a7c83568..75afa441e019 100644 --- a/Documentation/devicetree/bindings/crypto/fsl,sec-v4.0.yaml +++ b/Documentation/devicetree/bindings/crypto/fsl,sec-v4.0.yaml @@ -38,7 +38,9 @@ properties: compatible: oneOf: - items: - - const: fsl,sec-v5.4 + - enum: + - fsl,sec-v5.4 + - fsl,sec-v6.0 - const: fsl,sec-v5.0 - const: fsl,sec-v4.0 - items: @@ -94,6 +96,12 @@ patternProperties: compatible: oneOf: - items: + - const: fsl,sec-v6.0-job-ring + - const: fsl,sec-v5.2-job-ring + - const: fsl,sec-v5.0-job-ring + - const: fsl,sec-v4.4-job-ring + - const: fsl,sec-v4.0-job-ring + - items: - const: fsl,sec-v5.4-job-ring - const: fsl,sec-v5.0-job-ring - const: fsl,sec-v4.0-job-ring diff --git a/Documentation/devicetree/bindings/crypto/fsl,sec2.0.yaml b/Documentation/devicetree/bindings/crypto/fsl,sec2.0.yaml new file mode 100644 index 000000000000..2091b89bb726 --- /dev/null +++ b/Documentation/devicetree/bindings/crypto/fsl,sec2.0.yaml @@ -0,0 +1,144 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/crypto/fsl,sec2.0.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale SoC SEC Security Engines versions 1.x-2.x-3.x + +maintainers: + - J. Neuschäfer <j.ne@posteo.net> + +properties: + compatible: + description: + Should contain entries for this and backward compatible SEC versions, + high to low. Warning - SEC1 and SEC2 are mutually exclusive. + oneOf: + - items: + - const: fsl,sec3.3 + - const: fsl,sec3.1 + - const: fsl,sec3.0 + - const: fsl,sec2.4 + - const: fsl,sec2.2 + - const: fsl,sec2.1 + - const: fsl,sec2.0 + - items: + - const: fsl,sec3.1 + - const: fsl,sec3.0 + - const: fsl,sec2.4 + - const: fsl,sec2.2 + - const: fsl,sec2.1 + - const: fsl,sec2.0 + - items: + - const: fsl,sec3.0 + - const: fsl,sec2.4 + - const: fsl,sec2.2 + - const: fsl,sec2.1 + - const: fsl,sec2.0 + - items: + - const: fsl,sec2.4 + - const: fsl,sec2.2 + - const: fsl,sec2.1 + - const: fsl,sec2.0 + - items: + - const: fsl,sec2.2 + - const: fsl,sec2.1 + - const: fsl,sec2.0 + - items: + - const: fsl,sec2.1 + - const: fsl,sec2.0 + - items: + - const: fsl,sec2.0 + - items: + - const: fsl,sec1.2 + - const: fsl,sec1.0 + - items: + - const: fsl,sec1.0 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + fsl,num-channels: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 1, 4 ] + description: An integer representing the number of channels available. + + fsl,channel-fifo-len: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 100 + description: + An integer representing the number of descriptor pointers each channel + fetch fifo can hold. + + fsl,exec-units-mask: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 0xfff + description: | + The bitmask representing what execution units (EUs) are available. + EU information should be encoded following the SEC's Descriptor Header + Dword EU_SEL0 field documentation, i.e. as follows: + + bit 0 = reserved - should be 0 + bit 1 = set if SEC has the ARC4 EU (AFEU) + bit 2 = set if SEC has the DES/3DES EU (DEU) + bit 3 = set if SEC has the message digest EU (MDEU/MDEU-A) + bit 4 = set if SEC has the random number generator EU (RNG) + bit 5 = set if SEC has the public key EU (PKEU) + bit 6 = set if SEC has the AES EU (AESU) + bit 7 = set if SEC has the Kasumi EU (KEU) + bit 8 = set if SEC has the CRC EU (CRCU) + bit 11 = set if SEC has the message digest EU extended alg set (MDEU-B) + + remaining bits are reserved for future SEC EUs. + + fsl,descriptor-types-mask: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + The bitmask representing what descriptors are available. Descriptor type + information should be encoded following the SEC's Descriptor Header Dword + DESC_TYPE field documentation, i.e. as follows: + + bit 0 = SEC supports descriptor type aesu_ctr_nonsnoop + bit 1 = SEC supports descriptor type ipsec_esp + bit 2 = SEC supports descriptor type common_nonsnoop + bit 3 = SEC supports descriptor type 802.11i AES ccmp + bit 4 = SEC supports descriptor type hmac_snoop_no_afeu + bit 5 = SEC supports descriptor type srtp + bit 6 = SEC supports descriptor type non_hmac_snoop_no_afeu + bit 7 = SEC supports descriptor type pkeu_assemble + bit 8 = SEC supports descriptor type aesu_key_expand_output + bit 9 = SEC supports descriptor type pkeu_ptmul + bit 10 = SEC supports descriptor type common_nonsnoop_afeu + bit 11 = SEC supports descriptor type pkeu_ptadd_dbl + + ..and so on and so forth. + +required: + - compatible + - reg + - fsl,num-channels + - fsl,channel-fifo-len + - fsl,exec-units-mask + - fsl,descriptor-types-mask + +unevaluatedProperties: false + +examples: + - | + /* MPC8548E */ + crypto@30000 { + compatible = "fsl,sec2.1", "fsl,sec2.0"; + reg = <0x30000 0x10000>; + interrupts = <29 2>; + interrupt-parent = <&mpic>; + fsl,num-channels = <4>; + fsl,channel-fifo-len = <24>; + fsl,exec-units-mask = <0xfe>; + fsl,descriptor-types-mask = <0x12b0ebf>; + }; + +... diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec2.txt b/Documentation/devicetree/bindings/crypto/fsl-sec2.txt deleted file mode 100644 index 125f155d00d0..000000000000 --- a/Documentation/devicetree/bindings/crypto/fsl-sec2.txt +++ /dev/null @@ -1,65 +0,0 @@ -Freescale SoC SEC Security Engines versions 1.x-2.x-3.x - -Required properties: - -- compatible : Should contain entries for this and backward compatible - SEC versions, high to low, e.g., "fsl,sec2.1", "fsl,sec2.0" (SEC2/3) - e.g., "fsl,sec1.2", "fsl,sec1.0" (SEC1) - warning: SEC1 and SEC2 are mutually exclusive -- reg : Offset and length of the register set for the device -- interrupts : the SEC's interrupt number -- fsl,num-channels : An integer representing the number of channels - available. -- fsl,channel-fifo-len : An integer representing the number of - descriptor pointers each channel fetch fifo can hold. -- fsl,exec-units-mask : The bitmask representing what execution units - (EUs) are available. It's a single 32-bit cell. EU information - should be encoded following the SEC's Descriptor Header Dword - EU_SEL0 field documentation, i.e. as follows: - - bit 0 = reserved - should be 0 - bit 1 = set if SEC has the ARC4 EU (AFEU) - bit 2 = set if SEC has the DES/3DES EU (DEU) - bit 3 = set if SEC has the message digest EU (MDEU/MDEU-A) - bit 4 = set if SEC has the random number generator EU (RNG) - bit 5 = set if SEC has the public key EU (PKEU) - bit 6 = set if SEC has the AES EU (AESU) - bit 7 = set if SEC has the Kasumi EU (KEU) - bit 8 = set if SEC has the CRC EU (CRCU) - bit 11 = set if SEC has the message digest EU extended alg set (MDEU-B) - -remaining bits are reserved for future SEC EUs. - -- fsl,descriptor-types-mask : The bitmask representing what descriptors - are available. It's a single 32-bit cell. Descriptor type information - should be encoded following the SEC's Descriptor Header Dword DESC_TYPE - field documentation, i.e. as follows: - - bit 0 = set if SEC supports the aesu_ctr_nonsnoop desc. type - bit 1 = set if SEC supports the ipsec_esp descriptor type - bit 2 = set if SEC supports the common_nonsnoop desc. type - bit 3 = set if SEC supports the 802.11i AES ccmp desc. type - bit 4 = set if SEC supports the hmac_snoop_no_afeu desc. type - bit 5 = set if SEC supports the srtp descriptor type - bit 6 = set if SEC supports the non_hmac_snoop_no_afeu desc.type - bit 7 = set if SEC supports the pkeu_assemble descriptor type - bit 8 = set if SEC supports the aesu_key_expand_output desc.type - bit 9 = set if SEC supports the pkeu_ptmul descriptor type - bit 10 = set if SEC supports the common_nonsnoop_afeu desc. type - bit 11 = set if SEC supports the pkeu_ptadd_dbl descriptor type - - ..and so on and so forth. - -Example: - - /* MPC8548E */ - crypto@30000 { - compatible = "fsl,sec2.1", "fsl,sec2.0"; - reg = <0x30000 0x10000>; - interrupts = <29 2>; - interrupt-parent = <&mpic>; - fsl,num-channels = <4>; - fsl,channel-fifo-len = <24>; - fsl,exec-units-mask = <0xfe>; - fsl,descriptor-types-mask = <0x12b0ebf>; - }; diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec6.txt b/Documentation/devicetree/bindings/crypto/fsl-sec6.txt deleted file mode 100644 index 73b0eb950bb3..000000000000 --- a/Documentation/devicetree/bindings/crypto/fsl-sec6.txt +++ /dev/null @@ -1,157 +0,0 @@ -SEC 6 is as Freescale's Cryptographic Accelerator and Assurance Module (CAAM). -Currently Freescale powerpc chip C29X is embedded with SEC 6. -SEC 6 device tree binding include: - -SEC 6 Node - -Job Ring Node - -Full Example - -===================================================================== -SEC 6 Node - -Description - - Node defines the base address of the SEC 6 block. - This block specifies the address range of all global - configuration registers for the SEC 6 block. - For example, In C293, we could see three SEC 6 node. - -PROPERTIES - - - compatible - Usage: required - Value type: <string> - Definition: Must include "fsl,sec-v6.0". - - - fsl,sec-era - Usage: optional - Value type: <u32> - Definition: A standard property. Define the 'ERA' of the SEC - device. - - - #address-cells - Usage: required - Value type: <u32> - Definition: A standard property. Defines the number of cells - for representing physical addresses in child nodes. - - - #size-cells - Usage: required - Value type: <u32> - Definition: A standard property. Defines the number of cells - for representing the size of physical addresses in - child nodes. - - - reg - Usage: required - Value type: <prop-encoded-array> - Definition: A standard property. Specifies the physical - address and length of the SEC 6 configuration registers. - - - ranges - Usage: required - Value type: <prop-encoded-array> - Definition: A standard property. Specifies the physical address - range of the SEC 6.0 register space (-SNVS not included). A - triplet that includes the child address, parent address, & - length. - - Note: All other standard properties (see the Devicetree Specification) - are allowed but are optional. - -EXAMPLE - crypto@a0000 { - compatible = "fsl,sec-v6.0"; - fsl,sec-era = <6>; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xa0000 0x20000>; - ranges = <0 0xa0000 0x20000>; - }; - -===================================================================== -Job Ring (JR) Node - - Child of the crypto node defines data processing interface to SEC 6 - across the peripheral bus for purposes of processing - cryptographic descriptors. The specified address - range can be made visible to one (or more) cores. - The interrupt defined for this node is controlled within - the address range of this node. - - - compatible - Usage: required - Value type: <string> - Definition: Must include "fsl,sec-v6.0-job-ring". - - - reg - Usage: required - Value type: <prop-encoded-array> - Definition: Specifies a two JR parameters: an offset from - the parent physical address and the length the JR registers. - - - interrupts - Usage: required - Value type: <prop_encoded-array> - Definition: Specifies the interrupts generated by this - device. The value of the interrupts property - consists of one interrupt specifier. The format - of the specifier is defined by the binding document - describing the node's interrupt parent. - -EXAMPLE - jr@1000 { - compatible = "fsl,sec-v6.0-job-ring"; - reg = <0x1000 0x1000>; - interrupts = <49 2 0 0>; - }; - -=================================================================== -Full Example - -Since some chips may contain more than one SEC, the dtsi contains -only the node contents, not the node itself. A chip using the SEC -should include the dtsi inside each SEC node. Example: - -In qoriq-sec6.0.dtsi: - - compatible = "fsl,sec-v6.0"; - fsl,sec-era = <6>; - #address-cells = <1>; - #size-cells = <1>; - - jr@1000 { - compatible = "fsl,sec-v6.0-job-ring", - "fsl,sec-v5.2-job-ring", - "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.4-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x1000 0x1000>; - }; - - jr@2000 { - compatible = "fsl,sec-v6.0-job-ring", - "fsl,sec-v5.2-job-ring", - "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.4-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x2000 0x1000>; - }; - -In the C293 device tree, we add the include of public property: - - crypto@a0000 { - /include/ "qoriq-sec6.0.dtsi" - } - - crypto@a0000 { - reg = <0xa0000 0x20000>; - ranges = <0 0xa0000 0x20000>; - - jr@1000 { - interrupts = <49 2 0 0>; - }; - - jr@2000 { - interrupts = <50 2 0 0>; - }; - }; diff --git a/Documentation/devicetree/bindings/crypto/hisilicon,hip06-sec.yaml b/Documentation/devicetree/bindings/crypto/hisilicon,hip06-sec.yaml new file mode 100644 index 000000000000..2bfac9d1c020 --- /dev/null +++ b/Documentation/devicetree/bindings/crypto/hisilicon,hip06-sec.yaml @@ -0,0 +1,134 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/crypto/hisilicon,hip06-sec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon hip06/hip07 Security Accelerator + +maintainers: + - Jonathan Cameron <Jonathan.Cameron@huawei.com> + +properties: + compatible: + enum: + - hisilicon,hip06-sec + - hisilicon,hip07-sec + + reg: + items: + - description: Registers for backend processing engines + - description: Registers for common functionality + - description: Registers for queue 0 + - description: Registers for queue 1 + - description: Registers for queue 2 + - description: Registers for queue 3 + - description: Registers for queue 4 + - description: Registers for queue 5 + - description: Registers for queue 6 + - description: Registers for queue 7 + - description: Registers for queue 8 + - description: Registers for queue 9 + - description: Registers for queue 10 + - description: Registers for queue 11 + - description: Registers for queue 12 + - description: Registers for queue 13 + - description: Registers for queue 14 + - description: Registers for queue 15 + + interrupts: + items: + - description: SEC unit error queue interrupt + - description: Completion interrupt for queue 0 + - description: Error interrupt for queue 0 + - description: Completion interrupt for queue 1 + - description: Error interrupt for queue 1 + - description: Completion interrupt for queue 2 + - description: Error interrupt for queue 2 + - description: Completion interrupt for queue 3 + - description: Error interrupt for queue 3 + - description: Completion interrupt for queue 4 + - description: Error interrupt for queue 4 + - description: Completion interrupt for queue 5 + - description: Error interrupt for queue 5 + - description: Completion interrupt for queue 6 + - description: Error interrupt for queue 6 + - description: Completion interrupt for queue 7 + - description: Error interrupt for queue 7 + - description: Completion interrupt for queue 8 + - description: Error interrupt for queue 8 + - description: Completion interrupt for queue 9 + - description: Error interrupt for queue 9 + - description: Completion interrupt for queue 10 + - description: Error interrupt for queue 10 + - description: Completion interrupt for queue 11 + - description: Error interrupt for queue 11 + - description: Completion interrupt for queue 12 + - description: Error interrupt for queue 12 + - description: Completion interrupt for queue 13 + - description: Error interrupt for queue 13 + - description: Completion interrupt for queue 14 + - description: Error interrupt for queue 14 + - description: Completion interrupt for queue 15 + - description: Error interrupt for queue 15 + + dma-coherent: true + + iommus: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - dma-coherent + +additionalProperties: false + +examples: + - | + bus { + #address-cells = <2>; + #size-cells = <2>; + + crypto@400d2000000 { + compatible = "hisilicon,hip07-sec"; + reg = <0x400 0xd0000000 0x0 0x10000 + 0x400 0xd2000000 0x0 0x10000 + 0x400 0xd2010000 0x0 0x10000 + 0x400 0xd2020000 0x0 0x10000 + 0x400 0xd2030000 0x0 0x10000 + 0x400 0xd2040000 0x0 0x10000 + 0x400 0xd2050000 0x0 0x10000 + 0x400 0xd2060000 0x0 0x10000 + 0x400 0xd2070000 0x0 0x10000 + 0x400 0xd2080000 0x0 0x10000 + 0x400 0xd2090000 0x0 0x10000 + 0x400 0xd20a0000 0x0 0x10000 + 0x400 0xd20b0000 0x0 0x10000 + 0x400 0xd20c0000 0x0 0x10000 + 0x400 0xd20d0000 0x0 0x10000 + 0x400 0xd20e0000 0x0 0x10000 + 0x400 0xd20f0000 0x0 0x10000 + 0x400 0xd2100000 0x0 0x10000>; + interrupts = <576 4>, + <577 1>, <578 4>, + <579 1>, <580 4>, + <581 1>, <582 4>, + <583 1>, <584 4>, + <585 1>, <586 4>, + <587 1>, <588 4>, + <589 1>, <590 4>, + <591 1>, <592 4>, + <593 1>, <594 4>, + <595 1>, <596 4>, + <597 1>, <598 4>, + <599 1>, <600 4>, + <601 1>, <602 4>, + <603 1>, <604 4>, + <605 1>, <606 4>, + <607 1>, <608 4>; + dma-coherent; + iommus = <&p1_smmu_alg_a 0x600>; + }; + }; diff --git a/Documentation/devicetree/bindings/crypto/hisilicon,hip07-sec.txt b/Documentation/devicetree/bindings/crypto/hisilicon,hip07-sec.txt deleted file mode 100644 index d28fd1af01b4..000000000000 --- a/Documentation/devicetree/bindings/crypto/hisilicon,hip07-sec.txt +++ /dev/null @@ -1,67 +0,0 @@ -* Hisilicon hip07 Security Accelerator (SEC) - -Required properties: -- compatible: Must contain one of - - "hisilicon,hip06-sec" - - "hisilicon,hip07-sec" -- reg: Memory addresses and lengths of the memory regions through which - this device is controlled. - Region 0 has registers to control the backend processing engines. - Region 1 has registers for functionality common to all queues. - Regions 2-18 have registers for the 16 individual queues which are isolated - both in hardware and within the driver. -- interrupts: Interrupt specifiers. - Refer to interrupt-controller/interrupts.txt for generic interrupt client node - bindings. - Interrupt 0 is for the SEC unit error queue. - Interrupt 2N + 1 is the completion interrupt for queue N. - Interrupt 2N + 2 is the error interrupt for queue N. -- dma-coherent: The driver assumes coherent dma is possible. - -Optional properties: -- iommus: The SEC units are behind smmu-v3 iommus. - Refer to iommu/arm,smmu-v3.txt for more information. - -Example: - -p1_sec_a: crypto@400d2000000 { - compatible = "hisilicon,hip07-sec"; - reg = <0x400 0xd0000000 0x0 0x10000 - 0x400 0xd2000000 0x0 0x10000 - 0x400 0xd2010000 0x0 0x10000 - 0x400 0xd2020000 0x0 0x10000 - 0x400 0xd2030000 0x0 0x10000 - 0x400 0xd2040000 0x0 0x10000 - 0x400 0xd2050000 0x0 0x10000 - 0x400 0xd2060000 0x0 0x10000 - 0x400 0xd2070000 0x0 0x10000 - 0x400 0xd2080000 0x0 0x10000 - 0x400 0xd2090000 0x0 0x10000 - 0x400 0xd20a0000 0x0 0x10000 - 0x400 0xd20b0000 0x0 0x10000 - 0x400 0xd20c0000 0x0 0x10000 - 0x400 0xd20d0000 0x0 0x10000 - 0x400 0xd20e0000 0x0 0x10000 - 0x400 0xd20f0000 0x0 0x10000 - 0x400 0xd2100000 0x0 0x10000>; - interrupt-parent = <&p1_mbigen_sec_a>; - iommus = <&p1_smmu_alg_a 0x600>; - dma-coherent; - interrupts = <576 4>, - <577 1>, <578 4>, - <579 1>, <580 4>, - <581 1>, <582 4>, - <583 1>, <584 4>, - <585 1>, <586 4>, - <587 1>, <588 4>, - <589 1>, <590 4>, - <591 1>, <592 4>, - <593 1>, <594 4>, - <595 1>, <596 4>, - <597 1>, <598 4>, - <599 1>, <600 4>, - <601 1>, <602 4>, - <603 1>, <604 4>, - <605 1>, <606 4>, - <607 1>, <608 4>; -}; diff --git a/Documentation/devicetree/bindings/crypto/img,hash-accelerator.yaml b/Documentation/devicetree/bindings/crypto/img,hash-accelerator.yaml new file mode 100644 index 000000000000..46617561ef94 --- /dev/null +++ b/Documentation/devicetree/bindings/crypto/img,hash-accelerator.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/img,hash-accelerator.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Imagination Technologies hardware hash accelerator + +maintainers: + - James Hartley <james.hartley@imgtec.com> + +description: + The hash accelerator provides hardware hashing acceleration for + SHA1, SHA224, SHA256 and MD5 hashes. + +properties: + compatible: + const: img,hash-accelerator + + reg: + items: + - description: Register base address and size + - description: DMA port specifier + + interrupts: + maxItems: 1 + + dmas: + maxItems: 1 + + dma-names: + items: + - const: tx + + clocks: + items: + - description: System clock for hash block registers + - description: Hash clock for data path + + clock-names: + items: + - const: sys + - const: hash + +additionalProperties: false + +required: + - compatible + - reg + - interrupts + - dmas + - dma-names + - clocks + - clock-names + +examples: + - | + #include <dt-bindings/interrupt-controller/mips-gic.h> + #include <dt-bindings/clock/pistachio-clk.h> + + hash@18149600 { + compatible = "img,hash-accelerator"; + reg = <0x18149600 0x100>, <0x18101100 0x4>; + interrupts = <GIC_SHARED 59 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma 8 0xffffffff 0>; + dma-names = "tx"; + clocks = <&cr_periph SYS_CLK_HASH>, <&clk_periph PERIPH_CLK_ROM>; + clock-names = "sys", "hash"; + }; diff --git a/Documentation/devicetree/bindings/crypto/img-hash.txt b/Documentation/devicetree/bindings/crypto/img-hash.txt deleted file mode 100644 index 91a3d757d641..000000000000 --- a/Documentation/devicetree/bindings/crypto/img-hash.txt +++ /dev/null @@ -1,27 +0,0 @@ -Imagination Technologies hardware hash accelerator - -The hash accelerator provides hardware hashing acceleration for -SHA1, SHA224, SHA256 and MD5 hashes - -Required properties: - -- compatible : "img,hash-accelerator" -- reg : Offset and length of the register set for the module, and the DMA port -- interrupts : The designated IRQ line for the hashing module. -- dmas : DMA specifier as per Documentation/devicetree/bindings/dma/dma.txt -- dma-names : Should be "tx" -- clocks : Clock specifiers -- clock-names : "sys" Used to clock the hash block registers - "hash" Used to clock data through the accelerator - -Example: - - hash: hash@18149600 { - compatible = "img,hash-accelerator"; - reg = <0x18149600 0x100>, <0x18101100 0x4>; - interrupts = <GIC_SHARED 59 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&dma 8 0xffffffff 0>; - dma-names = "tx"; - clocks = <&cr_periph SYS_CLK_HASH>, <&clk_periph PERIPH_CLK_ROM>; - clock-names = "sys", "hash"; - }; diff --git a/Documentation/devicetree/bindings/crypto/inside-secure,safexcel-eip93.yaml b/Documentation/devicetree/bindings/crypto/inside-secure,safexcel-eip93.yaml new file mode 100644 index 000000000000..997bf9717f9e --- /dev/null +++ b/Documentation/devicetree/bindings/crypto/inside-secure,safexcel-eip93.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/crypto/inside-secure,safexcel-eip93.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Inside Secure SafeXcel EIP-93 cryptographic engine + +maintainers: + - Christian Marangi <ansuelsmth@gmail.com> + +description: | + The Inside Secure SafeXcel EIP-93 is a cryptographic engine IP block + integrated in varios devices with very different and generic name from + PKTE to simply vendor+EIP93. The real IP under the hood is actually + developed by Inside Secure and given to license to vendors. + + The IP block is sold with different model based on what feature are + needed and are identified with the final letter. Each letter correspond + to a specific set of feature and multiple letter reflect the sum of the + feature set. + + EIP-93 models: + - EIP-93i: (basic) DES/Triple DES, AES, PRNG, IPsec ESP, SRTP, SHA1 + - EIP-93ie: i + SHA224/256, AES-192/256 + - EIP-93is: i + SSL/DTLS/DTLS, MD5, ARC4 + - EIP-93ies: i + e + s + - EIP-93iw: i + AES-XCB-MAC, AES-CCM + +properties: + compatible: + oneOf: + - items: + - const: airoha,en7581-eip93 + - const: inside-secure,safexcel-eip93ies + - items: + - not: {} + description: Need a SoC specific compatible + - enum: + - inside-secure,safexcel-eip93i + - inside-secure,safexcel-eip93ie + - inside-secure,safexcel-eip93is + - inside-secure,safexcel-eip93iw + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + crypto@1e004000 { + compatible = "airoha,en7581-eip93", "inside-secure,safexcel-eip93ies"; + reg = <0x1fb70000 0x1000>; + + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; + }; diff --git a/Documentation/devicetree/bindings/crypto/inside-secure,safexcel.yaml b/Documentation/devicetree/bindings/crypto/inside-secure,safexcel.yaml index ef07258d16c1..343e2d04c797 100644 --- a/Documentation/devicetree/bindings/crypto/inside-secure,safexcel.yaml +++ b/Documentation/devicetree/bindings/crypto/inside-secure,safexcel.yaml @@ -47,6 +47,8 @@ properties: - const: core - const: reg + dma-coherent: true + required: - reg - interrupts diff --git a/Documentation/devicetree/bindings/crypto/marvell,orion-crypto.yaml b/Documentation/devicetree/bindings/crypto/marvell,orion-crypto.yaml new file mode 100644 index 000000000000..b44d36c50ec4 --- /dev/null +++ b/Documentation/devicetree/bindings/crypto/marvell,orion-crypto.yaml @@ -0,0 +1,133 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/crypto/marvell,orion-crypto.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Cryptographic Engines And Security Accelerator + +maintainers: + - Andrew Lunn <andrew@lunn.ch> + - Boris Brezillon <bbrezillon@kernel.org> + +description: | + Marvell Cryptographic Engines And Security Accelerator + +properties: + compatible: + enum: + - marvell,armada-370-crypto + - marvell,armada-xp-crypto + - marvell,armada-375-crypto + - marvell,armada-38x-crypto + - marvell,dove-crypto + - marvell,kirkwood-crypto + - marvell,orion-crypto + + reg: + minItems: 1 + items: + - description: Registers region + - description: SRAM region + deprecated: true + + reg-names: + minItems: 1 + items: + - const: regs + - const: sram + deprecated: true + + interrupts: + description: One interrupt for each CESA engine + minItems: 1 + maxItems: 2 + + clocks: + description: One or two clocks for each CESA engine + minItems: 1 + maxItems: 4 + + clock-names: + minItems: 1 + items: + - const: cesa0 + - const: cesa1 + - const: cesaz0 + - const: cesaz1 + + marvell,crypto-srams: + description: Phandle(s) to crypto SRAM. + $ref: /schemas/types.yaml#/definitions/phandle-array + minItems: 1 + maxItems: 2 + items: + maxItems: 1 + + marvell,crypto-sram-size: + description: SRAM size reserved for crypto operations. + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0x800 + +required: + - compatible + - reg + - reg-names + - interrupts + - marvell,crypto-srams + +allOf: + - if: + not: + properties: + compatible: + enum: + - marvell,kirkwood-crypto + - marvell,orion-crypto + then: + required: + - clocks + - if: + properties: + compatible: + contains: + enum: + - marvell,armada-370-crypto + - marvell,armada-375-crypto + - marvell,armada-38x-crypto + - marvell,armada-xp-crypto + then: + required: + - clock-names + - if: + properties: + compatible: + contains: + enum: + - marvell,armada-375-crypto + - marvell,armada-38x-crypto + then: + properties: + clocks: + minItems: 4 + clock-names: + minItems: 4 + else: + properties: + clocks: + maxItems: 2 + clock-names: + maxItems: 2 + +additionalProperties: false + +examples: + - | + crypto@30000 { + compatible = "marvell,orion-crypto"; + reg = <0x30000 0x10000>; + reg-names = "regs"; + interrupts = <22>; + marvell,crypto-srams = <&crypto_sram>; + marvell,crypto-sram-size = <0x600>; + }; diff --git a/Documentation/devicetree/bindings/crypto/marvell-cesa.txt b/Documentation/devicetree/bindings/crypto/marvell-cesa.txt deleted file mode 100644 index 28d3f2496b89..000000000000 --- a/Documentation/devicetree/bindings/crypto/marvell-cesa.txt +++ /dev/null @@ -1,44 +0,0 @@ -Marvell Cryptographic Engines And Security Accelerator - -Required properties: -- compatible: should be one of the following string - "marvell,orion-crypto" - "marvell,kirkwood-crypto" - "marvell,dove-crypto" - "marvell,armada-370-crypto" - "marvell,armada-xp-crypto" - "marvell,armada-375-crypto" - "marvell,armada-38x-crypto" -- reg: base physical address of the engine and length of memory mapped - region. Can also contain an entry for the SRAM attached to the CESA, - but this representation is deprecated and marvell,crypto-srams should - be used instead -- reg-names: "regs". Can contain an "sram" entry, but this representation - is deprecated and marvell,crypto-srams should be used instead -- interrupts: interrupt number -- clocks: reference to the crypto engines clocks. This property is not - required for orion and kirkwood platforms -- clock-names: "cesaX" and "cesazX", X should be replaced by the crypto engine - id. - This property is not required for the orion and kirkwoord - platforms. - "cesazX" clocks are not required on armada-370 platforms -- marvell,crypto-srams: phandle to crypto SRAM definitions - -Optional properties: -- marvell,crypto-sram-size: SRAM size reserved for crypto operations, if not - specified the whole SRAM is used (2KB) - - -Examples: - - crypto@90000 { - compatible = "marvell,armada-xp-crypto"; - reg = <0x90000 0x10000>; - reg-names = "regs"; - interrupts = <48>, <49>; - clocks = <&gateclk 23>, <&gateclk 23>; - clock-names = "cesa0", "cesa1"; - marvell,crypto-srams = <&crypto_sram0>, <&crypto_sram1>; - marvell,crypto-sram-size = <0x600>; - }; diff --git a/Documentation/devicetree/bindings/crypto/mediatek-crypto.txt b/Documentation/devicetree/bindings/crypto/mediatek-crypto.txt deleted file mode 100644 index 450da3661cad..000000000000 --- a/Documentation/devicetree/bindings/crypto/mediatek-crypto.txt +++ /dev/null @@ -1,25 +0,0 @@ -MediaTek cryptographic accelerators - -Required properties: -- compatible: Should be "mediatek,eip97-crypto" -- reg: Address and length of the register set for the device -- interrupts: Should contain the five crypto engines interrupts in numeric - order. These are global system and four descriptor rings. -- clocks: the clock used by the core -- clock-names: Must contain "cryp". -- power-domains: Must contain a reference to the PM domain. - - -Example: - crypto: crypto@1b240000 { - compatible = "mediatek,eip97-crypto"; - reg = <0 0x1b240000 0 0x20000>; - interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>, - <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>, - <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>, - <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>, - <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>; - clocks = <ðsys CLK_ETHSYS_CRYPTO>; - clock-names = "cryp"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; - }; diff --git a/Documentation/devicetree/bindings/crypto/mv_cesa.txt b/Documentation/devicetree/bindings/crypto/mv_cesa.txt deleted file mode 100644 index d9b92e2f3138..000000000000 --- a/Documentation/devicetree/bindings/crypto/mv_cesa.txt +++ /dev/null @@ -1,32 +0,0 @@ -Marvell Cryptographic Engines And Security Accelerator - -Required properties: -- compatible: should be one of the following string - "marvell,orion-crypto" - "marvell,kirkwood-crypto" - "marvell,dove-crypto" -- reg: base physical address of the engine and length of memory mapped - region. Can also contain an entry for the SRAM attached to the CESA, - but this representation is deprecated and marvell,crypto-srams should - be used instead -- reg-names: "regs". Can contain an "sram" entry, but this representation - is deprecated and marvell,crypto-srams should be used instead -- interrupts: interrupt number -- clocks: reference to the crypto engines clocks. This property is only - required for Dove platforms -- marvell,crypto-srams: phandle to crypto SRAM definitions - -Optional properties: -- marvell,crypto-sram-size: SRAM size reserved for crypto operations, if not - specified the whole SRAM is used (2KB) - -Examples: - - crypto@30000 { - compatible = "marvell,orion-crypto"; - reg = <0x30000 0x10000>; - reg-names = "regs"; - interrupts = <22>; - marvell,crypto-srams = <&crypto_sram>; - marvell,crypto-sram-size = <0x600>; - }; diff --git a/Documentation/devicetree/bindings/crypto/qcom,prng.yaml b/Documentation/devicetree/bindings/crypto/qcom,prng.yaml index 5e6f8b642545..ed7e16bd11d3 100644 --- a/Documentation/devicetree/bindings/crypto/qcom,prng.yaml +++ b/Documentation/devicetree/bindings/crypto/qcom,prng.yaml @@ -20,6 +20,7 @@ properties: - qcom,ipq5332-trng - qcom,ipq5424-trng - qcom,ipq9574-trng + - qcom,qcs615-trng - qcom,qcs8300-trng - qcom,sa8255p-trng - qcom,sa8775p-trng diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml index 3ed56d9d378e..e009cb712fb8 100644 --- a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml +++ b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml @@ -45,6 +45,7 @@ properties: - items: - enum: + - qcom,qcs615-qce - qcom,qcs8300-qce - qcom,sa8775p-qce - qcom,sc7280-qce @@ -55,6 +56,7 @@ properties: - qcom,sm8550-qce - qcom,sm8650-qce - qcom,sm8750-qce + - qcom,x1e80100-qce - const: qcom,sm8150-qce - const: qcom,qce diff --git a/Documentation/devicetree/bindings/display/apple,h7-display-pipe-mipi.yaml b/Documentation/devicetree/bindings/display/apple,h7-display-pipe-mipi.yaml new file mode 100644 index 000000000000..5e6da66499a5 --- /dev/null +++ b/Documentation/devicetree/bindings/display/apple,h7-display-pipe-mipi.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/apple,h7-display-pipe-mipi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Apple pre-DCP display controller MIPI interface + +maintainers: + - Sasha Finkelstein <fnkl.kernel@gmail.com> + +description: + The MIPI controller part of the pre-DCP Apple display controller + +allOf: + - $ref: dsi-controller.yaml# + +properties: + compatible: + items: + - enum: + - apple,t8112-display-pipe-mipi + - apple,t8103-display-pipe-mipi + - const: apple,h7-display-pipe-mipi + + reg: + maxItems: 1 + + power-domains: + maxItems: 1 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: Input port. Always connected to the primary controller + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: Output MIPI DSI port to the panel + + required: + - port@0 + - port@1 + +required: + - compatible + - reg + - ports + +unevaluatedProperties: false + +examples: + - | + dsi@28200000 { + compatible = "apple,t8103-display-pipe-mipi", "apple,h7-display-pipe-mipi"; + reg = <0x28200000 0xc000>; + power-domains = <&ps_dispdfr_mipi>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dfr_adp_out_mipi: endpoint { + remote-endpoint = <&dfr_adp_out_mipi>; + }; + }; + + port@1 { + reg = <1>; + + dfr_panel_in: endpoint { + remote-endpoint = <&dfr_mipi_out_panel>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/display/apple,h7-display-pipe.yaml b/Documentation/devicetree/bindings/display/apple,h7-display-pipe.yaml new file mode 100644 index 000000000000..102fb1804c0c --- /dev/null +++ b/Documentation/devicetree/bindings/display/apple,h7-display-pipe.yaml @@ -0,0 +1,88 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/apple,h7-display-pipe.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Apple pre-DCP display controller + +maintainers: + - Sasha Finkelstein <fnkl.kernel@gmail.com> + +description: + A secondary display controller used to drive the "touchbar" on + certain Apple laptops. + +properties: + compatible: + items: + - enum: + - apple,t8112-display-pipe + - apple,t8103-display-pipe + - const: apple,h7-display-pipe + + reg: + items: + - description: Primary register block, controls planes and blending + - description: + Contains other configuration registers like interrupt + and FIFO control + + reg-names: + items: + - const: be + - const: fe + + power-domains: + description: + Phandles to pmgr entries that are needed for this controller to turn on. + Aside from that, their specific functions are unknown + maxItems: 2 + + interrupts: + items: + - description: Unknown function + - description: Primary interrupt. Vsync events are reported via it + + interrupt-names: + items: + - const: be + - const: fe + + iommus: + maxItems: 1 + + port: + $ref: /schemas/graph.yaml#/properties/port + description: Output port. Always connected to apple,h7-display-pipe-mipi + +required: + - compatible + - reg + - interrupts + - port + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/apple-aic.h> + display-pipe@28200000 { + compatible = "apple,t8103-display-pipe", "apple,h7-display-pipe"; + reg = <0x28200000 0xc000>, + <0x28400000 0x4000>; + reg-names = "be", "fe"; + power-domains = <&ps_dispdfr_fe>, <&ps_dispdfr_be>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 502 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 506 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "be", "fe"; + iommus = <&displaydfr_dart 0>; + + port { + dfr_adp_out_mipi: endpoint { + remote-endpoint = <&dfr_mipi_in_adp>; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/display/bridge/lvds-codec.yaml b/Documentation/devicetree/bindings/display/bridge/lvds-codec.yaml index 6ceeed76e88e..0487bbffd7f7 100644 --- a/Documentation/devicetree/bindings/display/bridge/lvds-codec.yaml +++ b/Documentation/devicetree/bindings/display/bridge/lvds-codec.yaml @@ -41,6 +41,7 @@ properties: - enum: - ti,ds90cf364a # For the DS90CF364A FPD-Link LVDS Receiver - ti,ds90cf384a # For the DS90CF384A FPD-Link LVDS Receiver + - ti,sn65lvds822 # For the SN65LVDS822 FlatLink LVDS Receiver - ti,sn65lvds94 # For the SN65DS94 LVDS serdes - const: lvds-decoder # Generic LVDS decoders compatible fallback - enum: diff --git a/Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml b/Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml index 350fb8f400f0..5952e6448ed4 100644 --- a/Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml +++ b/Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml @@ -111,11 +111,27 @@ properties: unevaluatedProperties: false port@1: - $ref: /schemas/graph.yaml#/properties/port + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false description: DSI output port node to the panel or the next bridge in the chain + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + description: array of physical DSI data lane indexes. + minItems: 1 + items: + - const: 1 + - const: 2 + - const: 3 + - const: 4 + required: - port@0 - port@1 diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml index e08c24633926..5a99d9b9635e 100644 --- a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml +++ b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml @@ -128,7 +128,7 @@ required: - power-domains - ports -additionalProperties: false +unevaluatedProperties: false examples: - | @@ -180,4 +180,69 @@ examples: }; }; }; + + - | + #include <dt-bindings/gpio/gpio.h> + + dsi1: dsi@10860000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,r9a07g044-mipi-dsi", "renesas,rzg2l-mipi-dsi"; + reg = <0x10860000 0x20000>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "seq0", "seq1", "vin1", "rcv", + "ferr", "ppi", "debug"; + clocks = <&cpg CPG_MOD R9A07G044_MIPI_DSI_PLLCLK>, + <&cpg CPG_MOD R9A07G044_MIPI_DSI_SYSCLK>, + <&cpg CPG_MOD R9A07G044_MIPI_DSI_ACLK>, + <&cpg CPG_MOD R9A07G044_MIPI_DSI_PCLK>, + <&cpg CPG_MOD R9A07G044_MIPI_DSI_VCLK>, + <&cpg CPG_MOD R9A07G044_MIPI_DSI_LPCLK>; + clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk", "lpclk"; + resets = <&cpg R9A07G044_MIPI_DSI_CMN_RSTB>, + <&cpg R9A07G044_MIPI_DSI_ARESET_N>, + <&cpg R9A07G044_MIPI_DSI_PRESET_N>; + reset-names = "rst", "arst", "prst"; + power-domains = <&cpg>; + + panel@0 { + compatible = "rocktech,jh057n00900"; + reg = <0>; + vcc-supply = <®_2v8_p>; + iovcc-supply = <®_1v8_p>; + reset-gpios = <&gpio3 13 GPIO_ACTIVE_LOW>; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi1_out>; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi1_in: endpoint { + remote-endpoint = <&du_out_dsi1>; + }; + }; + + port@1 { + reg = <1>; + dsi1_out: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&panel_in>; + }; + }; + }; + }; ... diff --git a/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi83.yaml b/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi83.yaml index bad6f5c81b06..e69b6343a8eb 100644 --- a/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi83.yaml +++ b/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi83.yaml @@ -35,6 +35,9 @@ properties: vcc-supply: description: A 1.8V power supply (see regulator/regulator.yaml). + interrupts: + maxItems: 1 + ports: $ref: /schemas/graph.yaml#/properties/ports @@ -115,15 +118,11 @@ $defs: ti,lvds-vod-swing-clock-microvolt: description: LVDS diferential output voltage <min max> for clock lanes in microvolts. - $ref: /schemas/types.yaml#/definitions/uint32-array - minItems: 2 maxItems: 2 ti,lvds-vod-swing-data-microvolt: description: LVDS diferential output voltage <min max> for data lanes in microvolts. - $ref: /schemas/types.yaml#/definitions/uint32-array - minItems: 2 maxItems: 2 allOf: diff --git a/Documentation/devicetree/bindings/display/fsl,tcon.txt b/Documentation/devicetree/bindings/display/fsl,tcon.txt deleted file mode 100644 index 475008747801..000000000000 --- a/Documentation/devicetree/bindings/display/fsl,tcon.txt +++ /dev/null @@ -1,17 +0,0 @@ -Device Tree bindings for Freescale TCON Driver - -Required properties: -- compatible: Should be one of - * "fsl,vf610-tcon". - -- reg: Address and length of the register set for tcon. -- clocks: From common clock binding: handle to tcon ipg clock. -- clock-names: From common clock binding: Shall be "ipg". - -Examples: -timing-controller@4003d000 { - compatible = "fsl,vf610-tcon"; - reg = <0x4003d000 0x1000>; - clocks = <&clks VF610_CLK_TCON0>; - clock-names = "ipg"; -}; diff --git a/Documentation/devicetree/bindings/display/fsl,vf610-tcon.yaml b/Documentation/devicetree/bindings/display/fsl,vf610-tcon.yaml new file mode 100644 index 000000000000..06bd680524a5 --- /dev/null +++ b/Documentation/devicetree/bindings/display/fsl,vf610-tcon.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/fsl,vf610-tcon.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale TCON + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +properties: + compatible: + const: fsl,vf610-tcon + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: ipg + +required: + - compatible + - reg + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/vf610-clock.h> + + timing-controller@4003d000 { + compatible = "fsl,vf610-tcon"; + reg = <0x4003d000 0x1000>; + clocks = <&clks VF610_CLK_TCON0>; + clock-names = "ipg"; + }; diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx-display-subsystem.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx-display-subsystem.yaml new file mode 100644 index 000000000000..92a0a797d099 --- /dev/null +++ b/Documentation/devicetree/bindings/display/imx/fsl,imx-display-subsystem.yaml @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/imx/fsl,imx-display-subsystem.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX DRM master device + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +description: + The freescale i.MX DRM master device is a virtual device needed to list all + IPU or other display interface nodes that comprise the graphics subsystem. + +properties: + compatible: + const: fsl,imx-display-subsystem + + ports: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + Should contain a list of phandles pointing to camera + sensor interface ports of IPU devices. + +required: + - compatible + +additionalProperties: false + +examples: + - | + display-subsystem { + compatible = "fsl,imx-display-subsystem"; + ports = <&ipu_di0>; + }; diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx-parallel-display.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx-parallel-display.yaml new file mode 100644 index 000000000000..bbcfe7e2958b --- /dev/null +++ b/Documentation/devicetree/bindings/display/imx/fsl,imx-parallel-display.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/imx/fsl,imx-parallel-display.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Parallel display support + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +properties: + compatible: + const: fsl,imx-parallel-display + + interface-pix-fmt: + $ref: /schemas/types.yaml#/definitions/string + enum: + - rgb24 + - rgb565 + - bgr666 + - lvds666 + + ddc: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle describing the i2c bus handling the display data channel + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: input port connected to the IPU display interface + + port@1: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: output port connected to a panel + +required: + - compatible + +additionalProperties: false + +examples: + - | + display { + compatible = "fsl,imx-parallel-display"; + #address-cells = <1>; + #size-cells = <0>; + interface-pix-fmt = "rgb24"; + + port@0 { + reg = <0>; + + endpoint { + remote-endpoint = <&ipu_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + + endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx6q-ipu.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx6q-ipu.yaml new file mode 100644 index 000000000000..ec78645d4de0 --- /dev/null +++ b/Documentation/devicetree/bindings/display/imx/fsl,imx6q-ipu.yaml @@ -0,0 +1,97 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/imx/fsl,imx6q-ipu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX IPUv3 + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +properties: + compatible: + oneOf: + - enum: + - fsl,imx51-ipu + - fsl,imx53-ipu + - fsl,imx6q-ipu + - items: + - const: fsl,imx6qp-ipu + - const: fsl,imx6q-ipu + + reg: + maxItems: 1 + + interrupts: + minItems: 1 + maxItems: 2 + + clocks: + maxItems: 3 + + clock-names: + items: + - const: bus + - const: di0 + - const: di1 + + resets: + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + fsl,prg: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to prg node associated with this IPU instance + + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: CSI0 + + port@1: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: CSI1 + + port@2: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: DI0 + + port@3: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: DI1 + +required: + - compatible + - reg + - interrupts + - resets + +additionalProperties: false + +examples: + - | + display-controller@18000000 { + compatible = "fsl,imx53-ipu"; + reg = <0x18000000 0x080000000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <11 10>; + resets = <&src 2>; + + port@2 { + reg = <2>; + + endpoint { + remote-endpoint = <&display_in>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx6q-ldb.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx6q-ldb.yaml new file mode 100644 index 000000000000..1646f41d8f72 --- /dev/null +++ b/Documentation/devicetree/bindings/display/imx/fsl,imx6q-ldb.yaml @@ -0,0 +1,193 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/imx/fsl,imx6q-ldb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale LVDS Display Bridge (ldb) + +description: + The LVDS Display Bridge device tree node contains up to two lvds-channel + nodes describing each of the two LVDS encoder channels of the bridge. + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +properties: + compatible: + oneOf: + - enum: + - fsl,imx53-ldb + - items: + - enum: + - fsl,imx6q-ldb + - const: fsl,imx53-ldb + + reg: + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + gpr: + $ref: /schemas/types.yaml#/definitions/phandle + description: + The phandle points to the iomuxc-gpr region containing the LVDS + control register. + + clocks: + minItems: 6 + maxItems: 8 + + clock-names: + oneOf: + - items: + - const: di0_pll + - const: di1_pll + - const: di0_sel + - const: di1_sel + - const: di0 + - const: di1 + - items: + - const: di0_pll + - const: di1_pll + - const: di0_sel + - const: di1_sel + - const: di2_sel + - const: di3_sel + - const: di0 + - const: di1 + + fsl,dual-channel: + $ref: /schemas/types.yaml#/definitions/flag + description: + if it exists, only LVDS channel 0 should + be configured - one input will be distributed on both outputs in dual + channel mode + +patternProperties: + '^lvds-channel@[0-1]$': + type: object + description: + Each LVDS Channel has to contain either an of graph link to a panel device node + or a display-timings node that describes the video timings for the connected + LVDS display as well as the fsl,data-mapping and fsl,data-width properties. + + properties: + reg: + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + display-timings: + $ref: /schemas/display/panel/display-timings.yaml# + + fsl,data-mapping: + enum: + - spwg + - jeida + + fsl,data-width: + $ref: /schemas/types.yaml#/definitions/uint32 + description: should be <18> or <24> + enum: + - 18 + - 24 + + fsl,panel: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to lcd panel + + patternProperties: + '^port@[0-4]$': + $ref: /schemas/graph.yaml#/properties/port + description: + On i.MX5, the internal two-input-multiplexer is used. Due to hardware + limitations, only one input port (port@[0,1]) can be used for each channel + (lvds-channel@[0,1], respectively). + On i.MX6, there should be four input ports (port@[0-3]) that correspond + to the four LVDS multiplexer inputs. + A single output port (port@2 on i.MX5, port@4 on i.MX6) must be connected + to a panel input port. Optionally, the output port can be left out if + display-timings are used instead. + + additionalProperties: false + +required: + - compatible + - gpr + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/imx5-clock.h> + + ldb@53fa8008 { + compatible = "fsl,imx53-ldb"; + reg = <0x53fa8008 0x4>; + #address-cells = <1>; + #size-cells = <0>; + gpr = <&gpr>; + clocks = <&clks IMX5_CLK_LDB_DI0_SEL>, + <&clks IMX5_CLK_LDB_DI1_SEL>, + <&clks IMX5_CLK_IPU_DI0_SEL>, + <&clks IMX5_CLK_IPU_DI1_SEL>, + <&clks IMX5_CLK_LDB_DI0_GATE>, + <&clks IMX5_CLK_LDB_DI1_GATE>; + clock-names = "di0_pll", "di1_pll", + "di0_sel", "di1_sel", + "di0", "di1"; + + /* Using an of-graph endpoint link to connect the panel */ + lvds-channel@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + endpoint { + remote-endpoint = <&ipu_di0_lvds0>; + }; + }; + + port@2 { + reg = <2>; + + endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + + /* Using display-timings and fsl,data-mapping/width instead */ + lvds-channel@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; + + display-timings {/* ... */ + }; + + port@1 { + reg = <1>; + + endpoint { + remote-endpoint = <&ipu_di1_lvds1>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx6qp-pre.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx6qp-pre.yaml new file mode 100644 index 000000000000..73bc73ff6e69 --- /dev/null +++ b/Documentation/devicetree/bindings/display/imx/fsl,imx6qp-pre.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/imx/fsl,imx6qp-pre.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX PRE (Prefetch Resolve Engine) + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +properties: + compatible: + const: fsl,imx6qp-pre + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: axi + fsl,iram: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle pointing to the mmio-sram device node, that should be + used for the PRE SRAM double buffer. + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/imx6qdl-clock.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + pre@21c8000 { + compatible = "fsl,imx6qp-pre"; + reg = <0x021c8000 0x1000>; + interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>; + clocks = <&clks IMX6QDL_CLK_PRE0>; + clock-names = "axi"; + fsl,iram = <&ocram2>; + }; diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx6qp-prg.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx6qp-prg.yaml new file mode 100644 index 000000000000..582da8c489f4 --- /dev/null +++ b/Documentation/devicetree/bindings/display/imx/fsl,imx6qp-prg.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/imx/fsl,imx6qp-prg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX PRG (Prefetch Resolve Gasket) + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +properties: + compatible: + const: fsl,imx6qp-prg + + reg: + maxItems: 1 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: ipg + - const: axi + + fsl,pres: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + maxItems: 1 + description: + phandles to the PRE units attached to this PRG, with the fixed + PRE as the first entry and the muxable PREs following. + +required: + - compatible + - reg + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/imx6qdl-clock.h> + + prg@21cc000 { + compatible = "fsl,imx6qp-prg"; + reg = <0x021cc000 0x1000>; + clocks = <&clks IMX6QDL_CLK_PRG0_APB>, <&clks IMX6QDL_CLK_PRG0_AXI>; + clock-names = "ipg", "axi"; + fsl,pres = <&pre1>, <&pre2>, <&pre3>; + }; + diff --git a/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt b/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt deleted file mode 100644 index 269b1ae2fca9..000000000000 --- a/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt +++ /dev/null @@ -1,160 +0,0 @@ -Freescale i.MX DRM master device -================================ - -The freescale i.MX DRM master device is a virtual device needed to list all -IPU or other display interface nodes that comprise the graphics subsystem. - -Required properties: -- compatible: Should be "fsl,imx-display-subsystem" -- ports: Should contain a list of phandles pointing to display interface ports - of IPU devices - -example: - -display-subsystem { - compatible = "fsl,imx-display-subsystem"; - ports = <&ipu_di0>; -}; - - -Freescale i.MX IPUv3 -==================== - -Required properties: -- compatible: Should be "fsl,<chip>-ipu" where <chip> is one of - - imx51 - - imx53 - - imx6q - - imx6qp -- reg: should be register base and length as documented in the - datasheet -- interrupts: Should contain sync interrupt and error interrupt, - in this order. -- resets: phandle pointing to the system reset controller and - reset line index, see reset/fsl,imx-src.txt for details -Additional required properties for fsl,imx6qp-ipu: -- fsl,prg: phandle to prg node associated with this IPU instance -Optional properties: -- port@[0-3]: Port nodes with endpoint definitions as defined in - Documentation/devicetree/bindings/media/video-interfaces.txt. - Ports 0 and 1 should correspond to CSI0 and CSI1, - ports 2 and 3 should correspond to DI0 and DI1, respectively. - -example: - -ipu: ipu@18000000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx53-ipu"; - reg = <0x18000000 0x080000000>; - interrupts = <11 10>; - resets = <&src 2>; - - ipu_di0: port@2 { - reg = <2>; - - ipu_di0_disp0: endpoint { - remote-endpoint = <&display_in>; - }; - }; -}; - -Freescale i.MX PRE (Prefetch Resolve Engine) -============================================ - -Required properties: -- compatible: should be "fsl,imx6qp-pre" -- reg: should be register base and length as documented in the - datasheet -- clocks : phandle to the PRE axi clock input, as described - in Documentation/devicetree/bindings/clock/clock-bindings.txt and - Documentation/devicetree/bindings/clock/imx6q-clock.yaml. -- clock-names: should be "axi" -- interrupts: should contain the PRE interrupt -- fsl,iram: phandle pointing to the mmio-sram device node, that should be - used for the PRE SRAM double buffer. - -example: - -pre@21c8000 { - compatible = "fsl,imx6qp-pre"; - reg = <0x021c8000 0x1000>; - interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>; - clocks = <&clks IMX6QDL_CLK_PRE0>; - clock-names = "axi"; - fsl,iram = <&ocram2>; -}; - -Freescale i.MX PRG (Prefetch Resolve Gasket) -============================================ - -Required properties: -- compatible: should be "fsl,imx6qp-prg" -- reg: should be register base and length as documented in the - datasheet -- clocks : phandles to the PRG ipg and axi clock inputs, as described - in Documentation/devicetree/bindings/clock/clock-bindings.txt and - Documentation/devicetree/bindings/clock/imx6q-clock.yaml. -- clock-names: should be "ipg" and "axi" -- fsl,pres: phandles to the PRE units attached to this PRG, with the fixed - PRE as the first entry and the muxable PREs following. - -example: - -prg@21cc000 { - compatible = "fsl,imx6qp-prg"; - reg = <0x021cc000 0x1000>; - clocks = <&clks IMX6QDL_CLK_PRG0_APB>, - <&clks IMX6QDL_CLK_PRG0_AXI>; - clock-names = "ipg", "axi"; - fsl,pres = <&pre1>, <&pre2>, <&pre3>; -}; - -Parallel display support -======================== - -Required properties: -- compatible: Should be "fsl,imx-parallel-display" -Optional properties: -- interface-pix-fmt: How this display is connected to the - display interface. Currently supported types: "rgb24", "rgb565", "bgr666" - and "lvds666". -- ddc: phandle describing the i2c bus handling the display data - channel -- port@[0-1]: Port nodes with endpoint definitions as defined in - Documentation/devicetree/bindings/media/video-interfaces.txt. - Port 0 is the input port connected to the IPU display interface, - port 1 is the output port connected to a panel. - -example: - -disp0 { - compatible = "fsl,imx-parallel-display"; - interface-pix-fmt = "rgb24"; - - port@0 { - reg = <0>; - - display_in: endpoint { - remote-endpoint = <&ipu_di0_disp0>; - }; - }; - - port@1 { - reg = <1>; - - display_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; -}; - -panel { - ... - - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/display/imx/ldb.txt b/Documentation/devicetree/bindings/display/imx/ldb.txt deleted file mode 100644 index 03653a291b54..000000000000 --- a/Documentation/devicetree/bindings/display/imx/ldb.txt +++ /dev/null @@ -1,146 +0,0 @@ -Device-Tree bindings for LVDS Display Bridge (ldb) - -LVDS Display Bridge -=================== - -The LVDS Display Bridge device tree node contains up to two lvds-channel -nodes describing each of the two LVDS encoder channels of the bridge. - -Required properties: - - #address-cells : should be <1> - - #size-cells : should be <0> - - compatible : should be "fsl,imx53-ldb" or "fsl,imx6q-ldb". - Both LDB versions are similar, but i.MX6 has an additional - multiplexer in the front to select any of the four IPU display - interfaces as input for each LVDS channel. - - gpr : should be <&gpr> on i.MX53 and i.MX6q. - The phandle points to the iomuxc-gpr region containing the LVDS - control register. -- clocks, clock-names : phandles to the LDB divider and selector clocks and to - the display interface selector clocks, as described in - Documentation/devicetree/bindings/clock/clock-bindings.txt - The following clocks are expected on i.MX53: - "di0_pll" - LDB LVDS channel 0 mux - "di1_pll" - LDB LVDS channel 1 mux - "di0" - LDB LVDS channel 0 gate - "di1" - LDB LVDS channel 1 gate - "di0_sel" - IPU1 DI0 mux - "di1_sel" - IPU1 DI1 mux - On i.MX6q the following additional clocks are needed: - "di2_sel" - IPU2 DI0 mux - "di3_sel" - IPU2 DI1 mux - The needed clock numbers for each are documented in - Documentation/devicetree/bindings/clock/imx5-clock.yaml, and in - Documentation/devicetree/bindings/clock/imx6q-clock.yaml. - -Optional properties: - - pinctrl-names : should be "default" on i.MX53, not used on i.MX6q - - pinctrl-0 : a phandle pointing to LVDS pin settings on i.MX53, - not used on i.MX6q - - fsl,dual-channel : boolean. if it exists, only LVDS channel 0 should - be configured - one input will be distributed on both outputs in dual - channel mode - -LVDS Channel -============ - -Each LVDS Channel has to contain either an of graph link to a panel device node -or a display-timings node that describes the video timings for the connected -LVDS display as well as the fsl,data-mapping and fsl,data-width properties. - -Required properties: - - reg : should be <0> or <1> - - port: Input and output port nodes with endpoint definitions as defined in - Documentation/devicetree/bindings/graph.txt. - On i.MX5, the internal two-input-multiplexer is used. Due to hardware - limitations, only one input port (port@[0,1]) can be used for each channel - (lvds-channel@[0,1], respectively). - On i.MX6, there should be four input ports (port@[0-3]) that correspond - to the four LVDS multiplexer inputs. - A single output port (port@2 on i.MX5, port@4 on i.MX6) must be connected - to a panel input port. Optionally, the output port can be left out if - display-timings are used instead. - -Optional properties (required if display-timings are used): - - display-timings : A node that describes the display timings as defined in - Documentation/devicetree/bindings/display/panel/display-timing.txt. - - fsl,data-mapping : should be "spwg" or "jeida" - This describes how the color bits are laid out in the - serialized LVDS signal. - - fsl,data-width : should be <18> or <24> - -example: - -gpr: iomuxc-gpr@53fa8000 { - /* ... */ -}; - -ldb: ldb@53fa8008 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx53-ldb"; - gpr = <&gpr>; - clocks = <&clks IMX5_CLK_LDB_DI0_SEL>, - <&clks IMX5_CLK_LDB_DI1_SEL>, - <&clks IMX5_CLK_IPU_DI0_SEL>, - <&clks IMX5_CLK_IPU_DI1_SEL>, - <&clks IMX5_CLK_LDB_DI0_GATE>, - <&clks IMX5_CLK_LDB_DI1_GATE>; - clock-names = "di0_pll", "di1_pll", - "di0_sel", "di1_sel", - "di0", "di1"; - - /* Using an of-graph endpoint link to connect the panel */ - lvds-channel@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - port@0 { - reg = <0>; - - lvds0_in: endpoint { - remote-endpoint = <&ipu_di0_lvds0>; - }; - }; - - port@2 { - reg = <2>; - - lvds0_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; - - /* Using display-timings and fsl,data-mapping/width instead */ - lvds-channel@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - fsl,data-mapping = "spwg"; - fsl,data-width = <24>; - - display-timings { - /* ... */ - }; - - port@1 { - reg = <1>; - - lvds1_in: endpoint { - remote-endpoint = <&ipu_di1_lvds1>; - }; - }; - }; -}; - -panel: lvds-panel { - /* ... */ - - port { - panel_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml index 5d2089dc596e..daf90ebb39bf 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml @@ -27,6 +27,10 @@ properties: - mediatek,mt8195-mdp3-aal - items: - enum: + - mediatek,mt8188-mdp3-aal + - const: mediatek,mt8195-mdp3-aal + - items: + - enum: - mediatek,mt2712-disp-aal - mediatek,mt6795-disp-aal - const: mediatek,mt8173-disp-aal diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml index 6160439ce4d7..5564f4063317 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml @@ -29,6 +29,10 @@ properties: - mediatek,mt8195-mdp3-color - items: - enum: + - mediatek,mt8188-mdp3-color + - const: mediatek,mt8195-mdp3-color + - items: + - enum: - mediatek,mt7623-disp-color - mediatek,mt2712-disp-color - const: mediatek,mt2701-disp-color diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml index 0f1e556dc8ef..b659d79393a8 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml @@ -27,6 +27,7 @@ properties: - mediatek,mt8188-dp-intf - mediatek,mt8192-dpi - mediatek,mt8195-dp-intf + - mediatek,mt8195-dpi - items: - enum: - mediatek,mt6795-dpi @@ -35,6 +36,10 @@ properties: - enum: - mediatek,mt8365-dpi - const: mediatek,mt8192-dpi + - items: + - enum: + - mediatek,mt8188-dpi + - const: mediatek,mt8195-dpi reg: maxItems: 1 @@ -116,11 +121,13 @@ examples: - | #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/mt8173-clk.h> + #include <dt-bindings/power/mt8173-power.h> dpi: dpi@1401d000 { compatible = "mediatek,mt8173-dpi"; reg = <0x1401d000 0x1000>; interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DPI_PIXEL>, <&mmsys CLK_MM_DPI_ENGINE>, <&apmixedsys CLK_APMIXED_TVDPLL>; diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml index 846de6c17d93..a5b88eb97e3b 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml @@ -22,6 +22,9 @@ properties: oneOf: - enum: - mediatek,mt8195-disp-dsc + - items: + - const: mediatek,mt8188-disp-dsc + - const: mediatek,mt8195-disp-dsc reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml index 0de9f64f3f84..3798a25402d3 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml @@ -26,6 +26,10 @@ properties: - mediatek,mt8195-disp-merge - mediatek,mt8195-mdp3-merge - items: + - enum: + - mediatek,mt8188-mdp3-merge + - const: mediatek,mt8195-mdp3-merge + - items: - const: mediatek,mt6795-disp-merge - const: mediatek,mt8173-disp-merge - items: diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml new file mode 100644 index 000000000000..bde4dc556d4f --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek HDMI MT8195 series HDMI Display Data Channel (DDC) + +maintainers: + - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> + - CK Hu <ck.hu@mediatek.com> + +properties: + compatible: + oneOf: + - const: mediatek,mt8195-hdmi-ddc + - items: + - const: mediatek,mt8188-hdmi-ddc + - const: mediatek,mt8195-hdmi-ddc + + clocks: + maxItems: 1 + + power-domains: + maxItems: 1 + +required: + - compatible + - clocks + +additionalProperties: false + +examples: + - | + hdmi { + hdmi_ddc: i2c { + compatible = "mediatek,mt8195-hdmi-ddc"; + clocks = <&clk26m>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml new file mode 100644 index 000000000000..1b382f99d3ce --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml @@ -0,0 +1,151 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,mt8195-hdmi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT8195 series HDMI-TX Encoder + +maintainers: + - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> + - CK Hu <ck.hu@mediatek.com> + +description: + The MediaTek HDMI-TX v2 encoder can generate HDMI format data based on + the HDMI Specification 2.0b. + +properties: + compatible: + enum: + - mediatek,mt8188-hdmi-tx + - mediatek,mt8195-hdmi-tx + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: HDMI Peripheral Bus (APB) clock + - description: HDCP and HDMI_TOP clock + - description: HDCP, HDMI_TOP and HDMI Audio reference clock + - description: VPP HDMI Split clock + + clock-names: + items: + - const: bus + - const: hdcp + - const: hdcp24m + - const: hdmi-split + + i2c: + type: object + $ref: /schemas/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml + unevaluatedProperties: false + description: HDMI DDC I2C controller + + phys: + maxItems: 1 + description: PHY providing clocking TMDS and pixel to controller + + phy-names: + items: + - const: hdmi + + power-domains: + maxItems: 1 + + '#sound-dai-cells': + const: 1 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: + Input port, usually connected to the output port of a DPI + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: + Output port that must be connected either to the input port of + a HDMI connector node containing a ddc-i2c-bus, or to the input + port of an attached bridge chip, such as a SlimPort transmitter. + + required: + - port@0 + - port@1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - power-domains + - phys + - phy-names + - ports + +allOf: + - $ref: /schemas/sound/dai-common.yaml# + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/mt8195-clk.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/mt8195-power.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + hdmi@1c300000 { + compatible = "mediatek,mt8195-hdmi-tx"; + reg = <0 0x1c300000 0 0x1000>; + clocks = <&topckgen CLK_TOP_HDMI_APB>, + <&topckgen CLK_TOP_HDCP>, + <&topckgen CLK_TOP_HDCP_24M>, + <&vppsys1 CLK_VPP1_VPP_SPLIT_HDMI>; + clock-names = "bus", "hdcp", "hdcp24m", "hdmi-split"; + interrupts = <GIC_SPI 677 IRQ_TYPE_LEVEL_HIGH 0>; + phys = <&hdmi_phy>; + phy-names = "hdmi"; + power-domains = <&spm MT8195_POWER_DOMAIN_HDMI_TX>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_pins>; + #sound-dai-cells = <1>; + + hdmitx_ddc: i2c { + compatible = "mediatek,mt8195-hdmi-ddc"; + clocks = <&clk26m>; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hdmi_in: endpoint { + remote-endpoint = <&dpi1_out>; + }; + }; + + port@1 { + reg = <1>; + + hdmi_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml index be07bbdc54e3..86787866ced0 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml @@ -20,9 +20,13 @@ description: properties: compatible: - enum: - - mediatek,mt8188-disp-padding - - mediatek,mt8195-mdp3-padding + oneOf: + - enum: + - mediatek,mt8188-disp-padding + - mediatek,mt8195-mdp3-padding + - items: + - const: mediatek,mt8188-mdp3-padding + - const: mediatek,mt8195-mdp3-padding reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml index e00b88332f2f..246bbb509bea 100644 --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml @@ -31,6 +31,7 @@ properties: - qcom,sm8650-dp - items: - enum: + - qcom,sar2130p-dp - qcom,sm6350-dp - qcom,sm8150-dp - qcom,sm8250-dp diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml index ffbd1dc9470e..82fe95a6d959 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml @@ -23,6 +23,8 @@ properties: - qcom,msm8996-dsi-ctrl - qcom,msm8998-dsi-ctrl - qcom,qcm2290-dsi-ctrl + - qcom,sa8775p-dsi-ctrl + - qcom,sar2130p-dsi-ctrl - qcom,sc7180-dsi-ctrl - qcom,sc7280-dsi-ctrl - qcom,sdm660-dsi-ctrl @@ -231,6 +233,7 @@ allOf: then: properties: clocks: + minItems: 7 maxItems: 7 clock-names: items: @@ -248,29 +251,12 @@ allOf: contains: enum: - qcom,msm8916-dsi-ctrl - then: - properties: - clocks: - maxItems: 6 - clock-names: - items: - - const: mdp_core - - const: iface - - const: bus - - const: byte - - const: pixel - - const: core - - - if: - properties: - compatible: - contains: - enum: - qcom,msm8953-dsi-ctrl - qcom,msm8976-dsi-ctrl then: properties: clocks: + minItems: 6 maxItems: 6 clock-names: items: @@ -291,6 +277,7 @@ allOf: then: properties: clocks: + minItems: 7 maxItems: 7 clock-names: items: @@ -311,6 +298,7 @@ allOf: then: properties: clocks: + minItems: 7 maxItems: 7 clock-names: items: @@ -328,28 +316,15 @@ allOf: contains: enum: - qcom,msm8998-dsi-ctrl - - qcom,sm6125-dsi-ctrl - - qcom,sm6350-dsi-ctrl - then: - properties: - clocks: - maxItems: 6 - clock-names: - items: - - const: byte - - const: byte_intf - - const: pixel - - const: core - - const: iface - - const: bus - - - if: - properties: - compatible: - contains: - enum: + - qcom,sa8775p-dsi-ctrl + - qcom,sar2130p-dsi-ctrl - qcom,sc7180-dsi-ctrl - qcom,sc7280-dsi-ctrl + - qcom,sdm845-dsi-ctrl + - qcom,sm6115-dsi-ctrl + - qcom,sm6125-dsi-ctrl + - qcom,sm6350-dsi-ctrl + - qcom,sm6375-dsi-ctrl - qcom,sm6150-dsi-ctrl - qcom,sm7150-dsi-ctrl - qcom,sm8150-dsi-ctrl @@ -361,6 +336,7 @@ allOf: then: properties: clocks: + minItems: 6 maxItems: 6 clock-names: items: @@ -380,6 +356,7 @@ allOf: then: properties: clocks: + minItems: 9 maxItems: 9 clock-names: items: @@ -393,27 +370,6 @@ allOf: - const: pixel - const: core - - if: - properties: - compatible: - contains: - enum: - - qcom,sdm845-dsi-ctrl - - qcom,sm6115-dsi-ctrl - - qcom,sm6375-dsi-ctrl - then: - properties: - clocks: - maxItems: 6 - clock-names: - items: - - const: byte - - const: byte_intf - - const: pixel - - const: core - - const: iface - - const: bus - unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml index 321470435e65..3c75ff42999a 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml @@ -17,6 +17,8 @@ properties: enum: - qcom,dsi-phy-7nm - qcom,dsi-phy-7nm-8150 + - qcom,sa8775p-dsi-phy-5nm + - qcom,sar2130p-dsi-phy-5nm - qcom,sc7280-dsi-phy-7nm - qcom,sm6375-dsi-phy-7nm - qcom,sm8350-dsi-phy-5nm diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-common.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-common.yaml index 6b57ce41c95f..d0ce85a08b6d 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-phy-common.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-common.yaml @@ -15,6 +15,8 @@ description: properties: "#clock-cells": const: 1 + description: + See include/dt-bindings/clock/qcom,dsi-phy-28nm.h for clock IDs. "#phy-cells": const: 0 diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml b/Documentation/devicetree/bindings/display/msm/gmu.yaml index ab884e236429..4392aa7a4ffe 100644 --- a/Documentation/devicetree/bindings/display/msm/gmu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gmu.yaml @@ -123,6 +123,7 @@ allOf: compatible: contains: enum: + - qcom,adreno-gmu-623.0 - qcom,adreno-gmu-635.0 - qcom,adreno-gmu-660.1 - qcom,adreno-gmu-663.0 diff --git a/Documentation/devicetree/bindings/display/msm/hdmi.yaml b/Documentation/devicetree/bindings/display/msm/hdmi.yaml index d4a2033afea8..dfec6c3480f3 100644 --- a/Documentation/devicetree/bindings/display/msm/hdmi.yaml +++ b/Documentation/devicetree/bindings/display/msm/hdmi.yaml @@ -66,21 +66,6 @@ properties: maxItems: 1 description: hpd pin - qcom,hdmi-tx-mux-en-gpios: - maxItems: 1 - deprecated: true - description: HDMI mux enable pin - - qcom,hdmi-tx-mux-sel-gpios: - maxItems: 1 - deprecated: true - description: HDMI mux select pin - - qcom,hdmi-tx-mux-lpm-gpios: - maxItems: 1 - deprecated: true - description: HDMI mux lpm pin - '#sound-dai-cells': const: 1 @@ -89,12 +74,12 @@ properties: $ref: /schemas/graph.yaml#/properties/ports properties: port@0: - $ref: /schemas/graph.yaml#/$defs/port-base + $ref: /schemas/graph.yaml#/properties/port description: | Input endpoints of the controller. port@1: - $ref: /schemas/graph.yaml#/$defs/port-base + $ref: /schemas/graph.yaml#/properties/port description: | Output endpoints of the controller. diff --git a/Documentation/devicetree/bindings/display/msm/mdp4.yaml b/Documentation/devicetree/bindings/display/msm/mdp4.yaml index 35204a287579..03ee09faa335 100644 --- a/Documentation/devicetree/bindings/display/msm/mdp4.yaml +++ b/Documentation/devicetree/bindings/display/msm/mdp4.yaml @@ -18,9 +18,10 @@ properties: clocks: minItems: 6 - maxItems: 6 + maxItems: 8 clock-names: + minItems: 6 items: - const: core_clk - const: iface_clk @@ -28,6 +29,12 @@ properties: - const: lut_clk - const: hdmi_clk - const: tv_clk + - const: lcdc_clk + - const: pxo + description: XO used to drive the internal LVDS PLL + + '#clock-cells': + const: 0 reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml index 7c6462caa442..db9c43b20e2a 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml @@ -84,6 +84,18 @@ properties: items: - description: MDSS_CORE reset + interconnects: + minItems: 1 + items: + - description: Interconnect path from mdp0 (or a single mdp) port to the data bus + - description: Interconnect path from CPU to the reg bus + + interconnect-names: + minItems: 1 + items: + - const: mdp0-mem + - const: cpu-cfg + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml index a90a8b3f1a9e..1053b3bc4908 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml @@ -52,6 +52,24 @@ patternProperties: items: - const: qcom,sa8775p-dp + "^dsi@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + contains: + const: qcom,sa8775p-dsi-ctrl + + "^phy@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + contains: + enum: + - qcom,sa8775p-dsi-phy-5nm + - qcom,sa8775p-edp-phy + required: - compatible @@ -61,6 +79,7 @@ examples: - | #include <dt-bindings/interconnect/qcom,icc.h> #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/qcom,sa8775p-dispcc.h> #include <dt-bindings/clock/qcom,sa8775p-gcc.h> #include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h> #include <dt-bindings/power/qcom,rpmhpd.h> @@ -131,6 +150,20 @@ examples: remote-endpoint = <&mdss0_dp0_in>; }; }; + + port@1 { + reg = <1>; + dpu_intf1_out: endpoint { + remote-endpoint = <&mdss0_dsi0_in>; + }; + }; + + port@2 { + reg = <2>; + dpu_intf2_out: endpoint { + remote-endpoint = <&mdss0_dsi1_in>; + }; + }; }; mdss0_mdp_opp_table: opp-table { @@ -158,6 +191,180 @@ examples: }; }; + mdss0_dp0_phy: phy@aec2a00 { + compatible = "qcom,sa8775p-edp-phy"; + + reg = <0x0aec2a00 0x200>, + <0x0aec2200 0xd0>, + <0x0aec2600 0xd0>, + <0x0aec2000 0x1c8>; + + clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>; + clock-names = "aux", + "cfg_ahb"; + + #clock-cells = <1>; + #phy-cells = <0>; + + vdda-phy-supply = <&vreg_l1c>; + vdda-pll-supply = <&vreg_l4a>; + }; + + dsi@ae94000 { + compatible = "qcom,sa8775p-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x0ae94000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispc_byte_clk>, + <&dispcc_intf_clk>, + <&dispcc_pclk>, + <&dispcc_esc_clk>, + <&dispcc_ahb_clk>, + <&gcc_bus_clk>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + assigned-clocks = <&dispcc_byte_clk>, + <&dispcc_pclk>; + assigned-clock-parents = <&mdss0_dsi0_phy 0>, <&mdss0_dsi0_phy 1>; + phys = <&mdss0_dsi0_phy>; + + operating-points-v2 = <&dsi0_opp_table>; + power-domains = <&rpmhpd SA8775P_MMCX>; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss0_dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + mdss0_dsi0_out: endpoint { }; + }; + }; + + dsi0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + mdss0_dsi0_phy: phy@ae94400 { + compatible = "qcom,sa8775p-dsi-phy-5nm"; + reg = <0x0ae94400 0x200>, + <0x0ae94600 0x280>, + <0x0ae94900 0x27c>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc_iface_clk>, + <&rpmhcc_ref_clk>; + clock-names = "iface", "ref"; + + vdds-supply = <&vreg_dsi_supply>; + }; + + dsi@ae96000 { + compatible = "qcom,sa8775p-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x0ae96000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispc_byte_clk>, + <&dispcc_intf_clk>, + <&dispcc_pclk>, + <&dispcc_esc_clk>, + <&dispcc_ahb_clk>, + <&gcc_bus_clk>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + assigned-clocks = <&dispcc_byte_clk>, + <&dispcc_pclk>; + assigned-clock-parents = <&mdss0_dsi1_phy 0>, <&mdss0_dsi1_phy 1>; + phys = <&mdss0_dsi1_phy>; + + operating-points-v2 = <&dsi1_opp_table>; + power-domains = <&rpmhpd SA8775P_MMCX>; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss0_dsi1_in: endpoint { + remote-endpoint = <&dpu_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + mdss0_dsi1_out: endpoint { }; + }; + }; + + dsi1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + mdss0_dsi1_phy: phy@ae96400 { + compatible = "qcom,sa8775p-dsi-phy-5nm"; + reg = <0x0ae96400 0x200>, + <0x0ae96600 0x280>, + <0x0ae96900 0x27c>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc_iface_clk>, + <&rpmhcc_ref_clk>; + clock-names = "iface", "ref"; + + vdds-supply = <&vreg_dsi_supply>; + }; + displayport-controller@af54000 { compatible = "qcom,sa8775p-dp"; @@ -186,9 +393,9 @@ examples: assigned-clocks = <&dispcc_mdss_dptx0_link_clk_src>, <&dispcc_mdss_dptx0_pixel0_clk_src>; - assigned-clock-parents = <&mdss0_edp_phy 0>, <&mdss0_edp_phy 1>; + assigned-clock-parents = <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>; - phys = <&mdss0_edp_phy>; + phys = <&mdss0_dp0_phy>; phy-names = "dp"; operating-points-v2 = <&dp_opp_table>; diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sar2130p-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sar2130p-mdss.yaml new file mode 100644 index 000000000000..870144b53cec --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,sar2130p-mdss.yaml @@ -0,0 +1,439 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sar2130p-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SAR2130P Display MDSS + +maintainers: + - Dmitry Baryshkov <lumag@kernel.org> + +description: + SAR2310P MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like + DPU display controller, DSI and DP interfaces etc. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + const: qcom,sar2130p-mdss + + clocks: + items: + - description: Display MDSS AHB + - description: Display AHB + - description: Display hf AXI + - description: Display core + + iommus: + maxItems: 1 + + interconnects: + items: + - description: Interconnect path from mdp0 port to the data bus + - description: Interconnect path from CPU to the reg bus + + interconnect-names: + items: + - const: mdp0-mem + - const: cpu-cfg + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + const: qcom,sar2130p-dpu + + "^displayport-controller@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + contains: + const: qcom,sar2130p-dp + + "^dsi@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + contains: + const: qcom,sar2130p-dsi-ctrl + + "^phy@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + const: qcom,sar2130p-dsi-phy-5nm + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/qcom,rpmhpd.h> + #include <dt-bindings/phy/phy-qcom-qmp.h> + + display-subsystem@ae00000 { + compatible = "qcom,sar2130p-mdss"; + reg = <0x0ae00000 0x1000>; + reg-names = "mdss"; + + interconnects = <&mmss_noc_master_mdp &mc_virt_slave_ebi1>, + <&gem_noc_master_appss_proc &config_noc_slave_display_cfg>; + interconnect-names = "mdp0-mem", "cpu-cfg"; + + resets = <&dispcc_disp_cc_mdss_core_bcr>; + + power-domains = <&dispcc_mdss_gdsc>; + + clocks = <&dispcc_disp_cc_mdss_ahb_clk>, + <&gcc_gcc_disp_ahb_clk>, + <&gcc_gcc_disp_hf_axi_clk>, + <&dispcc_disp_cc_mdss_mdp_clk>; + clock-names = "iface", "bus", "nrt_bus", "core"; + + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x1c00 0x2>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + display-controller@ae01000 { + compatible = "qcom,sar2130p-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc_gcc_disp_ahb_clk>, + <&gcc_gcc_disp_hf_axi_clk>, + <&dispcc_disp_cc_mdss_ahb_clk>, + <&dispcc_disp_cc_mdss_mdp_lut_clk>, + <&dispcc_disp_cc_mdss_mdp_clk>, + <&dispcc_disp_cc_mdss_vsync_clk>; + clock-names = "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc_disp_cc_mdss_vsync_clk>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dpu_intf0_out: endpoint { + remote-endpoint = <&mdss_dp0_in>; + }; + }; + + port@1 { + reg = <1>; + + dpu_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; + }; + + port@2 { + reg = <2>; + + dpu_intf2_out: endpoint { + remote-endpoint = <&mdss_dsi1_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-325000000 { + opp-hz = /bits/ 64 <325000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-375000000 { + opp-hz = /bits/ 64 <375000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-514000000 { + opp-hz = /bits/ 64 <514000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + displayport-controller@ae90000 { + compatible = "qcom,sar2130p-dp", + "qcom,sm8350-dp"; + reg = <0xae90000 0x200>, + <0xae90200 0x200>, + <0xae90400 0xc00>, + <0xae91000 0x400>, + <0xae91400 0x400>; + + interrupt-parent = <&mdss>; + interrupts = <12>; + clocks = <&dispcc_disp_cc_mdss_ahb_clk>, + <&dispcc_disp_cc_mdss_dptx0_aux_clk>, + <&dispcc_disp_cc_mdss_dptx0_link_clk>, + <&dispcc_disp_cc_mdss_dptx0_link_intf_clk>, + <&dispcc_disp_cc_mdss_dptx0_pixel0_clk>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks = <&dispcc_disp_cc_mdss_dptx0_link_clk_src>, + <&dispcc_disp_cc_mdss_dptx0_pixel0_clk_src>; + assigned-clock-parents = <&usb_dp_qmpphy_QMP_USB43DP_DP_LINK_CLK>, + <&usb_dp_qmpphy_QMP_USB43DP_DP_VCO_DIV_CLK>; + + phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + operating-points-v2 = <&dp_opp_table>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dp0_in: endpoint { + remote-endpoint = <&dpu_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dp0_out: endpoint { + remote-endpoint = <&usb_dp_qmpphy_dp_in>; + }; + }; + }; + + dp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-162000000 { + opp-hz = /bits/ 64 <162000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + dsi@ae94000 { + compatible = "qcom,sar2130p-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; + reg = <0x0ae94000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc_disp_cc_mdss_byte0_clk>, + <&dispcc_disp_cc_mdss_byte0_intf_clk>, + <&dispcc_disp_cc_mdss_pclk0_clk>, + <&dispcc_disp_cc_mdss_esc0_clk>, + <&dispcc_disp_cc_mdss_ahb_clk>, + <&gcc_gcc_disp_hf_axi_clk>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc_disp_cc_mdss_byte0_clk_src>, + <&dispcc_disp_cc_mdss_pclk0_clk_src>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&mdss_dsi0_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dsi0_out: endpoint { + }; + }; + }; + + dsi_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + mdss_dsi0_phy: phy@ae94400 { + compatible = "qcom,sar2130p-dsi-phy-5nm"; + reg = <0x0ae95000 0x200>, + <0x0ae95200 0x280>, + <0x0ae95500 0x400>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc_disp_cc_mdss_ahb_clk>, + <&rpmhcc_rpmh_cxo_clk>; + clock-names = "iface", "ref"; + }; + + dsi@ae96000 { + compatible = "qcom,sar2130p-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; + reg = <0x0ae96000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <5>; + + clocks = <&dispcc_disp_cc_mdss_byte1_clk>, + <&dispcc_disp_cc_mdss_byte1_intf_clk>, + <&dispcc_disp_cc_mdss_pclk1_clk>, + <&dispcc_disp_cc_mdss_esc1_clk>, + <&dispcc_disp_cc_mdss_ahb_clk>, + <&gcc_gcc_disp_hf_axi_clk>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc_disp_cc_mdss_byte1_clk_src>, + <&dispcc_disp_cc_mdss_pclk1_clk_src>; + assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&mdss_dsi1_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dsi1_in: endpoint { + remote-endpoint = <&dpu_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dsi1_out: endpoint { + }; + }; + }; + }; + + mdss_dsi1_phy: phy@ae97000 { + compatible = "qcom,sar2130p-dsi-phy-5nm"; + reg = <0x0ae97000 0x200>, + <0x0ae97200 0x280>, + <0x0ae97500 0x400>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc_disp_cc_mdss_ahb_clk>, + <&rpmhcc_rpmh_cxo_clk>; + clock-names = "iface", "ref"; + }; + }; +... diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml index 6902795b4e2c..df9ec15ad6c3 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml @@ -17,6 +17,7 @@ $ref: /schemas/display/msm/dpu-common.yaml# properties: compatible: enum: + - qcom,sar2130p-dpu - qcom,sc7280-dpu - qcom,sc8280xp-dpu - qcom,sm8350-dpu diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml index 163fc83c1e80..68176de854b3 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml @@ -38,12 +38,16 @@ properties: maxItems: 1 interconnects: - maxItems: 2 + items: + - description: Interconnect path from the MDP0 port to the data bus + - description: Interconnect path from the MDP1 port to the data bus + - description: Interconnect path from the CPU to the reg bus interconnect-names: items: - const: mdp0-mem - const: mdp1-mem + - const: cpu-cfg patternProperties: "^display-controller@[0-9a-f]+$": @@ -88,6 +92,7 @@ examples: #include <dt-bindings/clock/qcom,gcc-sm8350.h> #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interconnect/qcom,icc.h> #include <dt-bindings/interconnect/qcom,sm8350.h> #include <dt-bindings/power/qcom,rpmhpd.h> @@ -97,8 +102,10 @@ examples: reg-names = "mdss"; interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, - <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; - interconnect-names = "mdp0-mem", "mdp1-mem"; + <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "mdp0-mem", "mdp1-mem", "cpu-cfg"; power-domains = <&dispcc MDSS_GDSC>; resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8550-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8550-mdss.yaml index 1ea50a2c7c8e..59192c59ddb9 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8550-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8550-mdss.yaml @@ -30,10 +30,14 @@ properties: maxItems: 1 interconnects: - maxItems: 2 + items: + - description: Interconnect path from mdp0 port to the data bus + - description: Interconnect path from CPU to the reg bus interconnect-names: - maxItems: 2 + items: + - const: mdp0-mem + - const: cpu-cfg patternProperties: "^display-controller@[0-9a-f]+$": @@ -91,9 +95,9 @@ examples: reg = <0x0ae00000 0x1000>; reg-names = "mdss"; - interconnects = <&mmss_noc MASTER_MDP 0 &gem_noc SLAVE_LLCC 0>, - <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; - interconnect-names = "mdp0-mem", "mdp1-mem"; + interconnects = <&mmss_noc MASTER_MDP 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_DISPLAY_CFG 0>; + interconnect-names = "mdp0-mem", "cpu-cfg"; resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8650-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8650-mdss.yaml index 24cece1e888b..a1c53e191033 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8650-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8650-mdss.yaml @@ -29,10 +29,14 @@ properties: maxItems: 1 interconnects: - maxItems: 2 + items: + - description: Interconnect path from mdp0 port to the data bus + - description: Interconnect path from CPU to the reg bus interconnect-names: - maxItems: 2 + items: + - const: mdp0-mem + - const: cpu-cfg patternProperties: "^display-controller@[0-9a-f]+$": @@ -75,12 +79,17 @@ examples: #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/power/qcom,rpmhpd.h> + #include <dt-bindings/interconnect/qcom,sm8650-rpmh.h> display-subsystem@ae00000 { compatible = "qcom,sm8650-mdss"; reg = <0x0ae00000 0x1000>; reg-names = "mdss"; + interconnects = <&mmss_noc MASTER_MDP 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_DISPLAY_CFG 0>; + interconnect-names = "mdp0-mem", "cpu-cfg"; + resets = <&dispcc_core_bcr>; power-domains = <&dispcc_gdsc>; diff --git a/Documentation/devicetree/bindings/display/panel/apple,summit.yaml b/Documentation/devicetree/bindings/display/panel/apple,summit.yaml new file mode 100644 index 000000000000..f081755325e9 --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/apple,summit.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/apple,summit.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Apple "Summit" display panel + +maintainers: + - Sasha Finkelstein <fnkl.kernel@gmail.com> + +description: + An OLED panel used as a touchbar on certain Apple laptops. + Contains a backlight device, which controls brightness of the panel itself. + The backlight common properties are included for this reason + +allOf: + - $ref: panel-common.yaml# + - $ref: /schemas/leds/backlight/common.yaml# + +properties: + compatible: + items: + - enum: + - apple,j293-summit + - apple,j493-summit + - const: apple,summit + + reg: + maxItems: 1 + +required: + - compatible + - reg + - max-brightness + - port + +unevaluatedProperties: false + +examples: + - | + dsi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "apple,j293-summit", "apple,summit"; + reg = <0>; + max-brightness = <255>; + + port { + endpoint { + remote-endpoint = <&dfr_bridge_out>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/display/panel/boe,td4320.yaml b/Documentation/devicetree/bindings/display/panel/boe,td4320.yaml new file mode 100644 index 000000000000..c6bff0ece360 --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/boe,td4320.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/boe,td4320.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: BOE TD4320 MIPI-DSI panels + +maintainers: + - Barnabas Czeman <barnabas.czeman@mainlining.org> + +description: + BOE TD4320 6.3" 1080x2340 panel found in Xiaomi Redmi Note 7 smartphone. + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + items: + - const: boe,td4320 + + reg: + maxItems: 1 + + iovcc-supply: + description: I/O voltage rail + + vsn-supply: + description: Negative source voltage rail + + vsp-supply: + description: Positive source voltage rail + +required: + - compatible + - reg + - reset-gpios + - port + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + dsi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "boe,td4320"; + reg = <0>; + backlight = <&backlight>; + reset-gpios = <&tlmm 45 GPIO_ACTIVE_LOW>; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/display/panel/himax,hx8279.yaml b/Documentation/devicetree/bindings/display/panel/himax,hx8279.yaml new file mode 100644 index 000000000000..f619aea82bdf --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/himax,hx8279.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/himax,hx8279.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Himax HX8279/HX8279-D based MIPI-DSI panels + +maintainers: + - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> + +description: + The Himax HX8279 is a 1803 channel outputs source driver with MIPI + TCON, which generates the horizontal and vertical control timing to + the source and gate drivers. + This DriverIC is most suitable for 1200x1920, 1080x1920, 1200x1600, + and 600x1024 panels and outputs full RGB888 over two or four lanes, + single or dual, MIPI-DSI video interface. + +allOf: + - $ref: panel-common-dual.yaml# + +properties: + compatible: + items: + - enum: + - aoly,sl101pm1794fog-v15 + - startek,kd070fhfid078 + - const: himax,hx8279 + + reg: + maxItems: 1 + + iovcc-supply: + description: I/O voltage supply + + vdd-supply: + description: Panel power supply + +required: + - compatible + - reg + - backlight + - reset-gpios + - iovcc-supply + - vdd-supply + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + dsi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "startek,kd070fhfid078", "himax,hx8279"; + reg = <0>; + backlight = <&backlight>; + enable-gpios = <&pio 25 GPIO_ACTIVE_HIGH>; + reset-gpios = <&pio 45 GPIO_ACTIVE_HIGH>; + iovcc-supply = <&vreg_lcm_vio>; + vdd-supply = <&vreg_lcm_vdd>; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/display/panel/himax,hx83102.yaml b/Documentation/devicetree/bindings/display/panel/himax,hx83102.yaml index c649fb085833..e4c1aa5deab9 100644 --- a/Documentation/devicetree/bindings/display/panel/himax,hx83102.yaml +++ b/Documentation/devicetree/bindings/display/panel/himax,hx83102.yaml @@ -18,8 +18,14 @@ properties: - enum: # Boe nv110wum-l60 11.0" WUXGA TFT LCD panel - boe,nv110wum-l60 + # CSOT pna957qt1-1 10.95" WUXGA TFT LCD panel + - csot,pna957qt1-1 # IVO t109nw41 11.0" WUXGA TFT LCD panel - ivo,t109nw41 + # KINGDISPLAY KD110N11-51IE 10.95" WUXGA TFT LCD panel + - kingdisplay,kd110n11-51ie + # STARRY 2082109QFH040022-50E 10.95" WUXGA TFT LCD panel + - starry,2082109qfh040022-50e # STARRY himax83102-j02 10.51" WUXGA TFT LCD panel - starry,himax83102-j02 - const: himax,hx83102 diff --git a/Documentation/devicetree/bindings/display/panel/leadtek,ltk050h3146w.yaml b/Documentation/devicetree/bindings/display/panel/leadtek,ltk050h3146w.yaml index e2a2dd4ef5fa..5fcea62fd58f 100644 --- a/Documentation/devicetree/bindings/display/panel/leadtek,ltk050h3146w.yaml +++ b/Documentation/devicetree/bindings/display/panel/leadtek,ltk050h3146w.yaml @@ -23,6 +23,7 @@ properties: maxItems: 1 backlight: true + port: true reset-gpios: true iovcc-supply: description: regulator that supplies the iovcc voltage diff --git a/Documentation/devicetree/bindings/display/panel/leadtek,ltk500hd1829.yaml b/Documentation/devicetree/bindings/display/panel/leadtek,ltk500hd1829.yaml index af9e0ea0e72f..b0e2c82232d3 100644 --- a/Documentation/devicetree/bindings/display/panel/leadtek,ltk500hd1829.yaml +++ b/Documentation/devicetree/bindings/display/panel/leadtek,ltk500hd1829.yaml @@ -22,6 +22,7 @@ properties: maxItems: 1 backlight: true + port: true reset-gpios: true iovcc-supply: description: regulator that supplies the iovcc voltage diff --git a/Documentation/devicetree/bindings/display/panel/lg,sw43408.yaml b/Documentation/devicetree/bindings/display/panel/lg,sw43408.yaml index bbaaa783d184..2219d3d4ac43 100644 --- a/Documentation/devicetree/bindings/display/panel/lg,sw43408.yaml +++ b/Documentation/devicetree/bindings/display/panel/lg,sw43408.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: LG SW43408 1080x2160 DSI panel maintainers: - - Caleb Connolly <caleb.connolly@linaro.org> + - Casey Connolly <casey.connolly@linaro.org> description: This panel is used on the Pixel 3, it is a 60hz OLED panel which diff --git a/Documentation/devicetree/bindings/display/panel/mitsubishi,aa104xd12.yaml b/Documentation/devicetree/bindings/display/panel/mitsubishi,aa104xd12.yaml index 3623ffa6518d..96621b89ae9e 100644 --- a/Documentation/devicetree/bindings/display/panel/mitsubishi,aa104xd12.yaml +++ b/Documentation/devicetree/bindings/display/panel/mitsubishi,aa104xd12.yaml @@ -33,7 +33,9 @@ properties: description: Reference to the regulator powering the panel VCC pins. data-mapping: - const: jeida-24 + enum: + - jeida-18 + - jeida-24 width-mm: const: 210 @@ -41,6 +43,7 @@ properties: height-mm: const: 158 + backlight: true panel-timing: true port: true @@ -48,7 +51,6 @@ additionalProperties: false required: - compatible - - vcc-supply - data-mapping - width-mm - height-mm diff --git a/Documentation/devicetree/bindings/display/panel/novatek,nt37801.yaml b/Documentation/devicetree/bindings/display/panel/novatek,nt37801.yaml new file mode 100644 index 000000000000..1b38c1d0af68 --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/novatek,nt37801.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/novatek,nt37801.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Novatek NT37801 AMOLED DSI Panel + +maintainers: + - Krzysztof Kozlowski <krzk@kernel.org> + +description: + Naming is inconclusive and different sources claim this is either Novatek + NT37801 or NT37810 AMOLED DSI Panel. + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + const: novatek,nt37801 + + reg: + maxItems: 1 + description: DSI virtual channel + + vci-supply: true + vdd-supply: true + vddio-supply: true + port: true + reset-gpios: true + +required: + - compatible + - reg + - vci-supply + - vdd-supply + - vddio-supply + - port + - reset-gpios + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + dsi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "novatek,nt37801"; + reg = <0>; + + vci-supply = <&vreg_l13b_3p0>; + vdd-supply = <&vreg_l11b_1p2>; + vddio-supply = <&vreg_l12b_1p8>; + + reset-gpios = <&tlmm 98 GPIO_ACTIVE_LOW>; + + port { + endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/display/panel/panel-simple-lvds-dual-ports.yaml b/Documentation/devicetree/bindings/display/panel/panel-simple-lvds-dual-ports.yaml index e80fc7006984..548f5ac14500 100644 --- a/Documentation/devicetree/bindings/display/panel/panel-simple-lvds-dual-ports.yaml +++ b/Documentation/devicetree/bindings/display/panel/panel-simple-lvds-dual-ports.yaml @@ -40,6 +40,8 @@ properties: - auo,g185han01 # AU Optronics Corporation 19.0" (1280x1024) TFT LCD panel - auo,g190ean01 + # BOE AV123Z7M-N17 12.3" (1920x720) LVDS TFT LCD panel + - boe,av123z7m-n17 # Kaohsiung Opto-Electronics Inc. 10.1" WUXGA (1920 x 1200) LVDS TFT LCD panel - koe,tx26d202vm0bwa # Lincoln Technology Solutions, LCD185-101CT 10.1" TFT 1920x1200 diff --git a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml index e3ee3a332bb7..5542c9229d54 100644 --- a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml +++ b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml @@ -63,6 +63,8 @@ properties: - auo,t215hvn01 # Shanghai AVIC Optoelectronics 7" 1024x600 color TFT-LCD panel - avic,tm070ddh03 + # BOE AV101HDT-a10 10.1" 1280x720 LVDS panel + - boe,av101hdt-a10 # BOE BP082WX1-100 8.2" WXGA (1280x800) LVDS panel - boe,bp082wx1-100 # BOE BP101WX1-100 10.1" WXGA (1280x800) LVDS panel @@ -224,6 +226,8 @@ properties: - netron-dy,e231732 # Newhaven Display International 480 x 272 TFT LCD panel - newhaven,nhd-4.3-480272ef-atxl + # NLT Technologies, Ltd. 15.6" WXGA (1366×768) LVDS TFT LCD panel + - nlt,nl13676bc25-03f # New Vision Display 7.0" 800 RGB x 480 TFT LCD panel - nvd,9128 # OKAYA Electric America, Inc. RS800480T-7X0GP 7" WVGA LCD panel @@ -244,6 +248,8 @@ properties: - osddisplays,osd070t1718-19ts # One Stop Displays OSD101T2045-53TS 10.1" 1920x1200 panel - osddisplays,osd101t2045-53ts + # POWERTIP PH128800T004-ZZA01 10.1" WXGA TFT LCD panel + - powertip,ph128800t004-zza01 # POWERTIP PH128800T006-ZHC01 10.1" WXGA TFT LCD panel - powertip,ph128800t006-zhc01 # POWERTIP PH800480T013-IDF2 7.0" WVGA TFT LCD panel @@ -282,6 +288,8 @@ properties: - startek,kd070wvfpa # Team Source Display Technology TST043015CMHX 4.3" WQVGA TFT LCD panel - team-source-display,tst043015cmhx + # Tianma Micro-electronics P0700WXF1MBAA 7.0" WXGA (1280x800) LVDS TFT LCD panel + - tianma,p0700wxf1mbaa # Tianma Micro-electronics TM070JDHG30 7.0" WXGA TFT LCD panel - tianma,tm070jdhg30 # Tianma Micro-electronics TM070JDHG34-00 7.0" WXGA (1280x800) LVDS TFT LCD panel diff --git a/Documentation/devicetree/bindings/display/panel/raydium,rm67200.yaml b/Documentation/devicetree/bindings/display/panel/raydium,rm67200.yaml new file mode 100644 index 000000000000..54c9c0ef45ec --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/raydium,rm67200.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/raydium,rm67200.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Raydium RM67200 based MIPI-DSI panels + +maintainers: + - Sebastian Reichel <sebastian.reichel@collabora.com> + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + items: + - enum: + - wanchanglong,w552793baa + - const: raydium,rm67200 + + reg: + maxItems: 1 + + vdd-supply: + description: 2.8V Logic voltage + + iovcc-supply: + description: 1.8V IO voltage + + vsp-supply: + description: positive 5.5V voltage + + vsn-supply: + description: negative 5.5V voltage + + backlight: true + port: true + reset-gpios: true + +required: + - compatible + - port + - reg + - reset-gpios + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + dsi { + #address-cells = <1>; + #size-cells = <0>; + panel@0 { + compatible = "wanchanglong,w552793baa", "raydium,rm67200"; + reg = <0>; + + vdd-supply = <®ulator1>; + iovcc-supply = <®ulator2>; + vsp-supply = <®ulator3>; + vsn-supply = <®ulator4>; + reset-gpios = <&gpiobank 42 GPIO_ACTIVE_LOW>; + + port { + panel0_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/display/panel/samsung,atna33xc20.yaml b/Documentation/devicetree/bindings/display/panel/samsung,atna33xc20.yaml index 684c2896d238..31f0c0f038e4 100644 --- a/Documentation/devicetree/bindings/display/panel/samsung,atna33xc20.yaml +++ b/Documentation/devicetree/bindings/display/panel/samsung,atna33xc20.yaml @@ -19,6 +19,8 @@ properties: - const: samsung,atna33xc20 - items: - enum: + # Samsung 14" WQXGA+ (2880×1800 pixels) eDP AMOLED panel + - samsung,atna40yk20 # Samsung 14.5" WQXGA+ (2880x1800 pixels) eDP AMOLED panel - samsung,atna45af01 # Samsung 14.5" 3K (2944x1840 pixels) eDP AMOLED panel diff --git a/Documentation/devicetree/bindings/display/panel/truly,nt35597-2K-display.yaml b/Documentation/devicetree/bindings/display/panel/truly,nt35597-2K-display.yaml new file mode 100644 index 000000000000..36be09c900f2 --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/truly,nt35597-2K-display.yaml @@ -0,0 +1,97 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/truly,nt35597-2K-display.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Truly NT35597 DSI 2K display + +maintainers: + - Neil Armstrong <neil.armstrong@linaro.org> + +description: | + Truly NT35597 DSI 2K display is used on the Qualcomm SDM845 MTP board. + +allOf: + - $ref: panel-common-dual.yaml# + +properties: + compatible: + const: truly,nt35597-2K-display + + reg: + maxItems: 1 + + vdda-supply: + description: regulator that provides the supply voltage Power IC supply + + vdispp-supply: + description: regulator that provides the supply voltage for positive LCD bias + + vdispn-supply: + description: regulator that provides the supply voltage for negative LCD bias + + reset-gpios: true + + mode-gpios: + description: + Gpio for choosing the mode of the display for single DSI or Dual DSI. + This should be low for dual DSI and high for single DSI mode. + + ports: + required: + - port@0 + - port@1 + +required: + - compatible + - reg + - vdda-supply + - reset-gpios + - mode-gpios + - ports + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + dsi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "truly,nt35597-2K-display"; + reg = <0>; + + vdda-supply = <&pm8998_l14>; + vdispp-supply = <&lab_regulator>; + vdispn-supply = <&ibb_regulator>; + + reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; + mode-gpios = <&tlmm 52 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + panel0_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + + panel1_in: endpoint { + remote-endpoint = <&dsi1_out>; + }; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/display/panel/visionox,g2647fb105.yaml b/Documentation/devicetree/bindings/display/panel/visionox,g2647fb105.yaml new file mode 100644 index 000000000000..49dcd9b8f670 --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/visionox,g2647fb105.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/visionox,g2647fb105.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Visionox G2647FB105 6.47" 1080x2340 MIPI-DSI Panel + +maintainers: + - Alexander Baransky <sanyapilot496@gmail.com> + +description: + The Visionox G2647FB105 is a 6.47 inch 1080x2340 MIPI-DSI CMD mode OLED panel. + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + const: visionox,g2647fb105 + + reg: + maxItems: 1 + + vdd3p3-supply: + description: 3.3V source voltage rail + + vddio-supply: + description: I/O source voltage rail + + vsn-supply: + description: Negative source voltage rail + + vsp-supply: + description: Positive source voltage rail + + reset-gpios: true + port: true + +required: + - compatible + - reg + - vdd3p3-supply + - vddio-supply + - vsn-supply + - vsp-supply + - reset-gpios + - port + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + dsi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "visionox,g2647fb105"; + reg = <0>; + + vdd3p3-supply = <&vreg_l7c_3p0>; + vddio-supply = <&vreg_l13a_1p8>; + vsn-supply = <&vreg_ibb>; + vsp-supply = <&vreg_lab>; + + reset-gpios = <&pm6150l_gpios 9 GPIO_ACTIVE_LOW>; + + port { + panel_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/display/panel/visionox,rm692e5.yaml b/Documentation/devicetree/bindings/display/panel/visionox,rm692e5.yaml new file mode 100644 index 000000000000..d4b4672815fe --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/visionox,rm692e5.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/visionox,rm692e5.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Visionox RM692E5 6.55" 2400x1080 120Hz MIPI-DSI Panel + +maintainers: + - Danila Tikhonov <danila@jiaxyga.com> + +description: + The Visionox RM692E5 is a generic DSI Panel IC used to control + AMOLED panels. + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + oneOf: + - enum: + - visionox,rm692e5 + - items: + - enum: + - nothing,rm692e5-spacewar + - const: visionox,rm692e5 + + reg: + maxItems: 1 + + vdd-supply: + description: 3.3V source voltage rail + + vddio-supply: + description: 1.8V I/O source voltage rail + + reset-gpios: true + port: true + +required: + - compatible + - reg + - reset-gpios + - vdd-supply + - vddio-supply + - port + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + dsi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "nothing,rm692e5-spacewar", + "visionox,rm692e5"; + reg = <0>; + + reset-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>; + + vdd-supply = <&vdd_oled>; + vddio-supply = <&vdd_io_oled>; + + port { + panel_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/display/renesas,du.yaml b/Documentation/devicetree/bindings/display/renesas,du.yaml index 3880b4c2ea9a..c27dfea7fc62 100644 --- a/Documentation/devicetree/bindings/display/renesas,du.yaml +++ b/Documentation/devicetree/bindings/display/renesas,du.yaml @@ -47,12 +47,26 @@ properties: maxItems: 1 # See compatible-specific constraints below. - clocks: true - clock-names: true + clocks: + minItems: 1 + maxItems: 8 + + clock-names: + minItems: 1 + maxItems: 8 + interrupts: + minItems: 1 + maxItems: 4 description: Interrupt specifiers, one per DU channel - resets: true - reset-names: true + + resets: + minItems: 1 + maxItems: 2 + + reset-names: + minItems: 1 + maxItems: 2 power-domains: maxItems: 1 @@ -74,7 +88,7 @@ properties: renesas,cmms: $ref: /schemas/types.yaml#/definitions/phandle-array - minItems: 1 + minItems: 2 maxItems: 4 items: maxItems: 1 @@ -174,6 +188,7 @@ allOf: - pattern: '^dclkin\.[01]$' interrupts: + minItems: 2 maxItems: 2 resets: @@ -229,6 +244,7 @@ allOf: - pattern: '^dclkin\.[01]$' interrupts: + minItems: 2 maxItems: 2 resets: @@ -282,6 +298,7 @@ allOf: - pattern: '^dclkin\.[01]$' interrupts: + minItems: 2 maxItems: 2 resets: @@ -336,6 +353,7 @@ allOf: - pattern: '^dclkin\.[01]$' interrupts: + minItems: 2 maxItems: 2 resets: @@ -397,6 +415,7 @@ allOf: - pattern: '^dclkin\.[012]$' interrupts: + minItems: 3 maxItems: 3 resets: @@ -461,9 +480,11 @@ allOf: - pattern: '^dclkin\.[0123]$' interrupts: + minItems: 4 maxItems: 4 resets: + minItems: 2 maxItems: 2 reset-names: @@ -534,9 +555,11 @@ allOf: - pattern: '^dclkin\.[012]$' interrupts: + minItems: 3 maxItems: 3 resets: + minItems: 2 maxItems: 2 reset-names: @@ -605,9 +628,11 @@ allOf: - pattern: '^dclkin\.[013]$' interrupts: + minItems: 3 maxItems: 3 resets: + minItems: 2 maxItems: 2 reset-names: @@ -726,6 +751,7 @@ allOf: - pattern: '^dclkin\.[01]$' interrupts: + minItems: 2 maxItems: 2 resets: diff --git a/Documentation/devicetree/bindings/display/rockchip/cdn-dp-rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/cdn-dp-rockchip.txt deleted file mode 100644 index 8df7d2e393d6..000000000000 --- a/Documentation/devicetree/bindings/display/rockchip/cdn-dp-rockchip.txt +++ /dev/null @@ -1,74 +0,0 @@ -Rockchip RK3399 specific extensions to the cdn Display Port -================================ - -Required properties: -- compatible: must be "rockchip,rk3399-cdn-dp" - -- reg: physical base address of the controller and length - -- clocks: from common clock binding: handle to dp clock. - -- clock-names: from common clock binding: - Required elements: "core-clk" "pclk" "spdif" "grf" - -- resets : a list of phandle + reset specifier pairs -- reset-names : string of reset names - Required elements: "apb", "core", "dptx", "spdif" -- power-domains : power-domain property defined with a phandle - to respective power domain. -- assigned-clocks: main clock, should be <&cru SCLK_DP_CORE> -- assigned-clock-rates : the DP core clk frequency, shall be: 100000000 - -- rockchip,grf: this soc should set GRF regs, so need get grf here. - -- ports: contain a port nodes with endpoint definitions as defined in - Documentation/devicetree/bindings/media/video-interfaces.txt. - contained 2 endpoints, connecting to the output of vop. - -- phys: from general PHY binding: the phandle for the PHY device. - -- extcon: extcon specifier for the Power Delivery - -- #sound-dai-cells = it must be 1 if your system is using 2 DAIs: I2S, SPDIF - -------------------------------------------------------------------------------- - -Example: - cdn_dp: dp@fec00000 { - compatible = "rockchip,rk3399-cdn-dp"; - reg = <0x0 0xfec00000 0x0 0x100000>; - interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>, - <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>; - clock-names = "core-clk", "pclk", "spdif", "grf"; - assigned-clocks = <&cru SCLK_DP_CORE>; - assigned-clock-rates = <100000000>; - power-domains = <&power RK3399_PD_HDCP>; - phys = <&tcphy0_dp>, <&tcphy1_dp>; - resets = <&cru SRST_DPTX_SPDIF_REC>; - reset-names = "spdif"; - extcon = <&fusb0>, <&fusb1>; - rockchip,grf = <&grf>; - #address-cells = <1>; - #size-cells = <0>; - #sound-dai-cells = <1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - dp_in: port { - #address-cells = <1>; - #size-cells = <0>; - dp_in_vopb: endpoint@0 { - reg = <0>; - remote-endpoint = <&vopb_out_dp>; - }; - - dp_in_vopl: endpoint@1 { - reg = <1>; - remote-endpoint = <&vopl_out_dp>; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,analogix-dp.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,analogix-dp.yaml index 60dedf9b2be7..d99b23b88cc5 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip,analogix-dp.yaml +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,analogix-dp.yaml @@ -15,6 +15,7 @@ properties: enum: - rockchip,rk3288-dp - rockchip,rk3399-edp + - rockchip,rk3588-edp clocks: minItems: 2 @@ -31,16 +32,23 @@ properties: maxItems: 1 resets: - maxItems: 1 + minItems: 1 + maxItems: 2 reset-names: - const: dp + minItems: 1 + items: + - const: dp + - const: apb rockchip,grf: $ref: /schemas/types.yaml#/definitions/phandle description: This SoC makes use of GRF regs. + aux-bus: + $ref: /schemas/display/dp-aux-bus.yaml# + required: - compatible - clocks @@ -52,6 +60,19 @@ required: allOf: - $ref: /schemas/display/bridge/analogix,dp.yaml# + - if: + properties: + compatible: + contains: + enum: + - rockchip,rk3588-edp + then: + properties: + resets: + minItems: 2 + reset-names: + minItems: 2 + unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,inno-hdmi.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,inno-hdmi.yaml index 5b87b0f1963e..290376bec079 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip,inno-hdmi.yaml +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,inno-hdmi.yaml @@ -23,13 +23,11 @@ properties: maxItems: 1 clocks: - minItems: 1 items: - description: The HDMI controller main clock - description: The HDMI PHY reference clock clock-names: - minItems: 1 items: - const: pclk - const: ref @@ -58,6 +56,12 @@ properties: - port@0 - port@1 + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to GRF used for control the polarity of hsync/vsync of rk3036 + HDMI. + required: - compatible - reg @@ -77,6 +81,8 @@ allOf: const: rockchip,rk3036-inno-hdmi then: + required: + - rockchip,grf properties: power-domains: false @@ -87,11 +93,6 @@ allOf: const: rockchip,rk3128-inno-hdmi then: - properties: - clocks: - minItems: 2 - clock-names: - minItems: 2 required: - power-domains @@ -106,10 +107,11 @@ examples: compatible = "rockchip,rk3036-inno-hdmi"; reg = <0x20034000 0x4000>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_HDMI>; - clock-names = "pclk"; + clocks = <&cru PCLK_HDMI>, <&cru SCLK_LCDC>; + clock-names = "pclk", "ref"; pinctrl-names = "default"; pinctrl-0 = <&hdmi_ctl>; + rockchip,grf = <&grf>; #sound-dai-cells = <0>; ports { diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,rk3399-cdn-dp.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,rk3399-cdn-dp.yaml new file mode 100644 index 000000000000..1a33128e77f5 --- /dev/null +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,rk3399-cdn-dp.yaml @@ -0,0 +1,170 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/rockchip/rockchip,rk3399-cdn-dp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip RK3399 specific extensions to the CDN Display Port + +maintainers: + - Andy Yan <andy.yan@rock-chip.com> + - Heiko Stuebner <heiko@sntech.de> + - Sandy Huang <hjc@rock-chips.com> + +allOf: + - $ref: /schemas/sound/dai-common.yaml# + +properties: + compatible: + items: + - const: rockchip,rk3399-cdn-dp + + reg: + maxItems: 1 + + clocks: + items: + - description: DP core work clock + - description: APB clock + - description: SPDIF interface clock + - description: GRF clock + + clock-names: + items: + - const: core-clk + - const: pclk + - const: spdif + - const: grf + + extcon: + $ref: /schemas/types.yaml#/definitions/phandle-array + minItems: 1 + items: + - description: Extcon device providing the cable state for DP PHY device 0 + - description: Extcon device providing the cable state for DP PHY device 1 + description: + List of phandle to the extcon device providing the cable state for the DP PHY. + + interrupts: + maxItems: 1 + + phys: + minItems: 1 + items: + - description: DP output to the DP PHY device 0 + - description: DP output to the DP PHY device 1 + description: + RK3399 have two DP-USB PHY, specifying one PHY which want to use, or + specify two PHYs here to let the driver determine which PHY to use. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: Input of the CDN DP + + properties: + endpoint@0: + description: Connection to the VOPB + + endpoint@1: + description: Connection to the VOPL + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: Output of the CDN DP + + required: + - port@0 + - port@1 + + power-domains: + maxItems: 1 + + resets: + maxItems: 4 + + reset-names: + items: + - const: spdif + - const: dptx + - const: apb + - const: core + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to GRF register to control HPD. + + "#sound-dai-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - phys + - ports + - resets + - reset-names + - rockchip,grf + - "#sound-dai-cells" + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/rk3399-cru.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/rk3399-power.h> + soc { + #address-cells = <2>; + #size-cells = <2>; + + dp@fec00000 { + compatible = "rockchip,rk3399-cdn-dp"; + reg = <0x0 0xfec00000 0x0 0x100000>; + assigned-clocks = <&cru SCLK_DP_CORE>; + assigned-clock-rates = <100000000>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>, <&cru SCLK_SPDIF_REC_DPTX>, + <&cru PCLK_VIO_GRF>; + clock-names = "core-clk", "pclk", "spdif", "grf"; + power-domains = <&power RK3399_PD_HDCP>; + phys = <&tcphy0_dp>, <&tcphy1_dp>; + resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>, + <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>; + reset-names = "spdif", "dptx", "apb", "core"; + rockchip,grf = <&grf>; + #sound-dai-cells = <1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + dp_in: port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + dp_in_vopb: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_dp>; + }; + + dp_in_vopl: endpoint@1 { + reg = <1>; + remote-endpoint = <&vopl_out_dp>; + }; + }; + + dp_out: port@1 { + reg = <1>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,rk3588-dw-hdmi-qp.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,rk3588-dw-hdmi-qp.yaml index d8e761865f27..96b4b088eebe 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip,rk3588-dw-hdmi-qp.yaml +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,rk3588-dw-hdmi-qp.yaml @@ -29,6 +29,7 @@ allOf: properties: compatible: enum: + - rockchip,rk3576-dw-hdmi-qp - rockchip,rk3588-dw-hdmi-qp reg: @@ -156,7 +157,7 @@ examples: <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH 0>, <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH 0>; interrupt-names = "avp", "cec", "earc", "main", "hpd"; - phys = <&hdptxphy_hdmi0>; + phys = <&hdptxphy0>; power-domains = <&power RK3588_PD_VO1>; resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMIHDP0>; reset-names = "ref", "hdp"; diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.yaml index b339b7e708c6..8b5f58103dda 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.yaml +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.yaml @@ -73,12 +73,6 @@ properties: port: $ref: /schemas/graph.yaml#/properties/port - assigned-clocks: - maxItems: 2 - - assigned-clock-rates: - maxItems: 2 - iommus: maxItems: 1 diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml index 2531726af306..f546d481b7e5 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml @@ -14,12 +14,14 @@ description: maintainers: - Sandy Huang <hjc@rock-chips.com> - Heiko Stuebner <heiko@sntech.de> + - Andy Yan <andyshrk@163.com> properties: compatible: enum: - rockchip,rk3566-vop - rockchip,rk3568-vop + - rockchip,rk3576-vop - rockchip,rk3588-vop reg: @@ -37,10 +39,21 @@ properties: - const: gamma-lut interrupts: - maxItems: 1 + minItems: 1 + maxItems: 4 description: - The VOP interrupt is shared by several interrupt sources, such as - frame start (VSYNC), line flag and other status interrupts. + For VOP version under rk3576, the interrupt is shared by several interrupt + sources, such as frame start (VSYNC), line flag and other interrupt status. + For VOP version from rk3576 there is a system interrupt for bus error, and + every video port has it's independent interrupts for vsync and other video + port related error interrupts. + + interrupt-names: + items: + - const: sys + - const: vp0 + - const: vp1 + - const: vp2 # See compatible-specific constraints below. clocks: @@ -53,6 +66,8 @@ properties: - description: Pixel clock for video port 2. - description: Pixel clock for video port 3. - description: Peripheral(vop grf/dsi) clock. + - description: Alternative pixel clock provided by HDMI0 PHY PLL. + - description: Alternative pixel clock provided by HDMI1 PHY PLL. clock-names: minItems: 5 @@ -64,6 +79,8 @@ properties: - const: dclk_vp2 - const: dclk_vp3 - const: pclk_vop + - const: pll_hdmiphy0 + - const: pll_hdmiphy1 rockchip,grf: $ref: /schemas/types.yaml#/definitions/phandle @@ -120,43 +137,100 @@ allOf: properties: compatible: contains: - const: rockchip,rk3588-vop + enum: + - rockchip,rk3566-vop + - rockchip,rk3568-vop then: properties: clocks: - minItems: 7 + maxItems: 5 + clock-names: - minItems: 7 + maxItems: 5 + + interrupts: + maxItems: 1 + + interrupt-names: false ports: required: - port@0 - port@1 - port@2 - - port@3 + + rockchip,vo1-grf: false + rockchip,vop-grf: false + rockchip,pmu: false required: - rockchip,grf - - rockchip,vo1-grf - - rockchip,vop-grf - - rockchip,pmu - else: + - if: + properties: + compatible: + contains: + enum: + - rockchip,rk3576-vop + then: properties: + clocks: + maxItems: 5 + + clock-names: + maxItems: 5 + + interrupts: + minItems: 4 + + interrupt-names: + minItems: 4 + + ports: + required: + - port@0 + - port@1 + - port@2 + rockchip,vo1-grf: false rockchip,vop-grf: false - rockchip,pmu: false + required: + - rockchip,grf + - rockchip,pmu + + - if: + properties: + compatible: + contains: + const: rockchip,rk3588-vop + then: + properties: clocks: - maxItems: 5 + minItems: 7 + maxItems: 9 + clock-names: - maxItems: 5 + minItems: 7 + maxItems: 9 + + interrupts: + maxItems: 1 + + interrupt-names: false ports: required: - port@0 - port@1 - port@2 + - port@3 + + required: + - rockchip,grf + - rockchip,vo1-grf + - rockchip,vop-grf + - rockchip,pmu additionalProperties: false @@ -184,6 +258,7 @@ examples: "dclk_vp1", "dclk_vp2"; power-domains = <&power RK3568_PD_VO>; + rockchip,grf = <&grf>; iommus = <&vop_mmu>; vop_out: ports { #address-cells = <1>; diff --git a/Documentation/devicetree/bindings/display/sitronix,st7571.yaml b/Documentation/devicetree/bindings/display/sitronix,st7571.yaml new file mode 100644 index 000000000000..4fea782fccd7 --- /dev/null +++ b/Documentation/devicetree/bindings/display/sitronix,st7571.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/sitronix,st7571.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sitronix ST7571 Display Controller + +maintainers: + - Marcus Folkesson <marcus.folkesson@gmail.com> + +description: + Sitronix ST7571 is a driver and controller for 4-level gray + scale and monochrome dot matrix LCD panels. + +allOf: + - $ref: panel/panel-common.yaml# + +properties: + compatible: + const: sitronix,st7571 + + reg: + maxItems: 1 + + sitronix,grayscale: + type: boolean + description: + Display supports 4-level grayscale. + + reset-gpios: true + width-mm: true + height-mm: true + panel-timing: true + +required: + - compatible + - reg + - reset-gpios + - width-mm + - height-mm + - panel-timing + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + display@3f { + compatible = "sitronix,st7571"; + reg = <0x3f>; + reset-gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; + width-mm = <37>; + height-mm = <27>; + + panel-timing { + hactive = <128>; + vactive = <96>; + hback-porch = <0>; + vback-porch = <0>; + clock-frequency = <0>; + hfront-porch = <0>; + hsync-len = <0>; + vfront-porch = <0>; + vsync-len = <0>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-mipi.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-mipi.yaml index f448624dd779..193ddb105283 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-mipi.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-mipi.yaml @@ -17,6 +17,7 @@ properties: compatible: enum: - nvidia,tegra114-mipi + - nvidia,tegra124-mipi - nvidia,tegra210-mipi - nvidia,tegra186-mipi diff --git a/Documentation/devicetree/bindings/display/truly,nt35597.txt b/Documentation/devicetree/bindings/display/truly,nt35597.txt deleted file mode 100644 index f39c77ee36ea..000000000000 --- a/Documentation/devicetree/bindings/display/truly,nt35597.txt +++ /dev/null @@ -1,59 +0,0 @@ -Truly model NT35597 DSI display driver - -The Truly NT35597 is a generic display driver, currently only configured -for use in the 2K display on the Qualcomm SDM845 MTP board. - -Required properties: -- compatible: should be "truly,nt35597-2K-display" -- vdda-supply: phandle of the regulator that provides the supply voltage - Power IC supply -- vdispp-supply: phandle of the regulator that provides the supply voltage - for positive LCD bias -- vdispn-supply: phandle of the regulator that provides the supply voltage - for negative LCD bias -- reset-gpios: phandle of gpio for reset line - This should be 8mA, gpio can be configured using mux, pinctrl, pinctrl-names - (active low) -- mode-gpios: phandle of the gpio for choosing the mode of the display - for single DSI or Dual DSI - This should be low for dual DSI and high for single DSI mode -- ports: This device has two video ports driven by two DSIs. Their connections - are modeled using the OF graph bindings specified in - Documentation/devicetree/bindings/graph.txt. - - port@0: DSI input port driven by master DSI - - port@1: DSI input port driven by secondary DSI - -Example: - - dsi@ae94000 { - panel@0 { - compatible = "truly,nt35597-2K-display"; - reg = <0>; - vdda-supply = <&pm8998_l14>; - vdispp-supply = <&lab_regulator>; - vdispn-supply = <&ibb_regulator>; - pinctrl-names = "default", "suspend"; - pinctrl-0 = <&dpu_dsi_active>; - pinctrl-1 = <&dpu_dsi_suspend>; - - reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; - mode-gpios = <&tlmm 52 GPIO_ACTIVE_HIGH>; - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - panel0_in: endpoint { - remote-endpoint = <&dsi0_out>; - }; - }; - - port@1 { - reg = <1>; - panel1_in: endpoint { - remote-endpoint = <&dsi1_out>; - }; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/dma/arm,dma-350.yaml b/Documentation/devicetree/bindings/dma/arm,dma-350.yaml new file mode 100644 index 000000000000..429f682f15d8 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/arm,dma-350.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/arm,dma-350.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Arm CoreLink DMA-350 Controller + +maintainers: + - Robin Murphy <robin.murphy@arm.com> + +allOf: + - $ref: dma-controller.yaml# + +properties: + compatible: + const: arm,dma-350 + + reg: + items: + - description: Base and size of the full register map + + interrupts: + minItems: 1 + items: + - description: Channel 0 interrupt + - description: Channel 1 interrupt + - description: Channel 2 interrupt + - description: Channel 3 interrupt + - description: Channel 4 interrupt + - description: Channel 5 interrupt + - description: Channel 6 interrupt + - description: Channel 7 interrupt + + "#dma-cells": + const: 1 + description: The cell is the trigger input number + +required: + - compatible + - reg + - interrupts + +unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/dma/atmel,at91sam9g45-dma.yaml b/Documentation/devicetree/bindings/dma/atmel,at91sam9g45-dma.yaml new file mode 100644 index 000000000000..a58dc407311b --- /dev/null +++ b/Documentation/devicetree/bindings/dma/atmel,at91sam9g45-dma.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/atmel,at91sam9g45-dma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Atmel Direct Memory Access Controller (DMA) + +maintainers: + - Ludovic Desroches <ludovic.desroches@microchip.com> + +description: + The Atmel Direct Memory Access Controller (DMAC) transfers data from a source + peripheral to a destination peripheral over one or more AMBA buses. One channel + is required for each source/destination pair. In the most basic configuration, + the DMAC has one master interface and one channel. The master interface reads + the data from a source and writes it to a destination. Two AMBA transfers are + required for each DMAC data transfer. This is also known as a dual-access transfer. + The DMAC is programmed via the APB interface. + +properties: + compatible: + enum: + - atmel,at91sam9g45-dma + - atmel,at91sam9rl-dma + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + "#dma-cells": + description: + Must be <2>, used to represent the number of integer cells in the dma + property of client devices. The two cells in order are + 1. The first cell represents the channel number. + 2. The second cell is 0 for RX and 1 for TX transfers. + const: 2 + + clocks: + maxItems: 1 + + clock-names: + const: dma_clk + +required: + - compatible + - reg + - interrupts + - "#dma-cells" + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + dma-controller@ffffec00 { + compatible = "atmel,at91sam9g45-dma"; + reg = <0xffffec00 0x200>; + interrupts = <21>; + #dma-cells = <2>; + clocks = <&pmc 2 20>; + clock-names = "dma_clk"; + }; + +... diff --git a/Documentation/devicetree/bindings/dma/atmel,sama5d4-dma.yaml b/Documentation/devicetree/bindings/dma/atmel,sama5d4-dma.yaml index 9ca1c5d1f00f..73fc13b902b3 100644 --- a/Documentation/devicetree/bindings/dma/atmel,sama5d4-dma.yaml +++ b/Documentation/devicetree/bindings/dma/atmel,sama5d4-dma.yaml @@ -32,6 +32,9 @@ properties: - microchip,sam9x60-dma - microchip,sam9x7-dma - const: atmel,sama5d4-dma + - items: + - const: microchip,sama7d65-dma + - const: microchip,sama7g5-dma "#dma-cells": description: | diff --git a/Documentation/devicetree/bindings/dma/atmel-dma.txt b/Documentation/devicetree/bindings/dma/atmel-dma.txt deleted file mode 100644 index f69bcf5a6343..000000000000 --- a/Documentation/devicetree/bindings/dma/atmel-dma.txt +++ /dev/null @@ -1,42 +0,0 @@ -* Atmel Direct Memory Access Controller (DMA) - -Required properties: -- compatible: Should be "atmel,<chip>-dma". -- reg: Should contain DMA registers location and length. -- interrupts: Should contain DMA interrupt. -- #dma-cells: Must be <2>, used to represent the number of integer cells in -the dmas property of client devices. - -Example: - -dma0: dma@ffffec00 { - compatible = "atmel,at91sam9g45-dma"; - reg = <0xffffec00 0x200>; - interrupts = <21>; - #dma-cells = <2>; -}; - -DMA clients connected to the Atmel DMA controller must use the format -described in the dma.txt file, using a three-cell specifier for each channel: -a phandle plus two integer cells. -The three cells in order are: - -1. A phandle pointing to the DMA controller. -2. The memory interface (16 most significant bits), the peripheral interface -(16 less significant bits). -3. Parameters for the at91 DMA configuration register which are device -dependent: - - bit 7-0: peripheral identifier for the hardware handshaking interface. The - identifier can be different for tx and rx. - - bit 11-8: FIFO configuration. 0 for half FIFO, 1 for ALAP, 2 for ASAP. - -Example: - -i2c0@i2c@f8010000 { - compatible = "atmel,at91sam9x5-i2c"; - reg = <0xf8010000 0x100>; - interrupts = <9 4 6>; - dmas = <&dma0 1 7>, - <&dma0 1 8>; - dma-names = "tx", "rx"; -}; diff --git a/Documentation/devicetree/bindings/dma/fsl,edma.yaml b/Documentation/devicetree/bindings/dma/fsl,edma.yaml index 4f925469533e..fa4248e2f1b9 100644 --- a/Documentation/devicetree/bindings/dma/fsl,edma.yaml +++ b/Documentation/devicetree/bindings/dma/fsl,edma.yaml @@ -28,6 +28,14 @@ properties: - fsl,imx95-edma5 - nxp,s32g2-edma - items: + - enum: + - fsl,imx94-edma3 + - const: fsl,imx93-edma3 + - items: + - enum: + - fsl,imx94-edma5 + - const: fsl,imx95-edma5 + - items: - const: fsl,ls1028a-edma - const: fsl,vf610-edma - items: @@ -40,11 +48,11 @@ properties: interrupts: minItems: 1 - maxItems: 64 + maxItems: 65 interrupt-names: minItems: 1 - maxItems: 64 + maxItems: 65 "#dma-cells": description: | diff --git a/Documentation/devicetree/bindings/dma/fsl,elo-dma.yaml b/Documentation/devicetree/bindings/dma/fsl,elo-dma.yaml new file mode 100644 index 000000000000..92288d76d51b --- /dev/null +++ b/Documentation/devicetree/bindings/dma/fsl,elo-dma.yaml @@ -0,0 +1,137 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/fsl,elo-dma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale Elo DMA Controller + +maintainers: + - J. Neuschäfer <j.ne@posteo.net> + +description: + This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx + series chips such as mpc8315, mpc8349, mpc8379 etc. + +properties: + compatible: + items: + - enum: + - fsl,mpc8313-dma + - fsl,mpc8315-dma + - fsl,mpc8323-dma + - fsl,mpc8347-dma + - fsl,mpc8349-dma + - fsl,mpc8360-dma + - fsl,mpc8377-dma + - fsl,mpc8378-dma + - fsl,mpc8379-dma + - const: fsl,elo-dma + + reg: + items: + - description: + DMA General Status Register, i.e. DGSR which contains status for + all the 4 DMA channels. + + cell-index: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Controller index. 0 for controller @ 0x8100. + + ranges: true + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + interrupts: + maxItems: 1 + description: Controller interrupt. + +required: + - compatible + - reg + +patternProperties: + "^dma-channel@[0-9a-f]+$": + type: object + additionalProperties: false + + properties: + compatible: + oneOf: + # native DMA channel + - items: + - enum: + - fsl,mpc8315-dma-channel + - fsl,mpc8323-dma-channel + - fsl,mpc8347-dma-channel + - fsl,mpc8349-dma-channel + - fsl,mpc8360-dma-channel + - fsl,mpc8377-dma-channel + - fsl,mpc8378-dma-channel + - fsl,mpc8379-dma-channel + - const: fsl,elo-dma-channel + + # audio DMA channel, see fsl,ssi.yaml + - const: fsl,ssi-dma-channel + + reg: + maxItems: 1 + + cell-index: + description: DMA channel index starts at 0. + + interrupts: + maxItems: 1 + description: + Per-channel interrupt. Only necessary if no controller interrupt has + been provided. + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + dma@82a8 { + compatible = "fsl,mpc8349-dma", "fsl,elo-dma"; + reg = <0x82a8 4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x8100 0x1a4>; + interrupts = <71 IRQ_TYPE_LEVEL_LOW>; + cell-index = <0>; + + dma-channel@0 { + compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; + reg = <0 0x80>; + cell-index = <0>; + interrupts = <71 IRQ_TYPE_LEVEL_LOW>; + }; + + dma-channel@80 { + compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupts = <71 IRQ_TYPE_LEVEL_LOW>; + }; + + dma-channel@100 { + compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupts = <71 IRQ_TYPE_LEVEL_LOW>; + }; + + dma-channel@180 { + compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupts = <71 IRQ_TYPE_LEVEL_LOW>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/dma/fsl,elo3-dma.yaml b/Documentation/devicetree/bindings/dma/fsl,elo3-dma.yaml new file mode 100644 index 000000000000..0f5e475657a7 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/fsl,elo3-dma.yaml @@ -0,0 +1,125 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/fsl,elo3-dma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale Elo3 DMA Controller + +maintainers: + - J. Neuschäfer <j.ne@posteo.net> + +description: + DMA controller which has same function as EloPlus except that Elo3 has 8 + channels while EloPlus has only 4, it is used in Freescale Txxx and Bxxx + series chips, such as t1040, t4240, b4860. + +properties: + compatible: + const: fsl,elo3-dma + + reg: + items: + - description: + DMA General Status Registers starting from DGSR0, for channel 1~4 + - description: + DMA General Status Registers starting from DGSR1, for channel 5~8 + + ranges: true + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + interrupts: + maxItems: 1 + +patternProperties: + "^dma-channel@[0-9a-f]+$": + type: object + additionalProperties: false + + properties: + compatible: + enum: + # native DMA channel + - fsl,eloplus-dma-channel + + # audio DMA channel, see fsl,ssi.yaml + - fsl,ssi-dma-channel + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + description: + Per-channel interrupt. Only necessary if no controller interrupt has + been provided. + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + dma@100300 { + compatible = "fsl,elo3-dma"; + reg = <0x100300 0x4>, + <0x100600 0x4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x100100 0x500>; + + dma-channel@0 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + interrupts = <28 IRQ_TYPE_EDGE_FALLING 0 0>; + }; + + dma-channel@80 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + interrupts = <29 IRQ_TYPE_EDGE_FALLING 0 0>; + }; + + dma-channel@100 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + interrupts = <30 IRQ_TYPE_EDGE_FALLING 0 0>; + }; + + dma-channel@180 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + interrupts = <31 IRQ_TYPE_EDGE_FALLING 0 0>; + }; + + dma-channel@300 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x300 0x80>; + interrupts = <76 IRQ_TYPE_EDGE_FALLING 0 0>; + }; + + dma-channel@380 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x380 0x80>; + interrupts = <77 IRQ_TYPE_EDGE_FALLING 0 0>; + }; + + dma-channel@400 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x400 0x80>; + interrupts = <78 IRQ_TYPE_EDGE_FALLING 0 0>; + }; + + dma-channel@480 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x480 0x80>; + interrupts = <79 IRQ_TYPE_EDGE_FALLING 0 0>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/dma/fsl,eloplus-dma.yaml b/Documentation/devicetree/bindings/dma/fsl,eloplus-dma.yaml new file mode 100644 index 000000000000..8992f244c4db --- /dev/null +++ b/Documentation/devicetree/bindings/dma/fsl,eloplus-dma.yaml @@ -0,0 +1,132 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/fsl,eloplus-dma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale EloPlus DMA Controller + +maintainers: + - J. Neuschäfer <j.ne@posteo.net> + +description: + This is a 4-channel DMA controller with extended addresses and chaining, + mainly used in Freescale mpc85xx/86xx, Pxxx and BSC series chips, such as + mpc8540, mpc8641 p4080, bsc9131 etc. + +properties: + compatible: + oneOf: + - items: + - enum: + - fsl,mpc8540-dma + - fsl,mpc8541-dma + - fsl,mpc8548-dma + - fsl,mpc8555-dma + - fsl,mpc8560-dma + - fsl,mpc8572-dma + - fsl,mpc8641-dma + - const: fsl,eloplus-dma + - const: fsl,eloplus-dma + + reg: + items: + - description: + DMA General Status Register, i.e. DGSR which contains + status for all the 4 DMA channels + + cell-index: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + controller index. 0 for controller @ 0x21000, 1 for controller @ 0xc000 + + ranges: true + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + interrupts: + maxItems: 1 + description: Controller interrupt. + +patternProperties: + "^dma-channel@[0-9a-f]+$": + type: object + additionalProperties: false + + properties: + compatible: + oneOf: + # native DMA channel + - items: + - enum: + - fsl,mpc8540-dma-channel + - fsl,mpc8541-dma-channel + - fsl,mpc8548-dma-channel + - fsl,mpc8555-dma-channel + - fsl,mpc8560-dma-channel + - fsl,mpc8572-dma-channel + - const: fsl,eloplus-dma-channel + + # audio DMA channel, see fsl,ssi.yaml + - const: fsl,ssi-dma-channel + + reg: + maxItems: 1 + + cell-index: + description: DMA channel index starts at 0. + + interrupts: + maxItems: 1 + description: + Per-channel interrupt. Only necessary if no controller interrupt has + been provided. + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + dma@21300 { + compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma"; + reg = <0x21300 4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x21100 0x200>; + cell-index = <0>; + + dma-channel@0 { + compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel"; + reg = <0 0x80>; + cell-index = <0>; + interrupts = <20 IRQ_TYPE_EDGE_FALLING>; + }; + + dma-channel@80 { + compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupts = <21 IRQ_TYPE_EDGE_FALLING>; + }; + + dma-channel@100 { + compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupts = <22 IRQ_TYPE_EDGE_FALLING>; + }; + + dma-channel@180 { + compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupts = <23 IRQ_TYPE_EDGE_FALLING>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/dma/fsl,mxs-dma.yaml b/Documentation/devicetree/bindings/dma/fsl,mxs-dma.yaml index a17cf2360dd4..75a7d9556699 100644 --- a/Documentation/devicetree/bindings/dma/fsl,mxs-dma.yaml +++ b/Documentation/devicetree/bindings/dma/fsl,mxs-dma.yaml @@ -31,6 +31,12 @@ properties: - fsl,imx6q-dma-apbh - fsl,imx6sx-dma-apbh - fsl,imx7d-dma-apbh + - fsl,imx8dxl-dma-apbh + - fsl,imx8mm-dma-apbh + - fsl,imx8mn-dma-apbh + - fsl,imx8mp-dma-apbh + - fsl,imx8mq-dma-apbh + - fsl,imx8qm-dma-apbh - fsl,imx8qxp-dma-apbh - const: fsl,imx28-dma-apbh - enum: diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra20-apbdma.txt b/Documentation/devicetree/bindings/dma/nvidia,tegra20-apbdma.txt deleted file mode 100644 index 447fb44e7abe..000000000000 --- a/Documentation/devicetree/bindings/dma/nvidia,tegra20-apbdma.txt +++ /dev/null @@ -1,44 +0,0 @@ -* NVIDIA Tegra APB DMA controller - -Required properties: -- compatible: Should be "nvidia,<chip>-apbdma" -- reg: Should contain DMA registers location and length. This should include - all of the per-channel registers. -- interrupts: Should contain all of the per-channel DMA interrupts. -- clocks: Must contain one entry, for the module clock. - See ../clocks/clock-bindings.txt for details. -- resets : Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names : Must include the following entries: - - dma -- #dma-cells : Must be <1>. This dictates the length of DMA specifiers in - client nodes' dmas properties. The specifier represents the DMA request - select value for the peripheral. For more details, consult the Tegra TRM's - documentation of the APB DMA channel control register REQ_SEL field. - -Examples: - -apbdma: dma@6000a000 { - compatible = "nvidia,tegra20-apbdma"; - reg = <0x6000a000 0x1200>; - interrupts = < 0 136 0x04 - 0 137 0x04 - 0 138 0x04 - 0 139 0x04 - 0 140 0x04 - 0 141 0x04 - 0 142 0x04 - 0 143 0x04 - 0 144 0x04 - 0 145 0x04 - 0 146 0x04 - 0 147 0x04 - 0 148 0x04 - 0 149 0x04 - 0 150 0x04 - 0 151 0x04 >; - clocks = <&tegra_car 34>; - resets = <&tegra_car 34>; - reset-names = "dma"; - #dma-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra20-apbdma.yaml b/Documentation/devicetree/bindings/dma/nvidia,tegra20-apbdma.yaml new file mode 100644 index 000000000000..a2ffd5209b3b --- /dev/null +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra20-apbdma.yaml @@ -0,0 +1,90 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/nvidia,tegra20-apbdma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra APB DMA Controller + +description: + The NVIDIA Tegra APB DMA controller is a hardware component that + enables direct memory access (DMA) on Tegra systems. It facilitates + data transfer between I/O devices and main memory without constant + CPU intervention. + +maintainers: + - Jonathan Hunter <jonathanh@nvidia.com> + +properties: + compatible: + oneOf: + - const: nvidia,tegra20-apbdma + - items: + - const: nvidia,tegra30-apbdma + - const: nvidia,tegra20-apbdma + + reg: + maxItems: 1 + + "#dma-cells": + const: 1 + + clocks: + maxItems: 1 + + interrupts: + description: + Should contain all of the per-channel DMA interrupts in + ascending order with respect to the DMA channel index. + minItems: 1 + maxItems: 32 + + resets: + maxItems: 1 + + reset-names: + const: dma + +required: + - compatible + - reg + - "#dma-cells" + - clocks + - interrupts + - resets + - reset-names + +allOf: + - $ref: dma-controller.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/reset/tegra186-reset.h> + dma-controller@6000a000 { + compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; + reg = <0x6000a000 0x1200>; + interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car 34>; + resets = <&tegra_car 34>; + reset-names = "dma"; + #dma-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml b/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml index d3f8c269916c..da0235e451d6 100644 --- a/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml @@ -19,6 +19,7 @@ properties: - enum: - nvidia,tegra210-adma - nvidia,tegra186-adma + - nvidia,tegra264-adma - items: - enum: - nvidia,tegra234-adma @@ -92,6 +93,7 @@ allOf: contains: enum: - nvidia,tegra186-adma + - nvidia,tegra264-adma then: anyOf: - properties: diff --git a/Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml b/Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml index 3ad0d9b1fbc5..f2f87f0f545b 100644 --- a/Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml +++ b/Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml @@ -42,6 +42,8 @@ properties: interrupts: maxItems: 1 + dma-coherent: true + iommus: minItems: 1 maxItems: 6 diff --git a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml index b356251de5a8..92b12762c472 100644 --- a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml +++ b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml @@ -11,19 +11,23 @@ maintainers: properties: compatible: - items: - - enum: - - renesas,r7s72100-dmac # RZ/A1H - - renesas,r9a07g043-dmac # RZ/G2UL and RZ/Five - - renesas,r9a07g044-dmac # RZ/G2{L,LC} - - renesas,r9a07g054-dmac # RZ/V2L - - renesas,r9a08g045-dmac # RZ/G3S - - const: renesas,rz-dmac + oneOf: + - items: + - enum: + - renesas,r7s72100-dmac # RZ/A1H + - renesas,r9a07g043-dmac # RZ/G2UL and RZ/Five + - renesas,r9a07g044-dmac # RZ/G2{L,LC} + - renesas,r9a07g054-dmac # RZ/V2L + - renesas,r9a08g045-dmac # RZ/G3S + - const: renesas,rz-dmac + + - const: renesas,r9a09g057-dmac # RZ/V2H(P) reg: items: - description: Control and channel register block - description: DMA extended resource selector block + minItems: 1 interrupts: maxItems: 17 @@ -52,6 +56,7 @@ properties: items: - description: DMA main clock - description: DMA register access clock + minItems: 1 clock-names: items: @@ -61,10 +66,10 @@ properties: '#dma-cells': const: 1 description: - The cell specifies the encoded MID/RID values of the DMAC port - connected to the DMA client and the slave channel configuration - parameters. - bits[0:9] - Specifies MID/RID value + The cell specifies the encoded MID/RID or the REQ No values of + the DMAC port connected to the DMA client and the slave channel + configuration parameters. + bits[0:9] - Specifies the MID/RID or the REQ No value bit[10] - Specifies DMA request high enable (HIEN) bit[11] - Specifies DMA request detection type (LVL) bits[12:14] - Specifies DMAACK output mode (AM) @@ -80,12 +85,26 @@ properties: items: - description: Reset for DMA ARESETN reset terminal - description: Reset for DMA RST_ASYNC reset terminal + minItems: 1 reset-names: items: - const: arst - const: rst_async + renesas,icu: + description: + It must contain the phandle to the ICU and the index of the DMAC as seen + from the ICU. + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: Phandle to the ICU node. + - description: + The number of the DMAC as seen from the ICU, i.e. parameter k from + register ICU_DMkSELy. This may differ from the actual DMAC instance + number. + required: - compatible - reg @@ -98,13 +117,25 @@ allOf: - $ref: dma-controller.yaml# - if: - not: - properties: - compatible: - contains: - enum: - - renesas,r7s72100-dmac + properties: + compatible: + contains: + enum: + - renesas,r9a07g043-dmac + - renesas,r9a07g044-dmac + - renesas,r9a07g054-dmac + - renesas,r9a08g045-dmac then: + properties: + reg: + minItems: 2 + clocks: + minItems: 2 + resets: + minItems: 2 + + renesas,icu: false + required: - clocks - clock-names @@ -112,6 +143,46 @@ allOf: - resets - reset-names + - if: + properties: + compatible: + contains: + const: renesas,r7s72100-dmac + then: + properties: + reg: + minItems: 2 + + clocks: false + clock-names: false + power-domains: false + resets: false + reset-names: false + renesas,icu: false + + - if: + properties: + compatible: + contains: + const: renesas,r9a09g057-dmac + then: + properties: + reg: + maxItems: 1 + clocks: + maxItems: 1 + resets: + maxItems: 1 + + clock-names: false + reset-names: false + + required: + - clocks + - power-domains + - renesas,icu + - resets + additionalProperties: false examples: diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml index 525f5f3932f5..935735a59afd 100644 --- a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml +++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml @@ -59,6 +59,8 @@ properties: minimum: 1 maximum: 8 + dma-noncoherent: true + resets: minItems: 1 maxItems: 2 diff --git a/Documentation/devicetree/bindings/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml b/Documentation/devicetree/bindings/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml index ac3198953b8e..b5399c65a731 100644 --- a/Documentation/devicetree/bindings/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml +++ b/Documentation/devicetree/bindings/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml @@ -75,7 +75,6 @@ additionalProperties: false examples: - | - #include <dt-bindings/clock/xlnx-zynqmp-clk.h> fpd_dma_chan1: dma-controller@fd500000 { compatible = "xlnx,zynqmp-dma-1.0"; @@ -84,7 +83,7 @@ examples: interrupts = <0 117 0x4>; #dma-cells = <1>; clock-names = "clk_main", "clk_apb"; - clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; + clocks = <&zynqmp_clk 19>, <&zynqmp_clk 31>; xlnx,bus-width = <128>; dma-coherent; }; diff --git a/Documentation/devicetree/bindings/dsp/fsl,dsp.yaml b/Documentation/devicetree/bindings/dsp/fsl,dsp.yaml index ab93ffd3d2e5..b8693e4b4b0d 100644 --- a/Documentation/devicetree/bindings/dsp/fsl,dsp.yaml +++ b/Documentation/devicetree/bindings/dsp/fsl,dsp.yaml @@ -82,6 +82,15 @@ properties: description: Phandle to syscon block which provide access for processor enablement + resets: + minItems: 1 + + reset-names: + minItems: 1 + items: + - const: runstall + - const: softreset + required: - compatible - reg @@ -164,6 +173,17 @@ allOf: - const: txdb1 - const: rxdb0 - const: rxdb1 + - if: + properties: + compatible: + contains: + enum: + - fsl,imx8mp-dsp + - fsl,imx8mp-hifi4 + then: + required: + - resets + - reset-names additionalProperties: false @@ -186,6 +206,7 @@ examples: }; - | #include <dt-bindings/clock/imx8mp-clock.h> + #include <dt-bindings/reset/imx8mp-reset-audiomix.h> dsp_reserved: dsp@92400000 { reg = <0x92400000 0x1000000>; no-map; @@ -220,5 +241,6 @@ examples: <&mu2 3 0>; memory-region = <&dsp_vdev0buffer>, <&dsp_vdev0vring0>, <&dsp_vdev0vring1>, <&dsp_reserved>; - fsl,dsp-ctrl = <&audio_blk_ctrl>; + resets = <&audio_blk_ctrl IMX8MP_AUDIOMIX_DSP_RUNSTALL>; + reset-names = "runstall"; }; diff --git a/Documentation/devicetree/bindings/dts-coding-style.rst b/Documentation/devicetree/bindings/dts-coding-style.rst index 4772ded8a987..202acac0507a 100644 --- a/Documentation/devicetree/bindings/dts-coding-style.rst +++ b/Documentation/devicetree/bindings/dts-coding-style.rst @@ -133,6 +133,9 @@ The above-described ordering follows this approach: 3. Status is the last information to annotate that device node is or is not finished (board resources are needed). +The individual properties inside each group shall use natural sort order by +the property name. + Example:: /* SoC DTSI */ @@ -158,7 +161,10 @@ Example:: /* Board DTS */ &device_node { - vdd-supply = <&board_vreg1>; + vdd-0v9-supply = <&board_vreg1>; + vdd-1v8-supply = <&board_vreg4>; + vdd-3v3-supply = <&board_vreg2>; + vdd-12v-supply = <&board_vreg3>; status = "okay"; } diff --git a/Documentation/devicetree/bindings/edac/altr,socfpga-ecc-manager.yaml b/Documentation/devicetree/bindings/edac/altr,socfpga-ecc-manager.yaml new file mode 100644 index 000000000000..ec4634c5fa89 --- /dev/null +++ b/Documentation/devicetree/bindings/edac/altr,socfpga-ecc-manager.yaml @@ -0,0 +1,323 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright (C) 2025 Altera Corporation +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/edac/altr,socfpga-ecc-manager.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Altera SoCFPGA ECC Manager + +maintainers: + - Matthew Gerlach <matthew.gerlach@altera.com> + +description: + This binding describes the device tree nodes required for the Altera SoCFPGA + ECC Manager for the Cyclone5, Arria5, Arria10, Stratix10, and Agilex chip + families. + +properties: + + compatible: + oneOf: + - items: + - const: altr,socfpga-s10-ecc-manager + - const: altr,socfpga-a10-ecc-manager + - const: altr,socfpga-a10-ecc-manager + - const: altr,socfpga-ecc-manager + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + interrupts: + minItems: 1 + maxItems: 2 + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + ranges: true + + altr,sysmgr-syscon: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to Stratix10 System Manager Block with the ECC manager registers + + sdramedac: + type: object + additionalProperties: false + + properties: + compatible: + enum: + - altr,sdram-edac-a10 + - altr,sdram-edac-s10 + + interrupts: + minItems: 1 + maxItems: 2 + + altr,sdr-syscon: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to SDRAM parent + + required: + - compatible + - interrupts + - altr,sdr-syscon + +patternProperties: + "^ocram-ecc@[a-f0-9]+$": + type: object + additionalProperties: false + + properties: + compatible: + oneOf: + - items: + - const: altr,socfpga-s10-ocram-ecc + - const: altr,socfpga-a10-ocram-ecc + - const: altr,socfpga-a10-ocram-ecc + - const: altr,socfpga-ocram-ecc + + reg: + maxItems: 1 + + interrupts: + minItems: 1 + maxItems: 2 + + iram: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to OCRAM parent + + altr,ecc-parent: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to OCRAM parent + + required: + - compatible + - reg + - interrupts + + "^usb[0-9]-ecc@[a-f0-9]+$": + type: object + additionalProperties: false + + properties: + compatible: + oneOf: + - items: + - const: altr,socfpga-s10-usb-ecc + - const: altr,socfpga-usb-ecc + - const: altr,socfpga-usb-ecc + + reg: + maxItems: 1 + + interrupts: + minItems: 1 + maxItems: 2 + + altr,ecc-parent: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to USB parent + + required: + - compatible + - reg + - interrupts + - altr,ecc-parent + + "^emac[0-9]-[t,r]x-ecc@[a-f0-9]+$": + type: object + additionalProperties: false + + properties: + compatible: + oneOf: + - items: + - const: altr,socfpga-s10-eth-mac-ecc + - const: altr,socfpga-eth-mac-ecc + - const: altr,socfpga-eth-mac-ecc + + reg: + maxItems: 1 + + interrupts: + minItems: 1 + maxItems: 2 + + altr,ecc-parent: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to ethernet parent + + required: + - compatible + - reg + - interrupts + - altr,ecc-parent + + "^sdmmc[a-f]-ecc@[a-f0-9]+$": + type: object + additionalProperties: false + + properties: + compatible: + oneOf: + - items: + - const: altr,socfpga-s10-sdmmc-ecc + - const: altr,socfpga-sdmmc-ecc + - const: altr,socfpga-sdmmc-ecc + + reg: + maxItems: 1 + + interrupts: + minItems: 2 + maxItems: 4 + + altr,ecc-parent: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to SD/MMC parent + + required: + - compatible + - reg + - interrupts + - altr,ecc-parent + + "^l2-ecc@[a-f0-9]+$": + type: object + additionalProperties: false + + properties: + compatible: + enum: + - altr,socfpga-a10-l2-ecc + - altr,socfpga-l2-ecc + + reg: + maxItems: 1 + + interrupts: + maxItems: 2 + + required: + - compatible + - reg + - interrupts + + "^dma-ecc@[a-f0-9]+$": + type: object + additionalProperties: false + + properties: + compatible: + const: altr,socfpga-dma-ecc + reg: + maxItems: 1 + + interrupts: + maxItems: 2 + + altr,ecc-parent: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to SD/MMC parent + + required: + - compatible + - reg + - interrupts + - altr,ecc-parent + +if: + properties: + compatible: + contains: + const: altr,socfpga-ecc-manager +then: + required: + - compatible + - "#address-cells" + - "#size-cells" + - ranges + +else: + required: + - compatible + - "#address-cells" + - "#size-cells" + - interrupts + - interrupt-controller + - "#interrupt-cells" + - ranges + - altr,sysmgr-syscon + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + eccmgr { + compatible = "altr,socfpga-s10-ecc-manager", + "altr,socfpga-a10-ecc-manager"; + altr,sysmgr-syscon = <&sysmgr>; + #address-cells = <1>; + #size-cells = <1>; + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + ranges; + + sdramedac { + compatible = "altr,sdram-edac-s10"; + altr,sdr-syscon = <&sdr>; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; + }; + + ocram-ecc@ff8cc000 { + compatible = "altr,socfpga-s10-ocram-ecc", + "altr,socfpga-a10-ocram-ecc"; + reg = <0xff8cc000 0x100>; + altr,ecc-parent = <&ocram>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; + }; + + usb0-ecc@ff8c4000 { + compatible = "altr,socfpga-s10-usb-ecc", + "altr,socfpga-usb-ecc"; + reg = <0xff8c4000 0x100>; + altr,ecc-parent = <&usb0>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; + }; + + emac0-rx-ecc@ff8c0000 { + compatible = "altr,socfpga-s10-eth-mac-ecc", + "altr,socfpga-eth-mac-ecc"; + reg = <0xff8c0000 0x100>; + altr,ecc-parent = <&gmac0>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; + }; + + emac0-tx-ecc@ff8c0400 { + compatible = "altr,socfpga-s10-eth-mac-ecc", + "altr,socfpga-eth-mac-ecc"; + reg = <0xff8c0400 0x100>; + altr,ecc-parent = <&gmac0>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + }; + + sdmmca-ecc@ff8c8c00 { + compatible = "altr,socfpga-s10-sdmmc-ecc", + "altr,socfpga-sdmmc-ecc"; + reg = <0xff8c8c00 0x100>; + altr,ecc-parent = <&mmc>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH>, + <15 IRQ_TYPE_LEVEL_HIGH>; + }; + }; diff --git a/Documentation/devicetree/bindings/edac/socfpga-eccmgr.txt b/Documentation/devicetree/bindings/edac/socfpga-eccmgr.txt deleted file mode 100644 index 8f52206cfd2a..000000000000 --- a/Documentation/devicetree/bindings/edac/socfpga-eccmgr.txt +++ /dev/null @@ -1,383 +0,0 @@ -Altera SoCFPGA ECC Manager -This driver uses the EDAC framework to implement the SOCFPGA ECC Manager. -The ECC Manager counts and corrects single bit errors and counts/handles -double bit errors which are uncorrectable. - -Cyclone5 and Arria5 ECC Manager -Required Properties: -- compatible : Should be "altr,socfpga-ecc-manager" -- #address-cells: must be 1 -- #size-cells: must be 1 -- ranges : standard definition, should translate from local addresses - -Subcomponents: - -L2 Cache ECC -Required Properties: -- compatible : Should be "altr,socfpga-l2-ecc" -- reg : Address and size for ECC error interrupt clear registers. -- interrupts : Should be single bit error interrupt, then double bit error - interrupt. Note the rising edge type. - -On Chip RAM ECC -Required Properties: -- compatible : Should be "altr,socfpga-ocram-ecc" -- reg : Address and size for ECC error interrupt clear registers. -- iram : phandle to On-Chip RAM definition. -- interrupts : Should be single bit error interrupt, then double bit error - interrupt. Note the rising edge type. - -Example: - - eccmgr: eccmgr@ffd08140 { - compatible = "altr,socfpga-ecc-manager"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - l2-ecc@ffd08140 { - compatible = "altr,socfpga-l2-ecc"; - reg = <0xffd08140 0x4>; - interrupts = <0 36 1>, <0 37 1>; - }; - - ocram-ecc@ffd08144 { - compatible = "altr,socfpga-ocram-ecc"; - reg = <0xffd08144 0x4>; - iram = <&ocram>; - interrupts = <0 178 1>, <0 179 1>; - }; - }; - -Arria10 SoCFPGA ECC Manager -The Arria10 SoC ECC Manager handles the IRQs for each peripheral -in a shared register instead of individual IRQs like the Cyclone5 -and Arria5. Therefore the device tree is different as well. - -Required Properties: -- compatible : Should be "altr,socfpga-a10-ecc-manager" -- altr,sysgr-syscon : phandle to Arria10 System Manager Block - containing the ECC manager registers. -- #address-cells: must be 1 -- #size-cells: must be 1 -- interrupts : Should be single bit error interrupt, then double bit error - interrupt. -- interrupt-controller : boolean indicator that ECC Manager is an interrupt controller -- #interrupt-cells : must be set to 2. -- ranges : standard definition, should translate from local addresses - -Subcomponents: - -L2 Cache ECC -Required Properties: -- compatible : Should be "altr,socfpga-a10-l2-ecc" -- reg : Address and size for ECC error interrupt clear registers. -- interrupts : Should be single bit error interrupt, then double bit error - interrupt, in this order. - -On-Chip RAM ECC -Required Properties: -- compatible : Should be "altr,socfpga-a10-ocram-ecc" -- reg : Address and size for ECC block registers. -- interrupts : Should be single bit error interrupt, then double bit error - interrupt, in this order. - -Ethernet FIFO ECC -Required Properties: -- compatible : Should be "altr,socfpga-eth-mac-ecc" -- reg : Address and size for ECC block registers. -- altr,ecc-parent : phandle to parent Ethernet node. -- interrupts : Should be single bit error interrupt, then double bit error - interrupt, in this order. - -NAND FIFO ECC -Required Properties: -- compatible : Should be "altr,socfpga-nand-ecc" -- reg : Address and size for ECC block registers. -- altr,ecc-parent : phandle to parent NAND node. -- interrupts : Should be single bit error interrupt, then double bit error - interrupt, in this order. - -DMA FIFO ECC -Required Properties: -- compatible : Should be "altr,socfpga-dma-ecc" -- reg : Address and size for ECC block registers. -- altr,ecc-parent : phandle to parent DMA node. -- interrupts : Should be single bit error interrupt, then double bit error - interrupt, in this order. - -USB FIFO ECC -Required Properties: -- compatible : Should be "altr,socfpga-usb-ecc" -- reg : Address and size for ECC block registers. -- altr,ecc-parent : phandle to parent USB node. -- interrupts : Should be single bit error interrupt, then double bit error - interrupt, in this order. - -QSPI FIFO ECC -Required Properties: -- compatible : Should be "altr,socfpga-qspi-ecc" -- reg : Address and size for ECC block registers. -- altr,ecc-parent : phandle to parent QSPI node. -- interrupts : Should be single bit error interrupt, then double bit error - interrupt, in this order. - -SDMMC FIFO ECC -Required Properties: -- compatible : Should be "altr,socfpga-sdmmc-ecc" -- reg : Address and size for ECC block registers. -- altr,ecc-parent : phandle to parent SD/MMC node. -- interrupts : Should be single bit error interrupt, then double bit error - interrupt, in this order for port A, and then single bit error interrupt, - then double bit error interrupt in this order for port B. - -Example: - - eccmgr: eccmgr@ffd06000 { - compatible = "altr,socfpga-a10-ecc-manager"; - altr,sysmgr-syscon = <&sysmgr>; - #address-cells = <1>; - #size-cells = <1>; - interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>, - <0 0 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <2>; - ranges; - - l2-ecc@ffd06010 { - compatible = "altr,socfpga-a10-l2-ecc"; - reg = <0xffd06010 0x4>; - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, - <32 IRQ_TYPE_LEVEL_HIGH>; - }; - - ocram-ecc@ff8c3000 { - compatible = "altr,socfpga-a10-ocram-ecc"; - reg = <0xff8c3000 0x90>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH>, - <33 IRQ_TYPE_LEVEL_HIGH> ; - }; - - emac0-rx-ecc@ff8c0800 { - compatible = "altr,socfpga-eth-mac-ecc"; - reg = <0xff8c0800 0x400>; - altr,ecc-parent = <&gmac0>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH>, - <36 IRQ_TYPE_LEVEL_HIGH>; - }; - - emac0-tx-ecc@ff8c0c00 { - compatible = "altr,socfpga-eth-mac-ecc"; - reg = <0xff8c0c00 0x400>; - altr,ecc-parent = <&gmac0>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH>, - <37 IRQ_TYPE_LEVEL_HIGH>; - }; - - nand-buf-ecc@ff8c2000 { - compatible = "altr,socfpga-nand-ecc"; - reg = <0xff8c2000 0x400>; - altr,ecc-parent = <&nand>; - interrupts = <11 IRQ_TYPE_LEVEL_HIGH>, - <43 IRQ_TYPE_LEVEL_HIGH>; - }; - - nand-rd-ecc@ff8c2400 { - compatible = "altr,socfpga-nand-ecc"; - reg = <0xff8c2400 0x400>; - altr,ecc-parent = <&nand>; - interrupts = <13 IRQ_TYPE_LEVEL_HIGH>, - <45 IRQ_TYPE_LEVEL_HIGH>; - }; - - nand-wr-ecc@ff8c2800 { - compatible = "altr,socfpga-nand-ecc"; - reg = <0xff8c2800 0x400>; - altr,ecc-parent = <&nand>; - interrupts = <12 IRQ_TYPE_LEVEL_HIGH>, - <44 IRQ_TYPE_LEVEL_HIGH>; - }; - - dma-ecc@ff8c8000 { - compatible = "altr,socfpga-dma-ecc"; - reg = <0xff8c8000 0x400>; - altr,ecc-parent = <&pdma>; - interrupts = <10 IRQ_TYPE_LEVEL_HIGH>, - <42 IRQ_TYPE_LEVEL_HIGH>; - - usb0-ecc@ff8c8800 { - compatible = "altr,socfpga-usb-ecc"; - reg = <0xff8c8800 0x400>; - altr,ecc-parent = <&usb0>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH>, - <34 IRQ_TYPE_LEVEL_HIGH>; - }; - - qspi-ecc@ff8c8400 { - compatible = "altr,socfpga-qspi-ecc"; - reg = <0xff8c8400 0x400>; - altr,ecc-parent = <&qspi>; - interrupts = <14 IRQ_TYPE_LEVEL_HIGH>, - <46 IRQ_TYPE_LEVEL_HIGH>; - }; - - sdmmc-ecc@ff8c2c00 { - compatible = "altr,socfpga-sdmmc-ecc"; - reg = <0xff8c2c00 0x400>; - altr,ecc-parent = <&mmc>; - interrupts = <15 IRQ_TYPE_LEVEL_HIGH>, - <47 IRQ_TYPE_LEVEL_HIGH>, - <16 IRQ_TYPE_LEVEL_HIGH>, - <48 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - -Stratix10 SoCFPGA ECC Manager (ARM64) -The Stratix10 SoC ECC Manager handles the IRQs for each peripheral -in a shared register similar to the Arria10. However, Stratix10 ECC -requires access to registers that can only be read from Secure Monitor -with SMC calls. Therefore the device tree is slightly different. Note -that only 1 interrupt is sent in Stratix10 because the double bit errors -are treated as SErrors in ARM64 instead of IRQs in ARM32. - -Required Properties: -- compatible : Should be "altr,socfpga-s10-ecc-manager" -- altr,sysgr-syscon : phandle to Stratix10 System Manager Block - containing the ECC manager registers. -- interrupts : Should be single bit error interrupt. -- interrupt-controller : boolean indicator that ECC Manager is an interrupt controller -- #interrupt-cells : must be set to 2. -- #address-cells: must be 1 -- #size-cells: must be 1 -- ranges : standard definition, should translate from local addresses - -Subcomponents: - -SDRAM ECC -Required Properties: -- compatible : Should be "altr,sdram-edac-s10" -- interrupts : Should be single bit error interrupt. - -On-Chip RAM ECC -Required Properties: -- compatible : Should be "altr,socfpga-s10-ocram-ecc" -- reg : Address and size for ECC block registers. -- altr,ecc-parent : phandle to parent OCRAM node. -- interrupts : Should be single bit error interrupt. - -Ethernet FIFO ECC -Required Properties: -- compatible : Should be "altr,socfpga-s10-eth-mac-ecc" -- reg : Address and size for ECC block registers. -- altr,ecc-parent : phandle to parent Ethernet node. -- interrupts : Should be single bit error interrupt. - -NAND FIFO ECC -Required Properties: -- compatible : Should be "altr,socfpga-s10-nand-ecc" -- reg : Address and size for ECC block registers. -- altr,ecc-parent : phandle to parent NAND node. -- interrupts : Should be single bit error interrupt. - -DMA FIFO ECC -Required Properties: -- compatible : Should be "altr,socfpga-s10-dma-ecc" -- reg : Address and size for ECC block registers. -- altr,ecc-parent : phandle to parent DMA node. -- interrupts : Should be single bit error interrupt. - -USB FIFO ECC -Required Properties: -- compatible : Should be "altr,socfpga-s10-usb-ecc" -- reg : Address and size for ECC block registers. -- altr,ecc-parent : phandle to parent USB node. -- interrupts : Should be single bit error interrupt. - -SDMMC FIFO ECC -Required Properties: -- compatible : Should be "altr,socfpga-s10-sdmmc-ecc" -- reg : Address and size for ECC block registers. -- altr,ecc-parent : phandle to parent SD/MMC node. -- interrupts : Should be single bit error interrupt for port A - and then single bit error interrupt for port B. - -Example: - - eccmgr { - compatible = "altr,socfpga-s10-ecc-manager"; - altr,sysmgr-syscon = <&sysmgr>; - #address-cells = <1>; - #size-cells = <1>; - interrupts = <0 15 4>; - interrupt-controller; - #interrupt-cells = <2>; - ranges; - - sdramedac { - compatible = "altr,sdram-edac-s10"; - interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; - }; - - ocram-ecc@ff8cc000 { - compatible = "altr,socfpga-s10-ocram-ecc"; - reg = <ff8cc000 0x100>; - altr,ecc-parent = <&ocram>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; - }; - - emac0-rx-ecc@ff8c0000 { - compatible = "altr,socfpga-s10-eth-mac-ecc"; - reg = <0xff8c0000 0x100>; - altr,ecc-parent = <&gmac0>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; - }; - - emac0-tx-ecc@ff8c0400 { - compatible = "altr,socfpga-s10-eth-mac-ecc"; - reg = <0xff8c0400 0x100>; - altr,ecc-parent = <&gmac0>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH>' - }; - - nand-buf-ecc@ff8c8000 { - compatible = "altr,socfpga-s10-nand-ecc"; - reg = <0xff8c8000 0x100>; - altr,ecc-parent = <&nand>; - interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; - }; - - nand-rd-ecc@ff8c8400 { - compatible = "altr,socfpga-s10-nand-ecc"; - reg = <0xff8c8400 0x100>; - altr,ecc-parent = <&nand>; - interrupts = <13 IRQ_TYPE_LEVEL_HIGH>; - }; - - nand-wr-ecc@ff8c8800 { - compatible = "altr,socfpga-s10-nand-ecc"; - reg = <0xff8c8800 0x100>; - altr,ecc-parent = <&nand>; - interrupts = <12 IRQ_TYPE_LEVEL_HIGH>; - }; - - dma-ecc@ff8c9000 { - compatible = "altr,socfpga-s10-dma-ecc"; - reg = <0xff8c9000 0x100>; - altr,ecc-parent = <&pdma>; - interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; - - usb0-ecc@ff8c4000 { - compatible = "altr,socfpga-s10-usb-ecc"; - reg = <0xff8c4000 0x100>; - altr,ecc-parent = <&usb0>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; - }; - - sdmmc-ecc@ff8c8c00 { - compatible = "altr,socfpga-s10-sdmmc-ecc"; - reg = <0xff8c8c00 0x100>; - altr,ecc-parent = <&mmc>; - interrupts = <14 IRQ_TYPE_LEVEL_HIGH>, - <15 IRQ_TYPE_LEVEL_HIGH>; - }; - }; diff --git a/Documentation/devicetree/bindings/eeprom/at24.yaml b/Documentation/devicetree/bindings/eeprom/at24.yaml index c9e4afbdc448..0ac68646c077 100644 --- a/Documentation/devicetree/bindings/eeprom/at24.yaml +++ b/Documentation/devicetree/bindings/eeprom/at24.yaml @@ -130,10 +130,13 @@ properties: - const: giantec,gt24c32a - const: atmel,24c32 - items: - - const: onnn,n24s64b + - enum: + - onnn,n24s64b + - puya,p24c64f - const: atmel,24c64 - items: - enum: + - giantec,gt24p128e - giantec,gt24p128f - renesas,r1ex24128 - samsung,s524ad0xd1 diff --git a/Documentation/devicetree/bindings/example-schema.yaml b/Documentation/devicetree/bindings/example-schema.yaml index 484f8babcda4..c731d5045e80 100644 --- a/Documentation/devicetree/bindings/example-schema.yaml +++ b/Documentation/devicetree/bindings/example-schema.yaml @@ -178,7 +178,9 @@ properties: description: Child nodes are just another property from a json-schema perspective. type: object # DT nodes are json objects - # Child nodes also need additionalProperties or unevaluatedProperties + # Child nodes also need additionalProperties or unevaluatedProperties, where + # 'false' should be used in most cases (see 'child-node-with-own-schema' + # below). additionalProperties: false properties: vendor,a-child-node-property: @@ -189,6 +191,17 @@ properties: required: - vendor,a-child-node-property + child-node-with-own-schema: + description: | + Child node with their own compatible and device schema which ends in + 'additionalProperties: false' or 'unevaluatedProperties: false' can + mention only the compatible and use here 'additionalProperties: true'. + type: object + additionalProperties: true + properties: + compatible: + const: vendor,sub-device + # Describe the relationship between different properties dependencies: # 'vendor,bool-property' is only allowed when 'vendor,string-array-property' diff --git a/Documentation/devicetree/bindings/firmware/fsl,scu.yaml b/Documentation/devicetree/bindings/firmware/fsl,scu.yaml index 557e524786c2..f9ba18f06369 100644 --- a/Documentation/devicetree/bindings/firmware/fsl,scu.yaml +++ b/Documentation/devicetree/bindings/firmware/fsl,scu.yaml @@ -45,6 +45,18 @@ properties: Keys provided by the SCU $ref: /schemas/input/fsl,scu-key.yaml + reset-controller: + type: object + properties: + compatible: + const: fsl,imx-scu-reset + '#reset-cells': + const: 1 + required: + - compatible + - '#reset-cells' + additionalProperties: false + mboxes: description: A list of phandles of TX MU channels followed by a list of phandles of diff --git a/Documentation/devicetree/bindings/firmware/google,gs101-acpm-ipc.yaml b/Documentation/devicetree/bindings/firmware/google,gs101-acpm-ipc.yaml new file mode 100644 index 000000000000..9785aac3b5f3 --- /dev/null +++ b/Documentation/devicetree/bindings/firmware/google,gs101-acpm-ipc.yaml @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright 2024 Linaro Ltd. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/firmware/google,gs101-acpm-ipc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos ACPM mailbox protocol + +maintainers: + - Tudor Ambarus <tudor.ambarus@linaro.org> + +description: | + ACPM (Alive Clock and Power Manager) is a firmware that operates on the + APM (Active Power Management) module that handles overall power management + activities. ACPM and masters regard each other as independent hardware + component and communicate with each other using mailbox messages and + shared memory. + + This binding is intended to define the interface the firmware implementing + ACPM provides for OSPM in the device tree. + +properties: + compatible: + const: google,gs101-acpm-ipc + + mboxes: + maxItems: 1 + + pmic: + description: Child node describing the main PMIC. + type: object + additionalProperties: true + + properties: + compatible: + const: samsung,s2mpg10-pmic + + shmem: + description: + List of phandle pointing to the shared memory (SHM) area. The memory + contains channels configuration data and the TX/RX ring buffers that + are used for passing messages to/from the ACPM firmware. + maxItems: 1 + +required: + - compatible + - mboxes + - shmem + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + power-management { + compatible = "google,gs101-acpm-ipc"; + mboxes = <&ap2apm_mailbox>; + shmem = <&apm_sram>; + + pmic { + compatible = "samsung,s2mpg10-pmic"; + interrupts-extended = <&gpa0 6 IRQ_TYPE_LEVEL_LOW>; + + regulators { + LDO1 { + regulator-name = "vdd_ldo1"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + }; + + // ... + + BUCK1 { + regulator-name = "vdd_mif"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.txt b/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.txt deleted file mode 100644 index 6eff1afd8daf..000000000000 --- a/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.txt +++ /dev/null @@ -1,57 +0,0 @@ -Intel Service Layer Driver for Stratix10 SoC -============================================ -Intel Stratix10 SoC is composed of a 64 bit quad-core ARM Cortex A53 hard -processor system (HPS) and Secure Device Manager (SDM). When the FPGA is -configured from HPS, there needs to be a way for HPS to notify SDM the -location and size of the configuration data. Then SDM will get the -configuration data from that location and perform the FPGA configuration. - -To meet the whole system security needs and support virtual machine requesting -communication with SDM, only the secure world of software (EL3, Exception -Layer 3) can interface with SDM. All software entities running on other -exception layers must channel through the EL3 software whenever it needs -service from SDM. - -Intel Stratix10 service layer driver, running at privileged exception level -(EL1, Exception Layer 1), interfaces with the service providers and provides -the services for FPGA configuration, QSPI, Crypto and warm reset. Service layer -driver also manages secure monitor call (SMC) to communicate with secure monitor -code running in EL3. - -Required properties: -------------------- -The svc node has the following mandatory properties, must be located under -the firmware node. - -- compatible: "intel,stratix10-svc" or "intel,agilex-svc" -- method: smc or hvc - smc - Secure Monitor Call - hvc - Hypervisor Call -- memory-region: - phandle to the reserved memory node. See - Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt - for details - -Example: -------- - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - service_reserved: svcbuffer@0 { - compatible = "shared-dma-pool"; - reg = <0x0 0x0 0x0 0x1000000>; - alignment = <0x1000>; - no-map; - }; - }; - - firmware { - svc { - compatible = "intel,stratix10-svc"; - method = "smc"; - memory-region = <&service_reserved>; - }; - }; diff --git a/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.yaml b/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.yaml new file mode 100644 index 000000000000..fac1e955852e --- /dev/null +++ b/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.yaml @@ -0,0 +1,93 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/firmware/intel,stratix10-svc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel Service Layer Driver for Stratix10 SoC + +maintainers: + - Dinh Nguyen <dinguyen@kernel.org> + - Mahesh Rao <mahesh.rao@altera.com> + +description: > + Intel Stratix10 SoC is composed of a 64 bit quad-core ARM Cortex A53 hard + processor system (HPS) and Secure Device Manager (SDM). When the FPGA is + configured from HPS, there needs to be a way for HPS to notify SDM the + location and size of the configuration data. Then SDM will get the + configuration data from that location and perform the FPGA configuration. + + To meet the whole system security needs and support virtual machine requesting + communication with SDM, only the secure world of software (EL3, Exception + Layer 3) can interface with SDM. All software entities running on other + exception layers must channel through the EL3 software whenever it needs + service from SDM. + + Intel Stratix10 service layer driver, running at privileged exception level + (EL1, Exception Layer 1), interfaces with the service providers and provides + the services for FPGA configuration, QSPI, Crypto and warm reset. Service layer + driver also manages secure monitor call (SMC) to communicate with secure monitor + code running in EL3. + +properties: + compatible: + enum: + - intel,stratix10-svc + - intel,agilex-svc + + method: + description: | + Supervisory call method to be used to communicate with the + secure service layer. + Permitted values are: + - "smc" : SMC #0, following the SMCCC + - "hvc" : HVC #0, following the SMCCC + + $ref: /schemas/types.yaml#/definitions/string-array + enum: + - smc + - hvc + + memory-region: + maxItems: 1 + description: + reserved memory region for the service layer driver to + communicate with the secure device manager. + + fpga-mgr: + $ref: /schemas/fpga/intel,stratix10-soc-fpga-mgr.yaml + description: Optional child node for fpga manager to perform fabric configuration. + +required: + - compatible + - method + - memory-region + +additionalProperties: false + +examples: + - | + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + + service_reserved: svcbuffer@0 { + compatible = "shared-dma-pool"; + reg = <0x0 0x0 0x0 0x1000000>; + alignment = <0x1000>; + no-map; + }; + }; + + firmware { + svc { + compatible = "intel,stratix10-svc"; + method = "smc"; + memory-region = <&service_reserved>; + + fpga-mgr { + compatible = "intel,stratix10-soc-fpga-mgr"; + }; + }; + }; + diff --git a/Documentation/devicetree/bindings/firmware/nxp,imx95-scmi.yaml b/Documentation/devicetree/bindings/firmware/nxp,imx95-scmi.yaml index 1a95010a546b..2bda2e0e1369 100644 --- a/Documentation/devicetree/bindings/firmware/nxp,imx95-scmi.yaml +++ b/Documentation/devicetree/bindings/firmware/nxp,imx95-scmi.yaml @@ -11,6 +11,18 @@ maintainers: - Peng Fan <peng.fan@nxp.com> properties: + protocol@80: + description: + SCMI LMM protocol which is for boot, shutdown, and reset of other logical + machines (LM). It is usually used to allow one LM to manage another used + as an offload or accelerator engine. + $ref: '/schemas/firmware/arm,scmi.yaml#/$defs/protocol-node' + unevaluatedProperties: false + + properties: + reg: + const: 0x80 + protocol@81: $ref: '/schemas/firmware/arm,scmi.yaml#/$defs/protocol-node' unevaluatedProperties: false @@ -19,6 +31,17 @@ properties: reg: const: 0x81 + protocol@82: + description: + SCMI CPU Protocol which allows an agent to start or stop a CPU. It is + used to manage auxiliary CPUs in a LM. + $ref: '/schemas/firmware/arm,scmi.yaml#/$defs/protocol-node' + unevaluatedProperties: false + + properties: + reg: + const: 0x82 + protocol@84: $ref: '/schemas/firmware/arm,scmi.yaml#/$defs/protocol-node' unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/firmware/thead,th1520-aon.yaml b/Documentation/devicetree/bindings/firmware/thead,th1520-aon.yaml new file mode 100644 index 000000000000..bbc183200400 --- /dev/null +++ b/Documentation/devicetree/bindings/firmware/thead,th1520-aon.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/firmware/thead,th1520-aon.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: T-HEAD TH1520 AON (Always-On) Firmware + +description: | + The Always-On (AON) subsystem in the TH1520 SoC is responsible for managing + low-power states, system wakeup events, and power management tasks. It is + designed to operate independently in a dedicated power domain, allowing it to + remain functional even during the SoC's deep sleep states. + + At the heart of the AON subsystem is the E902, a low-power core that executes + firmware responsible for coordinating tasks such as power domain control, + clock management, and system wakeup signaling. Communication between the main + SoC and the AON subsystem is handled through a mailbox interface, which + enables message-based interactions with the AON firmware. + +maintainers: + - Michal Wilczynski <m.wilczynski@samsung.com> + +properties: + compatible: + const: thead,th1520-aon + + mboxes: + maxItems: 1 + + mbox-names: + items: + - const: aon + + "#power-domain-cells": + const: 1 + +required: + - compatible + - mboxes + - mbox-names + - "#power-domain-cells" + +additionalProperties: false + +examples: + - | + aon: aon { + compatible = "thead,th1520-aon"; + mboxes = <&mbox_910t 1>; + mbox-names = "aon"; + #power-domain-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml b/Documentation/devicetree/bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml new file mode 100644 index 000000000000..6e536d6b28a9 --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fpga/intel,stratix10-soc-fpga-mgr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel Stratix10 SoC FPGA Manager + +maintainers: + - Mahesh Rao <mahesh.rao@altera.com> + - Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com> + - Niravkumar L Rabara <nirav.rabara@altera.com> + +description: + The Intel Stratix10 SoC consists of a 64-bit quad-core ARM Cortex A53 hard + processor system (HPS) and a Secure Device Manager (SDM). The Stratix10 + SoC FPGA Manager driver is used to configure/reconfigure the FPGA fabric + on the die.The driver communicates with SDM/ATF via the stratix10-svc + platform driver for performing its operations. + +properties: + compatible: + enum: + - intel,stratix10-soc-fpga-mgr + - intel,agilex-soc-fpga-mgr + +required: + - compatible + +additionalProperties: false + +examples: + - | + fpga-mgr { + compatible = "intel,stratix10-soc-fpga-mgr"; + }; diff --git a/Documentation/devicetree/bindings/fpga/intel-stratix10-soc-fpga-mgr.txt b/Documentation/devicetree/bindings/fpga/intel-stratix10-soc-fpga-mgr.txt deleted file mode 100644 index 0f874137ca46..000000000000 --- a/Documentation/devicetree/bindings/fpga/intel-stratix10-soc-fpga-mgr.txt +++ /dev/null @@ -1,18 +0,0 @@ -Intel Stratix10 SoC FPGA Manager - -Required properties: -The fpga_mgr node has the following mandatory property, must be located under -firmware/svc node. - -- compatible : should contain "intel,stratix10-soc-fpga-mgr" or - "intel,agilex-soc-fpga-mgr" - -Example: - - firmware { - svc { - fpga_mgr: fpga-mgr { - compatible = "intel,stratix10-soc-fpga-mgr"; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/fsi/ibm,p9-scom.yaml b/Documentation/devicetree/bindings/fsi/ibm,p9-scom.yaml index 8cd14a70bedf..b106f5212ea9 100644 --- a/Documentation/devicetree/bindings/fsi/ibm,p9-scom.yaml +++ b/Documentation/devicetree/bindings/fsi/ibm,p9-scom.yaml @@ -16,6 +16,7 @@ description: properties: compatible: enum: + - ibm,fsi2pib - ibm,p9-scom - ibm,i2cr-scom diff --git a/Documentation/devicetree/bindings/gpio/aspeed,ast2400-gpio.yaml b/Documentation/devicetree/bindings/gpio/aspeed,ast2400-gpio.yaml index b9afd07a9d24..b16273e69dfe 100644 --- a/Documentation/devicetree/bindings/gpio/aspeed,ast2400-gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/aspeed,ast2400-gpio.yaml @@ -46,6 +46,12 @@ properties: minimum: 12 maximum: 232 +patternProperties: + "-hog(-[0-9]+)?$": + type: object + required: + - gpio-hog + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/gpio/atmel,at91rm9200-gpio.yaml b/Documentation/devicetree/bindings/gpio/atmel,at91rm9200-gpio.yaml index 3dd70933ed8e..d810043b56b6 100644 --- a/Documentation/devicetree/bindings/gpio/atmel,at91rm9200-gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/atmel,at91rm9200-gpio.yaml @@ -69,13 +69,13 @@ examples: #include <dt-bindings/interrupt-controller/irq.h> gpio@fffff400 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff400 0x200>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff400 0x200>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; }; ... diff --git a/Documentation/devicetree/bindings/gpio/blaize,blzp1600-gpio.yaml b/Documentation/devicetree/bindings/gpio/blaize,blzp1600-gpio.yaml new file mode 100644 index 000000000000..a05f6ea619c3 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/blaize,blzp1600-gpio.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/blaize,blzp1600-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Blaize BLZP1600 GPIO controller + +description: + Blaize BLZP1600 GPIO controller is an implementation of the VeriSilicon + APB GPIO v0.2 IP block. It has 32 ports each of which are intended to be + represented as child nodes with the generic GPIO-controller properties + as described in this binding's file. + +maintainers: + - Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com> + - James Cowgill <james.cowgill@blaize.com> + - Matt Redfearn <matt.redfearn@blaize.com> + - Neil Jones <neil.jones@blaize.com> + +properties: + $nodename: + pattern: "^gpio@[0-9a-f]+$" + + compatible: + enum: + - blaize,blzp1600-gpio + + reg: + maxItems: 1 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + ngpios: + default: 32 + minimum: 1 + maximum: 32 + + interrupts: + maxItems: 1 + + gpio-line-names: true + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + +required: + - compatible + - reg + - gpio-controller + - '#gpio-cells' + +dependencies: + interrupt-controller: [ interrupts ] + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + gpio: gpio@4c0000 { + compatible = "blaize,blzp1600-gpio"; + reg = <0x004c0000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + }; +... diff --git a/Documentation/devicetree/bindings/gpio/fairchild,74hc595.yaml b/Documentation/devicetree/bindings/gpio/fairchild,74hc595.yaml index 0e5c22929bde..ab35bcf98101 100644 --- a/Documentation/devicetree/bindings/gpio/fairchild,74hc595.yaml +++ b/Documentation/devicetree/bindings/gpio/fairchild,74hc595.yaml @@ -71,15 +71,15 @@ unevaluatedProperties: false examples: - | spi { - #address-cells = <1>; - #size-cells = <0>; - - gpio5: gpio5@0 { - compatible = "fairchild,74hc595"; - reg = <0>; - gpio-controller; - #gpio-cells = <2>; - registers-number = <4>; - spi-max-frequency = <100000>; - }; + #address-cells = <1>; + #size-cells = <0>; + + gpio5@0 { + compatible = "fairchild,74hc595"; + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + registers-number = <4>; + spi-max-frequency = <100000>; + }; }; diff --git a/Documentation/devicetree/bindings/gpio/gpio-mvebu.yaml b/Documentation/devicetree/bindings/gpio/gpio-mvebu.yaml index 33d4e4716516..7ed5f9c4dde9 100644 --- a/Documentation/devicetree/bindings/gpio/gpio-mvebu.yaml +++ b/Documentation/devicetree/bindings/gpio/gpio-mvebu.yaml @@ -72,6 +72,9 @@ properties: "#gpio-cells": const: 2 + gpio-ranges: + maxItems: 1 + marvell,pwm-offset: $ref: /schemas/types.yaml#/definitions/uint32 description: Offset in the register map for the pwm registers (in bytes) @@ -96,6 +99,13 @@ properties: - const: axi minItems: 1 +patternProperties: + "^(.+-hog(-[0-9]+)?)$": + type: object + + required: + - gpio-hog + required: - compatible - gpio-controller diff --git a/Documentation/devicetree/bindings/gpio/gpio-mxs.yaml b/Documentation/devicetree/bindings/gpio/gpio-mxs.yaml index 8ff54369d16c..b58e08c8ecd8 100644 --- a/Documentation/devicetree/bindings/gpio/gpio-mxs.yaml +++ b/Documentation/devicetree/bindings/gpio/gpio-mxs.yaml @@ -84,52 +84,52 @@ examples: reg = <0x80018000 0x2000>; gpio@0 { - compatible = "fsl,imx28-gpio"; - reg = <0>; - interrupts = <127>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; + compatible = "fsl,imx28-gpio"; + reg = <0>; + interrupts = <127>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; }; gpio@1 { - compatible = "fsl,imx28-gpio"; - reg = <1>; - interrupts = <126>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; + compatible = "fsl,imx28-gpio"; + reg = <1>; + interrupts = <126>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; }; gpio@2 { - compatible = "fsl,imx28-gpio"; - reg = <2>; - interrupts = <125>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; + compatible = "fsl,imx28-gpio"; + reg = <2>; + interrupts = <125>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; }; gpio@3 { - compatible = "fsl,imx28-gpio"; - reg = <3>; - interrupts = <124>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; + compatible = "fsl,imx28-gpio"; + reg = <3>; + interrupts = <124>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; }; gpio@4 { - compatible = "fsl,imx28-gpio"; - reg = <4>; - interrupts = <123>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; + compatible = "fsl,imx28-gpio"; + reg = <4>; + interrupts = <123>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; }; }; diff --git a/Documentation/devicetree/bindings/gpio/gpio-pca95xx.yaml b/Documentation/devicetree/bindings/gpio/gpio-pca95xx.yaml index 7b1eb08fa055..4d3f52f8d1b8 100644 --- a/Documentation/devicetree/bindings/gpio/gpio-pca95xx.yaml +++ b/Documentation/devicetree/bindings/gpio/gpio-pca95xx.yaml @@ -17,6 +17,9 @@ properties: compatible: oneOf: - items: + - const: toradex,ecgpiol16 + - const: nxp,pcal6416 + - items: - const: diodes,pi4ioe5v6534q - const: nxp,pcal6534 - items: @@ -132,6 +135,7 @@ allOf: - maxim,max7325 - maxim,max7326 - maxim,max7327 + - toradex,ecgpiol16 then: properties: reset-gpios: false diff --git a/Documentation/devicetree/bindings/gpio/gpio-vf610.yaml b/Documentation/devicetree/bindings/gpio/gpio-vf610.yaml index cabda2eab4a2..a31f64b6d40b 100644 --- a/Documentation/devicetree/bindings/gpio/gpio-vf610.yaml +++ b/Documentation/devicetree/bindings/gpio/gpio-vf610.yaml @@ -28,6 +28,7 @@ properties: - items: - enum: - fsl,imx93-gpio + - fsl,imx94-gpio - fsl,imx95-gpio - const: fsl,imx8ulp-gpio @@ -69,6 +70,13 @@ properties: minItems: 1 maxItems: 4 + gpio-reserved-ranges: true + + ngpios: + minimum: 1 + maximum: 32 + default: 32 + patternProperties: "^.+-hog(-[0-9]+)?$": type: object diff --git a/Documentation/devicetree/bindings/gpio/loongson,ls-gpio.yaml b/Documentation/devicetree/bindings/gpio/loongson,ls-gpio.yaml index cf3b1b270aa8..b68159600e2b 100644 --- a/Documentation/devicetree/bindings/gpio/loongson,ls-gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/loongson,ls-gpio.yaml @@ -20,7 +20,10 @@ properties: - loongson,ls2k2000-gpio1 - loongson,ls2k2000-gpio2 - loongson,ls3a5000-gpio + - loongson,ls3a6000-gpio # Loongson-3A6000 node GPIO - loongson,ls7a-gpio + - loongson,ls7a2000-gpio1 # LS7A2000 chipset GPIO + - loongson,ls7a2000-gpio2 # LS7A2000 ACPI GPIO - items: - const: loongson,ls2k1000-gpio - const: loongson,ls2k-gpio diff --git a/Documentation/devicetree/bindings/gpio/maxim,max77759-gpio.yaml b/Documentation/devicetree/bindings/gpio/maxim,max77759-gpio.yaml new file mode 100644 index 000000000000..55734190d5eb --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/maxim,max77759-gpio.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/maxim,max77759-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Maxim Integrated MAX77759 GPIO + +maintainers: + - André Draszik <andre.draszik@linaro.org> + +description: | + This module is part of the MAX77759 PMIC. For additional information, see + Documentation/devicetree/bindings/mfd/maxim,max77759.yaml. + + The MAX77759 is a PMIC integrating, amongst others, a GPIO controller + including interrupt support for 2 GPIO lines. + +properties: + compatible: + const: maxim,max77759-gpio + + "#gpio-cells": + const: 2 + + gpio-controller: true + + gpio-line-names: + minItems: 1 + maxItems: 2 + + "#interrupt-cells": + const: 2 + + interrupt-controller: true + +required: + - compatible + - "#gpio-cells" + - gpio-controller + - "#interrupt-cells" + - interrupt-controller + +additionalProperties: false diff --git a/Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.yaml b/Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.yaml index 4ef06b2ff1ff..065f5761a93f 100644 --- a/Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.yaml @@ -111,6 +111,9 @@ properties: gpio-controller: true + gpio-ranges: + maxItems: 1 + "#gpio-cells": description: | Indicates how many cells are used in a consumer's GPIO specifier. In the diff --git a/Documentation/devicetree/bindings/gpio/nxp,pcf8575.yaml b/Documentation/devicetree/bindings/gpio/nxp,pcf8575.yaml index 3718103e966a..5a6ecaa7b44b 100644 --- a/Documentation/devicetree/bindings/gpio/nxp,pcf8575.yaml +++ b/Documentation/devicetree/bindings/gpio/nxp,pcf8575.yaml @@ -73,6 +73,43 @@ properties: wakeup-source: true + reset-gpios: + maxItems: 1 + description: + GPIO controlling the (reset active LOW) RESET# pin. + + The active polarity of the GPIO must translate to the low state of the + RESET# pin on the IC, i.e. if a GPIO is directly routed to the RESET# pin + without any inverter, GPIO_ACTIVE_LOW is expected. + + Performing a reset makes all lines initialized to their input (pulled-up) + state. + +allOf: + - if: + properties: + compatible: + not: + contains: + enum: + - nxp,pca9670 + - nxp,pca9671 + - nxp,pca9672 + - nxp,pca9673 + then: + properties: + reset-gpios: false + + # lines-initial-states XOR reset-gpios + # Performing a reset reinitializes all lines to a known state which + # may not match passed lines-initial-states + - if: + required: + - lines-initial-states + then: + properties: + reset-gpios: false + patternProperties: "^(.+-hog(-[0-9]+)?)$": type: object @@ -91,17 +128,17 @@ additionalProperties: false examples: - | i2c { - #address-cells = <1>; - #size-cells = <0>; - - pcf8575: gpio@20 { - compatible = "nxp,pcf8575"; - reg = <0x20>; - interrupt-parent = <&irqpin2>; - interrupts = <3 0>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; + #address-cells = <1>; + #size-cells = <0>; + + gpio@20 { + compatible = "nxp,pcf8575"; + reg = <0x20>; + interrupt-parent = <&irqpin2>; + interrupts = <3 0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; }; diff --git a/Documentation/devicetree/bindings/gpio/realtek,otto-gpio.yaml b/Documentation/devicetree/bindings/gpio/realtek,otto-gpio.yaml index 39fd959c45d2..728099c65824 100644 --- a/Documentation/devicetree/bindings/gpio/realtek,otto-gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/realtek,otto-gpio.yaml @@ -81,7 +81,7 @@ dependencies: examples: - | - gpio@3500 { + gpio@3500 { compatible = "realtek,rtl8380-gpio", "realtek,otto-gpio"; reg = <0x3500 0x1c>; gpio-controller; @@ -91,9 +91,9 @@ examples: #interrupt-cells = <2>; interrupt-parent = <&rtlintc>; interrupts = <23>; - }; + }; - | - gpio@3300 { + gpio@3300 { compatible = "realtek,rtl9300-gpio", "realtek,otto-gpio"; reg = <0x3300 0x1c>, <0x3338 0x8>; gpio-controller; @@ -103,6 +103,6 @@ examples: #interrupt-cells = <2>; interrupt-parent = <&rtlintc>; interrupts = <13>; - }; + }; ... diff --git a/Documentation/devicetree/bindings/gpio/renesas,em-gio.yaml b/Documentation/devicetree/bindings/gpio/renesas,em-gio.yaml index 8bdef812c87c..49fb8f613ead 100644 --- a/Documentation/devicetree/bindings/gpio/renesas,em-gio.yaml +++ b/Documentation/devicetree/bindings/gpio/renesas,em-gio.yaml @@ -57,14 +57,14 @@ examples: - | #include <dt-bindings/interrupt-controller/arm-gic.h> gpio0: gpio@e0050000 { - compatible = "renesas,em-gio"; - reg = <0xe0050000 0x2c>, <0xe0050040 0x20>; - interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pfc 0 0 32>; - ngpios = <32>; - interrupt-controller; - #interrupt-cells = <2>; + compatible = "renesas,em-gio"; + reg = <0xe0050000 0x2c>, <0xe0050040 0x20>; + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 0 32>; + ngpios = <32>; + interrupt-controller; + #interrupt-cells = <2>; }; diff --git a/Documentation/devicetree/bindings/gpio/renesas,rcar-gpio.yaml b/Documentation/devicetree/bindings/gpio/renesas,rcar-gpio.yaml index cc7a950a6030..d32e103a64aa 100644 --- a/Documentation/devicetree/bindings/gpio/renesas,rcar-gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/renesas,rcar-gpio.yaml @@ -138,16 +138,16 @@ examples: #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/power/r8a77470-sysc.h> gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a77470", "renesas,rcar-gen2-gpio"; - reg = <0xe6053000 0x50>; - interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 909>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pfc 0 96 30>; - gpio-reserved-ranges = <17 10>; - interrupt-controller; - #interrupt-cells = <2>; + compatible = "renesas,gpio-r8a77470", "renesas,rcar-gen2-gpio"; + reg = <0xe6053000 0x50>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 909>; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 909>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 96 30>; + gpio-reserved-ranges = <17 10>; + interrupt-controller; + #interrupt-cells = <2>; }; diff --git a/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml b/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml index fc095646adea..4bdc201b719e 100644 --- a/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml @@ -76,8 +76,8 @@ additionalProperties: false examples: - | - #include <dt-bindings/clock/sifive-fu540-prci.h> - gpio@10060000 { + #include <dt-bindings/clock/sifive-fu540-prci.h> + gpio@10060000 { compatible = "sifive,fu540-c000-gpio", "sifive,gpio0"; interrupt-parent = <&plic>; interrupts = <7>, <8>, <9>, <10>, <11>, <12>, <13>, <14>, <15>, <16>, @@ -88,6 +88,6 @@ examples: #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; - }; + }; ... diff --git a/Documentation/devicetree/bindings/gpio/spacemit,k1-gpio.yaml b/Documentation/devicetree/bindings/gpio/spacemit,k1-gpio.yaml new file mode 100644 index 000000000000..ec0232e72c71 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/spacemit,k1-gpio.yaml @@ -0,0 +1,96 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/spacemit,k1-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SpacemiT K1 GPIO controller + +maintainers: + - Yixun Lan <dlan@gentoo.org> + +description: + The controller's registers are organized as sets of eight 32-bit + registers with each set of port controlling 32 pins. A single + interrupt line is shared for all of the pins by the controller. + +properties: + $nodename: + pattern: "^gpio@[0-9a-f]+$" + + compatible: + const: spacemit,k1-gpio + + reg: + maxItems: 1 + + clocks: + items: + - description: GPIO Core Clock + - description: GPIO Bus Clock + + clock-names: + items: + - const: core + - const: bus + + resets: + maxItems: 1 + + gpio-controller: true + + "#gpio-cells": + const: 3 + description: + The first two cells are the GPIO bank index and offset inside the bank, + the third cell should specify GPIO flag. + + gpio-ranges: true + + interrupts: + maxItems: 1 + + interrupt-controller: true + + "#interrupt-cells": + const: 3 + description: + The first two cells are the GPIO bank index and offset inside the bank, + the third cell should specify interrupt flag. The controller does not + support level interrupts, so flags of IRQ_TYPE_LEVEL_HIGH, + IRQ_TYPE_LEVEL_LOW should not be used. + Refer <dt-bindings/interrupt-controller/irq.h> for valid flags. + +required: + - compatible + - reg + - clocks + - clock-names + - gpio-controller + - "#gpio-cells" + - interrupts + - interrupt-controller + - "#interrupt-cells" + - gpio-ranges + +additionalProperties: false + +examples: + - | + gpio@d4019000 { + compatible = "spacemit,k1-gpio"; + reg = <0xd4019000 0x800>; + clocks =<&ccu 9>, <&ccu 61>; + clock-names = "core", "bus"; + gpio-controller; + #gpio-cells = <3>; + interrupts = <58>; + interrupt-controller; + interrupt-parent = <&plic>; + #interrupt-cells = <3>; + gpio-ranges = <&pinctrl 0 0 0 32>, + <&pinctrl 1 0 32 32>, + <&pinctrl 2 0 64 32>, + <&pinctrl 3 0 96 32>; + }; +... diff --git a/Documentation/devicetree/bindings/gpio/toshiba,gpio-visconti.yaml b/Documentation/devicetree/bindings/gpio/toshiba,gpio-visconti.yaml index b085450b527f..712063417bc8 100644 --- a/Documentation/devicetree/bindings/gpio/toshiba,gpio-visconti.yaml +++ b/Documentation/devicetree/bindings/gpio/toshiba,gpio-visconti.yaml @@ -48,22 +48,22 @@ additionalProperties: false examples: - | - #include <dt-bindings/interrupt-controller/irq.h> - #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> - soc { + soc { #address-cells = <2>; #size-cells = <2>; gpio: gpio@28020000 { - compatible = "toshiba,gpio-tmpv7708"; - reg = <0 0x28020000 0 0x1000>; - #gpio-cells = <0x2>; - gpio-ranges = <&pmux 0 0 32>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&gic>; + compatible = "toshiba,gpio-tmpv7708"; + reg = <0 0x28020000 0 0x1000>; + #gpio-cells = <0x2>; + gpio-ranges = <&pmux 0 0 32>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; }; - }; + }; ... diff --git a/Documentation/devicetree/bindings/gpio/xlnx,gpio-xilinx.yaml b/Documentation/devicetree/bindings/gpio/xlnx,gpio-xilinx.yaml index d3d8a2e143ed..8fbf12ca067e 100644 --- a/Documentation/devicetree/bindings/gpio/xlnx,gpio-xilinx.yaml +++ b/Documentation/devicetree/bindings/gpio/xlnx,gpio-xilinx.yaml @@ -126,29 +126,29 @@ examples: - | #include <dt-bindings/interrupt-controller/arm-gic.h> - gpio@a0020000 { - compatible = "xlnx,xps-gpio-1.00.a"; - reg = <0xa0020000 0x10000>; - #gpio-cells = <2>; - #interrupt-cells = <0x2>; - clocks = <&zynqmp_clk 71>; - gpio-controller; - interrupt-controller; - interrupt-names = "ip2intc_irpt"; - interrupt-parent = <&gic>; - interrupts = <0 89 4>; - xlnx,all-inputs = <0x0>; - xlnx,all-inputs-2 = <0x0>; - xlnx,all-outputs = <0x0>; - xlnx,all-outputs-2 = <0x0>; - xlnx,dout-default = <0x0>; - xlnx,dout-default-2 = <0x0>; - xlnx,gpio-width = <0x20>; - xlnx,gpio2-width = <0x20>; - xlnx,interrupt-present = <0x1>; - xlnx,is-dual = <0x1>; - xlnx,tri-default = <0xFFFFFFFF>; - xlnx,tri-default-2 = <0xFFFFFFFF>; - }; + gpio@a0020000 { + compatible = "xlnx,xps-gpio-1.00.a"; + reg = <0xa0020000 0x10000>; + #gpio-cells = <2>; + #interrupt-cells = <0x2>; + clocks = <&zynqmp_clk 71>; + gpio-controller; + interrupt-controller; + interrupt-names = "ip2intc_irpt"; + interrupt-parent = <&gic>; + interrupts = <0 89 4>; + xlnx,all-inputs = <0x0>; + xlnx,all-inputs-2 = <0x0>; + xlnx,all-outputs = <0x0>; + xlnx,all-outputs-2 = <0x0>; + xlnx,dout-default = <0x0>; + xlnx,dout-default-2 = <0x0>; + xlnx,gpio-width = <0x20>; + xlnx,gpio2-width = <0x20>; + xlnx,interrupt-present = <0x1>; + xlnx,is-dual = <0x1>; + xlnx,tri-default = <0xFFFFFFFF>; + xlnx,tri-default-2 = <0xFFFFFFFF>; + }; ... diff --git a/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml b/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml index bb93baa88879..e13e9d6dd148 100644 --- a/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml +++ b/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml @@ -12,7 +12,6 @@ description: PS_MODE). Every pin can be configured as input/output. maintainers: - - Mubin Sayyed <mubin.sayyed@amd.com> - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> properties: diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml index 735c7f06c24e..b8d659d272d0 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml @@ -17,6 +17,7 @@ properties: oneOf: - items: - enum: + - allwinner,sun50i-h616-mali - amlogic,meson-g12a-mali - mediatek,mt8183-mali - mediatek,mt8183b-mali @@ -24,7 +25,11 @@ properties: - realtek,rtd1619-mali - renesas,r9a07g044-mali - renesas,r9a07g054-mali + - renesas,r9a09g047-mali + - renesas,r9a09g056-mali + - renesas,r9a09g057-mali - rockchip,px30-mali + - rockchip,rk3562-mali - rockchip,rk3568-mali - rockchip,rk3576-mali - const: arm,mali-bifrost # Mali Bifrost GPU model/revision is fully discoverable @@ -142,6 +147,9 @@ allOf: enum: - renesas,r9a07g044-mali - renesas,r9a07g054-mali + - renesas,r9a09g047-mali + - renesas,r9a09g056-mali + - renesas,r9a09g057-mali then: properties: interrupts: diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml index 0801da33a385..48daba21a890 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml @@ -47,10 +47,13 @@ properties: - const: arm,mali-t760 - items: - enum: + - samsung,exynos7870-mali + - const: arm,mali-t830 + - items: + - enum: - rockchip,rk3399-mali - const: arm,mali-t860 - # "arm,mali-t830" # "arm,mali-t880" reg: diff --git a/Documentation/devicetree/bindings/gpu/brcm,bcm-v3d.yaml b/Documentation/devicetree/bindings/gpu/brcm,bcm-v3d.yaml index dc078ceeca9a..43c6d2d72456 100644 --- a/Documentation/devicetree/bindings/gpu/brcm,bcm-v3d.yaml +++ b/Documentation/devicetree/bindings/gpu/brcm,bcm-v3d.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Broadcom V3D GPU maintainers: - - Eric Anholt <eric@anholt.net> + - Maíra Canal <mcanal@igalia.com> - Nicolas Saenz Julienne <nsaenzjulienne@suse.de> properties: @@ -22,20 +22,12 @@ properties: - brcm,7278-v3d reg: - items: - - description: hub register (required) - - description: core0 register (required) - - description: GCA cache controller register (if GCA controller present) - - description: bridge register (if no external reset controller) minItems: 2 + maxItems: 4 reg-names: - items: - - const: hub - - const: core0 - - enum: [ bridge, gca ] - - enum: [ bridge, gca ] minItems: 2 + maxItems: 4 interrupts: items: @@ -58,6 +50,76 @@ required: - reg-names - interrupts +allOf: + - if: + properties: + compatible: + contains: + const: brcm,2711-v3d + then: + properties: + reg: + items: + - description: hub register + - description: core0 register + reg-names: + items: + - const: hub + - const: core0 + - if: + properties: + compatible: + contains: + const: brcm,2712-v3d + then: + properties: + reg: + items: + - description: hub register + - description: core0 register + - description: SMS state manager register + reg-names: + items: + - const: hub + - const: core0 + - const: sms + - if: + properties: + compatible: + contains: + const: brcm,7268-v3d + then: + properties: + reg: + items: + - description: hub register + - description: core0 register + - description: GCA cache controller register + - description: bridge register + reg-names: + items: + - const: hub + - const: core0 + - const: gca + - const: bridge + - if: + properties: + compatible: + contains: + const: brcm,7278-v3d + then: + properties: + reg: + items: + - description: hub register + - description: core0 register + - description: bridge register + reg-names: + items: + - const: hub + - const: core0 + - const: bridge + additionalProperties: false examples: @@ -66,9 +128,9 @@ examples: compatible = "brcm,7268-v3d"; reg = <0xf1200000 0x4000>, <0xf1208000 0x4000>, - <0xf1204000 0x100>, - <0xf1204100 0x100>; - reg-names = "hub", "core0", "bridge", "gca"; + <0xf1204100 0x100>, + <0xf1204000 0x100>; + reg-names = "hub", "core0", "gca", "bridge"; interrupts = <0 78 4>, <0 77 4>; }; diff --git a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml index 256e252f8087..4450e2e73b3c 100644 --- a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml +++ b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml @@ -12,10 +12,28 @@ maintainers: properties: compatible: - items: - - enum: - - ti,am62-gpu - - const: img,img-axe # IMG AXE GPU model/revision is fully discoverable + oneOf: + - items: + - enum: + - ti,am62-gpu + - const: img,img-axe-1-16m + # This deprecated element must be kept around to allow old kernels to + # work with newer dts. + - const: img,img-axe + - const: img,img-rogue + - items: + - enum: + - ti,j721s2-gpu + - const: img,img-bxs-4-64 + - const: img,img-rogue + + # This legacy combination of compatible strings was introduced early on + # before the more specific GPU identifiers were used. + - items: + - enum: + - ti,am62-gpu + - const: img,img-axe + deprecated: true reg: maxItems: 1 @@ -35,6 +53,18 @@ properties: maxItems: 1 power-domains: + minItems: 1 + maxItems: 2 + + power-domain-names: + items: + - const: a + - const: b + minItems: 1 + + dma-coherent: true + + resets: maxItems: 1 required: @@ -47,11 +77,49 @@ required: additionalProperties: false allOf: + # Constraints added alongside the new compatible strings that would otherwise + # create an ABI break. + - if: + properties: + compatible: + contains: + const: img,img-rogue + then: + required: + - power-domains + - power-domain-names + + - if: + properties: + compatible: + contains: + const: img,img-axe-1-16m + then: + properties: + power-domains: + maxItems: 1 + power-domain-names: + maxItems: 1 + + - if: + properties: + compatible: + contains: + const: img,img-bxs-4-64 + then: + properties: + power-domains: + minItems: 2 + power-domain-names: + minItems: 2 + - if: properties: compatible: contains: - const: ti,am62-gpu + enum: + - ti,am62-gpu + - ti,j721s2-gpu then: properties: clocks: @@ -64,10 +132,12 @@ examples: #include <dt-bindings/soc/ti,sci_pm_domain.h> gpu@fd00000 { - compatible = "ti,am62-gpu", "img,img-axe"; + compatible = "ti,am62-gpu", "img,img-axe-1-16m", "img,img-axe", + "img,img-rogue"; reg = <0x0fd00000 0x20000>; clocks = <&k3_clks 187 0>; clock-names = "core"; interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>; + power-domain-names = "a"; }; diff --git a/Documentation/devicetree/bindings/hwinfo/samsung,exynos-chipid.yaml b/Documentation/devicetree/bindings/hwinfo/samsung,exynos-chipid.yaml index 385aac7161a0..383020450d78 100644 --- a/Documentation/devicetree/bindings/hwinfo/samsung,exynos-chipid.yaml +++ b/Documentation/devicetree/bindings/hwinfo/samsung,exynos-chipid.yaml @@ -19,9 +19,11 @@ properties: - enum: - samsung,exynos5433-chipid - samsung,exynos7-chipid + - samsung,exynos7870-chipid - const: samsung,exynos4210-chipid - items: - enum: + - samsung,exynos2200-chipid - samsung,exynos7885-chipid - samsung,exynos8895-chipid - samsung,exynos9810-chipid diff --git a/Documentation/devicetree/bindings/hwinfo/via,vt8500-scc-id.yaml b/Documentation/devicetree/bindings/hwinfo/via,vt8500-scc-id.yaml new file mode 100644 index 000000000000..b0f425a4a882 --- /dev/null +++ b/Documentation/devicetree/bindings/hwinfo/via,vt8500-scc-id.yaml @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwinfo/via,vt8500-scc-id.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: VIA/WonderMedia SoC system configuration information + +maintainers: + - Alexey Charkov <alchark@gmail.com> + +description: + The system configuration controller on VIA/WonderMedia SoC's contains a chip + identifier and revision used to differentiate between different hardware + versions of on-chip IP blocks having their own peculiarities which may or + may not be captured by their respective DT compatible strings + +properties: + compatible: + items: + - const: via,vt8500-scc-id + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + chipid@d8120000 { + compatible = "via,vt8500-scc-id"; + reg = <0xd8120000 0x4>; + }; diff --git a/Documentation/devicetree/bindings/hwmon/adi,ad741x.yaml b/Documentation/devicetree/bindings/hwmon/adi,ad741x.yaml index ce7f8ce9da0a..236d8b52ef85 100644 --- a/Documentation/devicetree/bindings/hwmon/adi,ad741x.yaml +++ b/Documentation/devicetree/bindings/hwmon/adi,ad741x.yaml @@ -1,7 +1,6 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- - $id: http://devicetree.org/schemas/hwmon/adi,ad741x.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# diff --git a/Documentation/devicetree/bindings/hwmon/adi,adm1275.yaml b/Documentation/devicetree/bindings/hwmon/adi,adm1275.yaml index fd79bf2e0d16..ddb72857c846 100644 --- a/Documentation/devicetree/bindings/hwmon/adi,adm1275.yaml +++ b/Documentation/devicetree/bindings/hwmon/adi,adm1275.yaml @@ -1,7 +1,6 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- - $id: http://devicetree.org/schemas/hwmon/adi,adm1275.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# diff --git a/Documentation/devicetree/bindings/hwmon/adi,ltc2991.yaml b/Documentation/devicetree/bindings/hwmon/adi,ltc2991.yaml index 011e5b65c79c..1ff44cb22ef4 100644 --- a/Documentation/devicetree/bindings/hwmon/adi,ltc2991.yaml +++ b/Documentation/devicetree/bindings/hwmon/adi,ltc2991.yaml @@ -1,7 +1,6 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- - $id: http://devicetree.org/schemas/hwmon/adi,ltc2991.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# diff --git a/Documentation/devicetree/bindings/hwmon/gpio-fan.yaml b/Documentation/devicetree/bindings/hwmon/gpio-fan.yaml index 7f30cfc87350..4faebbb4c7ab 100644 --- a/Documentation/devicetree/bindings/hwmon/gpio-fan.yaml +++ b/Documentation/devicetree/bindings/hwmon/gpio-fan.yaml @@ -23,6 +23,9 @@ properties: alarm-gpios: maxItems: 1 + fan-supply: + description: Power supply for fan + gpio-fan,speed-map: $ref: /schemas/types.yaml#/definitions/uint32-matrix minItems: 2 diff --git a/Documentation/devicetree/bindings/hwmon/lltc,ltc2978.yaml b/Documentation/devicetree/bindings/hwmon/lltc,ltc2978.yaml index 37e1dc9c7dd3..aa801ef1640b 100644 --- a/Documentation/devicetree/bindings/hwmon/lltc,ltc2978.yaml +++ b/Documentation/devicetree/bindings/hwmon/lltc,ltc2978.yaml @@ -12,6 +12,8 @@ maintainers: properties: compatible: enum: + - lltc,lt7170 + - lltc,lt7171 - lltc,ltc2972 - lltc,ltc2974 - lltc,ltc2975 @@ -30,6 +32,7 @@ properties: - lltc,ltc7880 - lltc,ltm2987 - lltc,ltm4664 + - lltc,ltm4673 - lltc,ltm4675 - lltc,ltm4676 - lltc,ltm4677 @@ -46,6 +49,7 @@ properties: description: | list of regulators provided by this controller. Valid names of regulators depend on number of supplies supported per device: + * lt7170, lt7171 : vout0 * ltc2972 vout0 - vout1 * ltc2974, ltc2975 : vout0 - vout3 * ltc2977, ltc2979, ltc2980, ltm2987 : vout0 - vout7 @@ -55,6 +59,7 @@ properties: * ltc7880 : vout0 - vout1 * ltc3883 : vout0 * ltm4664 : vout0 - vout1 + * ltm4673 : vout0 - vout3 * ltm4675, ltm4676, ltm4677, ltm4678 : vout0 - vout1 * ltm4680, ltm4686 : vout0 - vout1 * ltm4700 : vout0 - vout1 diff --git a/Documentation/devicetree/bindings/hwmon/maxim,max20730.yaml b/Documentation/devicetree/bindings/hwmon/maxim,max20730.yaml index 93e86e3b4602..8af0d7458e62 100644 --- a/Documentation/devicetree/bindings/hwmon/maxim,max20730.yaml +++ b/Documentation/devicetree/bindings/hwmon/maxim,max20730.yaml @@ -1,7 +1,6 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- - $id: http://devicetree.org/schemas/hwmon/maxim,max20730.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# diff --git a/Documentation/devicetree/bindings/hwmon/maxim,max6639.yaml b/Documentation/devicetree/bindings/hwmon/maxim,max6639.yaml index 4f5837a30773..139a95e00fe5 100644 --- a/Documentation/devicetree/bindings/hwmon/maxim,max6639.yaml +++ b/Documentation/devicetree/bindings/hwmon/maxim,max6639.yaml @@ -1,7 +1,6 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- - $id: http://devicetree.org/schemas/hwmon/maxim,max6639.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# diff --git a/Documentation/devicetree/bindings/hwmon/maxim,max6650.yaml b/Documentation/devicetree/bindings/hwmon/maxim,max6650.yaml index 2c26104a5e16..24c7697fdc1a 100644 --- a/Documentation/devicetree/bindings/hwmon/maxim,max6650.yaml +++ b/Documentation/devicetree/bindings/hwmon/maxim,max6650.yaml @@ -1,7 +1,6 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- - $id: http://devicetree.org/schemas/hwmon/maxim,max6650.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# diff --git a/Documentation/devicetree/bindings/hwmon/microchip,emc2305.yaml b/Documentation/devicetree/bindings/hwmon/microchip,emc2305.yaml new file mode 100644 index 000000000000..d3f06ebc19fa --- /dev/null +++ b/Documentation/devicetree/bindings/hwmon/microchip,emc2305.yaml @@ -0,0 +1,111 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwmon/microchip,emc2305.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip EMC2305 SMBus compliant PWM fan controller + +maintainers: + - Michael Shych <michaelsh@nvidia.com> + +description: + Microchip EMC2301/2/3/5 pwm controller which supports up to five programmable + fan control circuits. + +properties: + compatible: + oneOf: + - enum: + - microchip,emc2305 + - items: + - enum: + - microchip,emc2303 + - microchip,emc2302 + - microchip,emc2301 + - const: microchip,emc2305 + + reg: + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + '#pwm-cells': + const: 3 + description: | + Number of cells in a PWM specifier. + - cell 0: The PWM frequency + - cell 1: The PWM polarity: 0 or PWM_POLARITY_INVERTED + - cell 2: The PWM output config: + - 0 (Open-Drain) + - 1 (Push-Pull) + +patternProperties: + '^fan@[0-4]$': + $ref: fan-common.yaml# + unevaluatedProperties: false + properties: + reg: + description: + The fan number used to determine the associated PWM channel. + maxItems: 1 + + required: + - reg + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include <dt-bindings/pwm/pwm.h> + i2c { + #address-cells = <1>; + #size-cells = <0>; + + fan_controller: fan-controller@2f { + compatible = "microchip,emc2305"; + reg = <0x2f>; + #address-cells = <1>; + #size-cells = <0>; + #pwm-cells = <3>; + + fan@0 { + reg = <0x0>; + pwms = <&fan_controller 26000 PWM_POLARITY_INVERTED 1>; + #cooling-cells = <2>; + }; + + fan@1 { + reg = <0x1>; + pwms = <&fan_controller 26000 0 1>; + #cooling-cells = <2>; + }; + + fan@2 { + reg = <0x2>; + pwms = <&fan_controller 26000 0 1>; + #cooling-cells = <2>; + }; + + fan@3 { + reg = <0x3>; + pwms = <&fan_controller 26000 0 1>; + #cooling-cells = <2>; + }; + + fan@4 { + reg = <0x4>; + pwms = <&fan_controller 26000 0 1>; + #cooling-cells = <2>; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/hwmon/national,lm90.yaml b/Documentation/devicetree/bindings/hwmon/national,lm90.yaml index 6e59c8fdef30..4feb76919404 100644 --- a/Documentation/devicetree/bindings/hwmon/national,lm90.yaml +++ b/Documentation/devicetree/bindings/hwmon/national,lm90.yaml @@ -32,6 +32,9 @@ properties: - national,lm89 - national,lm90 - national,lm99 + - nuvoton,nct7716 + - nuvoton,nct7717 + - nuvoton,nct7718 - nxp,sa56004 - onnn,nct1008 - ti,tmp451 @@ -120,6 +123,8 @@ allOf: - dallas,max6659 - dallas,max6695 - dallas,max6696 + - nuvoton,nct7716 + - nuvoton,nct7717 then: patternProperties: "^channel@([0-2])$": @@ -155,6 +160,7 @@ allOf: - national,lm89 - national,lm90 - national,lm99 + - nuvoton,nct7718 - nxp,sa56004 - winbond,w83l771 then: diff --git a/Documentation/devicetree/bindings/hwmon/ntc-thermistor.yaml b/Documentation/devicetree/bindings/hwmon/ntc-thermistor.yaml index 3d0146e20d3e..b8e500e6cd9f 100644 --- a/Documentation/devicetree/bindings/hwmon/ntc-thermistor.yaml +++ b/Documentation/devicetree/bindings/hwmon/ntc-thermistor.yaml @@ -76,7 +76,7 @@ properties: - const: murata,ncp03wf104 - const: murata,ncp15xh103 - const: samsung,1404-001221 - # Deprecated "ntp," compatible strings + # Deprecated "ntc," compatible strings - const: ntc,ncp15wb473 deprecated: true - const: ntc,ncp18wb473 diff --git a/Documentation/devicetree/bindings/hwmon/nuvoton,nct6775.yaml b/Documentation/devicetree/bindings/hwmon/nuvoton,nct6775.yaml index e3db642878d4..244470282890 100644 --- a/Documentation/devicetree/bindings/hwmon/nuvoton,nct6775.yaml +++ b/Documentation/devicetree/bindings/hwmon/nuvoton,nct6775.yaml @@ -1,7 +1,6 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- - $id: http://devicetree.org/schemas/hwmon/nuvoton,nct6775.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# diff --git a/Documentation/devicetree/bindings/hwmon/nuvoton,nct7363.yaml b/Documentation/devicetree/bindings/hwmon/nuvoton,nct7363.yaml index c1e5dedc2f6a..625fcf5d3b54 100644 --- a/Documentation/devicetree/bindings/hwmon/nuvoton,nct7363.yaml +++ b/Documentation/devicetree/bindings/hwmon/nuvoton,nct7363.yaml @@ -1,7 +1,6 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- - $id: http://devicetree.org/schemas/hwmon/nuvoton,nct7363.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# diff --git a/Documentation/devicetree/bindings/hwmon/nuvoton,nct7802.yaml b/Documentation/devicetree/bindings/hwmon/nuvoton,nct7802.yaml index cd8dcd797031..c16a33227e94 100644 --- a/Documentation/devicetree/bindings/hwmon/nuvoton,nct7802.yaml +++ b/Documentation/devicetree/bindings/hwmon/nuvoton,nct7802.yaml @@ -1,7 +1,6 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- - $id: http://devicetree.org/schemas/hwmon/nuvoton,nct7802.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# diff --git a/Documentation/devicetree/bindings/hwmon/pmbus/adi,lt3074.yaml b/Documentation/devicetree/bindings/hwmon/pmbus/adi,lt3074.yaml new file mode 100644 index 000000000000..bf028a8718f1 --- /dev/null +++ b/Documentation/devicetree/bindings/hwmon/pmbus/adi,lt3074.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwmon/pmbus/adi,lt3074.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices LT3074 voltage regulator + +maintainers: + - Cedric Encarnacion <cedricjustine.encarnacion@analog.com> + +description: | + The LT3074 is a low voltage, ultra-low noise and ultra-fast transient + response linear regulator. It allows telemetry for input/output voltage, + output current and temperature through the PMBus serial interface. + + Datasheet: + https://www.analog.com/en/products/lt3074.html + +allOf: + - $ref: /schemas/regulator/regulator.yaml# + +properties: + compatible: + enum: + - adi,lt3074 + + reg: + maxItems: 1 + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + regulator@6d { + compatible = "adi,lt3074"; + reg = <0x6d>; + regulator-name = "vout"; + regulator-max-microvolt = <1250000>; + regulator-min-microvolt = <1150000>; + }; + }; diff --git a/Documentation/devicetree/bindings/hwmon/pmbus/mps,mpq8785.yaml b/Documentation/devicetree/bindings/hwmon/pmbus/mps,mpq8785.yaml new file mode 100644 index 000000000000..90970a0433e9 --- /dev/null +++ b/Documentation/devicetree/bindings/hwmon/pmbus/mps,mpq8785.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwmon/pmbus/mps,mpq8785.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Monolithic Power Systems Multiphase Voltage Regulators with PMBus + +maintainers: + - Charles Hsu <ythsu0511@gmail.com> + +description: + Monolithic Power Systems digital multiphase voltage regulators with PMBus. + +properties: + compatible: + enum: + - mps,mpm3695 + - mps,mpm3695-25 + - mps,mpm82504 + - mps,mpq8785 + + reg: + maxItems: 1 + + mps,vout-fb-divider-ratio-permille: + description: + The feedback resistor divider ratio, expressed in permille + (Vfb / Vout * 1000). This value is written to the PMBUS_VOUT_SCALE_LOOP + register and is required for correct output voltage presentation. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 4095 + default: 706 + +required: + - compatible + - reg + +allOf: + - if: + properties: + compatible: + enum: + - mps,mpm3695 + - mps,mpm82504 + then: + properties: + mps,vout-fb-divider-ratio-permille: + maximum: 1023 + + - if: + properties: + compatible: + const: mps,mpq8785 + then: + properties: + mps,vout-fb-divider-ratio-permille: + maximum: 2047 + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + pmic@30 { + compatible = "mps,mpm82504"; + reg = <0x30>; + mps,vout-fb-divider-ratio-permille = <600>; + }; + }; diff --git a/Documentation/devicetree/bindings/hwmon/pmbus/ti,ucd90320.yaml b/Documentation/devicetree/bindings/hwmon/pmbus/ti,ucd90320.yaml index e8feee38c76c..f8bea1c0e94a 100644 --- a/Documentation/devicetree/bindings/hwmon/pmbus/ti,ucd90320.yaml +++ b/Documentation/devicetree/bindings/hwmon/pmbus/ti,ucd90320.yaml @@ -28,6 +28,15 @@ properties: reg: maxItems: 1 + gpio-controller: true + + gpio-line-names: + minItems: 84 + maxItems: 84 + + '#gpio-cells': + const: 1 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/hwmon/sophgo,sg2042-hwmon-mcu.yaml b/Documentation/devicetree/bindings/hwmon/sophgo,sg2042-hwmon-mcu.yaml index f0667ac41d75..b76805d39427 100644 --- a/Documentation/devicetree/bindings/hwmon/sophgo,sg2042-hwmon-mcu.yaml +++ b/Documentation/devicetree/bindings/hwmon/sophgo,sg2042-hwmon-mcu.yaml @@ -11,7 +11,11 @@ maintainers: properties: compatible: - const: sophgo,sg2042-hwmon-mcu + oneOf: + - items: + - const: sophgo,sg2044-hwmon-mcu + - const: sophgo,sg2042-hwmon-mcu + - const: sophgo,sg2042-hwmon-mcu reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/hwmon/ti,adc128d818.yaml b/Documentation/devicetree/bindings/hwmon/ti,adc128d818.yaml index a32035409cee..78e3d97e2ae5 100644 --- a/Documentation/devicetree/bindings/hwmon/ti,adc128d818.yaml +++ b/Documentation/devicetree/bindings/hwmon/ti,adc128d818.yaml @@ -1,7 +1,6 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- - $id: http://devicetree.org/schemas/hwmon/ti,adc128d818.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# diff --git a/Documentation/devicetree/bindings/hwmon/ti,ads7828.yaml b/Documentation/devicetree/bindings/hwmon/ti,ads7828.yaml index 926be9a29044..fb80456120e1 100644 --- a/Documentation/devicetree/bindings/hwmon/ti,ads7828.yaml +++ b/Documentation/devicetree/bindings/hwmon/ti,ads7828.yaml @@ -1,7 +1,6 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- - $id: http://devicetree.org/schemas/hwmon/ti,ads7828.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# diff --git a/Documentation/devicetree/bindings/hwmon/ti,amc6821.yaml b/Documentation/devicetree/bindings/hwmon/ti,amc6821.yaml index 5d33f1a23d03..9ca7356760a7 100644 --- a/Documentation/devicetree/bindings/hwmon/ti,amc6821.yaml +++ b/Documentation/devicetree/bindings/hwmon/ti,amc6821.yaml @@ -28,6 +28,17 @@ properties: i2c-mux: type: object + fan: + $ref: fan-common.yaml# + unevaluatedProperties: false + + "#pwm-cells": + const: 2 + description: | + Number of cells in a PWM specifier. + - cell 0: PWM period in nanoseconds + - cell 1: PWM polarity: 0 or PWM_POLARITY_INVERTED + required: - compatible - reg @@ -50,9 +61,14 @@ examples: #address-cells = <1>; #size-cells = <0>; - fan@18 { + fan_controller: fan@18 { compatible = "ti,amc6821"; reg = <0x18>; + #pwm-cells = <2>; + + fan { + pwms = <&fan_controller 40000 0>; + }; }; }; diff --git a/Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml b/Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml index 05a9cb36cd82..d1fb7b9abda0 100644 --- a/Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml +++ b/Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml @@ -1,7 +1,6 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- - $id: http://devicetree.org/schemas/hwmon/ti,ina2xx.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# @@ -20,6 +19,7 @@ description: | properties: compatible: enum: + - silergy,sq52206 - silergy,sy24655 - ti,ina209 - ti,ina219 @@ -27,6 +27,7 @@ properties: - ti,ina226 - ti,ina230 - ti,ina231 + - ti,ina233 - ti,ina237 - ti,ina238 - ti,ina260 @@ -58,6 +59,9 @@ properties: shunt voltage, and a value of 4 maps to ADCRANGE=0 such that a wider voltage range is used. + For SQ52206,the shunt-gain value 1 mapps to ADCRANGE=10/11, the value 2 + mapps to ADCRANGE=01, and the value 4 mapps to ADCRANGE=00. + The default value is device dependent, and is defined by the reset value of PGA/ADCRANGE in the respective configuration registers. $ref: /schemas/types.yaml#/definitions/uint32 @@ -75,12 +79,42 @@ properties: the alert polarity to active-high. $ref: /schemas/types.yaml#/definitions/flag + ti,maximum-expected-current-microamp: + description: | + This value indicates the maximum current in microamps that you can + expect to measure with ina233 in your circuit. + + This value will be used to calculate the Current_LSB and current/power + coefficient for the pmbus and to calibrate the IC. + minimum: 32768 + maximum: 4294967295 + default: 32768000 + required: - compatible - reg allOf: - $ref: hwmon-common.yaml# + - if: + properties: + compatible: + contains: + enum: + - silergy,sq52206 + - silergy,sy24655 + - ti,ina209 + - ti,ina219 + - ti,ina220 + - ti,ina226 + - ti,ina230 + - ti,ina231 + - ti,ina237 + - ti,ina238 + - ti,ina260 + then: + properties: + ti,maximum-expected-current-microamp: false unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/hwmon/ti,lm87.yaml b/Documentation/devicetree/bindings/hwmon/ti,lm87.yaml index f553235a7321..63d8cf467806 100644 --- a/Documentation/devicetree/bindings/hwmon/ti,lm87.yaml +++ b/Documentation/devicetree/bindings/hwmon/ti,lm87.yaml @@ -1,7 +1,6 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- - $id: http://devicetree.org/schemas/hwmon/ti,lm87.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# diff --git a/Documentation/devicetree/bindings/hwmon/ti,tmp102.yaml b/Documentation/devicetree/bindings/hwmon/ti,tmp102.yaml index 7e5b62a0215d..4c89448eba0d 100644 --- a/Documentation/devicetree/bindings/hwmon/ti,tmp102.yaml +++ b/Documentation/devicetree/bindings/hwmon/ti,tmp102.yaml @@ -23,6 +23,9 @@ properties: "#thermal-sensor-cells": const: 1 + vcc-supply: + description: Power supply for tmp102 + required: - compatible - reg @@ -42,6 +45,7 @@ examples: reg = <0x48>; interrupt-parent = <&gpio7>; interrupts = <16 IRQ_TYPE_LEVEL_LOW>; + vcc-supply = <&supply>; #thermal-sensor-cells = <1>; }; }; diff --git a/Documentation/devicetree/bindings/hwmon/ti,tmp513.yaml b/Documentation/devicetree/bindings/hwmon/ti,tmp513.yaml index 227858e76058..cba5b4a1b81f 100644 --- a/Documentation/devicetree/bindings/hwmon/ti,tmp513.yaml +++ b/Documentation/devicetree/bindings/hwmon/ti,tmp513.yaml @@ -1,7 +1,6 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- - $id: http://devicetree.org/schemas/hwmon/ti,tmp513.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# diff --git a/Documentation/devicetree/bindings/hwmon/ti,tps23861.yaml b/Documentation/devicetree/bindings/hwmon/ti,tps23861.yaml index f58248c29e22..ee7de53e1918 100644 --- a/Documentation/devicetree/bindings/hwmon/ti,tps23861.yaml +++ b/Documentation/devicetree/bindings/hwmon/ti,tps23861.yaml @@ -1,7 +1,6 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- - $id: http://devicetree.org/schemas/hwmon/ti,tps23861.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# diff --git a/Documentation/devicetree/bindings/hwmon/winbond,w83781d.yaml b/Documentation/devicetree/bindings/hwmon/winbond,w83781d.yaml index 31ce77a4b087..6971ecb314eb 100644 --- a/Documentation/devicetree/bindings/hwmon/winbond,w83781d.yaml +++ b/Documentation/devicetree/bindings/hwmon/winbond,w83781d.yaml @@ -1,7 +1,6 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- - $id: http://devicetree.org/schemas/hwmon/winbond,w83781d.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# diff --git a/Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml b/Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml index 70cc2ee9ee27..8d47b290b4ed 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml +++ b/Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml @@ -30,6 +30,7 @@ properties: - items: - enum: - samsung,exynos5433-hsi2c + - samsung,exynos7870-hsi2c - tesla,fsd-hsi2c - const: samsung,exynos7-hsi2c - items: diff --git a/Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.yaml b/Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.yaml index 1dcb9c78de3b..969030a6f82a 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.yaml +++ b/Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.yaml @@ -26,6 +26,7 @@ properties: - fsl,imx8qm-lpi2c - fsl,imx8ulp-lpi2c - fsl,imx93-lpi2c + - fsl,imx94-lpi2c - fsl,imx95-lpi2c - const: fsl,imx7ulp-lpi2c diff --git a/Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml b/Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml index fda0467cdd95..23fe8ff76645 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml +++ b/Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml @@ -52,6 +52,7 @@ properties: - const: mediatek,mt8173-i2c - items: - enum: + - mediatek,mt6893-i2c - mediatek,mt8195-i2c - const: mediatek,mt8192-i2c diff --git a/Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml b/Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml index a9dae5b52f28..2f1e97969c3f 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml +++ b/Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml @@ -37,6 +37,8 @@ properties: - rockchip,px30-i2c - rockchip,rk3308-i2c - rockchip,rk3328-i2c + - rockchip,rk3528-i2c + - rockchip,rk3562-i2c - rockchip,rk3568-i2c - rockchip,rk3576-i2c - rockchip,rk3588-i2c diff --git a/Documentation/devicetree/bindings/i2c/i2c-wmt.txt b/Documentation/devicetree/bindings/i2c/i2c-wmt.txt deleted file mode 100644 index 94a425eaa6c7..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-wmt.txt +++ /dev/null @@ -1,24 +0,0 @@ -* Wondermedia I2C Controller - -Required properties : - - - compatible : should be "wm,wm8505-i2c" - - reg : Offset and length of the register set for the device - - interrupts : <IRQ> where IRQ is the interrupt number - - clocks : phandle to the I2C clock source - -Optional properties : - - - clock-frequency : desired I2C bus clock frequency in Hz. - Valid values are 100000 and 400000. - Default to 100000 if not specified, or invalid value. - -Example : - - i2c_0: i2c@d8280000 { - compatible = "wm,wm8505-i2c"; - reg = <0xd8280000 0x1000>; - interrupts = <19>; - clocks = <&clki2c0>; - clock-frequency = <400000>; - }; diff --git a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml index b57ae6963e62..6b6f6762d122 100644 --- a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml @@ -97,7 +97,10 @@ properties: resets: items: - - description: module reset + - description: + Module reset. This property is optional for controllers in Tegra194, + Tegra234 etc where an internal software reset is available as an + alternative. reset-names: items: @@ -116,6 +119,13 @@ properties: - const: rx - const: tx +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + allOf: - $ref: /schemas/i2c/i2c-controller.yaml - if: @@ -169,6 +179,18 @@ allOf: properties: power-domains: false + - if: + not: + properties: + compatible: + contains: + enum: + - nvidia,tegra194-i2c + then: + required: + - resets + - reset-names + unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-qup.yaml b/Documentation/devicetree/bindings/i2c/qcom,i2c-qup.yaml index f43947514d48..758d8f6321e1 100644 --- a/Documentation/devicetree/bindings/i2c/qcom,i2c-qup.yaml +++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-qup.yaml @@ -40,6 +40,9 @@ properties: - const: tx - const: rx + interconnects: + maxItems: 1 + interrupts: maxItems: 1 @@ -52,9 +55,15 @@ properties: - const: default - const: sleep + power-domains: + maxItems: 1 + reg: maxItems: 1 + required-opps: + maxItems: 1 + required: - compatible - clock-names @@ -67,7 +76,9 @@ unevaluatedProperties: false examples: - | #include <dt-bindings/clock/qcom,gcc-msm8998.h> + #include <dt-bindings/interconnect/qcom,msm8996.h> #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/qcom-rpmpd.h> i2c@c175000 { compatible = "qcom,i2c-qup-v2.2.1"; @@ -82,6 +93,9 @@ examples: pinctrl-names = "default", "sleep"; pinctrl-0 = <&blsp1_i2c1_default>; pinctrl-1 = <&blsp1_i2c1_sleep>; + power-domains = <&rpmpd MSM8909_VDDCX>; + required-opps = <&rpmpd_opp_svs_krait>; + interconnects = <&pnoc MASTER_BLSP_1 &bimc SLAVE_EBI_CH0>; clock-frequency = <400000>; #address-cells = <1>; diff --git a/Documentation/devicetree/bindings/i2c/realtek,rtl9301-i2c.yaml b/Documentation/devicetree/bindings/i2c/realtek,rtl9301-i2c.yaml index eddfd329c67b..69ac5db8b914 100644 --- a/Documentation/devicetree/bindings/i2c/realtek,rtl9301-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/realtek,rtl9301-i2c.yaml @@ -26,7 +26,8 @@ properties: - const: realtek,rtl9301-i2c reg: - description: Register offset and size this I2C controller. + items: + - description: Register offset and size this I2C controller. "#address-cells": const: 1 diff --git a/Documentation/devicetree/bindings/i2c/renesas,riic.yaml b/Documentation/devicetree/bindings/i2c/renesas,riic.yaml index 1b7fed232642..cc39511a49d6 100644 --- a/Documentation/devicetree/bindings/i2c/renesas,riic.yaml +++ b/Documentation/devicetree/bindings/i2c/renesas,riic.yaml @@ -29,6 +29,7 @@ properties: - enum: - renesas,riic-r9a08g045 # RZ/G3S - renesas,riic-r9a09g047 # RZ/G3E + - renesas,riic-r9a09g056 # RZ/V2N - const: renesas,riic-r9a09g057 # RZ/V2H(P) - const: renesas,riic-r9a09g057 # RZ/V2H(P) diff --git a/Documentation/devicetree/bindings/i2c/samsung,s3c2410-i2c.yaml b/Documentation/devicetree/bindings/i2c/samsung,s3c2410-i2c.yaml index bbc568485627..6ba7d793504c 100644 --- a/Documentation/devicetree/bindings/i2c/samsung,s3c2410-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/samsung,s3c2410-i2c.yaml @@ -22,6 +22,7 @@ properties: - samsung,exynos5-sata-phy-i2c - items: - enum: + - samsung,exynos7870-i2c - samsung,exynos7885-i2c - samsung,exynos850-i2c - const: samsung,s3c2440-i2c diff --git a/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml b/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml index e5d05263c45a..d904191bb0c6 100644 --- a/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml @@ -27,15 +27,18 @@ properties: oneOf: - description: Generic Synopsys DesignWare I2C controller const: snps,designware-i2c - - description: Microsemi Ocelot SoCs I2C controller + - description: Renesas RZ/N1D I2C controller items: - - const: mscc,ocelot-i2c + - const: renesas,r9a06g032-i2c # RZ/N1D + - const: renesas,rzn1-i2c # RZ/N1 - const: snps,designware-i2c - description: Baikal-T1 SoC System I2C controller const: baikal,bt1-sys-i2c - - description: T-HEAD TH1520 SoCs I2C controller - items: - - const: thead,th1520-i2c + - items: + - enum: + - mscc,ocelot-i2c + - sophgo,sg2044-i2c + - thead,th1520-i2c - const: snps,designware-i2c reg: diff --git a/Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml b/Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml new file mode 100644 index 000000000000..3d6aefb0d0f1 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/spacemit,k1-i2c.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: I2C controller embedded in SpacemiT's K1 SoC + +maintainers: + - Troy Mitchell <troymitchell988@gmail.com> + +properties: + compatible: + const: spacemit,k1-i2c + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: I2C Functional Clock + - description: APB Bus Clock + + clock-names: + items: + - const: func + - const: bus + + clock-frequency: + description: | + K1 support three different modes which running different frequencies + standard speed mode: up to 100000 (100Hz) + fast speed mode : up to 400000 (400Hz) + high speed mode : up to 3300000 (3.3Mhz) + default: 400000 + maximum: 3300000 + +required: + - compatible + - reg + - interrupts + - clocks + +unevaluatedProperties: false + +examples: + - | + i2c@d4010800 { + compatible = "spacemit,k1-i2c"; + reg = <0xd4010800 0x38>; + interrupt-parent = <&plic>; + interrupts = <36>; + clocks =<&ccu 32>, <&ccu 84>; + clock-names = "func", "bus"; + clock-frequency = <100000>; + }; + +... diff --git a/Documentation/devicetree/bindings/i2c/ti,omap4-i2c.yaml b/Documentation/devicetree/bindings/i2c/ti,omap4-i2c.yaml index 8c2e35fabf5b..58d32ceeacfc 100644 --- a/Documentation/devicetree/bindings/i2c/ti,omap4-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/ti,omap4-i2c.yaml @@ -47,6 +47,11 @@ properties: $ref: /schemas/types.yaml#/definitions/string deprecated: true + mux-states: + description: + mux controller node to route the I2C signals from SoC to clients. + maxItems: 1 + required: - compatible - reg @@ -87,4 +92,5 @@ examples: interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; + mux-states = <&i2c_mux 1>; }; diff --git a/Documentation/devicetree/bindings/i2c/wm,wm8505-i2c.yaml b/Documentation/devicetree/bindings/i2c/wm,wm8505-i2c.yaml new file mode 100644 index 000000000000..e498ce47b885 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/wm,wm8505-i2c.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/wm,wm8505-i2c.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: I2C Controller on WonderMedia WM8505 and related SoCs + +maintainers: + - Alexey Charkov <alchark@gmail.com> + +allOf: + - $ref: /schemas/i2c/i2c-controller.yaml# + +properties: + compatible: + const: wm,wm8505-i2c + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-frequency: + enum: [100000, 400000] + +required: + - compatible + - reg + - interrupts + - clocks + +unevaluatedProperties: false + +examples: + - | + i2c_0: i2c@d8280000 { + compatible = "wm,wm8505-i2c"; + reg = <0xd8280000 0x1000>; + interrupts = <19>; + clocks = <&clki2c0>; + clock-frequency = <400000>; + }; diff --git a/Documentation/devicetree/bindings/i3c/silvaco,i3c-master.yaml b/Documentation/devicetree/bindings/i3c/silvaco,i3c-master.yaml index c56ff77677f1..853092f7522d 100644 --- a/Documentation/devicetree/bindings/i3c/silvaco,i3c-master.yaml +++ b/Documentation/devicetree/bindings/i3c/silvaco,i3c-master.yaml @@ -9,12 +9,17 @@ title: Silvaco I3C master maintainers: - Conor Culhane <conor.culhane@silvaco.com> -allOf: - - $ref: i3c.yaml# - properties: compatible: - const: silvaco,i3c-master-v1 + oneOf: + - enum: + - nuvoton,npcm845-i3c + - silvaco,i3c-master-v1 + - items: + - enum: + - nxp,imx94-i3c + - nxp,imx95-i3c + - const: silvaco,i3c-master-v1 reg: maxItems: 1 @@ -23,12 +28,14 @@ properties: maxItems: 1 clocks: + minItems: 2 items: - description: system clock - description: bus clock - description: other (slower) events clock clock-names: + minItems: 2 items: - const: pclk - const: fast_clk @@ -44,6 +51,34 @@ required: - clock-names - clocks +allOf: + - $ref: i3c.yaml# + - if: + properties: + compatible: + enum: + - nuvoton,npcm845-i3c + - silvaco,i3c-master-v1 + then: + properties: + clocks: + minItems: 3 + clock-names: + minItems: 3 + - if: + properties: + compatible: + contains: + enum: + - nxp,imx94-i3c + - nxp,imx95-i3c + then: + properties: + clocks: + maxItems: 2 + clock-names: + maxItems: 2 + unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml b/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml index 4fc13e3c0f75..5f6467375811 100644 --- a/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml +++ b/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml @@ -34,6 +34,9 @@ properties: interrupts: maxItems: 1 + power-domains: + maxItems: 1 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml new file mode 100644 index 000000000000..54e7349317b7 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml @@ -0,0 +1,110 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright 2024 Analog Devices Inc. +# Copyright 2024 BayLibre, SAS. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/adi,ad4030.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices AD4030 and AD4630 ADC families + +maintainers: + - Michael Hennerich <michael.hennerich@analog.com> + - Nuno Sa <nuno.sa@analog.com> + +description: | + Analog Devices AD4030 single channel and AD4630/AD4632 dual channel precision + SAR ADC families + + * https://www.analog.com/media/en/technical-documentation/data-sheets/ad4030-24-4032-24.pdf + * https://www.analog.com/media/en/technical-documentation/data-sheets/ad4630-24_ad4632-24.pdf + * https://www.analog.com/media/en/technical-documentation/data-sheets/ad4630-16-4632-16.pdf + +properties: + compatible: + enum: + - adi,ad4030-24 + - adi,ad4032-24 + - adi,ad4630-16 + - adi,ad4630-24 + - adi,ad4632-16 + - adi,ad4632-24 + + reg: + maxItems: 1 + + spi-max-frequency: + maximum: 102040816 + + spi-rx-bus-width: + enum: [1, 2, 4] + + vdd-5v-supply: true + vdd-1v8-supply: true + vio-supply: true + + ref-supply: + description: + Optional External unbuffered reference. Used when refin-supply is not + connected. + + refin-supply: + description: + Internal buffered Reference. Used when ref-supply is not connected. + + cnv-gpios: + description: + The Convert Input (CNV). It initiates the sampling conversions. + maxItems: 1 + + reset-gpios: + description: + The Reset Input (/RST). Used for asynchronous device reset. + maxItems: 1 + + interrupts: + description: + The BUSY pin is used to signal that the conversions results are available + to be transferred when in SPI Clocking Mode. This nodes should be + connected to an interrupt that is triggered when the BUSY line goes low. + maxItems: 1 + + interrupt-names: + const: busy + +required: + - compatible + - reg + - vdd-5v-supply + - vdd-1v8-supply + - vio-supply + - cnv-gpios + +oneOf: + - required: + - ref-supply + - required: + - refin-supply + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + spi { + #address-cells = <1>; + #size-cells = <0>; + + adc@0 { + compatible = "adi,ad4030-24"; + reg = <0>; + spi-max-frequency = <80000000>; + vdd-5v-supply = <&supply_5V>; + vdd-1v8-supply = <&supply_1_8V>; + vio-supply = <&supply_1_8V>; + ref-supply = <&supply_5V>; + cnv-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; + }; + }; diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4695.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad4695.yaml index 7d2229dee444..cbde7a0505d2 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad4695.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4695.yaml @@ -84,6 +84,10 @@ properties: description: The Reset Input (RESET). Should be configured GPIO_ACTIVE_LOW. maxItems: 1 + pwms: + description: PWM signal connected to the CNV pin. + maxItems: 1 + interrupts: minItems: 1 items: @@ -106,6 +110,15 @@ properties: The first cell is the GPn number: 0 to 3. The second cell takes standard GPIO flags. + '#trigger-source-cells': + description: | + First cell indicates the output signal: 0 = BUSY, 1 = ALERT. + Second cell indicates which GPn pin is used: 0, 2 or 3. + + For convenience, macros for these values are available in + dt-bindings/iio/adc/adi,ad4695.h. + const: 2 + "#address-cells": const: 1 diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4851.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad4851.yaml new file mode 100644 index 000000000000..c6676d91b4e6 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4851.yaml @@ -0,0 +1,153 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright 2024 Analog Devices Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/adi,ad4851.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices AD485X family + +maintainers: + - Sergiu Cuciurean <sergiu.cuciurean@analog.com> + - Dragos Bogdan <dragos.bogdan@analog.com> + - Antoniu Miclaus <antoniu.miclaus@analog.com> + +description: | + Analog Devices AD485X fully buffered, 8-channel simultaneous sampling, + 16/20-bit, 1 MSPS data acquisition system (DAS) with differential, wide + common-mode range inputs. + + https://www.analog.com/media/en/technical-documentation/data-sheets/ad4855.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/ad4856.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/ad4857.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/ad4858.pdf + +$ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + enum: + - adi,ad4851 + - adi,ad4852 + - adi,ad4853 + - adi,ad4854 + - adi,ad4855 + - adi,ad4856 + - adi,ad4857 + - adi,ad4858 + - adi,ad4858i + + reg: + maxItems: 1 + + vcc-supply: true + + vee-supply: true + + vdd-supply: true + + vddh-supply: true + + vddl-supply: true + + vio-supply: true + + vrefbuf-supply: true + + vrefio-supply: true + + pwms: + description: PWM connected to the CNV pin. + maxItems: 1 + + io-backends: + maxItems: 1 + + pd-gpios: + maxItems: 1 + + spi-max-frequency: + maximum: 25000000 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + +patternProperties: + "^channel(@[0-7])?$": + $ref: adc.yaml + type: object + description: Represents the channels which are connected to the ADC. + + properties: + reg: + description: + The channel number, as specified in the datasheet (from 0 to 7). + minimum: 0 + maximum: 7 + + diff-channels: + description: + Each channel can be configured as a bipolar differential channel. + The ADC uses the same positive and negative inputs for this. + This property must be specified as 'reg' (or the channel number) for + both positive and negative inputs (i.e. diff-channels = <reg reg>). + Since the configuration is bipolar differential, the 'bipolar' + property is required. + items: + minimum: 0 + maximum: 7 + + bipolar: true + + required: + - reg + + additionalProperties: false + +required: + - compatible + - reg + - vcc-supply + - vee-supply + - vdd-supply + - vio-supply + - pwms + +unevaluatedProperties: false + +examples: + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + + adc@0{ + #address-cells = <1>; + #size-cells = <0>; + compatible = "adi,ad4858"; + reg = <0>; + spi-max-frequency = <10000000>; + vcc-supply = <&vcc>; + vdd-supply = <&vdd>; + vee-supply = <&vee>; + vddh-supply = <&vddh>; + vddl-supply = <&vddl>; + vio-supply = <&vio>; + pwms = <&pwm_gen 0 0>; + io-backends = <&iio_backend>; + + channel@0 { + reg = <0>; + diff-channels = <0 0>; + bipolar; + }; + + channel@1 { + reg = <1>; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7191.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7191.yaml new file mode 100644 index 000000000000..801ed319ee82 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7191.yaml @@ -0,0 +1,149 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2025 Analog Devices Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/adi,ad7191.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices AD7191 ADC + +maintainers: + - Alisa-Dariana Roman <alisa.roman@analog.com> + +description: | + Bindings for the Analog Devices AD7191 ADC device. Datasheet can be + found here: + https://www.analog.com/media/en/technical-documentation/data-sheets/AD7191.pdf + The device's PDOWN pin must be connected to the SPI controller's chip select + pin. + +properties: + compatible: + enum: + - adi,ad7191 + + reg: + maxItems: 1 + + spi-cpol: true + + spi-cpha: true + + clocks: + maxItems: 1 + description: + Must be present when CLKSEL pin is tied HIGH to select external clock + source (either a crystal between MCLK1 and MCLK2 pins, or a + CMOS-compatible clock driving MCLK2 pin). Must be absent when CLKSEL pin + is tied LOW to use the internal 4.92MHz clock. + + interrupts: + maxItems: 1 + + avdd-supply: + description: AVdd voltage supply + + dvdd-supply: + description: DVdd voltage supply + + vref-supply: + description: Vref voltage supply + + odr-gpios: + description: + ODR1 and ODR2 pins for output data rate selection. Should be defined if + adi,odr-value is absent. + minItems: 2 + maxItems: 2 + + adi,odr-value: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Should be present if ODR pins are pin-strapped. Possible values: + 120 Hz (ODR1=0, ODR2=0) + 60 Hz (ODR1=0, ODR2=1) + 50 Hz (ODR1=1, ODR2=0) + 10 Hz (ODR1=1, ODR2=1) + If defined, odr-gpios must be absent. + enum: [120, 60, 50, 10] + + pga-gpios: + description: + PGA1 and PGA2 pins for gain selection. Should be defined if adi,pga-value + is absent. + minItems: 2 + maxItems: 2 + + adi,pga-value: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Should be present if PGA pins are pin-strapped. Possible values: + Gain 1 (PGA1=0, PGA2=0) + Gain 8 (PGA1=0, PGA2=1) + Gain 64 (PGA1=1, PGA2=0) + Gain 128 (PGA1=1, PGA2=1) + If defined, pga-gpios must be absent. + enum: [1, 8, 64, 128] + + temp-gpios: + description: TEMP pin for temperature sensor enable. + maxItems: 1 + + chan-gpios: + description: CHAN pin for input channel selection. + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - avdd-supply + - dvdd-supply + - vref-supply + - spi-cpol + - spi-cpha + - temp-gpios + - chan-gpios + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + - oneOf: + - required: + - adi,odr-value + - required: + - odr-gpios + - oneOf: + - required: + - adi,pga-value + - required: + - pga-gpios + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interrupt-controller/irq.h> + + spi { + #address-cells = <1>; + #size-cells = <0>; + + adc@0 { + compatible = "adi,ad7191"; + reg = <0>; + spi-max-frequency = <1000000>; + spi-cpol; + spi-cpha; + clocks = <&ad7191_mclk>; + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&gpio>; + avdd-supply = <&avdd>; + dvdd-supply = <&dvdd>; + vref-supply = <&vref>; + adi,pga-value = <1>; + odr-gpios = <&gpio 23 GPIO_ACTIVE_HIGH>, <&gpio 24 GPIO_ACTIVE_HIGH>; + temp-gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; + chan-gpios = <&gpio 27 GPIO_ACTIVE_HIGH>; + }; + }; diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7380.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7380.yaml index ada08005b3cd..8dae89ecb64d 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7380.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7380.yaml @@ -25,8 +25,10 @@ description: | * https://www.analog.com/en/products/ad7386-4.html * https://www.analog.com/en/products/ad7387-4.html * https://www.analog.com/en/products/ad7388-4.html + * https://www.analog.com/en/products/ad7389-4.html * https://www.analog.com/en/products/adaq4370-4.html * https://www.analog.com/en/products/adaq4380-4.html + * https://www.analog.com/en/products/adaq4381-4.html $ref: /schemas/spi/spi-peripheral-props.yaml# @@ -48,8 +50,10 @@ properties: - adi,ad7386-4 - adi,ad7387-4 - adi,ad7388-4 + - adi,ad7389-4 - adi,adaq4370-4 - adi,adaq4380-4 + - adi,adaq4381-4 reg: maxItems: 1 @@ -201,6 +205,7 @@ allOf: - adi,ad7380-4 - adi,adaq4370-4 - adi,adaq4380-4 + - adi,adaq4381-4 then: properties: refio-supply: false @@ -210,6 +215,15 @@ allOf: properties: refin-supply: false + # adi,ad7389-4 is internal reference only + - if: + properties: + compatible: + const: adi,ad7389-4 + then: + properties: + refio-supply: false + # adaq devices need more supplies and using channel to declare gain property # only applies to adaq devices - if: @@ -218,6 +232,7 @@ allOf: enum: - adi,adaq4370-4 - adi,adaq4380-4 + - adi,adaq4381-4 then: required: - vs-p-supply diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7476.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7476.yaml index 44c671eeda73..d0cb32f136e5 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7476.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7476.yaml @@ -17,35 +17,40 @@ description: | properties: compatible: - enum: - - adi,ad7091 - - adi,ad7091r - - adi,ad7273 - - adi,ad7274 - - adi,ad7276 - - adi,ad7277 - - adi,ad7278 - - adi,ad7466 - - adi,ad7467 - - adi,ad7468 - - adi,ad7475 - - adi,ad7476 - - adi,ad7476a - - adi,ad7477 - - adi,ad7477a - - adi,ad7478 - - adi,ad7478a - - adi,ad7495 - - adi,ad7910 - - adi,ad7920 - - adi,ad7940 - - ti,adc081s - - ti,adc101s - - ti,adc121s - - ti,ads7866 - - ti,ads7867 - - ti,ads7868 - - lltc,ltc2314-14 + oneOf: + - items: + - enum: + - adi,ad7091 + - adi,ad7091r + - adi,ad7273 + - adi,ad7274 + - adi,ad7276 + - adi,ad7277 + - adi,ad7278 + - adi,ad7466 + - adi,ad7467 + - adi,ad7468 + - adi,ad7475 + - adi,ad7476 + - adi,ad7476a + - adi,ad7477 + - adi,ad7477a + - adi,ad7478 + - adi,ad7478a + - adi,ad7495 + - adi,ad7910 + - adi,ad7920 + - adi,ad7940 + - ti,adc081s + - ti,adc101s + - ti,adc121s + - ti,ads7866 + - ti,ads7867 + - ti,ads7868 + - lltc,ltc2314-14 + - items: + - const: rohm,bu79100g + - const: ti,ads7866 reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml index 52d3f1ce3367..1a5209139e13 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml @@ -45,6 +45,14 @@ properties: "#size-cells": const: 0 + '#trigger-source-cells': + description: | + Cell indicates the output signal: 0 = BUSY, 1 = FIRSTDATA. + + For convenience, macros for these values are available in + dt-bindings/iio/adc/adi,ad7606.h. + const: 1 + # According to the datasheet, "Data is clocked in from SDI on the falling # edge of SCLK, while data is clocked out on DOUTA on the rising edge of # SCLK". Also, even if not stated textually in the datasheet, it is made @@ -215,12 +223,6 @@ allOf: - required: - pwms - - oneOf: - - required: - - interrupts - - required: - - io-backends - - if: properties: compatible: diff --git a/Documentation/devicetree/bindings/iio/adc/adi,axi-adc.yaml b/Documentation/devicetree/bindings/iio/adc/adi,axi-adc.yaml index e1f450b80db2..cf74f84d6103 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,axi-adc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,axi-adc.yaml @@ -17,13 +17,25 @@ description: | interface for the actual ADC, while this IP core will interface to the data-lines of the ADC and handle the streaming of data into memory via DMA. + In some cases, the AXI ADC interface is used to perform specialized + operation to a particular ADC, e.g access the physical bus through + specific registers to write ADC registers. + In this case, we use a different compatible which indicates the target + IP core's name. + The following IP is currently supported: + - AXI AD7606x: specialized version of the IP core for all the chips from + the ad7606 family. https://wiki.analog.com/resources/fpga/docs/axi_adc_ip + https://analogdevicesinc.github.io/hdl/library/axi_ad485x/index.html + http://analogdevicesinc.github.io/hdl/library/axi_ad7606x/index.html properties: compatible: enum: - adi,axi-adc-10.0.a + - adi,axi-ad7606x + - adi,axi-ad485x reg: maxItems: 1 @@ -47,17 +59,48 @@ properties: '#io-backend-cells': const: 0 + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + +patternProperties: + "^adc@[0-9a-f]+$": + type: object + properties: + reg: + maxItems: 1 + additionalProperties: true + required: + - compatible + - reg + required: - compatible - dmas - reg - clocks +allOf: + - if: + properties: + compatible: + not: + contains: + const: adi,axi-ad7606x + then: + properties: + '#address-cells': false + '#size-cells': false + patternProperties: + "^adc@[0-9a-f]+$": false + additionalProperties: false examples: - | - axi-adc@44a00000 { + adc@44a00000 { compatible = "adi,axi-adc-10.0.a"; reg = <0x44a00000 0x10000>; dmas = <&rx_dma 0>; @@ -65,4 +108,31 @@ examples: clocks = <&axi_clk>; #io-backend-cells = <0>; }; + - | + #include <dt-bindings/gpio/gpio.h> + parallel_bus_controller@44a00000 { + compatible = "adi,axi-ad7606x"; + reg = <0x44a00000 0x10000>; + dmas = <&rx_dma 0>; + dma-names = "rx"; + clocks = <&ext_clk>; + #address-cells = <1>; + #size-cells = <0>; + + adc@0 { + compatible = "adi,ad7606b"; + reg = <0>; + pwms = <&axi_pwm_gen 0 0>; + pwm-names = "convst1"; + avcc-supply = <&adc_vref>; + vdrive-supply = <&vdd_supply>; + reset-gpios = <&gpio0 91 GPIO_ACTIVE_HIGH>; + standby-gpios = <&gpio0 90 GPIO_ACTIVE_LOW>; + adi,range-gpios = <&gpio0 89 GPIO_ACTIVE_HIGH>; + adi,oversampling-ratio-gpios = <&gpio0 88 GPIO_ACTIVE_HIGH + &gpio0 87 GPIO_ACTIVE_HIGH + &gpio0 86 GPIO_ACTIVE_HIGH>; + io-backends = <¶llel_bus_controller>; + }; + }; ... diff --git a/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.yaml b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.yaml index b0962a4583ac..bb9825e7346d 100644 --- a/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.yaml @@ -23,6 +23,7 @@ properties: - amlogic,meson8m2-saradc - amlogic,meson-gxbb-saradc - amlogic,meson-gxl-saradc + - amlogic,meson-gxlx-saradc - amlogic,meson-gxm-saradc - amlogic,meson-axg-saradc - amlogic,meson-g12a-saradc diff --git a/Documentation/devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml b/Documentation/devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml index 6168b44ea72c..b489c984c1bb 100644 --- a/Documentation/devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml @@ -34,6 +34,7 @@ properties: - const: mediatek,mt2701-auxadc - items: - enum: + - mediatek,mt6893-auxadc - mediatek,mt8183-auxadc - mediatek,mt8186-auxadc - mediatek,mt8188-auxadc diff --git a/Documentation/devicetree/bindings/iio/adc/microchip,mcp3911.yaml b/Documentation/devicetree/bindings/iio/adc/microchip,mcp3911.yaml index 06951ec5f5da..3a69ec60edb9 100644 --- a/Documentation/devicetree/bindings/iio/adc/microchip,mcp3911.yaml +++ b/Documentation/devicetree/bindings/iio/adc/microchip,mcp3911.yaml @@ -32,6 +32,9 @@ properties: spi-max-frequency: maximum: 20000000 + reset-gpios: + maxItems: 1 + clocks: description: | Phandle and clock identifier for external sampling clock. @@ -71,6 +74,7 @@ unevaluatedProperties: false examples: - | + #include <dt-bindings/gpio/gpio.h> spi { #address-cells = <1>; #size-cells = <0>; @@ -80,6 +84,7 @@ examples: reg = <0>; interrupt-parent = <&gpio5>; interrupts = <15 2>; + reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; spi-max-frequency = <20000000>; microchip,device-addr = <0>; vref-supply = <&vref_reg>; diff --git a/Documentation/devicetree/bindings/iio/adc/nuvoton,nct7201.yaml b/Documentation/devicetree/bindings/iio/adc/nuvoton,nct7201.yaml new file mode 100644 index 000000000000..8ce7d415d956 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/nuvoton,nct7201.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/nuvoton,nct7201.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton nct7201 and similar ADCs + +maintainers: + - Eason Yang <j2anfernee@gmail.com> + +description: | + The NCT7201/NCT7202 is a Nuvoton Hardware Monitor IC, contains up to 12 + voltage monitoring channels, with SMBus interface, and up to 4 sets SMBus + address selection by ADDR connection. It also provides ALERT# signal for + event notification and reset input RSTIN# to recover it from a fault + condition. + + NCT7201 contains 8 voltage monitor inputs (VIN1~VIN8). + NCT7202 contains 12 voltage monitor inputs (VIN1~VIN12). + +properties: + compatible: + enum: + - nuvoton,nct7201 + - nuvoton,nct7202 + + reg: + maxItems: 1 + + vdd-supply: + description: + A 3.3V to supply that powers the chip. + + vref-supply: + description: + The regulator supply for the ADC reference voltage. + + interrupts: + maxItems: 1 + + reset-gpios: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interrupt-controller/irq.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + adc@1d { + compatible = "nuvoton,nct7202"; + reg = <0x1d>; + vdd-supply = <&vdd>; + vref-supply = <&vref>; + interrupt-parent = <&gpio3>; + interrupts = <30 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio3 28 GPIO_ACTIVE_LOW>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/iio/adc/nxp,imx93-adc.yaml b/Documentation/devicetree/bindings/iio/adc/nxp,imx93-adc.yaml index dfc3f512918f..c2e5ff418920 100644 --- a/Documentation/devicetree/bindings/iio/adc/nxp,imx93-adc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/nxp,imx93-adc.yaml @@ -19,7 +19,14 @@ description: properties: compatible: - const: nxp,imx93-adc + oneOf: + - enum: + - nxp,imx93-adc + - items: + - enum: + - nxp,imx94-adc + - nxp,imx95-adc + - const: nxp,imx93-adc reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-rradc.yaml b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-rradc.yaml index f39bc92c2b99..862e450da214 100644 --- a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-rradc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-rradc.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm's SPMI PMIC Round Robin ADC maintainers: - - Caleb Connolly <caleb.connolly@linaro.org> + - Casey Connolly <casey.connolly@linaro.org> description: | The Qualcomm SPMI Round Robin ADC (RRADC) provides interface to clients to diff --git a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.yaml b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.yaml index fd93ed3991e0..41e0c56ef8e3 100644 --- a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.yaml @@ -15,6 +15,8 @@ properties: - const: rockchip,saradc - const: rockchip,rk3066-tsadc - const: rockchip,rk3399-saradc + - const: rockchip,rk3528-saradc + - const: rockchip,rk3562-saradc - const: rockchip,rk3588-saradc - items: - const: rockchip,rk3576-saradc diff --git a/Documentation/devicetree/bindings/iio/adc/rohm,bd79104.yaml b/Documentation/devicetree/bindings/iio/adc/rohm,bd79104.yaml new file mode 100644 index 000000000000..2a8ad4fdfc6b --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/rohm,bd79104.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/rohm,bd79104.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ROHM Semiconductor BD79104 ADC + +maintainers: + - Matti Vaittinen <mazziesaccount@gmail.com> + +description: | + 12 bit SPI ADC with 8 channels. + +properties: + compatible: + const: rohm,bd79104 + + reg: + maxItems: 1 + + vdd-supply: true + iovdd-supply: true + +# The component data-sheet says the frequency is 20M. I, however, found +# that the ROHM evaluation board BD79104FV-EVK-001 had problems with 20M. +# I have successfully used it with 4M. My _assumption_ is that this is not +# the limitation of the component itself, but a limitation of the EVK. + spi-max-frequency: + maximum: 20000000 + + "#io-channel-cells": + const: 1 + + spi-cpha: true + spi-cpol: true + +required: + - compatible + - reg + - vdd-supply + - iovdd-supply + - spi-cpha + - spi-cpol + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + spi { + #address-cells = <1>; + #size-cells = <0>; + + adc@0 { + compatible = "rohm,bd79104"; + reg = <0>; + vdd-supply = <&vdd_supply>; + iovdd-supply = <&iovdd_supply>; + spi-max-frequency = <4000000>; + spi-cpha; + spi-cpol; + #io-channel-cells = <1>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/iio/adc/rohm,bd79124.yaml b/Documentation/devicetree/bindings/iio/adc/rohm,bd79124.yaml new file mode 100644 index 000000000000..503285823376 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/rohm,bd79124.yaml @@ -0,0 +1,114 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/rohm,bd79124.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ROHM BD79124 ADC/GPO + +maintainers: + - Matti Vaittinen <mazziesaccount@gmail.com> + +description: | + The ROHM BD79124 is a 12-bit, 8-channel, SAR ADC. The ADC supports + an automatic measurement mode, with an alarm interrupt for out-of-window + measurements. ADC input pins can be also configured as general purpose + outputs. + +properties: + compatible: + const: rohm,bd79124 + + reg: + description: + I2C slave address. + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-controller: true + + "#gpio-cells": + const: 1 + description: + The pin number. + + vdd-supply: true + + iovdd-supply: true + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +patternProperties: + "^channel@[0-7]+$": + type: object + $ref: /schemas/iio/adc/adc.yaml# + description: Represents ADC channel. + + properties: + reg: + description: AIN pin number + minimum: 0 + maximum: 7 + + required: + - reg + + additionalProperties: false + +required: + - compatible + - reg + - iovdd-supply + - vdd-supply + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/leds/common.h> + i2c { + #address-cells = <1>; + #size-cells = <0>; + adc: adc@10 { + compatible = "rohm,bd79124"; + reg = <0x10>; + + interrupt-parent = <&gpio1>; + interrupts = <29 8>; + + vdd-supply = <&dummyreg>; + iovdd-supply = <&dummyreg>; + + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + reg = <0>; + }; + channel@1 { + reg = <1>; + }; + channel@2 { + reg = <2>; + }; + channel@3 { + reg = <3>; + }; + channel@4 { + reg = <4>; + }; + channel@5 { + reg = <5>; + }; + channel@6 { + reg = <6>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml b/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml index ef9dcc365eab..17bb60e18a1c 100644 --- a/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml @@ -498,7 +498,7 @@ patternProperties: examples: - | // Example 1: with stm32f429, ADC1, single-ended channel 8 - adc123: adc@40012000 { + adc123: adc@40012000 { compatible = "st,stm32f4-adc-core"; reg = <0x40012000 0x400>; interrupts = <18>; @@ -512,28 +512,28 @@ examples: #address-cells = <1>; #size-cells = <0>; adc@0 { - compatible = "st,stm32f4-adc"; - #io-channel-cells = <1>; - reg = <0x0>; - clocks = <&rcc 0 168>; - interrupt-parent = <&adc123>; - interrupts = <0>; - st,adc-channels = <8>; - dmas = <&dma2 0 0 0x400 0x0>; - dma-names = "rx"; - assigned-resolution-bits = <8>; + compatible = "st,stm32f4-adc"; + #io-channel-cells = <1>; + reg = <0x0>; + clocks = <&rcc 0 168>; + interrupt-parent = <&adc123>; + interrupts = <0>; + st,adc-channels = <8>; + dmas = <&dma2 0 0 0x400 0x0>; + dma-names = "rx"; + assigned-resolution-bits = <8>; }; // ... // other adc child nodes follow... - }; + }; - | // Example 2: with stm32mp157c to setup ADC1 with: // - channels 0 & 1 as single-ended // - channels 2 & 3 as differential (with resp. 6 & 7 negative inputs) - #include <dt-bindings/interrupt-controller/arm-gic.h> - #include <dt-bindings/clock/stm32mp1-clks.h> - adc12: adc@48003000 { + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/stm32mp1-clks.h> + adc12: adc@48003000 { compatible = "st,stm32mp1-adc-core"; reg = <0x48003000 0x400>; interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, @@ -550,27 +550,27 @@ examples: #address-cells = <1>; #size-cells = <0>; adc@0 { - compatible = "st,stm32mp1-adc"; - #io-channel-cells = <1>; - reg = <0x0>; - interrupt-parent = <&adc12>; - interrupts = <0>; - st,adc-channels = <0 1>; - st,adc-diff-channels = <2 6>, <3 7>; - st,min-sample-time-nsecs = <5000>; - dmas = <&dmamux1 9 0x400 0x05>; - dma-names = "rx"; + compatible = "st,stm32mp1-adc"; + #io-channel-cells = <1>; + reg = <0x0>; + interrupt-parent = <&adc12>; + interrupts = <0>; + st,adc-channels = <0 1>; + st,adc-diff-channels = <2 6>, <3 7>; + st,min-sample-time-nsecs = <5000>; + dmas = <&dmamux1 9 0x400 0x05>; + dma-names = "rx"; }; // ... // other adc child node follow... - }; + }; - | // Example 3: with stm32mp157c to setup ADC2 with: // - internal channels 13, 14, 15. - #include <dt-bindings/interrupt-controller/arm-gic.h> - #include <dt-bindings/clock/stm32mp1-clks.h> - adc122: adc@48003000 { + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/stm32mp1-clks.h> + adc122: adc@48003000 { compatible = "st,stm32mp1-adc-core"; reg = <0x48003000 0x400>; interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, @@ -587,28 +587,28 @@ examples: #address-cells = <1>; #size-cells = <0>; adc@100 { - compatible = "st,stm32mp1-adc"; - #io-channel-cells = <1>; - reg = <0x100>; - interrupts = <1>; - #address-cells = <1>; - #size-cells = <0>; - channel@13 { - reg = <13>; - label = "vrefint"; - st,min-sample-time-ns = <9000>; - }; - channel@14 { - reg = <14>; - label = "vddcore"; - st,min-sample-time-ns = <9000>; - }; - channel@15 { - reg = <15>; - label = "vbat"; - st,min-sample-time-ns = <9000>; - }; + compatible = "st,stm32mp1-adc"; + #io-channel-cells = <1>; + reg = <0x100>; + interrupts = <1>; + #address-cells = <1>; + #size-cells = <0>; + channel@13 { + reg = <13>; + label = "vrefint"; + st,min-sample-time-ns = <9000>; + }; + channel@14 { + reg = <14>; + label = "vddcore"; + st,min-sample-time-ns = <9000>; + }; + channel@15 { + reg = <15>; + label = "vbat"; + st,min-sample-time-ns = <9000>; + }; }; - }; + }; ... diff --git a/Documentation/devicetree/bindings/iio/adc/ti,ads7138.yaml b/Documentation/devicetree/bindings/iio/adc/ti,ads7138.yaml new file mode 100644 index 000000000000..a51893e207d4 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/ti,ads7138.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/ti,ads7138.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments ADS7128/ADS7138 analog-to-digital converter (ADC) + +maintainers: + - Tobias Sperling <tobias.sperling@softing.com> + +description: | + The ADS7128 and ADS7138 chips are 12-bit, 8 channel analog-to-digital + converters (ADC) with build-in digital window comparator (DWC), using the + I2C interface. + ADS7128 differs in the addition of further hardware features, like a + root-mean-square (RMS) and a zero-crossing-detect (ZCD) module. + + Datasheets: + https://www.ti.com/product/ADS7128 + https://www.ti.com/product/ADS7138 + +properties: + compatible: + enum: + - ti,ads7128 + - ti,ads7138 + + reg: + maxItems: 1 + + avdd-supply: + description: + The regulator used as analog supply voltage as well as reference voltage. + + interrupts: + description: + Interrupt on ALERT pin, triggers on low level. + maxItems: 1 + +required: + - compatible + - reg + - avdd-supply + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + i2c { + #address-cells = <1>; + #size-cells = <0>; + + adc@10 { + compatible = "ti,ads7138"; + reg = <0x10>; + avdd-supply = <®_stb_3v3>; + interrupt-parent = <&gpio2>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/iio/adc/xlnx,zynqmp-ams.yaml b/Documentation/devicetree/bindings/iio/adc/xlnx,zynqmp-ams.yaml index 8cbad7e792b6..a403392fb263 100644 --- a/Documentation/devicetree/bindings/iio/adc/xlnx,zynqmp-ams.yaml +++ b/Documentation/devicetree/bindings/iio/adc/xlnx,zynqmp-ams.yaml @@ -193,7 +193,6 @@ additionalProperties: false examples: - | - #include <dt-bindings/clock/xlnx-zynqmp-clk.h> bus { #address-cells = <2>; @@ -204,7 +203,7 @@ examples: interrupt-parent = <&gic>; interrupts = <0 56 4>; reg = <0x0 0xffa50000 0x0 0x800>; - clocks = <&zynqmp_clk AMS_REF>; + clocks = <&zynqmp_clk 70>; #address-cells = <1>; #size-cells = <1>; #io-channel-cells = <1>; diff --git a/Documentation/devicetree/bindings/iio/chemical/winsen,mhz19b.yaml b/Documentation/devicetree/bindings/iio/chemical/winsen,mhz19b.yaml new file mode 100644 index 000000000000..2a6ddb33f163 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/chemical/winsen,mhz19b.yaml @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/chemical/winsen,mhz19b.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MHZ19B CO2 sensor + +maintainers: + - Gyeyoung Baek <gye976@gmail.com> + +properties: + compatible: + const: winsen,mhz19b + + vin-supply: + description: Regulator that provides power to the sensor + +required: + - compatible + - vin-supply + +additionalProperties: false + +examples: + - | + serial { + co2-sensor { + compatible = "winsen,mhz19b"; + vin-supply = <&vdd>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/iio/dac/adi,ad3530r.yaml b/Documentation/devicetree/bindings/iio/dac/adi,ad3530r.yaml new file mode 100644 index 000000000000..a355d52a9d64 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/dac/adi,ad3530r.yaml @@ -0,0 +1,100 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/dac/adi,ad3530r.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices AD3530R and Similar DACs + +maintainers: + - Kim Seer Paller <kimseer.paller@analog.com> + +description: | + The AD3530/AD3530R (8-channel) and AD3531/AD3531R (4-channel) are low-power, + 16-bit, buffered voltage output digital-to-analog converters (DACs) with + software-programmable gain controls, providing full-scale output spans of 2.5V + or 5V for reference voltages of 2.5V. These devices operate from a single 2.7V + to 5.5V supply and are guaranteed monotonic by design. The "R" variants + include a 2.5V, 5ppm/°C internal reference, which is disabled by default. + Datasheet can be found here: + https://www.analog.com/media/en/technical-documentation/data-sheets/ad3530_ad530r.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/ad3531-ad3531r.pdf + +properties: + compatible: + enum: + - adi,ad3530 + - adi,ad3530r + - adi,ad3531 + - adi,ad3531r + + reg: + maxItems: 1 + + spi-max-frequency: + maximum: 50000000 + + vdd-supply: + description: Power Supply Input. + + iovdd-supply: + description: Digital Power Supply Input. + + io-channels: + description: + ADC channel used to monitor internal die temperature, output voltages, and + current of a selected channel via the MUXOUT pin. + maxItems: 1 + + ref-supply: + description: + Reference Input/Output. The voltage at the REF pin sets the full-scale + range of all channels. If not provided the internal reference is used and + also provided on the VREF pin. + + reset-gpios: + description: + Active low signal that is falling edge sensitive. When it is deasserted, + the digital core initialization is performed and all DAC registers except + the Interface Configuration A register are reset to their default values. + maxItems: 1 + + ldac-gpios: + description: + LDAC pin to be used as a hardware trigger to update the DAC channels. If + not present, the DAC channels are updated by Software LDAC. + maxItems: 1 + + adi,range-double: + description: + Configure the output range for all channels. If the property is present, + the output will range from 0V to 2Vref. If the property is not present, + the output will range from 0V to Vref. + type: boolean + +required: + - compatible + - reg + - vdd-supply + - iovdd-supply + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false + +examples: + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + dac@0 { + compatible = "adi,ad3530r"; + reg = <0>; + spi-max-frequency = <1000000>; + + vdd-supply = <&vdd>; + iovdd-supply = <&iovdd>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml b/Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml index 2d2561a52683..547044b8e246 100644 --- a/Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml +++ b/Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml @@ -217,7 +217,7 @@ required: - reg - spi-max-frequency -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/iio/dac/adi,ad5380.yaml b/Documentation/devicetree/bindings/iio/dac/adi,ad5380.yaml index 9eb9928500e2..3e323f1a5458 100644 --- a/Documentation/devicetree/bindings/iio/dac/adi,ad5380.yaml +++ b/Documentation/devicetree/bindings/iio/dac/adi,ad5380.yaml @@ -55,18 +55,18 @@ examples: #address-cells = <1>; #size-cells = <0>; dac@0 { - reg = <0>; - compatible = "adi,ad5390-5"; - vref-supply = <&dacvref>; + reg = <0>; + compatible = "adi,ad5390-5"; + vref-supply = <&dacvref>; }; }; - | i2c { - #address-cells = <1>; - #size-cells = <0>; - dac@42 { - reg = <0x42>; - compatible = "adi,ad5380-3"; - }; + #address-cells = <1>; + #size-cells = <0>; + dac@42 { + reg = <0x42>; + compatible = "adi,ad5380-3"; + }; }; ... diff --git a/Documentation/devicetree/bindings/iio/dac/adi,ad7293.yaml b/Documentation/devicetree/bindings/iio/dac/adi,ad7293.yaml index 5ee80bf6aa11..f994c1ef6d41 100644 --- a/Documentation/devicetree/bindings/iio/dac/adi,ad7293.yaml +++ b/Documentation/devicetree/bindings/iio/dac/adi,ad7293.yaml @@ -27,6 +27,8 @@ properties: vdrive-supply: true + vrefin-supply: true + reset-gpios: maxItems: 1 diff --git a/Documentation/devicetree/bindings/iio/dac/adi,ltc2664.yaml b/Documentation/devicetree/bindings/iio/dac/adi,ltc2664.yaml index 33490853497b..1aece3392b77 100644 --- a/Documentation/devicetree/bindings/iio/dac/adi,ltc2664.yaml +++ b/Documentation/devicetree/bindings/iio/dac/adi,ltc2664.yaml @@ -144,7 +144,7 @@ required: allOf: - $ref: /schemas/spi/spi-peripheral-props.yaml# -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/iio/dac/adi,ltc2672.yaml b/Documentation/devicetree/bindings/iio/dac/adi,ltc2672.yaml index c8c434c10643..3c8e5781e42c 100644 --- a/Documentation/devicetree/bindings/iio/dac/adi,ltc2672.yaml +++ b/Documentation/devicetree/bindings/iio/dac/adi,ltc2672.yaml @@ -124,7 +124,7 @@ required: allOf: - $ref: /schemas/spi/spi-peripheral-props.yaml# -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/iio/dac/microchip,mcp4821.yaml b/Documentation/devicetree/bindings/iio/dac/microchip,mcp4821.yaml index 0dc577c33918..26011b5639d8 100644 --- a/Documentation/devicetree/bindings/iio/dac/microchip,mcp4821.yaml +++ b/Documentation/devicetree/bindings/iio/dac/microchip,mcp4821.yaml @@ -64,7 +64,7 @@ required: - reg - vdd-supply -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/iio/dac/rohm,bd79703.yaml b/Documentation/devicetree/bindings/iio/dac/rohm,bd79703.yaml index 941a49c93943..c00fa50e42e8 100644 --- a/Documentation/devicetree/bindings/iio/dac/rohm,bd79703.yaml +++ b/Documentation/devicetree/bindings/iio/dac/rohm,bd79703.yaml @@ -5,19 +5,26 @@ $id: http://devicetree.org/schemas/iio/dac/rohm,bd79703.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: ROHM BD79703 DAC device driver +title: ROHM BD79700, BD79701, BD79702 and BD79703 DACs maintainers: - Matti Vaittinen <mazziesaccount@gmail.com> description: | - The ROHM BD79703 is a 6 channel, 8-bit DAC. - Datasheet can be found here: + The ROHM BD7970[0,1,2,3] are 8-bit DACs. The BD79700 has 2 channels, + BD79701 3 channels, BD79702 4 channels and BD79703 has 6 channels. + Datasheets for BD79702 and BD79703 can be found from https://fscdn.rohm.com/en/products/databook/datasheet/ic/data_converter/dac/bd79702fv-lb_bd79703fv-lb-e.pdf + and for the BD79700 and the BD79701 from + https://fscdn.rohm.com/en/products/databook/datasheet/ic/data_converter/dac/bd79700fvm-lb_bd79701fvm-lb-e.pdf properties: compatible: - const: rohm,bd79703 + enum: + - rohm,bd79700 + - rohm,bd79701 + - rohm,bd79702 + - rohm,bd79703 reg: maxItems: 1 @@ -27,23 +34,35 @@ properties: vfs-supply: description: - The regulator to use as a full scale voltage. The voltage should be between 2.7V .. VCC + The regulator to use as a full scale voltage. The voltage should be + between 2.7V .. VCC. Not present on BD79700 and BD79701. vcc-supply: description: - The regulator supplying the operating voltage. Should be between 2.7V ... 5.5V + The regulator supplying the operating voltage. Should be between + 2.7V ... 5.5V. Is used also as a Vfs on BD79700 and BD79701. required: - compatible - reg - spi-max-frequency - - vfs-supply - vcc-supply +if: + properties: + compatible: + contains: + enum: + - rohm,bd79702 + - rohm,bd79703 +then: + required: + - vfs-supply + allOf: - $ref: /schemas/spi/spi-peripheral-props.yaml# -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/iio/filter/adi,admv8818.yaml b/Documentation/devicetree/bindings/iio/filter/adi,admv8818.yaml index b77e855bd594..ff0cb553e871 100644 --- a/Documentation/devicetree/bindings/iio/filter/adi,admv8818.yaml +++ b/Documentation/devicetree/bindings/iio/filter/adi,admv8818.yaml @@ -44,6 +44,24 @@ properties: '#clock-cells': const: 0 + adi,lpf-margin-mhz: + description: + Sets the minimum distance between the fundamental frequency of `rf_in` + and the corner frequency of the low-pass, output filter when operated in + 'auto' mode. The selected low-pass corner frequency will be greater than, + or equal to, `rf_in` + `lpf-margin-hz`. If not setting is found that + satisfies this relationship the filter will be put into 'bypass'. + default: 0 + + adi,hpf-margin-mhz: + description: + Sets the minimum distance between the fundamental frequency of `rf_in` + and the corner frequency of the high-pass, input filter when operated in + 'auto' mode. The selected high-pass corner frequency will be less than, + or equal to, `rf_in` - `hpf-margin-hz`. If not setting is found that + satisfies this relationship the filter will be put into 'bypass'. + default: 0 + required: - compatible - reg @@ -61,6 +79,8 @@ examples: spi-max-frequency = <10000000>; clocks = <&admv8818_rfin>; clock-names = "rf_in"; + adi,lpf-margin-mhz = <300>; + adi,hpf-margin-mhz = <300>; }; }; ... diff --git a/Documentation/devicetree/bindings/iio/frequency/adf4371.yaml b/Documentation/devicetree/bindings/iio/frequency/adf4371.yaml index 1cb2adaf66f9..53d607441612 100644 --- a/Documentation/devicetree/bindings/iio/frequency/adf4371.yaml +++ b/Documentation/devicetree/bindings/iio/frequency/adf4371.yaml @@ -30,8 +30,9 @@ properties: clock-names: description: - Must be "clkin" - maxItems: 1 + Must be "clkin" if the input reference is single ended or "clkin-diff" + if the input reference is differential. + enum: [clkin, clkin-diff] adi,mute-till-lock-en: type: boolean diff --git a/Documentation/devicetree/bindings/iio/gyroscope/invensense,mpu3050.yaml b/Documentation/devicetree/bindings/iio/gyroscope/invensense,mpu3050.yaml index d1a6103fc37a..f3242dc0e7e6 100644 --- a/Documentation/devicetree/bindings/iio/gyroscope/invensense,mpu3050.yaml +++ b/Documentation/devicetree/bindings/iio/gyroscope/invensense,mpu3050.yaml @@ -21,7 +21,7 @@ properties: vlogic-supply: true interrupts: - minItems: 1 + maxItems: 1 description: Interrupt mapping for the trigger interrupt from the internal oscillator. diff --git a/Documentation/devicetree/bindings/iio/humidity/sciosense,ens210.yaml b/Documentation/devicetree/bindings/iio/humidity/sciosense,ens210.yaml index ed0ea938f7f8..1e25cf781cf1 100644 --- a/Documentation/devicetree/bindings/iio/humidity/sciosense,ens210.yaml +++ b/Documentation/devicetree/bindings/iio/humidity/sciosense,ens210.yaml @@ -43,13 +43,13 @@ additionalProperties: false examples: - | i2c { - #address-cells = <1>; - #size-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - temperature-sensor@43 { - compatible = "sciosense,ens210"; - reg = <0x43>; - }; + temperature-sensor@43 { + compatible = "sciosense,ens210"; + reg = <0x43>; + }; }; ... diff --git a/Documentation/devicetree/bindings/iio/imu/adi,adis16550.yaml b/Documentation/devicetree/bindings/iio/imu/adi,adis16550.yaml new file mode 100644 index 000000000000..cf5324de4fd6 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/imu/adi,adis16550.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/imu/adi,adis16550.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices ADIS16550 and similar IMUs + +maintainers: + - Nuno Sa <nuno.sa@analog.com> + - Ramona Gradinariu <ramona.gradinariu@analog.com> + - Antoniu Miclaus <antoniu.miclaus@analog.com> + - Robert Budai <robert.budai@analog.com> + +properties: + compatible: + enum: + - adi,adis16550 + + reg: + maxItems: 1 + + spi-cpha: true + + spi-cpol: true + + spi-max-frequency: + maximum: 15000000 + + vdd-supply: true + + interrupts: + maxItems: 1 + + reset-gpios: + description: + Active low RESET pin. + maxItems: 1 + + clocks: + description: If not provided, then the internal clock is used. + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - spi-cpha + - spi-cpol + - spi-max-frequency + - vdd-supply + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + spi { + #address-cells = <1>; + #size-cells = <0>; + imu@0 { + compatible = "adi,adis16550"; + reg = <0>; + spi-max-frequency = <15000000>; + spi-cpol; + spi-cpha; + vdd-supply = <&vdd>; + interrupts = <4 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&gpio>; + }; + }; diff --git a/Documentation/devicetree/bindings/iio/imu/invensense,icm42600.yaml b/Documentation/devicetree/bindings/iio/imu/invensense,icm42600.yaml index 7e4492bbd027..d4d4e5c3d856 100644 --- a/Documentation/devicetree/bindings/iio/imu/invensense,icm42600.yaml +++ b/Documentation/devicetree/bindings/iio/imu/invensense,icm42600.yaml @@ -39,7 +39,16 @@ properties: maxItems: 1 interrupts: - maxItems: 1 + minItems: 1 + maxItems: 2 + + interrupt-names: + minItems: 1 + maxItems: 2 + items: + enum: + - INT1 + - INT2 drive-open-drain: type: boolean @@ -76,6 +85,7 @@ examples: reg = <0x68>; interrupt-parent = <&gpio2>; interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "INT1"; vdd-supply = <&vdd>; vddio-supply = <&vddio>; }; @@ -95,6 +105,7 @@ examples: spi-cpol; interrupt-parent = <&gpio1>; interrupts = <2 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "INT1"; vdd-supply = <&vdd>; vddio-supply = <&vddio>; }; diff --git a/Documentation/devicetree/bindings/iio/light/bh1750.yaml b/Documentation/devicetree/bindings/iio/light/bh1750.yaml index 1a88b3c253d5..9df81c271411 100644 --- a/Documentation/devicetree/bindings/iio/light/bh1750.yaml +++ b/Documentation/devicetree/bindings/iio/light/bh1750.yaml @@ -24,6 +24,10 @@ properties: reg: maxItems: 1 + reset-gpios: + description: GPIO connected to the DVI reset pin (active low) + maxItems: 1 + required: - compatible - reg @@ -32,6 +36,7 @@ additionalProperties: false examples: - | + #include <dt-bindings/gpio/gpio.h> i2c { #address-cells = <1>; #size-cells = <0>; @@ -39,6 +44,7 @@ examples: light-sensor@23 { compatible = "rohm,bh1750"; reg = <0x23>; + reset-gpios = <&gpio2 17 GPIO_ACTIVE_LOW>; }; }; diff --git a/Documentation/devicetree/bindings/iio/light/brcm,apds9160.yaml b/Documentation/devicetree/bindings/iio/light/brcm,apds9160.yaml new file mode 100644 index 000000000000..bb1cc4404a55 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/light/brcm,apds9160.yaml @@ -0,0 +1,78 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/light/brcm,apds9160.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom Combined Proximity & Ambient light sensor + +maintainers: + - Mikael Gonella-Bolduc <m.gonella.bolduc@gmail.com> + +description: | + Datasheet: https://docs.broadcom.com/docs/APDS-9160-003-DS + +properties: + compatible: + enum: + - brcm,apds9160 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + vdd-supply: true + + ps-cancellation-duration: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Proximity sensor cancellation pulse duration in half clock cycles. + This parameter determines a cancellation pulse duration. + The cancellation is applied in the integration phase to cancel out + unwanted reflected light from very near objects such as tempered glass + in front of the sensor. + default: 0 + maximum: 63 + + ps-cancellation-current-picoamp: + description: + Proximity sensor crosstalk cancellation current in picoampere. + This parameter adjusts the current in steps of 2400 pA up to 276000 pA. + The provided value must be a multiple of 2400 and in one of these ranges + [60000 - 96000] + [120000 - 156000] + [180000 - 216000] + [240000 - 276000] + This parameter is used in conjunction with the cancellation duration. + minimum: 60000 + maximum: 276000 + multipleOf: 2400 + +required: + - compatible + - reg + - vdd-supply + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + light-sensor@53 { + compatible = "brcm,apds9160"; + reg = <0x53>; + vdd-supply = <&vdd_reg>; + interrupts = <29 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&pinctrl>; + ps-cancellation-duration = <10>; + ps-cancellation-current-picoamp = <62400>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/iio/light/dynaimage,al3010.yaml b/Documentation/devicetree/bindings/iio/light/dynaimage,al3010.yaml index a3a979553e32..f1048c30e73e 100644 --- a/Documentation/devicetree/bindings/iio/light/dynaimage,al3010.yaml +++ b/Documentation/devicetree/bindings/iio/light/dynaimage,al3010.yaml @@ -4,14 +4,16 @@ $id: http://devicetree.org/schemas/iio/light/dynaimage,al3010.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Dyna-Image AL3010 sensor +title: Dyna-Image AL3000a/AL3010 sensor maintainers: - David Heidelberg <david@ixit.cz> properties: compatible: - const: dynaimage,al3010 + enum: + - dynaimage,al3000a + - dynaimage,al3010 reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/iio/magnetometer/silabs,si7210.yaml b/Documentation/devicetree/bindings/iio/magnetometer/silabs,si7210.yaml new file mode 100644 index 000000000000..d4a3f7981c36 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/magnetometer/silabs,si7210.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/magnetometer/silabs,si7210.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Si7210 magnetic position and temperature sensor + +maintainers: + - Antoni Pokusinski <apokusinski01@gmail.com> + +description: | + Silabs Si7210 I2C Hall effect magnetic position and temperature sensor. + https://www.silabs.com/documents/public/data-sheets/si7210-datasheet.pdf + +properties: + compatible: + const: silabs,si7210 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + vdd-supply: + description: Regulator that provides power to the sensor + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + i2c { + #address-cells = <1>; + #size-cells = <0>; + magnetometer@30 { + compatible = "silabs,si7210"; + reg = <0x30>; + interrupt-parent = <&gpio1>; + interrupts = <4 IRQ_TYPE_EDGE_FALLING>; + vdd-supply = <&vdd_3v3_reg>; + }; + }; diff --git a/Documentation/devicetree/bindings/iio/pressure/honeywell,hsc030pa.yaml b/Documentation/devicetree/bindings/iio/pressure/honeywell,hsc030pa.yaml index 89977b9f01cf..412c7bcc310f 100644 --- a/Documentation/devicetree/bindings/iio/pressure/honeywell,hsc030pa.yaml +++ b/Documentation/devicetree/bindings/iio/pressure/honeywell,hsc030pa.yaml @@ -102,7 +102,7 @@ required: allOf: - $ref: /schemas/spi/spi-peripheral-props.yaml -additionalProperties: false +unevaluatedProperties: false dependentSchemas: honeywell,pmin-pascal: diff --git a/Documentation/devicetree/bindings/iio/pressure/honeywell,mprls0025pa.yaml b/Documentation/devicetree/bindings/iio/pressure/honeywell,mprls0025pa.yaml index 6994b30015bd..c756aa863103 100644 --- a/Documentation/devicetree/bindings/iio/pressure/honeywell,mprls0025pa.yaml +++ b/Documentation/devicetree/bindings/iio/pressure/honeywell,mprls0025pa.yaml @@ -115,7 +115,7 @@ allOf: honeywell,pmin-pascal: false honeywell,pmax-pascal: false -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/iio/temperature/maxim,max31865.yaml b/Documentation/devicetree/bindings/iio/temperature/maxim,max31865.yaml index 7cc365e0ebc8..7c0c6ab6fc69 100644 --- a/Documentation/devicetree/bindings/iio/temperature/maxim,max31865.yaml +++ b/Documentation/devicetree/bindings/iio/temperature/maxim,max31865.yaml @@ -40,15 +40,15 @@ unevaluatedProperties: false examples: - | spi { - #address-cells = <1>; - #size-cells = <0>; - - temperature-sensor@0 { - compatible = "maxim,max31865"; - reg = <0>; - spi-max-frequency = <400000>; - spi-cpha; - maxim,3-wire; - }; + #address-cells = <1>; + #size-cells = <0>; + + temperature-sensor@0 { + compatible = "maxim,max31865"; + reg = <0>; + spi-max-frequency = <400000>; + spi-cpha; + maxim,3-wire; + }; }; ... diff --git a/Documentation/devicetree/bindings/iio/temperature/ti,tmp117.yaml b/Documentation/devicetree/bindings/iio/temperature/ti,tmp117.yaml index 58aa1542776b..fbba5e934861 100644 --- a/Documentation/devicetree/bindings/iio/temperature/ti,tmp117.yaml +++ b/Documentation/devicetree/bindings/iio/temperature/ti,tmp117.yaml @@ -44,8 +44,8 @@ examples: #size-cells = <0>; tmp117@48 { - compatible = "ti,tmp117"; - reg = <0x48>; - vcc-supply = <&pmic_reg_3v3>; + compatible = "ti,tmp117"; + reg = <0x48>; + vcc-supply = <&pmic_reg_3v3>; }; }; diff --git a/Documentation/devicetree/bindings/input/dlg,da7280.txt b/Documentation/devicetree/bindings/input/dlg,da7280.txt deleted file mode 100644 index 96ee5d50e111..000000000000 --- a/Documentation/devicetree/bindings/input/dlg,da7280.txt +++ /dev/null @@ -1,108 +0,0 @@ -Dialog Semiconductor DA7280 Haptics bindings - -Required properties: -- compatible: Should be "dlg,da7280". -- reg: Specifies the I2C slave address. - -- interrupt-parent : Specifies the phandle of the interrupt controller to - which the IRQs from DA7280 are delivered to. - -- dlg,actuator-type: Set Actuator type. it should be one of: - "LRA" - Linear Resonance Actuator type. - "ERM-bar" - Bar type Eccentric Rotating Mass. - "ERM-coin" - Coin type Eccentric Rotating Mass. - -- dlg,const-op-mode: Haptic operation mode for FF_CONSTANT. - Possible values: - 1 - Direct register override(DRO) mode triggered by i2c(default), - 2 - PWM data source mode controlled by PWM duty, -- dlg,periodic-op-mode: Haptic operation mode for FF_PERIODIC. - Possible values: - 1 - Register triggered waveform memory(RTWM) mode, the pattern - assigned to the PS_SEQ_ID played as much times as PS_SEQ_LOOP, - 2 - Edge triggered waveform memory(ETWM) mode, external GPI(N) - control are required to enable/disable and it needs to keep - device enabled by sending magnitude (X > 0), - the pattern is assigned to the GPI(N)_SEQUENCE_ID below. - The default value is 1 for both of the operation modes. - For more details, please see the datasheet. - -- dlg,nom-microvolt: Nominal actuator voltage rating. - Valid values: 0 - 6000000. -- dlg,abs-max-microvolt: Absolute actuator maximum voltage rating. - Valid values: 0 - 6000000. -- dlg,imax-microamp: Actuator max current rating. - Valid values: 0 - 252000. - Default: 130000. -- dlg,impd-micro-ohms: the impedance of the actuator in micro ohms. - Valid values: 0 - 1500000000. - -Optional properties: -- pwms : phandle to the physical PWM(Pulse Width Modulation) device. - PWM properties should be named "pwms". And number of cell is different - for each pwm device. - (See Documentation/devicetree/bindings/pwm/pwm.txt - for further information relating to pwm properties) - -- dlg,ps-seq-id: the PS_SEQ_ID(pattern ID in waveform memory inside chip) - to play back when RTWM-MODE is enabled. - Valid range: 0 - 15. -- dlg,ps-seq-loop: the PS_SEQ_LOOP, Number of times the pre-stored sequence - pointed to by PS_SEQ_ID or GPI(N)_SEQUENCE_ID is repeated. - Valid range: 0 - 15. -- dlg,gpiN-seq-id: the GPI(N)_SEQUENCE_ID, pattern to play - when gpi0 is triggered, 'N' must be 0 - 2. - Valid range: 0 - 15. -- dlg,gpiN-mode: the pattern mode which can select either - "Single-pattern" or "Multi-pattern", 'N' must be 0 - 2. -- dlg,gpiN-polarity: gpiN polarity which can be chosen among - "Rising-edge", "Falling-edge" and "Both-edge", - 'N' must be 0 - 2 - Haptic will work by this edge option in case of ETWM mode. - -- dlg,resonant-freq-hz: use in case of LRA. - the frequency range: 50 - 300. - Default: 205. - -- dlg,bemf-sens-enable: Enable for internal loop computations. -- dlg,freq-track-enable: Enable for resonant frequency tracking. -- dlg,acc-enable: Enable for active acceleration. -- dlg,rapid-stop-enable: Enable for rapid stop. -- dlg,amp-pid-enable: Enable for the amplitude PID. -- dlg,mem-array: Customized waveform memory(patterns) data downloaded to - the device during initialization. This is an array of 100 values(u8). - -For further information, see device datasheet. - -====== - -Example: - - haptics: da7280-haptics@4a { - compatible = "dlg,da7280"; - reg = <0x4a>; - interrupt-parent = <&gpio6>; - interrupts = <11 IRQ_TYPE_LEVEL_LOW>; - dlg,actuator-type = "LRA"; - dlg,dlg,const-op-mode = <1>; - dlg,dlg,periodic-op-mode = <1>; - dlg,nom-microvolt = <2000000>; - dlg,abs-max-microvolt = <2000000>; - dlg,imax-microamp = <170000>; - dlg,resonant-freq-hz = <180>; - dlg,impd-micro-ohms = <10500000>; - dlg,freq-track-enable; - dlg,rapid-stop-enable; - dlg,mem-array = < - 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 - 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 - 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 - 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 - 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 - 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 - 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 - 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 - 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 - 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 - >; - }; diff --git a/Documentation/devicetree/bindings/input/dlg,da7280.yaml b/Documentation/devicetree/bindings/input/dlg,da7280.yaml new file mode 100644 index 000000000000..0d06755aaaa8 --- /dev/null +++ b/Documentation/devicetree/bindings/input/dlg,da7280.yaml @@ -0,0 +1,248 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/dlg,da7280.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Dialog Semiconductor DA7280 Low Power High-Definition Haptic Driver + +maintainers: + - Roy Im <roy.im.opensource@diasemi.com> + +properties: + compatible: + const: dlg,da7280 + + reg: + maxItems: 1 + description: I2C address of the device. + + interrupts: + maxItems: 1 + + dlg,actuator-type: + enum: + - LRA # Linear Resonance Actuator type + - ERM-bar # Bar type Eccentric Rotating Mass + - ERM-coin # Coin type Eccentric Rotating Mass + + dlg,const-op-mode: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: + - 1 # Direct register override (DRO) mode triggered by i2c (default) + - 2 # PWM data source mode controlled by PWM duty + description: + Haptic operation mode for FF_CONSTANT + + dlg,periodic-op-mode: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: + - 1 # Register triggered waveform memory(RTWM) mode, the pattern + # assigned to the PS_SEQ_ID played as much times as PS_SEQ_LOOP + - 2 # Edge triggered waveform memory(ETWM) mode, external GPI(N) + # control are required to enable/disable and it needs to keep + # device enabled by sending magnitude (X > 0), + # the pattern is assigned to the GPI(N)_SEQUENCE_ID below + default: 1 + description: + Haptic operation mode for FF_PERIODIC. + The default value is 1 for both of the operation modes. + For more details, please see the datasheet + + dlg,nom-microvolt: + minimum: 0 + maximum: 6000000 + description: + Nominal actuator voltage rating + + dlg,abs-max-microvolt: + minimum: 0 + maximum: 6000000 + description: + Absolute actuator maximum voltage rating + + dlg,imax-microamp: + minimum: 0 + maximum: 252000 + default: 130000 + description: + Actuator max current rating + + dlg,impd-micro-ohms: + minimum: 0 + maximum: 1500000000 + description: + Impedance of the actuator + + pwms: + maxItems: 1 + + dlg,ps-seq-id: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 15 + description: + The PS_SEQ_ID(pattern ID in waveform memory inside chip) + to play back when RTWM-MODE is enabled + + dlg,ps-seq-loop: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 15 + description: + The PS_SEQ_LOOP, Number of times the pre-stored sequence pointed to by + PS_SEQ_ID or GPI(N)_SEQUENCE_ID is repeated + + dlg,gpi0-seq-id: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 15 + description: + the GPI0_SEQUENCE_ID, pattern to play when gpi0 is triggered + + dlg,gpi1-seq-id: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 15 + description: + the GPI1_SEQUENCE_ID, pattern to play when gpi1 is triggered + + dlg,gpi2-seq-id: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 15 + description: + the GPI2_SEQUENCE_ID, pattern to play when gpi2 is triggered + + dlg,gpi0-mode: + enum: + - Single-pattern + - Multi-pattern + description: + Pattern mode for gpi0 + + dlg,gpi1-mode: + enum: + - Single-pattern + - Multi-pattern + description: + Pattern mode for gpi1 + + dlg,gpi2-mode: + enum: + - Single-pattern + - Multi-pattern + description: + Pattern mode for gpi2 + + dlg,gpi0-polarity: + enum: + - Rising-edge + - Falling-edge + - Both-edge + description: + gpi0 polarity, Haptic will work by this edge option in case of ETWM mode + + dlg,gpi1-polarity: + enum: + - Rising-edge + - Falling-edge + - Both-edge + description: + gpi1 polarity, Haptic will work by this edge option in case of ETWM mode + + dlg,gpi2-polarity: + enum: + - Rising-edge + - Falling-edge + - Both-edge + description: + gpi2 polarity, Haptic will work by this edge option in case of ETWM mode + + dlg,resonant-freq-hz: + minimum: 50 + maximum: 300 + default: 205 + + dlg,bemf-sens-enable: + $ref: /schemas/types.yaml#/definitions/flag + description: + Enable for internal loop computations + + dlg,freq-track-enable: + $ref: /schemas/types.yaml#/definitions/flag + description: + Enable for resonant frequency tracking + + dlg,acc-enable: + $ref: /schemas/types.yaml#/definitions/flag + description: + Enable for active acceleration + + dlg,rapid-stop-enable: + $ref: /schemas/types.yaml#/definitions/flag + description: + Enable for rapid stop + + dlg,amp-pid-enable: + $ref: /schemas/types.yaml#/definitions/flag + description: + Enable for the amplitude PID + + dlg,mem-array: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 100 + description: + Customized waveform memory (patterns) data downloaded to the device during initialization. + Each entry value must be included between 0 and 255. + +required: + - compatible + - reg + - interrupts + - dlg,actuator-type + - dlg,const-op-mode + - dlg,periodic-op-mode + - dlg,nom-microvolt + - dlg,abs-max-microvolt + - dlg,imax-microamp + - dlg,impd-micro-ohms + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interrupt-controller/irq.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + haptics@4a { + compatible = "dlg,da7280"; + reg = <0x4a>; + interrupt-parent = <&gpio6>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + dlg,actuator-type = "LRA"; + dlg,const-op-mode = <1>; + dlg,periodic-op-mode = <1>; + dlg,nom-microvolt = <2000000>; + dlg,abs-max-microvolt = <2000000>; + dlg,imax-microamp = <170000>; + dlg,resonant-freq-hz = <180>; + dlg,impd-micro-ohms = <10500000>; + dlg,freq-track-enable; + dlg,rapid-stop-enable; + dlg,mem-array = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; + }; + }; diff --git a/Documentation/devicetree/bindings/input/elan,ekth6915.yaml b/Documentation/devicetree/bindings/input/elan,ekth6915.yaml index cb3e1801b0d3..0840e4ab28b7 100644 --- a/Documentation/devicetree/bindings/input/elan,ekth6915.yaml +++ b/Documentation/devicetree/bindings/input/elan,ekth6915.yaml @@ -4,14 +4,14 @@ $id: http://devicetree.org/schemas/input/elan,ekth6915.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Elan eKTH6915 touchscreen controller +title: Elan I2C-HID touchscreen controllers maintainers: - Douglas Anderson <dianders@chromium.org> description: - Supports the Elan eKTH6915 touchscreen controller. - This touchscreen controller uses the i2c-hid protocol with a reset GPIO. + Supports the Elan eKTH6915 and other I2C-HID touchscreen controllers. + These touchscreen controller use the i2c-hid protocol with a reset GPIO. allOf: - $ref: /schemas/input/touchscreen/touchscreen.yaml# @@ -23,12 +23,14 @@ properties: - enum: - elan,ekth5015m - const: elan,ekth6915 + - items: + - const: elan,ekth8d18 + - const: elan,ekth6a12nay - enum: - elan,ekth6915 - elan,ekth6a12nay - reg: - const: 0x10 + reg: true interrupts: maxItems: 1 diff --git a/Documentation/devicetree/bindings/input/gpio-matrix-keypad.txt b/Documentation/devicetree/bindings/input/gpio-matrix-keypad.txt deleted file mode 100644 index 570dc10f0cd7..000000000000 --- a/Documentation/devicetree/bindings/input/gpio-matrix-keypad.txt +++ /dev/null @@ -1,49 +0,0 @@ -* GPIO driven matrix keypad device tree bindings - -GPIO driven matrix keypad is used to interface a SoC with a matrix keypad. -The matrix keypad supports multiple row and column lines, a key can be -placed at each intersection of a unique row and a unique column. The matrix -keypad can sense a key-press and key-release by means of GPIO lines and -report the event using GPIO interrupts to the cpu. - -Required Properties: -- compatible: Should be "gpio-matrix-keypad" -- row-gpios: List of gpios used as row lines. The gpio specifier - for this property depends on the gpio controller to - which these row lines are connected. -- col-gpios: List of gpios used as column lines. The gpio specifier - for this property depends on the gpio controller to - which these column lines are connected. -- linux,keymap: The definition can be found at - bindings/input/matrix-keymap.txt - -Optional Properties: -- linux,no-autorepeat: do no enable autorepeat feature. -- wakeup-source: use any event on keypad as wakeup event. - (Legacy property supported: "linux,wakeup") -- debounce-delay-ms: debounce interval in milliseconds -- col-scan-delay-us: delay, measured in microseconds, that is needed - before we can scan keypad after activating column gpio -- drive-inactive-cols: drive inactive columns during scan, - default is to turn inactive columns into inputs. - -Example: - matrix-keypad { - compatible = "gpio-matrix-keypad"; - debounce-delay-ms = <5>; - col-scan-delay-us = <2>; - - row-gpios = <&gpio2 25 0 - &gpio2 26 0 - &gpio2 27 0>; - - col-gpios = <&gpio2 21 0 - &gpio2 22 0>; - - linux,keymap = <0x0000008B - 0x0100009E - 0x02000069 - 0x0001006A - 0x0101001C - 0x0201006C>; - }; diff --git a/Documentation/devicetree/bindings/input/gpio-matrix-keypad.yaml b/Documentation/devicetree/bindings/input/gpio-matrix-keypad.yaml new file mode 100644 index 000000000000..ebfff9e42a36 --- /dev/null +++ b/Documentation/devicetree/bindings/input/gpio-matrix-keypad.yaml @@ -0,0 +1,103 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- + +$id: http://devicetree.org/schemas/input/gpio-matrix-keypad.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: GPIO matrix keypad + +maintainers: + - Marek Vasut <marek.vasut@gmail.com> + +description: + GPIO driven matrix keypad is used to interface a SoC with a matrix keypad. + The matrix keypad supports multiple row and column lines, a key can be + placed at each intersection of a unique row and a unique column. The matrix + keypad can sense a key-press and key-release by means of GPIO lines and + report the event using GPIO interrupts to the cpu. + +allOf: + - $ref: /schemas/input/matrix-keymap.yaml# + +properties: + compatible: + const: gpio-matrix-keypad + + row-gpios: + description: + List of GPIOs used as row lines. The gpio specifier for this property + depends on the gpio controller to which these row lines are connected. + + col-gpios: + description: + List of GPIOs used as column lines. The gpio specifier for this property + depends on the gpio controller to which these column lines are connected. + + linux,keymap: true + + linux,no-autorepeat: + type: boolean + description: Do not enable autorepeat feature. + + gpio-activelow: + type: boolean + description: + Force GPIO polarity to active low. + In the absence of this property GPIOs are treated as active high. + + debounce-delay-ms: + description: Debounce interval in milliseconds. + default: 0 + + col-scan-delay-us: + description: + Delay, measured in microseconds, that is needed + before we can scan keypad after activating column gpio. + default: 0 + + all-cols-on-delay-us: + description: + Delay, measured in microseconds, that is needed + after activating all column gpios. + default: 0 + + drive-inactive-cols: + type: boolean + description: + Drive inactive columns during scan, + default is to turn inactive columns into inputs. + + wakeup-source: true + +required: + - compatible + - row-gpios + - col-gpios + - linux,keymap + +additionalProperties: false + +examples: + - | + matrix-keypad { + compatible = "gpio-matrix-keypad"; + debounce-delay-ms = <5>; + col-scan-delay-us = <2>; + + row-gpios = <&gpio2 25 0 + &gpio2 26 0 + &gpio2 27 0>; + + col-gpios = <&gpio2 21 0 + &gpio2 22 0>; + + linux,keymap = <0x0000008B + 0x0100009E + 0x02000069 + 0x0001006A + 0x0101001C + 0x0201006C>; + + wakeup-source; + }; diff --git a/Documentation/devicetree/bindings/input/mediatek,mt6779-keypad.yaml b/Documentation/devicetree/bindings/input/mediatek,mt6779-keypad.yaml index 517a4ac1bea3..e365413732e7 100644 --- a/Documentation/devicetree/bindings/input/mediatek,mt6779-keypad.yaml +++ b/Documentation/devicetree/bindings/input/mediatek,mt6779-keypad.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Mediatek's Keypad Controller maintainers: - - Mattijs Korpershoek <mkorpershoek@baylibre.com> + - Mattijs Korpershoek <mkorpershoek@kernel.org> allOf: - $ref: /schemas/input/matrix-keymap.yaml# diff --git a/Documentation/devicetree/bindings/input/qcom,pm8921-keypad.yaml b/Documentation/devicetree/bindings/input/qcom,pm8921-keypad.yaml index 88764adcd696..e03611eef93d 100644 --- a/Documentation/devicetree/bindings/input/qcom,pm8921-keypad.yaml +++ b/Documentation/devicetree/bindings/input/qcom,pm8921-keypad.yaml @@ -62,28 +62,28 @@ unevaluatedProperties: false examples: - | - #include <dt-bindings/input/input.h> - #include <dt-bindings/interrupt-controller/irq.h> - pmic { - #address-cells = <1>; - #size-cells = <0>; + #include <dt-bindings/input/input.h> + #include <dt-bindings/interrupt-controller/irq.h> + pmic { + #address-cells = <1>; + #size-cells = <0>; - keypad@148 { - compatible = "qcom,pm8921-keypad"; - reg = <0x148>; - interrupt-parent = <&pmicintc>; - interrupts = <74 IRQ_TYPE_EDGE_RISING>, <75 IRQ_TYPE_EDGE_RISING>; - linux,keymap = < - MATRIX_KEY(0, 0, KEY_VOLUMEUP) - MATRIX_KEY(0, 1, KEY_VOLUMEDOWN) - MATRIX_KEY(0, 2, KEY_CAMERA_FOCUS) - MATRIX_KEY(0, 3, KEY_CAMERA) - >; - keypad,num-rows = <1>; - keypad,num-columns = <5>; - debounce = <15>; - scan-delay = <32>; - row-hold = <91500>; - }; - }; + keypad@148 { + compatible = "qcom,pm8921-keypad"; + reg = <0x148>; + interrupt-parent = <&pmicintc>; + interrupts = <74 IRQ_TYPE_EDGE_RISING>, <75 IRQ_TYPE_EDGE_RISING>; + linux,keymap = < + MATRIX_KEY(0, 0, KEY_VOLUMEUP) + MATRIX_KEY(0, 1, KEY_VOLUMEDOWN) + MATRIX_KEY(0, 2, KEY_CAMERA_FOCUS) + MATRIX_KEY(0, 3, KEY_CAMERA) + >; + keypad,num-rows = <1>; + keypad,num-columns = <5>; + debounce = <15>; + scan-delay = <32>; + row-hold = <91500>; + }; + }; ... diff --git a/Documentation/devicetree/bindings/input/qcom,pm8921-pwrkey.yaml b/Documentation/devicetree/bindings/input/qcom,pm8921-pwrkey.yaml index 12c74c083258..64590894857a 100644 --- a/Documentation/devicetree/bindings/input/qcom,pm8921-pwrkey.yaml +++ b/Documentation/devicetree/bindings/input/qcom,pm8921-pwrkey.yaml @@ -52,24 +52,24 @@ unevaluatedProperties: false examples: - | - #include <dt-bindings/interrupt-controller/irq.h> - ssbi { - #address-cells = <1>; - #size-cells = <0>; + #include <dt-bindings/interrupt-controller/irq.h> + ssbi { + #address-cells = <1>; + #size-cells = <0>; - pmic@0 { - reg = <0x0>; - #address-cells = <1>; - #size-cells = <0>; + pmic@0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; - pwrkey@1c { - compatible = "qcom,pm8921-pwrkey"; - reg = <0x1c>; - interrupt-parent = <&pmicint>; - interrupts = <50 IRQ_TYPE_EDGE_RISING>, <51 IRQ_TYPE_EDGE_RISING>; - debounce = <15625>; - pull-up; - }; - }; - }; + pwrkey@1c { + compatible = "qcom,pm8921-pwrkey"; + reg = <0x1c>; + interrupt-parent = <&pmicint>; + interrupts = <50 IRQ_TYPE_EDGE_RISING>, <51 IRQ_TYPE_EDGE_RISING>; + debounce = <15625>; + pull-up; + }; + }; + }; ... diff --git a/Documentation/devicetree/bindings/input/touchscreen/apple,z2-multitouch.yaml b/Documentation/devicetree/bindings/input/touchscreen/apple,z2-multitouch.yaml new file mode 100644 index 000000000000..402ca6bffd34 --- /dev/null +++ b/Documentation/devicetree/bindings/input/touchscreen/apple,z2-multitouch.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/touchscreen/apple,z2-multitouch.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Apple touchscreens attached using the Z2 protocol + +maintainers: + - Sasha Finkelstein <fnkl.kernel@gmail.com> + +description: A series of touschscreen controllers used in Apple products + +allOf: + - $ref: touchscreen.yaml# + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + enum: + - apple,j293-touchbar + - apple,j493-touchbar + + interrupts: + maxItems: 1 + + reset-gpios: + maxItems: 1 + + firmware-name: + maxItems: 1 + + apple,z2-cal-blob: + $ref: /schemas/types.yaml#/definitions/uint8-array + maxItems: 4096 + description: + Calibration blob supplied by the bootloader + +required: + - compatible + - interrupts + - reset-gpios + - firmware-name + - touchscreen-size-x + - touchscreen-size-y + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interrupt-controller/irq.h> + + spi { + #address-cells = <1>; + #size-cells = <0>; + + touchscreen@0 { + compatible = "apple,j293-touchbar"; + reg = <0>; + spi-max-frequency = <11500000>; + reset-gpios = <&pinctrl_ap 139 GPIO_ACTIVE_LOW>; + interrupts-extended = <&pinctrl_ap 194 IRQ_TYPE_EDGE_FALLING>; + firmware-name = "apple/dfrmtfw-j293.bin"; + touchscreen-size-x = <23045>; + touchscreen-size-y = <640>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.yaml b/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.yaml index 70a922e213f2..ab821490284a 100644 --- a/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.yaml +++ b/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.yaml @@ -103,16 +103,9 @@ properties: minimum: 0 maximum: 255 - touchscreen-size-x: true - touchscreen-size-y: true - touchscreen-fuzz-x: true - touchscreen-fuzz-y: true - touchscreen-inverted-x: true - touchscreen-inverted-y: true - touchscreen-swapped-x-y: true interrupt-controller: true -additionalProperties: false +unevaluatedProperties: false required: - compatible diff --git a/Documentation/devicetree/bindings/input/touchscreen/goodix,gt9916.yaml b/Documentation/devicetree/bindings/input/touchscreen/goodix,gt9916.yaml index d90f045ac06c..c40d92b7f4af 100644 --- a/Documentation/devicetree/bindings/input/touchscreen/goodix,gt9916.yaml +++ b/Documentation/devicetree/bindings/input/touchscreen/goodix,gt9916.yaml @@ -19,6 +19,7 @@ allOf: properties: compatible: enum: + - goodix,gt9897 - goodix,gt9916 reg: diff --git a/Documentation/devicetree/bindings/input/touchscreen/ti,ads7843.yaml b/Documentation/devicetree/bindings/input/touchscreen/ti,ads7843.yaml index 604921733d2c..8f6335d7da1c 100644 --- a/Documentation/devicetree/bindings/input/touchscreen/ti,ads7843.yaml +++ b/Documentation/devicetree/bindings/input/touchscreen/ti,ads7843.yaml @@ -164,20 +164,20 @@ examples: #size-cells = <0>; touchscreen@0 { - compatible = "ti,tsc2046"; - reg = <0>; /* CS0 */ - interrupt-parent = <&gpio1>; - interrupts = <8 0>; /* BOOT6 / GPIO 8 */ - pendown-gpio = <&gpio1 8 0>; - spi-max-frequency = <1000000>; - vcc-supply = <®_vcc3>; - wakeup-source; - - ti,pressure-max = /bits/ 16 <255>; - ti,x-max = /bits/ 16 <8000>; - ti,x-min = /bits/ 16 <0>; - ti,x-plate-ohms = /bits/ 16 <40>; - ti,y-max = /bits/ 16 <4800>; - ti,y-min = /bits/ 16 <0>; - }; + compatible = "ti,tsc2046"; + reg = <0>; /* CS0 */ + interrupt-parent = <&gpio1>; + interrupts = <8 0>; /* BOOT6 / GPIO 8 */ + pendown-gpio = <&gpio1 8 0>; + spi-max-frequency = <1000000>; + vcc-supply = <®_vcc3>; + wakeup-source; + + ti,pressure-max = /bits/ 16 <255>; + ti,x-max = /bits/ 16 <8000>; + ti,x-min = /bits/ 16 <0>; + ti,x-plate-ohms = /bits/ 16 <40>; + ti,y-max = /bits/ 16 <4800>; + ti,y-min = /bits/ 16 <0>; + }; }; diff --git a/Documentation/devicetree/bindings/interconnect/qcom,msm8939.yaml b/Documentation/devicetree/bindings/interconnect/qcom,msm8939.yaml index 4b08be72bbd7..534644cccdcb 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,msm8939.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,msm8939.yaml @@ -70,8 +70,8 @@ examples: reg = <0x00580000 0x14000>; #interconnect-cells = <1>; - snoc_mm: interconnect-snoc { - compatible = "qcom,msm8939-snoc-mm"; - #interconnect-cells = <1>; - }; + snoc_mm: interconnect-snoc { + compatible = "qcom,msm8939-snoc-mm"; + #interconnect-cells = <1>; + }; }; diff --git a/Documentation/devicetree/bindings/interconnect/qcom,msm8953.yaml b/Documentation/devicetree/bindings/interconnect/qcom,msm8953.yaml index 343ff62d7b65..56cdb77b369a 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,msm8953.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,msm8953.yaml @@ -84,17 +84,17 @@ additionalProperties: false examples: - | - #include <dt-bindings/clock/qcom,gcc-msm8953.h> + #include <dt-bindings/clock/qcom,gcc-msm8953.h> - snoc: interconnect@580000 { - compatible = "qcom,msm8953-snoc"; - reg = <0x580000 0x16080>; + interconnect@580000 { + compatible = "qcom,msm8953-snoc"; + reg = <0x580000 0x16080>; - #interconnect-cells = <2>; + #interconnect-cells = <2>; - snoc_mm: interconnect-snoc { - compatible = "qcom,msm8953-snoc-mm"; + interconnect-snoc { + compatible = "qcom,msm8953-snoc-mm"; - #interconnect-cells = <2>; - }; - }; + #interconnect-cells = <2>; + }; + }; diff --git a/Documentation/devicetree/bindings/interconnect/qcom,msm8974.yaml b/Documentation/devicetree/bindings/interconnect/qcom,msm8974.yaml index 8004c4baf397..95ce25ce1f7d 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,msm8974.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,msm8974.yaml @@ -50,13 +50,13 @@ additionalProperties: false examples: - | - #include <dt-bindings/clock/qcom,rpmcc.h> - - bimc: interconnect@fc380000 { - reg = <0xfc380000 0x6a000>; - compatible = "qcom,msm8974-bimc"; - #interconnect-cells = <1>; - clock-names = "bus", "bus_a"; - clocks = <&rpmcc RPM_SMD_BIMC_CLK>, - <&rpmcc RPM_SMD_BIMC_A_CLK>; - }; + #include <dt-bindings/clock/qcom,rpmcc.h> + + interconnect@fc380000 { + reg = <0xfc380000 0x6a000>; + compatible = "qcom,msm8974-bimc"; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_BIMC_CLK>, + <&rpmcc RPM_SMD_BIMC_A_CLK>; + }; diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml index 4ac0863205b3..cd4bb912e0dc 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml @@ -28,6 +28,7 @@ properties: - const: qcom,osm-l3 - items: - enum: + - qcom,sa8775p-epss-l3 - qcom,sc7280-epss-l3 - qcom,sc8280xp-epss-l3 - qcom,sm6375-cpucp-l3 diff --git a/Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml b/Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml index 5aaa92a7cef7..01d436d4a553 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml @@ -41,10 +41,10 @@ unevaluatedProperties: false examples: - | - #include <dt-bindings/clock/qcom,rpmcc.h> + #include <dt-bindings/clock/qcom,rpmcc.h> - bimc: interconnect@400000 { - compatible = "qcom,msm8916-bimc"; - reg = <0x00400000 0x62000>; - #interconnect-cells = <1>; - }; + interconnect@400000 { + compatible = "qcom,msm8916-bimc"; + reg = <0x00400000 0x62000>; + #interconnect-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml index 1b9164dc162f..dad3ad2fd93b 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml @@ -127,19 +127,19 @@ unevaluatedProperties: false examples: - | - #include <dt-bindings/interconnect/qcom,sdm845.h> + #include <dt-bindings/interconnect/qcom,sdm845.h> - mem_noc: interconnect@1380000 { - compatible = "qcom,sdm845-mem-noc"; - reg = <0x01380000 0x27200>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; + interconnect@1380000 { + compatible = "qcom,sdm845-mem-noc"; + reg = <0x01380000 0x27200>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; - mmss_noc: interconnect@1740000 { - compatible = "qcom,sdm845-mmss-noc"; - reg = <0x01740000 0x1c1000>; - #interconnect-cells = <1>; - qcom,bcm-voter-names = "apps", "disp"; - qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>; - }; + interconnect@1740000 { + compatible = "qcom,sdm845-mmss-noc"; + reg = <0x01740000 0x1c1000>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "apps", "disp"; + qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>; + }; diff --git a/Documentation/devicetree/bindings/interconnect/qcom,sdx75-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,sdx75-rpmh.yaml index 71cf7e252bfc..4b5e9f9b07ec 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,sdx75-rpmh.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,sdx75-rpmh.yaml @@ -78,15 +78,15 @@ examples: #include <dt-bindings/clock/qcom,rpmh.h> clk_virt: interconnect-0 { - compatible = "qcom,sdx75-clk-virt"; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - clocks = <&rpmhcc RPMH_QPIC_CLK>; + compatible = "qcom,sdx75-clk-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&rpmhcc RPMH_QPIC_CLK>; }; system_noc: interconnect@1640000 { - compatible = "qcom,sdx75-system-noc"; - reg = <0x1640000 0x4b400>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; + compatible = "qcom,sdx75-system-noc"; + reg = <0x1640000 0x4b400>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/abilis,tb10x-ictl.txt b/Documentation/devicetree/bindings/interrupt-controller/abilis,tb10x-ictl.txt deleted file mode 100644 index 5a4dd263fc12..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/abilis,tb10x-ictl.txt +++ /dev/null @@ -1,37 +0,0 @@ -TB10x Top Level Interrupt Controller -==================================== - -The Abilis TB10x SOC contains a custom interrupt controller. It performs -one-to-one mapping of external interrupt sources to CPU interrupts and -provides support for reconfigurable trigger modes. - -Required properties -------------------- - -- compatible: Should be "abilis,tb10x-ictl" -- reg: specifies physical base address and size of register range. -- interrupt-congroller: Identifies the node as an interrupt controller. -- #interrupt cells: Specifies the number of cells used to encode an interrupt - source connected to this controller. The value shall be 2. -- interrupts: Specifies the list of interrupt lines which are handled by - the interrupt controller in the parent controller's notation. Interrupts - are mapped one-to-one to parent interrupts. - -Example -------- - -intc: interrupt-controller { /* Parent interrupt controller */ - interrupt-controller; - #interrupt-cells = <1>; /* For example below */ - /* ... */ -}; - -tb10x_ictl: pic@2000 { /* TB10x interrupt controller */ - compatible = "abilis,tb10x-ictl"; - reg = <0x2000 0x20>; - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&intc>; - interrupts = <5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 30 31>; -}; diff --git a/Documentation/devicetree/bindings/interrupt-controller/abilis,tb10x-ictl.yaml b/Documentation/devicetree/bindings/interrupt-controller/abilis,tb10x-ictl.yaml new file mode 100644 index 000000000000..cd2c49670e7b --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/abilis,tb10x-ictl.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/abilis,tb10x-ictl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TB10x Top Level Interrupt Controller + +maintainers: + - Christian Ruppert <christian.ruppert@abilis.com> + +description: + The Abilis TB10x SOC contains a custom interrupt controller. It performs + one-to-one mapping of external interrupt sources to CPU interrupts and + provides support for reconfigurable trigger modes. + +properties: + compatible: + const: abilis,tb10x-ictl + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + interrupts: + description: A one-to-one mapping of external interrupt sources to parent + interrupts. + minItems: 1 + maxItems: 32 + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + - interrupts + +additionalProperties: false + +examples: + - | + interrupt-controller@2000 { + compatible = "abilis,tb10x-ictl"; + reg = <0x2000 0x20>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <5>, <6>, <7>, <8>, <9>, <10>, <11>, <12>, <13>, <14>, + <15>, <16>, <17>, <18>, <19>, <20>, <21>, <22>, <23>, + <24>, <25>, <26>, <27>, <28>, <29>, <30>, <31>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/al,alpine-msix.txt b/Documentation/devicetree/bindings/interrupt-controller/al,alpine-msix.txt deleted file mode 100644 index 5669764f9cc9..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/al,alpine-msix.txt +++ /dev/null @@ -1,25 +0,0 @@ -Alpine MSIX controller - -See arm,gic-v3.txt for SPI and MSI definitions. - -Required properties: - -- compatible: should be "al,alpine-msix" -- reg: physical base address and size of the registers -- interrupt-controller: identifies the node as an interrupt controller -- msi-controller: identifies the node as an PCI Message Signaled Interrupt - controller -- al,msi-base-spi: SPI base of the MSI frame -- al,msi-num-spis: number of SPIs assigned to the MSI frame, relative to SPI0 - -Example: - -msix: msix { - compatible = "al,alpine-msix"; - reg = <0x0 0xfbe00000 0x0 0x100000>; - interrupt-parent = <&gic>; - interrupt-controller; - msi-controller; - al,msi-base-spi = <160>; - al,msi-num-spis = <160>; -}; diff --git a/Documentation/devicetree/bindings/interrupt-controller/al,alpine-msix.yaml b/Documentation/devicetree/bindings/interrupt-controller/al,alpine-msix.yaml new file mode 100644 index 000000000000..9f1ff8ec686f --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/al,alpine-msix.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/al,alpine-msix.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Alpine MSIX controller + +maintainers: + - Antoine Tenart <atenart@kernel.org> + +properties: + compatible: + const: al,alpine-msix + + reg: + maxItems: 1 + + interrupt-parent: true + + msi-controller: true + + al,msi-base-spi: + description: SPI base of the MSI frame + $ref: /schemas/types.yaml#/definitions/uint32 + + al,msi-num-spis: + description: number of SPIs assigned to the MSI frame, relative to SPI0 + $ref: /schemas/types.yaml#/definitions/uint32 + +required: + - compatible + - reg + - msi-controller + - al,msi-base-spi + - al,msi-num-spis + +additionalProperties: false + +examples: + - | + msi-controller@fbe00000 { + compatible = "al,alpine-msix"; + reg = <0xfbe00000 0x100000>; + interrupt-parent = <&gic>; + msi-controller; + al,msi-base-spi = <160>; + al,msi-num-spis = <160>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml index f49b43f45f3d..06e3621a8c06 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml @@ -26,6 +26,7 @@ properties: deprecated: true - const: allwinner,sun7i-a20-sc-nmi - const: allwinner,sun9i-a80-nmi + - const: allwinner,sun55i-a523-nmi - items: - enum: - allwinner,sun8i-v3s-nmi diff --git a/Documentation/devicetree/bindings/pci/altr,msi-controller.yaml b/Documentation/devicetree/bindings/interrupt-controller/altr,msi-controller.yaml index 98814862d006..d046954b8a27 100644 --- a/Documentation/devicetree/bindings/pci/altr,msi-controller.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/altr,msi-controller.yaml @@ -2,7 +2,7 @@ # Copyright (C) 2015, 2024, Intel Corporation %YAML 1.2 --- -$id: http://devicetree.org/schemas/altr,msi-controller.yaml# +$id: http://devicetree.org/schemas/interrupt-controller/altr,msi-controller.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Altera PCIe MSI controller diff --git a/Documentation/devicetree/bindings/interrupt-controller/amazon,al-fic.txt b/Documentation/devicetree/bindings/interrupt-controller/amazon,al-fic.txt deleted file mode 100644 index c676b03c752e..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/amazon,al-fic.txt +++ /dev/null @@ -1,27 +0,0 @@ -Amazon's Annapurna Labs Fabric Interrupt Controller - -Required properties: - -- compatible: should be "amazon,al-fic" -- reg: physical base address and size of the registers -- interrupt-controller: identifies the node as an interrupt controller -- #interrupt-cells : must be 2. Specifies the number of cells needed to encode - an interrupt source. Supported trigger types are low-to-high edge - triggered and active high level-sensitive. -- interrupts: describes which input line in the interrupt parent, this - fic's output is connected to. This field property depends on the parent's - binding - -Please refer to interrupts.txt in this directory for details of the common -Interrupt Controllers bindings used by client devices. - -Example: - -amazon_fic: interrupt-controller@fd8a8500 { - compatible = "amazon,al-fic"; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x0 0xfd8a8500 0x0 0x1000>; - interrupt-parent = <&gic>; - interrupts = <GIC_SPI 0x0 IRQ_TYPE_LEVEL_HIGH>; -}; diff --git a/Documentation/devicetree/bindings/interrupt-controller/amazon,al-fic.yaml b/Documentation/devicetree/bindings/interrupt-controller/amazon,al-fic.yaml new file mode 100644 index 000000000000..26bc05dee0bc --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/amazon,al-fic.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/amazon,al-fic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amazon Annapurna Labs Fabric Interrupt Controller + +maintainers: + - Talel Shenhar <talel@amazon.com> + +properties: + compatible: + const: amazon,al-fic + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + - interrupts + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + interrupt-controller@fd8a8500 { + compatible = "amazon,al-fic"; + reg = <0xfd8a8500 0x1000>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 0x0 IRQ_TYPE_LEVEL_HIGH>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml index a93744763787..3d60d9e9e208 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml @@ -35,6 +35,9 @@ properties: - amlogic,meson-sm1-gpio-intc - amlogic,meson-a1-gpio-intc - amlogic,meson-s4-gpio-intc + - amlogic,a4-gpio-intc + - amlogic,a4-gpio-ao-intc + - amlogic,a5-gpio-intc - amlogic,c3-gpio-intc - amlogic,t7-gpio-intc - const: amlogic,meson-gpio-intc @@ -49,7 +52,7 @@ properties: amlogic,channel-interrupts: description: Array with the upstream hwirq numbers - minItems: 8 + minItems: 2 maxItems: 12 $ref: /schemas/types.yaml#/definitions/uint32-array @@ -60,6 +63,20 @@ required: - "#interrupt-cells" - amlogic,channel-interrupts +if: + properties: + compatible: + contains: + const: amlogic,a4-gpio-ao-intc +then: + properties: + amlogic,channel-interrupts: + maxItems: 2 +else: + properties: + amlogic,channel-interrupts: + minItems: 8 + additionalProperties: false examples: diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,nvic.txt b/Documentation/devicetree/bindings/interrupt-controller/arm,nvic.txt deleted file mode 100644 index 386ab37a383f..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/arm,nvic.txt +++ /dev/null @@ -1,36 +0,0 @@ -* ARM Nested Vector Interrupt Controller (NVIC) - -The NVIC provides an interrupt controller that is tightly coupled to -Cortex-M based processor cores. The NVIC implemented on different SoCs -vary in the number of interrupts and priority bits per interrupt. - -Main node required properties: - -- compatible : should be one of: - "arm,v6m-nvic" - "arm,v7m-nvic" - "arm,v8m-nvic" -- interrupt-controller : Identifies the node as an interrupt controller -- #interrupt-cells : Specifies the number of cells needed to encode an - interrupt source. The type shall be a <u32> and the value shall be 2. - - The 1st cell contains the interrupt number for the interrupt type. - - The 2nd cell is the priority of the interrupt. - -- reg : Specifies base physical address(s) and size of the NVIC registers. - This is at a fixed address (0xe000e100) and size (0xc00). - -- arm,num-irq-priority-bits: The number of priority bits implemented by the - given SoC - -Example: - - intc: interrupt-controller@e000e100 { - compatible = "arm,v7m-nvic"; - #interrupt-cells = <2>; - #address-cells = <1>; - interrupt-controller; - reg = <0xe000e100 0xc00>; - arm,num-irq-priority-bits = <4>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,nvic.yaml b/Documentation/devicetree/bindings/interrupt-controller/arm,nvic.yaml new file mode 100644 index 000000000000..d89eca956c5f --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,nvic.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/arm,nvic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM Nested Vector Interrupt Controller (NVIC) + +maintainers: + - Rob Herring <robh@kernel.org> + +description: + The NVIC provides an interrupt controller that is tightly coupled to Cortex-M + based processor cores. The NVIC implemented on different SoCs vary in the + number of interrupts and priority bits per interrupt. + +properties: + compatible: + enum: + - arm,v6m-nvic + - arm,v7m-nvic + - arm,v8m-nvic + + reg: + maxItems: 1 + + '#address-cells': + const: 0 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + description: | + Number of cells to encode an interrupt source: + first = interrupt number, second = priority. + + arm,num-irq-priority-bits: + description: Number of priority bits implemented by the SoC + minimum: 1 + maximum: 8 + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + - arm,num-irq-priority-bits + +additionalProperties: false + +examples: + - | + interrupt-controller@e000e100 { + compatible = "arm,v7m-nvic"; + #interrupt-cells = <2>; + #address-cells = <0>; + interrupt-controller; + reg = <0xe000e100 0xc00>; + arm,num-irq-priority-bits = <4>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,versatile-fpga-irq.txt b/Documentation/devicetree/bindings/interrupt-controller/arm,versatile-fpga-irq.txt deleted file mode 100644 index ea939f54c5eb..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/arm,versatile-fpga-irq.txt +++ /dev/null @@ -1,38 +0,0 @@ -* ARM Versatile FPGA interrupt controller - -One or more FPGA IRQ controllers can be synthesized in an ARM reference board -such as the Integrator or Versatile family. The output of these different -controllers are OR:ed together and fed to the CPU tile's IRQ input. Each -instance can handle up to 32 interrupts. - -Required properties: -- compatible: "arm,versatile-fpga-irq" -- interrupt-controller: Identifies the node as an interrupt controller -- #interrupt-cells: The number of cells to define the interrupts. Must be 1 - as the FPGA IRQ controller has no configuration options for interrupt - sources. The cell is a u32 and defines the interrupt number. -- reg: The register bank for the FPGA interrupt controller. -- clear-mask: a u32 number representing the mask written to clear all IRQs - on the controller at boot for example. -- valid-mask: a u32 number representing a bit mask determining which of - the interrupts are valid. Unconnected/unused lines are set to 0, and - the system till not make it possible for devices to request these - interrupts. - -The "oxsemi,ox810se-rps-irq" compatible is deprecated. - -Example: - -pic: pic@14000000 { - compatible = "arm,versatile-fpga-irq"; - #interrupt-cells = <1>; - interrupt-controller; - reg = <0x14000000 0x100>; - clear-mask = <0xffffffff>; - valid-mask = <0x003fffff>; -}; - -Optional properties: -- interrupts: if the FPGA IRQ controller is cascaded, i.e. if its IRQ - output is simply connected to the input of another IRQ controller, - then the parent IRQ shall be specified in this property. diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,versatile-fpga-irq.yaml b/Documentation/devicetree/bindings/interrupt-controller/arm,versatile-fpga-irq.yaml new file mode 100644 index 000000000000..8d581b3aac3a --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,versatile-fpga-irq.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/arm,versatile-fpga-irq.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM Versatile FPGA IRQ Controller + +maintainers: + - Linus Walleij <linus.walleij@linaro.org> + +description: + One or more FPGA IRQ controllers can be synthesized in an ARM reference board + such as the Integrator or Versatile family. The output of these different + controllers are OR:ed together and fed to the CPU tile's IRQ input. Each + instance can handle up to 32 interrupts. + +properties: + compatible: + const: arm,versatile-fpga-irq + + interrupt-controller: true + + '#interrupt-cells': + const: 1 + + reg: + maxItems: 1 + + clear-mask: + description: A mask written to clear all IRQs on the controller at boot. + $ref: /schemas/types.yaml#/definitions/uint32 + + valid-mask: + description: + A bit mask determining which interrupts are valid; unused lines are set to 0. + $ref: /schemas/types.yaml#/definitions/uint32 + + interrupts: + maxItems: 1 + +additionalProperties: false + +required: + - compatible + - interrupt-controller + - '#interrupt-cells' + - reg + - clear-mask + - valid-mask + +examples: + - | + interrupt-controller@14000000 { + compatible = "arm,versatile-fpga-irq"; + #interrupt-cells = <1>; + interrupt-controller; + reg = <0x14000000 0x100>; + clear-mask = <0xffffffff>; + valid-mask = <0x003fffff>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-i2c-ic.txt b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-i2c-ic.txt deleted file mode 100644 index 033cc82e5684..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-i2c-ic.txt +++ /dev/null @@ -1,25 +0,0 @@ -Device tree configuration for the I2C Interrupt Controller on the AST24XX and -AST25XX SoCs. - -Required Properties: -- #address-cells : should be 1 -- #size-cells : should be 1 -- #interrupt-cells : should be 1 -- compatible : should be "aspeed,ast2400-i2c-ic" - or "aspeed,ast2500-i2c-ic" -- reg : address start and range of controller -- interrupts : interrupt number -- interrupt-controller : denotes that the controller receives and fires - new interrupts for child busses - -Example: - -i2c_ic: interrupt-controller@0 { - #address-cells = <1>; - #size-cells = <1>; - #interrupt-cells = <1>; - compatible = "aspeed,ast2400-i2c-ic"; - reg = <0x0 0x40>; - interrupts = <12>; - interrupt-controller; -}; diff --git a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-i2c-ic.yaml b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-i2c-ic.yaml new file mode 100644 index 000000000000..6cff6a7231bb --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-i2c-ic.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2400-i2c-ic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Aspeed I2C Interrupt Controller (AST24XX/AST25XX) + +maintainers: + - Ryan Chen <ryan_chen@aspeedtech.com> + +properties: + compatible: + enum: + - aspeed,ast2400-i2c-ic + - aspeed,ast2500-i2c-ic + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 1 + +required: + - compatible + - reg + - '#interrupt-cells' + - interrupts + - interrupt-controller + +additionalProperties: false + +examples: + - | + interrupt-controller@0 { + compatible = "aspeed,ast2400-i2c-ic"; + reg = <0x0 0x40>; + #interrupt-cells = <1>; + interrupts = <12>; + interrupt-controller; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2500-scu-ic.yaml b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2500-scu-ic.yaml new file mode 100644 index 000000000000..d5287a2bf866 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2500-scu-ic.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright 2025 Eddie James +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2500-scu-ic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Aspeed AST25XX and AST26XX SCU Interrupt Controller + +maintainers: + - Eddie James <eajames@linux.ibm.com> + +properties: + compatible: + enum: + - aspeed,ast2500-scu-ic + - aspeed,ast2600-scu-ic0 + - aspeed,ast2600-scu-ic1 + + reg: + maxItems: 1 + + '#interrupt-cells': + const: 1 + + interrupts: + maxItems: 1 + + interrupt-controller: true + +required: + - compatible + - reg + - '#interrupt-cells' + - interrupts + - interrupt-controller + +additionalProperties: false + +examples: + - | + interrupt-controller@18 { + compatible = "aspeed,ast2500-scu-ic"; + reg = <0x18 0x4>; + #interrupt-cells = <1>; + interrupts = <21>; + interrupt-controller; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2xxx-scu-ic.txt b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2xxx-scu-ic.txt deleted file mode 100644 index 251ed44171db..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2xxx-scu-ic.txt +++ /dev/null @@ -1,23 +0,0 @@ -Aspeed AST25XX and AST26XX SCU Interrupt Controller - -Required Properties: - - #interrupt-cells : must be 1 - - compatible : must be "aspeed,ast2500-scu-ic", - "aspeed,ast2600-scu-ic0" or - "aspeed,ast2600-scu-ic1" - - interrupts : interrupt from the parent controller - - interrupt-controller : indicates that the controller receives and - fires new interrupts for child busses - -Example: - - syscon@1e6e2000 { - ranges = <0 0x1e6e2000 0x1a8>; - - scu_ic: interrupt-controller@18 { - #interrupt-cells = <1>; - compatible = "aspeed,ast2500-scu-ic"; - interrupts = <21>; - interrupt-controller; - }; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2712-msix.yaml b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2712-msix.yaml new file mode 100644 index 000000000000..c84614663b5d --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2712-msix.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm2712-msix.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom bcm2712 MSI-X Interrupt Peripheral support + +maintainers: + - Stanimir Varbanov <svarbanov@suse.de> + +description: + This interrupt controller is used to provide interrupt vectors to the + generic interrupt controller (GIC) on bcm2712. It will be used as + external MSI-X controller for PCIe root complex. + +allOf: + - $ref: /schemas/interrupt-controller/msi-controller.yaml# + +properties: + compatible: + const: brcm,bcm2712-mip + + reg: + items: + - description: Base register address + - description: PCIe message address + + "#msi-cells": + const: 0 + + brcm,msi-offset: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Shift the allocated MSI's. + +unevaluatedProperties: false + +required: + - compatible + - reg + - msi-controller + - msi-ranges + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + axi { + #address-cells = <2>; + #size-cells = <2>; + + msi-controller@1000130000 { + compatible = "brcm,bcm2712-mip"; + reg = <0x10 0x00130000 0x00 0xc0>, + <0xff 0xfffff000 0x00 0x1000>; + msi-controller; + #msi-cells = <0>; + msi-ranges = <&gicv2 GIC_SPI 128 IRQ_TYPE_EDGE_RISING 64>; + }; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt deleted file mode 100644 index bdd173056f72..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt +++ /dev/null @@ -1,131 +0,0 @@ -BCM2835 Top-Level ("ARMCTRL") Interrupt Controller - -The BCM2835 contains a custom top-level interrupt controller, which supports -72 interrupt sources using a 2-level register scheme. The interrupt -controller, or the HW block containing it, is referred to occasionally -as "armctrl" in the SoC documentation, hence naming of this binding. - -The BCM2836 contains the same interrupt controller with the same -interrupts, but the per-CPU interrupt controller is the root, and an -interrupt there indicates that the ARMCTRL has an interrupt to handle. - -Required properties: - -- compatible : should be "brcm,bcm2835-armctrl-ic" or - "brcm,bcm2836-armctrl-ic" -- reg : Specifies base physical address and size of the registers. -- interrupt-controller : Identifies the node as an interrupt controller -- #interrupt-cells : Specifies the number of cells needed to encode an - interrupt source. The value shall be 2. - - The 1st cell is the interrupt bank; 0 for interrupts in the "IRQ basic - pending" register, or 1/2 respectively for interrupts in the "IRQ pending - 1/2" register. - - The 2nd cell contains the interrupt number within the bank. Valid values - are 0..7 for bank 0, and 0..31 for bank 1. - -Additional required properties for brcm,bcm2836-armctrl-ic: -- interrupts : Specifies the interrupt on the parent for this interrupt - controller to handle. - -The interrupt sources are as follows: - -Bank 0: -0: ARM_TIMER -1: ARM_MAILBOX -2: ARM_DOORBELL_0 -3: ARM_DOORBELL_1 -4: VPU0_HALTED -5: VPU1_HALTED -6: ILLEGAL_TYPE0 -7: ILLEGAL_TYPE1 - -Bank 1: -0: TIMER0 -1: TIMER1 -2: TIMER2 -3: TIMER3 -4: CODEC0 -5: CODEC1 -6: CODEC2 -7: VC_JPEG -8: ISP -9: VC_USB -10: VC_3D -11: TRANSPOSER -12: MULTICORESYNC0 -13: MULTICORESYNC1 -14: MULTICORESYNC2 -15: MULTICORESYNC3 -16: DMA0 -17: DMA1 -18: VC_DMA2 -19: VC_DMA3 -20: DMA4 -21: DMA5 -22: DMA6 -23: DMA7 -24: DMA8 -25: DMA9 -26: DMA10 -27: DMA11-14 - shared interrupt for DMA 11 to 14 -28: DMAALL - triggers on all dma interrupts (including channel 15) -29: AUX -30: ARM -31: VPUDMA - -Bank 2: -0: HOSTPORT -1: VIDEOSCALER -2: CCP2TX -3: SDC -4: DSI0 -5: AVE -6: CAM0 -7: CAM1 -8: HDMI0 -9: HDMI1 -10: PIXELVALVE1 -11: I2CSPISLV -12: DSI1 -13: PWA0 -14: PWA1 -15: CPR -16: SMI -17: GPIO0 -18: GPIO1 -19: GPIO2 -20: GPIO3 -21: VC_I2C -22: VC_SPI -23: VC_I2SPCM -24: VC_SDIO -25: VC_UART -26: SLIMBUS -27: VEC -28: CPG -29: RNG -30: VC_ARASANSDIO -31: AVSPMON - -Example: - -/* BCM2835, first level */ -intc: interrupt-controller { - compatible = "brcm,bcm2835-armctrl-ic"; - reg = <0x7e00b200 0x200>; - interrupt-controller; - #interrupt-cells = <2>; -}; - -/* BCM2836, second level */ -intc: interrupt-controller { - compatible = "brcm,bcm2836-armctrl-ic"; - reg = <0x7e00b200 0x200>; - interrupt-controller; - #interrupt-cells = <2>; - - interrupt-parent = <&local_intc>; - interrupts = <8>; -}; diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.yaml b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.yaml new file mode 100644 index 000000000000..625eb22bedf0 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.yaml @@ -0,0 +1,162 @@ +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm2835-armctrl-ic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: BCM2835 ARMCTRL Interrupt Controller + +maintainers: + - Florian Fainelli <florian.fainelli@broadcom.com> + - Raspberry Pi Kernel Maintenance <kernel-list@raspberrypi.com> + +description: > + The BCM2835 contains a custom top-level interrupt controller, which supports + 72 interrupt sources using a 2-level register scheme. The interrupt + controller, or the HW block containing it, is referred to occasionally as + "armctrl" in the SoC documentation, hence naming of this binding. + + The BCM2836 contains the same interrupt controller with the same interrupts, + but the per-CPU interrupt controller is the root, and an interrupt there + indicates that the ARMCTRL has an interrupt to handle. + + The interrupt sources are as follows: + + Bank 0: + 0: ARM_TIMER + 1: ARM_MAILBOX + 2: ARM_DOORBELL_0 + 3: ARM_DOORBELL_1 + 4: VPU0_HALTED + 5: VPU1_HALTED + 6: ILLEGAL_TYPE0 + 7: ILLEGAL_TYPE1 + + Bank 1: + 0: TIMER0 + 1: TIMER1 + 2: TIMER2 + 3: TIMER3 + 4: CODEC0 + 5: CODEC1 + 6: CODEC2 + 7: VC_JPEG + 8: ISP + 9: VC_USB + 10: VC_3D + 11: TRANSPOSER + 12: MULTICORESYNC0 + 13: MULTICORESYNC1 + 14: MULTICORESYNC2 + 15: MULTICORESYNC3 + 16: DMA0 + 17: DMA1 + 18: VC_DMA2 + 19: VC_DMA3 + 20: DMA4 + 21: DMA5 + 22: DMA6 + 23: DMA7 + 24: DMA8 + 25: DMA9 + 26: DMA10 + 27: DMA11-14 - shared interrupt for DMA 11 to 14 + 28: DMAALL - triggers on all dma interrupts (including channel 15) + 29: AUX + 30: ARM + 31: VPUDMA + + Bank 2: + 0: HOSTPORT + 1: VIDEOSCALER + 2: CCP2TX + 3: SDC + 4: DSI0 + 5: AVE + 6: CAM0 + 7: CAM1 + 8: HDMI0 + 9: HDMI1 + 10: PIXELVALVE1 + 11: I2CSPISLV + 12: DSI1 + 13: PWA0 + 14: PWA1 + 15: CPR + 16: SMI + 17: GPIO0 + 18: GPIO1 + 19: GPIO2 + 20: GPIO3 + 21: VC_I2C + 22: VC_SPI + 23: VC_I2SPCM + 24: VC_SDIO + 25: VC_UART + 26: SLIMBUS + 27: VEC + 28: CPG + 29: RNG + 30: VC_ARASANSDIO + 31: AVSPMON + +properties: + compatible: + enum: + - brcm,bcm2835-armctrl-ic + - brcm,bcm2836-armctrl-ic + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + description: > + The 1st cell is the interrupt bank; 0 for interrupts in the "IRQ basic + pending" register, or 1/2 respectively for interrupts in the "IRQ pending + 1/2" register. + + The 2nd cell contains the interrupt number within the bank. Valid values + are 0..7 for bank 0, and 0..31 for bank 1. + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + +allOf: + - if: + properties: + compatible: + contains: + const: brcm,bcm2836-armctrl-ic + then: + required: + - interrupts + else: + properties: + interrupts: false + +additionalProperties: false + +examples: + - | + interrupt-controller@7e00b200 { + compatible = "brcm,bcm2835-armctrl-ic"; + reg = <0x7e00b200 0x200>; + interrupt-controller; + #interrupt-cells = <2>; + }; + - | + interrupt-controller@7e00b200 { + compatible = "brcm,bcm2836-armctrl-ic"; + reg = <0x7e00b200 0x200>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <8>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-l1-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-l1-intc.txt deleted file mode 100644 index 2bc19b1ac877..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-l1-intc.txt +++ /dev/null @@ -1,55 +0,0 @@ -Broadcom BCM6345-style Level 1 interrupt controller - -This block is a first level interrupt controller that is typically connected -directly to one of the HW INT lines on each CPU. - -Key elements of the hardware design include: - -- 32, 64 or 128 incoming level IRQ lines - -- Most onchip peripherals are wired directly to an L1 input - -- A separate instance of the register set for each CPU, allowing individual - peripheral IRQs to be routed to any CPU - -- Contains one or more enable/status word pairs per CPU - -- No atomic set/clear operations - -- No polarity/level/edge settings - -- No FIFO or priority encoder logic; software is expected to read all - 2-4 status words to determine which IRQs are pending - -Required properties: - -- compatible: should be "brcm,bcm<soc>-l1-intc", "brcm,bcm6345-l1-intc" -- reg: specifies the base physical address and size of the registers; - the number of supported IRQs is inferred from the size argument -- interrupt-controller: identifies the node as an interrupt controller -- #interrupt-cells: specifies the number of cells needed to encode an interrupt - source, should be 1. -- interrupts: specifies the interrupt line(s) in the interrupt-parent controller - node; valid values depend on the type of parent interrupt controller - -If multiple reg ranges and interrupt-parent entries are present on an SMP -system, the driver will allow IRQ SMP affinity to be set up through the -/proc/irq/ interface. In the simplest possible configuration, only one -reg range and one interrupt-parent is needed. - -The driver operates in native CPU endian by default, there is no support for -specifying an alternative endianness. - -Example: - -periph_intc: interrupt-controller@10000000 { - compatible = "brcm,bcm63168-l1-intc", "brcm,bcm6345-l1-intc"; - reg = <0x10000020 0x20>, - <0x10000040 0x20>; - - interrupt-controller; - #interrupt-cells = <1>; - - interrupt-parent = <&cpu_intc>; - interrupts = <2>, <3>; -}; diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-l1-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-l1-intc.yaml new file mode 100644 index 000000000000..ca6a2ff43acd --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-l1-intc.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm6345-l1-intc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom BCM6345-style Level 1 interrupt controller + +maintainers: + - Simon Arlott <simon@octiron.net> + +description: > + This block is a first level interrupt controller that is typically connected + directly to one of the HW INT lines on each CPU. + + Key elements of the hardware design include: + + - 32, 64 or 128 incoming level IRQ lines + + - Most onchip peripherals are wired directly to an L1 input + + - A separate instance of the register set for each CPU, allowing individual + peripheral IRQs to be routed to any CPU + + - Contains one or more enable/status word pairs per CPU + + - No atomic set/clear operations + + - No polarity/level/edge settings + + - No FIFO or priority encoder logic; software is expected to read all + 2-4 status words to determine which IRQs are pending + + If multiple reg ranges and interrupt-parent entries are present on an SMP + system, the driver will allow IRQ SMP affinity to be set up through the + /proc/irq/ interface. In the simplest possible configuration, only one + reg range and one interrupt-parent is needed. + + The driver operates in native CPU endian by default, there is no support for + specifying an alternative endianness. + +properties: + compatible: + const: brcm,bcm6345-l1-intc + + reg: + description: One entry per CPU core + minItems: 1 + maxItems: 2 + + interrupt-controller: true + + "#interrupt-cells": + const: 1 + + interrupts: + description: One entry per CPU core + minItems: 1 + maxItems: 2 + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + - interrupts + +additionalProperties: false + +examples: + - | + interrupt-controller@10000000 { + compatible = "brcm,bcm6345-l1-intc"; + reg = <0x10000020 0x20>, + <0x10000040 0x20>; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupts = <2>, <3>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/cdns,xtensa-mx.txt b/Documentation/devicetree/bindings/interrupt-controller/cdns,xtensa-mx.txt deleted file mode 100644 index d4de980e55fa..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/cdns,xtensa-mx.txt +++ /dev/null @@ -1,18 +0,0 @@ -* Xtensa Interrupt Distributor and Programmable Interrupt Controller (MX) - -Required properties: -- compatible: Should be "cdns,xtensa-mx". - -Remaining properties have exact same meaning as in Xtensa PIC -(see cdns,xtensa-pic.txt). - -Examples: - pic: pic { - compatible = "cdns,xtensa-mx"; - /* one cell: internal irq number, - * two cells: second cell == 0: internal irq number - * second cell == 1: external irq number - */ - #interrupt-cells = <2>; - interrupt-controller; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/cdns,xtensa-pic.txt b/Documentation/devicetree/bindings/interrupt-controller/cdns,xtensa-pic.txt deleted file mode 100644 index 026ef4cfc1d5..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/cdns,xtensa-pic.txt +++ /dev/null @@ -1,25 +0,0 @@ -* Xtensa built-in Programmable Interrupt Controller (PIC) - -Required properties: -- compatible: Should be "cdns,xtensa-pic". -- interrupt-controller: Identifies the node as an interrupt controller. -- #interrupt-cells: The number of cells to define the interrupts. - It may be either 1 or 2. - When it's 1, the first cell is the internal IRQ number. - When it's 2, the first cell is the IRQ number, and the second cell - specifies whether it's internal (0) or external (1). - Periferals are usually connected to a fixed external IRQ, but for different - core variants it may be mapped to different internal IRQ. - IRQ sensitivity and priority are fixed for each core variant and may not be - changed at runtime. - -Examples: - pic: pic { - compatible = "cdns,xtensa-pic"; - /* one cell: internal irq number, - * two cells: second cell == 0: internal irq number - * second cell == 1: external irq number - */ - #interrupt-cells = <2>; - interrupt-controller; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/cdns,xtensa-pic.yaml b/Documentation/devicetree/bindings/interrupt-controller/cdns,xtensa-pic.yaml new file mode 100644 index 000000000000..6773207fee01 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/cdns,xtensa-pic.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright 2025 Max Filippov <jcmvbkbc@gmail.com> + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/cdns,xtensa-pic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xtensa Interrupt Controllers + +maintainers: + - Max Filippov <jcmvbkbc@gmail.com> + +description: + Xtensa Interrupt Distributor and Programmable Interrupt Controller (MX) and + Xtensa built-in Programmable Interrupt Controller (PIC) + +properties: + compatible: + enum: + - cdns,xtensa-mx + - cdns,xtensa-pic + + '#interrupt-cells': + enum: [ 1, 2 ] + description: + Number of cells to define the interrupts. When 1, the first cell is the + internal IRQ number; when 2, the second cell specifies internal (0) or + external (1). + + interrupt-controller: true + +required: + - compatible + - '#interrupt-cells' + - interrupt-controller + +additionalProperties: false + +examples: + - | + interrupt-controller { + compatible = "cdns,xtensa-pic"; + /* one cell: internal irq number, + * two cells: second cell == 0: internal irq number + * second cell == 1: external irq number + */ + #interrupt-cells = <2>; + interrupt-controller; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/chrp,open-pic.yaml b/Documentation/devicetree/bindings/interrupt-controller/chrp,open-pic.yaml new file mode 100644 index 000000000000..f0d9bbd7d510 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/chrp,open-pic.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/chrp,open-pic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Open PIC Interrupt Controller + +maintainers: + - Rob Herring <robh@kernel.org> + +description: + This binding specifies what properties must be available in the device tree + representation of an Open PIC compliant interrupt controller. This binding is + based on the binding defined for Open PIC in [1] and is a superset of that + binding. + +properties: + compatible: + oneOf: + - items: + - const: fsl,mpic + - const: chrp,open-pic + - const: chrp,open-pic + + device_type: + const: open-pci + deprecated: true + + reg: + maxItems: 1 + + interrupt-controller: true + + '#address-cells': + const: 0 + + '#interrupt-cells': + const: 2 + + pic-no-reset: + description: Indicates the PIC shall not be reset during runtime initialization. + type: boolean + +required: + - compatible + - reg + - interrupt-controller + - '#address-cells' + - '#interrupt-cells' + +additionalProperties: false + +examples: + - | + interrupt-controller@40000 { + compatible = "chrp,open-pic"; + reg = <0x40000 0x40000>; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + pic-no-reset; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/cirrus,clps711x-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/cirrus,clps711x-intc.txt deleted file mode 100644 index 969b4582ec60..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/cirrus,clps711x-intc.txt +++ /dev/null @@ -1,41 +0,0 @@ -Cirrus Logic CLPS711X Interrupt Controller - -Required properties: - -- compatible: Should be "cirrus,ep7209-intc". -- reg: Specifies base physical address of the registers set. -- interrupt-controller: Identifies the node as an interrupt controller. -- #interrupt-cells: Specifies the number of cells needed to encode an - interrupt source. The value shall be 1. - -The interrupt sources are as follows: -ID Name Description ---------------------------- -1: BLINT Battery low (FIQ) -3: MCINT Media changed (FIQ) -4: CSINT CODEC sound -5: EINT1 External 1 -6: EINT2 External 2 -7: EINT3 External 3 -8: TC1OI TC1 under flow -9: TC2OI TC2 under flow -10: RTCMI RTC compare match -11: TINT 64Hz tick -12: UTXINT1 UART1 transmit FIFO half empty -13: URXINT1 UART1 receive FIFO half full -14: UMSINT UART1 modem status changed -15: SSEOTI SSI1 end of transfer -16: KBDINT Keyboard -17: SS2RX SSI2 receive FIFO half or greater full -18: SS2TX SSI2 transmit FIFO less than half empty -28: UTXINT2 UART2 transmit FIFO half empty -29: URXINT2 UART2 receive FIFO half full -32: DAIINT DAI interface (FIQ) - -Example: - intc: interrupt-controller { - compatible = "cirrus,ep7312-intc", "cirrus,ep7209-intc"; - reg = <0x80000000 0x4000>; - interrupt-controller; - #interrupt-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/cirrus,ep7209-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/cirrus,ep7209-intc.yaml new file mode 100644 index 000000000000..d3cc49d29e10 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/cirrus,ep7209-intc.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/cirrus,ep7209-intc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cirrus Logic CLPS711X Interrupt Controller + +maintainers: + - Alexander Shiyan <shc_work@mail.ru> + +description: > + Cirrus Logic CLPS711X Interrupt Controller + + The interrupt sources are as follows: + ID Name Description + --------------------------- + 1: BLINT Battery low (FIQ) + 3: MCINT Media changed (FIQ) + 4: CSINT CODEC sound + 5: EINT1 External 1 + 6: EINT2 External 2 + 7: EINT3 External 3 + 8: TC1OI TC1 under flow + 9: TC2OI TC2 under flow + 10: RTCMI RTC compare match + 11: TINT 64Hz tick + 12: UTXINT1 UART1 transmit FIFO half empty + 13: URXINT1 UART1 receive FIFO half full + 14: UMSINT UART1 modem status changed + 15: SSEOTI SSI1 end of transfer + 16: KBDINT Keyboard + 17: SS2RX SSI2 receive FIFO half or greater full + 18: SS2TX SSI2 transmit FIFO less than half empty + 28: UTXINT2 UART2 transmit FIFO half empty + 29: URXINT2 UART2 receive FIFO half full + 32: DAIINT DAI interface (FIQ) + +properties: + compatible: + oneOf: + - items: + - const: cirrus,ep7312-intc + - const: cirrus,ep7209-intc + - items: + - const: cirrus,ep7209-intc + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 1 + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + +additionalProperties: false + +examples: + - | + interrupt-controller@80000000 { + compatible = "cirrus,ep7312-intc", "cirrus,ep7209-intc"; + reg = <0x80000000 0x4000>; + interrupt-controller; + #interrupt-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/cnxt,cx92755-ic.yaml b/Documentation/devicetree/bindings/interrupt-controller/cnxt,cx92755-ic.yaml new file mode 100644 index 000000000000..3f016cf47812 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/cnxt,cx92755-ic.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/cnxt,cx92755-ic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Conexant Digicolor Interrupt Controller + +maintainers: + - Baruch Siach <baruch@tkos.co.il> + +description: Conexant Digicolor Interrupt Controller + +properties: + compatible: + const: cnxt,cx92755-ic + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 1 + + syscon: + description: A phandle to the syscon node describing UC registers + $ref: /schemas/types.yaml#/definitions/phandle + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + - syscon + +additionalProperties: false + +examples: + - | + interrupt-controller@f0000040 { + compatible = "cnxt,cx92755-ic"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0xf0000040 0x40>; + syscon = <&uc_regs>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/csky,apb-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/csky,apb-intc.txt deleted file mode 100644 index 44286dcbac62..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/csky,apb-intc.txt +++ /dev/null @@ -1,62 +0,0 @@ -============================== -C-SKY APB Interrupt Controller -============================== - -C-SKY APB Interrupt Controller is a simple soc interrupt controller -on the apb bus and we only use it as root irq controller. - - - csky,apb-intc is used in a lot of csky fpgas and socs, it support 64 irq nums. - - csky,dual-apb-intc consists of 2 apb-intc and 128 irq nums supported. - - csky,gx6605s-intc is gx6605s soc internal irq interrupt controller, 64 irq nums. - -============================= -intc node bindings definition -============================= - - Description: Describes APB interrupt controller - - PROPERTIES - - - compatible - Usage: required - Value type: <string> - Definition: must be "csky,apb-intc" - "csky,dual-apb-intc" - "csky,gx6605s-intc" - - #interrupt-cells - Usage: required - Value type: <u32> - Definition: must be <1> - - reg - Usage: required - Value type: <u32 u32> - Definition: <phyaddr size> in soc from cpu view - - interrupt-controller: - Usage: required - - csky,support-pulse-signal: - Usage: select - Description: to support pulse signal flag - -Examples: ---------- - - intc: interrupt-controller@500000 { - compatible = "csky,apb-intc"; - #interrupt-cells = <1>; - reg = <0x00500000 0x400>; - interrupt-controller; - }; - - intc: interrupt-controller@500000 { - compatible = "csky,dual-apb-intc"; - #interrupt-cells = <1>; - reg = <0x00500000 0x400>; - interrupt-controller; - }; - - intc: interrupt-controller@500000 { - compatible = "csky,gx6605s-intc"; - #interrupt-cells = <1>; - reg = <0x00500000 0x400>; - interrupt-controller; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/csky,apb-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/csky,apb-intc.yaml new file mode 100644 index 000000000000..902648ead975 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/csky,apb-intc.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/csky,apb-intc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: C-SKY APB Interrupt Controller + +maintainers: + - Guo Ren <guoren@kernel.org> + +description: > + C-SKY APB Interrupt Controller is a simple soc interrupt controller on the apb + bus and we only use it as root irq controller. + + - csky,apb-intc is used in a lot of csky fpgas and socs, it support 64 irq nums. + - csky,dual-apb-intc consists of 2 apb-intc and 128 irq nums supported. + - csky,gx6605s-intc is gx6605s soc internal irq interrupt controller, 64 irq nums. + +properties: + compatible: + enum: + - csky,apb-intc + - csky,dual-apb-intc + - csky,gx6605s-intc + + reg: + maxItems: 1 + + '#interrupt-cells': + const: 1 + + interrupt-controller: true + + csky,support-pulse-signal: + type: boolean + description: Support for pulse signal flag. + +additionalProperties: false + +required: + - compatible + - reg + - '#interrupt-cells' + - interrupt-controller + +examples: + - | + intc: interrupt-controller@500000 { + compatible = "csky,apb-intc"; + #interrupt-cells = <1>; + reg = <0x00500000 0x400>; + interrupt-controller; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/csky,mpintc.txt b/Documentation/devicetree/bindings/interrupt-controller/csky,mpintc.txt deleted file mode 100644 index e6bbcae4d07f..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/csky,mpintc.txt +++ /dev/null @@ -1,52 +0,0 @@ -=========================================== -C-SKY Multi-processors Interrupt Controller -=========================================== - -C-SKY Multi-processors Interrupt Controller is designed for ck807/ck810/ck860 -SMP soc, and it also could be used in non-SMP system. - -Interrupt number definition: - 0-15 : software irq, and we use 15 as our IPI_IRQ. - 16-31 : private irq, and we use 16 as the co-processor timer. - 31-1024: common irq for soc ip. - -Interrupt trigger mode: (Defined in dt-bindings/interrupt-controller/irq.h) - IRQ_TYPE_LEVEL_HIGH (default) - IRQ_TYPE_LEVEL_LOW - IRQ_TYPE_EDGE_RISING - IRQ_TYPE_EDGE_FALLING - -============================= -intc node bindings definition -============================= - - Description: Describes SMP interrupt controller - - PROPERTIES - - - compatible - Usage: required - Value type: <string> - Definition: must be "csky,mpintc" - - #interrupt-cells - Usage: required - Value type: <u32> - Definition: <2> - - interrupt-controller: - Usage: required - -Examples: ("interrupts = <irq_num IRQ_TYPE_XXX>") ---------- -#include <dt-bindings/interrupt-controller/irq.h> - - intc: interrupt-controller { - compatible = "csky,mpintc"; - #interrupt-cells = <2>; - interrupt-controller; - }; - - device: device-example { - ... - interrupts = <34 IRQ_TYPE_EDGE_RISING>; - interrupt-parent = <&intc>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/csky,mpintc.yaml b/Documentation/devicetree/bindings/interrupt-controller/csky,mpintc.yaml new file mode 100644 index 000000000000..3df7739e31c4 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/csky,mpintc.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/csky,mpintc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: C-SKY Multi-processors Interrupt Controller + +maintainers: + - Guo Ren <guoren@kernel.org> + +description: > + C-SKY Multi-processors Interrupt Controller is designed for ck807/ck810/ck860 + SMP soc, and it also could be used in non-SMP system. + + Interrupt number definition: + 0-15 : software irq, and we use 15 as our IPI_IRQ. + 16-31 : private irq, and we use 16 as the co-processor timer. + 31-1024: common irq for soc ip. + +properties: + compatible: + const: csky,mpintc + + '#interrupt-cells': + const: 2 + + interrupt-controller: true + +required: + - compatible + - "#interrupt-cells" + - interrupt-controller + +additionalProperties: false + +examples: + - | + interrupt-controller { + compatible = "csky,mpintc"; + #interrupt-cells = <2>; + interrupt-controller; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/digicolor-ic.txt b/Documentation/devicetree/bindings/interrupt-controller/digicolor-ic.txt deleted file mode 100644 index 42d41ec84c7b..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/digicolor-ic.txt +++ /dev/null @@ -1,21 +0,0 @@ -Conexant Digicolor Interrupt Controller - -Required properties: - -- compatible : should be "cnxt,cx92755-ic" -- reg : Specifies base physical address and size of the interrupt controller - registers (IC) area -- interrupt-controller : Identifies the node as an interrupt controller -- #interrupt-cells : Specifies the number of cells needed to encode an - interrupt source. The value shall be 1. -- syscon: A phandle to the syscon node describing UC registers - -Example: - - intc: interrupt-controller@f0000040 { - compatible = "cnxt,cx92755-ic"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0xf0000040 0x40>; - syscon = <&uc_regs>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/econet,en751221-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/econet,en751221-intc.yaml new file mode 100644 index 000000000000..5536319c49c3 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/econet,en751221-intc.yaml @@ -0,0 +1,78 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/econet,en751221-intc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: EcoNet EN751221 Interrupt Controller + +maintainers: + - Caleb James DeLisle <cjd@cjdns.fr> + +description: + The EcoNet EN751221 Interrupt Controller is a simple interrupt controller + designed for the MIPS 34Kc MT SMP processor with 2 VPEs. Each interrupt can + be routed to either VPE but not both, so to support per-CPU interrupts, a + secondary IRQ number is allocated to control masking/unmasking on VPE#1. For + lack of a better term we call these "shadow interrupts". The assignment of + shadow interrupts is defined by the SoC integrator when wiring the interrupt + lines, so they are configurable in the device tree. + +allOf: + - $ref: /schemas/interrupt-controller.yaml# + +properties: + compatible: + const: econet,en751221-intc + + reg: + maxItems: 1 + + "#interrupt-cells": + const: 1 + + interrupt-controller: true + + interrupts: + maxItems: 1 + description: Interrupt line connecting this controller to its parent. + + econet,shadow-interrupts: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + description: + An array of interrupt number pairs where each pair represents a shadow + interrupt relationship. The first number in each pair is the primary IRQ, + and the second is its shadow IRQ used for VPE#1 control. For example, + <8 3> means IRQ 8 is shadowed by IRQ 3, so IRQ 3 cannot be mapped, but + when VPE#1 requests IRQ 8, it will manipulate the IRQ 3 mask bit. + minItems: 1 + maxItems: 20 + items: + items: + - description: primary per-CPU IRQ + - description: shadow IRQ number + +required: + - compatible + - reg + - interrupt-controller + - "#interrupt-cells" + - interrupts + +additionalProperties: false + +examples: + - | + interrupt-controller@1fb40000 { + compatible = "econet,en751221-intc"; + reg = <0x1fb40000 0x100>; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&cpuintc>; + interrupts = <2>; + + econet,shadow-interrupts = <7 2>, <8 3>, <13 12>, <30 29>; + }; +... diff --git a/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt b/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt deleted file mode 100644 index 888b2b9f7064..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt +++ /dev/null @@ -1,17 +0,0 @@ -EZchip NPS Interrupt Controller - -Required properties: - -- compatible : should be "ezchip,nps400-ic" -- interrupt-controller : Identifies the node as an interrupt controller -- #interrupt-cells : Specifies the number of cells needed to encode an - interrupt source. The value shall be 1. - - -Example: - -intc: interrupt-controller { - compatible = "ezchip,nps400-ic"; - interrupt-controller; - #interrupt-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.yaml b/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.yaml new file mode 100644 index 000000000000..589c6ebf6c1a --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.yaml @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ezchip,nps400-ic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: EZchip NPS Interrupt Controller + +maintainers: + - Noam Camus <noamc@ezchip.com> + +properties: + compatible: + const: ezchip,nps400-ic + + interrupt-controller: true + + '#interrupt-cells': + const: 1 + +required: + - compatible + - interrupt-controller + - '#interrupt-cells' + +additionalProperties: false + +examples: + - | + interrupt-controller { + compatible = "ezchip,nps400-ic"; + interrupt-controller; + #interrupt-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/faraday,ftintc010.txt b/Documentation/devicetree/bindings/interrupt-controller/faraday,ftintc010.txt deleted file mode 100644 index 24428d47f487..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/faraday,ftintc010.txt +++ /dev/null @@ -1,25 +0,0 @@ -* Faraday Technologt FTINTC010 interrupt controller - -This interrupt controller is a stock IP block from Faraday Technology found -in the Gemini SoCs and other designs. - -Required properties: -- compatible: must be one of - "faraday,ftintc010" - "cortina,gemini-interrupt-controller" (deprecated) -- reg: The register bank for the interrupt controller. -- interrupt-controller: Identifies the node as an interrupt controller -- #interrupt-cells: The number of cells to define the interrupts. - Must be 2 as the controller can specify level or rising edge - IRQs. The bindings follows the standard binding for controllers - with two cells specified in - interrupt-controller/interrupts.txt - -Example: - -interrupt-controller@48000000 { - compatible = "faraday,ftintc010" - reg = <0x48000000 0x1000>; - interrupt-controller; - #interrupt-cells = <2>; -}; diff --git a/Documentation/devicetree/bindings/interrupt-controller/faraday,ftintc010.yaml b/Documentation/devicetree/bindings/interrupt-controller/faraday,ftintc010.yaml new file mode 100644 index 000000000000..980e5c45f25b --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/faraday,ftintc010.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +--- +$id: http://devicetree.org/schemas/interrupt-controller/faraday,ftintc010.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Faraday Technology FTINTC010 interrupt controller + +maintainers: + - Linus Walleij <linus.walleij@linaro.org> + +description: + This interrupt controller is a stock IP block from Faraday Technology found + in the Gemini SoCs and other designs. + +properties: + compatible: + oneOf: + - items: + - const: moxa,moxart-ic + - const: faraday,ftintc010 + - enum: + - faraday,ftintc010 + - cortina,gemini-interrupt-controller + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + resets: + maxItems: 1 + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + +additionalProperties: false + +examples: + - | + interrupt-controller@48000000 { + compatible = "faraday,ftintc010"; + reg = <0x48000000 0x1000>; + interrupt-controller; + #interrupt-cells = <2>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.yaml b/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.yaml index 6076ddf56bb5..c49688be1058 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.yaml @@ -19,6 +19,7 @@ properties: - fsl,imx8mp-irqsteer - fsl,imx8qm-irqsteer - fsl,imx8qxp-irqsteer + - fsl,imx94-irqsteer - const: fsl,imx-irqsteer reg: diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,tzic.yaml b/Documentation/devicetree/bindings/interrupt-controller/fsl,tzic.yaml new file mode 100644 index 000000000000..5f2c8761a31d --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,tzic.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/fsl,tzic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale tzic Interrupt controller + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +properties: + compatible: + oneOf: + - items: + - enum: + - fsl,imx51-tzic + - fsl,imx53-tzic + - const: fsl,tzic + - items: + - const: fsl,imx50-tzic + - const: fsl,imx53-tzic + - const: fsl,tzic + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 1 + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + +additionalProperties: false + +examples: + - | + tz-interrupt-controller@fffc000 { + compatible = "fsl,imx53-tzic", "fsl,tzic"; + reg = <0x0fffc000 0x4000>; + interrupt-controller; + #interrupt-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/google,goldfish-pic.txt b/Documentation/devicetree/bindings/interrupt-controller/google,goldfish-pic.txt deleted file mode 100644 index 35f752706e7d..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/google,goldfish-pic.txt +++ /dev/null @@ -1,30 +0,0 @@ -Android Goldfish PIC - -Android Goldfish programmable interrupt device used by Android -emulator. - -Required properties: - -- compatible : should contain "google,goldfish-pic" -- reg : <registers mapping> -- interrupts : <interrupt mapping> - -Example for mips when used in cascade mode: - - cpuintc { - #interrupt-cells = <0x1>; - #address-cells = <0>; - interrupt-controller; - compatible = "mti,cpu-interrupt-controller"; - }; - - interrupt-controller@1f000000 { - compatible = "google,goldfish-pic"; - reg = <0x1f000000 0x1000>; - - interrupt-controller; - #interrupt-cells = <0x1>; - - interrupt-parent = <&cpuintc>; - interrupts = <0x2>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/google,goldfish-pic.yaml b/Documentation/devicetree/bindings/interrupt-controller/google,goldfish-pic.yaml new file mode 100644 index 000000000000..ac3c3c3ca186 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/google,goldfish-pic.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/google,goldfish-pic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Android Goldfish PIC + +maintainers: + - Miodrag Dinic <miodrag.dinic@mips.com> + +description: + Android Goldfish programmable interrupt device used by Android emulator. + +properties: + compatible: + const: google,goldfish-pic + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 1 + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + +examples: + - | + interrupt-controller@1f000000 { + compatible = "google,goldfish-pic"; + reg = <0x1f000000 0x1000>; + interrupt-controller; + #interrupt-cells = <1>; + interrupts = <2>; + }; + +additionalProperties: false diff --git a/Documentation/devicetree/bindings/interrupt-controller/img,pdc-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/img,pdc-intc.txt deleted file mode 100644 index 5dc2a55ad811..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/img,pdc-intc.txt +++ /dev/null @@ -1,105 +0,0 @@ -* ImgTec Powerdown Controller (PDC) Interrupt Controller Binding - -This binding specifies what properties must be available in the device tree -representation of a PDC IRQ controller. This has a number of input interrupt -lines which can wake the system, and are passed on through output interrupt -lines. - -Required properties: - - - compatible: Specifies the compatibility list for the interrupt controller. - The type shall be <string> and the value shall include "img,pdc-intc". - - - reg: Specifies the base PDC physical address(s) and size(s) of the - addressable register space. The type shall be <prop-encoded-array>. - - - interrupt-controller: The presence of this property identifies the node - as an interrupt controller. No property value shall be defined. - - - #interrupt-cells: Specifies the number of cells needed to encode an - interrupt source. The type shall be a <u32> and the value shall be 2. - - - num-perips: Number of waking peripherals. - - - num-syswakes: Number of SysWake inputs. - - - interrupts: List of interrupt specifiers. The first specifier shall be the - shared SysWake interrupt, and remaining specifies shall be PDC peripheral - interrupts in order. - -* Interrupt Specifier Definition - - Interrupt specifiers consists of 2 cells encoded as follows: - - - <1st-cell>: The interrupt-number that identifies the interrupt source. - 0-7: Peripheral interrupts - 8-15: SysWake interrupts - - - <2nd-cell>: The level-sense information, encoded using the Linux interrupt - flags as follows (only 4 valid for peripheral interrupts): - 0 = none (decided by software) - 1 = low-to-high edge triggered - 2 = high-to-low edge triggered - 3 = both edge triggered - 4 = active-high level-sensitive (required for perip irqs) - 8 = active-low level-sensitive - -* Examples - -Example 1: - - /* - * TZ1090 PDC block - */ - pdc: pdc@02006000 { - // This is an interrupt controller node. - interrupt-controller; - - // Three cells to encode interrupt sources. - #interrupt-cells = <2>; - - // Offset address of 0x02006000 and size of 0x1000. - reg = <0x02006000 0x1000>; - - // Compatible with Meta hardware trigger block. - compatible = "img,pdc-intc"; - - // Three peripherals are connected. - num-perips = <3>; - - // Four SysWakes are connected. - num-syswakes = <4>; - - interrupts = <18 4 /* level */>, /* Syswakes */ - <30 4 /* level */>, /* Peripheral 0 (RTC) */ - <29 4 /* level */>, /* Peripheral 1 (IR) */ - <31 4 /* level */>; /* Peripheral 2 (WDT) */ - }; - -Example 2: - - /* - * An SoC peripheral that is wired through the PDC. - */ - rtc0 { - // The interrupt controller that this device is wired to. - interrupt-parent = <&pdc>; - - // Interrupt source Peripheral 0 - interrupts = <0 /* Peripheral 0 (RTC) */ - 4> /* IRQ_TYPE_LEVEL_HIGH */ - }; - -Example 3: - - /* - * An interrupt generating device that is wired to a SysWake pin. - */ - touchscreen0 { - // The interrupt controller that this device is wired to. - interrupt-parent = <&pdc>; - - // Interrupt source SysWake 0 that is active-low level-sensitive - interrupts = <8 /* SysWake0 */ - 8 /* IRQ_TYPE_LEVEL_LOW */>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/img,pdc-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/img,pdc-intc.yaml new file mode 100644 index 000000000000..99e7a4281595 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/img,pdc-intc.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/img,pdc-intc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ImgTec Powerdown Controller (PDC) Interrupt Controller + +maintainers: + - James Hogan <jhogan@kernel.org> + +description: + ImgTec Powerdown Controller (PDC) Interrupt Controller has a number of input + interrupt lines which can wake the system, and are passed on through output + interrupt lines. + +properties: + compatible: + const: img,pdc-intc + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + description: > + <1st-cell>: The interrupt-number that identifies the interrupt source. + 0-7: Peripheral interrupts + 8-15: SysWake interrupts + + <2nd-cell>: The level-sense information, encoded using the Linux interrupt + flags as follows (only 4 valid for peripheral interrupts): + 0 = none (decided by software) + 1 = low-to-high edge triggered + 2 = high-to-low edge triggered + 3 = both edge triggered + 4 = active-high level-sensitive (required for perip irqs) + 8 = active-low level-sensitive + const: 2 + + num-perips: + description: Number of waking peripherals + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 8 + + num-syswakes: + description: Number of SysWake inputs + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 8 + + interrupts: + description: + First entry is syswake IRQ. Subsequent entries are 1 per peripheral. + minItems: 2 + maxItems: 9 + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + - num-perips + - num-syswakes + - interrupts + +additionalProperties: false + +examples: + - | + interrupt-controller@2006000 { + compatible = "img,pdc-intc"; + reg = <0x02006000 0x1000>; + interrupts = <18 4>, <30 4>, <29 4>, <31 4>; + interrupt-controller; + #interrupt-cells = <2>; + num-perips = <3>; + num-syswakes = <4>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt deleted file mode 100644 index ee2ad36f8df8..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt +++ /dev/null @@ -1,26 +0,0 @@ -J-Core Advanced Interrupt Controller - -Required properties: - -- compatible: Should be "jcore,aic1" for the (obsolete) first-generation aic - with 8 interrupt lines with programmable priorities, or "jcore,aic2" for - the "aic2" core with 64 interrupts. - -- reg: Memory region(s) for configuration. For SMP, there should be one - region per cpu, indexed by the sequential, zero-based hardware cpu - number. - -- interrupt-controller: Identifies the node as an interrupt controller - -- #interrupt-cells: Specifies the number of cells needed to encode an - interrupt source. The value shall be 1. - - -Example: - -aic: interrupt-controller@200 { - compatible = "jcore,aic2"; - reg = < 0x200 0x30 0x500 0x30 >; - interrupt-controller; - #interrupt-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.yaml b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.yaml new file mode 100644 index 000000000000..df8abc24591c --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright 2018 Linaro Ltd. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/jcore,aic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: J-Core Advanced Interrupt Controller + +maintainers: + - Rich Felker <dalias@libc.org> + +properties: + compatible: + enum: + - jcore,aic1 + - jcore,aic2 + + reg: + description: Memory region(s) for configuration. For SMP, there should be one + region per CPU, indexed by the sequential, zero-based hardware CPU number. + + interrupt-controller: true + + '#interrupt-cells': + const: 1 + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + +additionalProperties: false + +examples: + - | + aic: interrupt-controller@200 { + compatible = "jcore,aic2"; + reg = <0x200 0x30>, <0x500 0x30>; + interrupt-controller; + #interrupt-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/lsi,zevio-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/lsi,zevio-intc.txt deleted file mode 100644 index aee38e7c13e7..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/lsi,zevio-intc.txt +++ /dev/null @@ -1,18 +0,0 @@ -TI-NSPIRE interrupt controller - -Required properties: -- compatible: Compatible property value should be "lsi,zevio-intc". - -- reg: Physical base address of the controller and length of memory mapped - region. - -- interrupt-controller : Identifies the node as an interrupt controller - -Example: - -interrupt-controller { - compatible = "lsi,zevio-intc"; - interrupt-controller; - reg = <0xDC000000 0x1000>; - #interrupt-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/interrupt-controller/lsi,zevio-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/lsi,zevio-intc.yaml new file mode 100644 index 000000000000..e66b25f579c3 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/lsi,zevio-intc.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright 2025 Daniel Tang <dt.tangr@gmail.com> +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/lsi,zevio-intc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI-NSPIRE Interrupt Controller + +maintainers: + - Daniel Tang <dt.tangr@gmail.com> + +description: | + TI-NSPIRE interrupt controller + +properties: + compatible: + const: lsi,zevio-intc + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 1 + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + +additionalProperties: false + +examples: + - | + interrupt-controller@dc000000 { + compatible = "lsi,zevio-intc"; + interrupt-controller; + reg = <0xdc000000 0x1000>; + #interrupt-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,ap806-gicp.yaml b/Documentation/devicetree/bindings/interrupt-controller/marvell,ap806-gicp.yaml new file mode 100644 index 000000000000..5faedd95b9a9 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/marvell,ap806-gicp.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/marvell,ap806-gicp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell GICP Controller + +maintainers: + - Thomas Petazzoni <thomas.petazzoni@bootlin.com> + +description: + GICP is a Marvell extension of the GIC that allows to trigger GIC SPI + interrupts by doing a memory transaction. It is used by the ICU + located in the Marvell CP110 to turn wired interrupts inside the CP + into GIC SPI interrupts. + +properties: + compatible: + const: marvell,ap806-gicp + + reg: + maxItems: 1 + + marvell,spi-ranges: + description: Tuples of GIC SPI interrupt ranges available for this GICP + $ref: /schemas/types.yaml#/definitions/uint32-matrix + items: + items: + - description: SPI interrupt base + - description: Number of interrupts in the range + + msi-controller: true + +required: + - compatible + - reg + - msi-controller + - marvell,spi-ranges + +additionalProperties: false + +examples: + - | + msi-controller@3f0040 { + compatible = "marvell,ap806-gicp"; + reg = <0x3f0040 0x10>; + marvell,spi-ranges = <64 64>, <288 64>; + msi-controller; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,ap806-sei.yaml b/Documentation/devicetree/bindings/interrupt-controller/marvell,ap806-sei.yaml new file mode 100644 index 000000000000..e812f9a86307 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/marvell,ap806-sei.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/marvell,ap806-sei.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell SEI (System Error Interrupt) Controller + +maintainers: + - Miquel Raynal <miquel.raynal@bootlin.com> + +description: > + Marvell SEI (System Error Interrupt) controller is an interrupt aggregator. It + receives interrupts from several sources and aggregates them to a single + interrupt line (an SPI) on the parent interrupt controller. + + This interrupt controller can handle up to 64 SEIs, a set comes from the AP + and is wired while a second set comes from the CPs by the mean of MSIs. + +properties: + compatible: + const: marvell,ap806-sei + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + '#interrupt-cells': + const: 1 + + interrupt-controller: true + + msi-controller: true + +required: + - compatible + - reg + - interrupts + - '#interrupt-cells' + - interrupt-controller + - msi-controller + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + interrupt-controller@3f0200 { + compatible = "marvell,ap806-sei"; + reg = <0x3f0200 0x40>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + interrupt-controller; + msi-controller; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,armada-8k-pic.txt b/Documentation/devicetree/bindings/interrupt-controller/marvell,armada-8k-pic.txt deleted file mode 100644 index 86a7b4cd03f5..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/marvell,armada-8k-pic.txt +++ /dev/null @@ -1,25 +0,0 @@ -Marvell Armada 7K/8K PIC Interrupt controller ---------------------------------------------- - -This is the Device Tree binding for the PIC, a secondary interrupt -controller available on the Marvell Armada 7K/8K ARM64 SoCs, and -typically connected to the GIC as the primary interrupt controller. - -Required properties: -- compatible: should be "marvell,armada-8k-pic" -- interrupt-controller: identifies the node as an interrupt controller -- #interrupt-cells: the number of cells to define interrupts on this - controller. Should be 1 -- reg: the register area for the PIC interrupt controller -- interrupts: the interrupt to the primary interrupt controller, - typically the GIC - -Example: - - pic: interrupt-controller@3f0100 { - compatible = "marvell,armada-8k-pic"; - reg = <0x3f0100 0x10>; - #interrupt-cells = <1>; - interrupt-controller; - interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,armada-8k-pic.yaml b/Documentation/devicetree/bindings/interrupt-controller/marvell,armada-8k-pic.yaml new file mode 100644 index 000000000000..5a455f7353db --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/marvell,armada-8k-pic.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/marvell,armada-8k-pic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Armada 7K/8K PIC Interrupt controller + +maintainers: + - Thomas Petazzoni <thomas.petazzoni@bootlin.com> + +description: + The Marvell Armada 7K/8K PIC is a secondary interrupt controller available on + the Marvell Armada 7K/8K ARM64 SoCs, and typically connected to the GIC as the + primary interrupt controller. + +properties: + compatible: + const: marvell,armada-8k-pic + + reg: + maxItems: 1 + + "#interrupt-cells": + const: 1 + + interrupt-controller: true + + interrupts: + maxItems: 1 + description: Interrupt to the primary interrupt controller (GIC). + +required: + - compatible + - reg + - "#interrupt-cells" + - interrupt-controller + - interrupts + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + interrupt-controller@3f0100 { + compatible = "marvell,armada-8k-pic"; + reg = <0x3f0100 0x10>; + #interrupt-cells = <1>; + interrupt-controller; + interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,cp110-icu.yaml b/Documentation/devicetree/bindings/interrupt-controller/marvell,cp110-icu.yaml new file mode 100644 index 000000000000..9d4f06f45372 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/marvell,cp110-icu.yaml @@ -0,0 +1,98 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/marvell,cp110-icu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +maintainers: + - Miquel Raynal <miquel.raynal@bootlin.com> + - Thomas Petazzoni <thomas.petazzoni@bootlin.com> + +title: Marvell ICU Interrupt Controller + +description: + The Marvell ICU (Interrupt Consolidation Unit) controller is responsible for + collecting all wired-interrupt sources in the CP and communicating them to the + GIC in the AP. The unit translates interrupt requests on input wires to MSG + memory mapped transactions to the GIC. These messages access different GIC + memory areas depending on their type (NSR, SR, SEI, REI, etc). + +properties: + compatible: + const: marvell,cp110-icu + + reg: + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + + ranges: true + +patternProperties: + "^interrupt-controller@": + type: object + description: Interrupt group child nodes + additionalProperties: false + + properties: + compatible: + enum: + - marvell,cp110-icu-nsr + - marvell,cp110-icu-sr + - marvell,cp110-icu-sei + - marvell,cp110-icu-rei + + reg: + maxItems: 1 + + '#interrupt-cells': + const: 2 + + interrupt-controller: true + + msi-parent: + maxItems: 1 + description: Phandle to the GICP controller + + required: + - compatible + - reg + - '#interrupt-cells' + - interrupt-controller + - msi-parent + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + interrupt-controller@1e0000 { + compatible = "marvell,cp110-icu"; + reg = <0x1e0000 0x440>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + interrupt-controller@10 { + compatible = "marvell,cp110-icu-nsr"; + reg = <0x10 0x20>; + #interrupt-cells = <2>; + interrupt-controller; + msi-parent = <&gicp>; + }; + + interrupt-controller@50 { + compatible = "marvell,cp110-icu-sei"; + reg = <0x50 0x10>; + #interrupt-cells = <2>; + interrupt-controller; + msi-parent = <&sei>; + }; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,gicp.txt b/Documentation/devicetree/bindings/interrupt-controller/marvell,gicp.txt deleted file mode 100644 index 64a00ceb7da4..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/marvell,gicp.txt +++ /dev/null @@ -1,27 +0,0 @@ -Marvell GICP Controller ------------------------ - -GICP is a Marvell extension of the GIC that allows to trigger GIC SPI -interrupts by doing a memory transaction. It is used by the ICU -located in the Marvell CP110 to turn wired interrupts inside the CP -into GIC SPI interrupts. - -Required properties: - -- compatible: Must be "marvell,ap806-gicp" - -- reg: Must be the address and size of the GICP SPI registers - -- marvell,spi-ranges: tuples of GIC SPI interrupts ranges available - for this GICP - -- msi-controller: indicates that this is an MSI controller - -Example: - -gicp_spi: gicp-spi@3f0040 { - compatible = "marvell,ap806-gicp"; - reg = <0x3f0040 0x10>; - marvell,spi-ranges = <64 64>, <288 64>; - msi-controller; -}; diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,icu.txt b/Documentation/devicetree/bindings/interrupt-controller/marvell,icu.txt deleted file mode 100644 index 1c94a57a661e..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/marvell,icu.txt +++ /dev/null @@ -1,112 +0,0 @@ -Marvell ICU Interrupt Controller --------------------------------- - -The Marvell ICU (Interrupt Consolidation Unit) controller is -responsible for collecting all wired-interrupt sources in the CP and -communicating them to the GIC in the AP, the unit translates interrupt -requests on input wires to MSG memory mapped transactions to the GIC. -These messages will access a different GIC memory area depending on -their type (NSR, SR, SEI, REI, etc). - -Required properties: - -- compatible: Should be "marvell,cp110-icu" - -- reg: Should contain ICU registers location and length. - -Subnodes: Each group of interrupt is declared as a subnode of the ICU, -with their own compatible. - -Required properties for the icu_nsr/icu_sei subnodes: - -- compatible: Should be one of: - * "marvell,cp110-icu-nsr" - * "marvell,cp110-icu-sr" - * "marvell,cp110-icu-sei" - * "marvell,cp110-icu-rei" - -- #interrupt-cells: Specifies the number of cells needed to encode an - interrupt source. The value shall be 2. - - The 1st cell is the index of the interrupt in the ICU unit. - - The 2nd cell is the type of the interrupt. See arm,gic.txt for - details. - -- interrupt-controller: Identifies the node as an interrupt - controller. - -- msi-parent: Should point to the GICP controller, the GIC extension - that allows to trigger interrupts using MSG memory mapped - transactions. - -Note: each 'interrupts' property referring to any 'icu_xxx' node shall - have a different number within [0:206]. - -Example: - -icu: interrupt-controller@1e0000 { - compatible = "marvell,cp110-icu"; - reg = <0x1e0000 0x440>; - - CP110_LABEL(icu_nsr): interrupt-controller@10 { - compatible = "marvell,cp110-icu-nsr"; - reg = <0x10 0x20>; - #interrupt-cells = <2>; - interrupt-controller; - msi-parent = <&gicp>; - }; - - CP110_LABEL(icu_sei): interrupt-controller@50 { - compatible = "marvell,cp110-icu-sei"; - reg = <0x50 0x10>; - #interrupt-cells = <2>; - interrupt-controller; - msi-parent = <&sei>; - }; -}; - -node1 { - interrupt-parent = <&icu_nsr>; - interrupts = <106 IRQ_TYPE_LEVEL_HIGH>; -}; - -node2 { - interrupt-parent = <&icu_sei>; - interrupts = <107 IRQ_TYPE_LEVEL_HIGH>; -}; - -/* Would not work with the above nodes */ -node3 { - interrupt-parent = <&icu_nsr>; - interrupts = <107 IRQ_TYPE_LEVEL_HIGH>; -}; - -The legacy bindings were different in this way: - -- #interrupt-cells: The value was 3. - The 1st cell was the group type of the ICU interrupt. Possible - group types were: - ICU_GRP_NSR (0x0) : Shared peripheral interrupt, non-secure - ICU_GRP_SR (0x1) : Shared peripheral interrupt, secure - ICU_GRP_SEI (0x4) : System error interrupt - ICU_GRP_REI (0x5) : RAM error interrupt - The 2nd cell was the index of the interrupt in the ICU unit. - The 3rd cell was the type of the interrupt. See arm,gic.txt for - details. - -Example: - -icu: interrupt-controller@1e0000 { - compatible = "marvell,cp110-icu"; - reg = <0x1e0000 0x440>; - - #interrupt-cells = <3>; - interrupt-controller; - msi-parent = <&gicp>; -}; - -node1 { - interrupt-parent = <&icu>; - interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>; -}; diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,odmi-controller.txt b/Documentation/devicetree/bindings/interrupt-controller/marvell,odmi-controller.txt deleted file mode 100644 index 0ebfc952cb34..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/marvell,odmi-controller.txt +++ /dev/null @@ -1,42 +0,0 @@ - -* Marvell ODMI for MSI support - -Some Marvell SoCs have an On-Die Message Interrupt (ODMI) controller -which can be used by on-board peripheral for MSI interrupts. - -Required properties: - -- compatible : The value here should contain: - - "marvell,ap806-odmi-controller", "marvell,odmi-controller". - -- interrupt,controller : Identifies the node as an interrupt controller. - -- msi-controller : Identifies the node as an MSI controller. - -- marvell,odmi-frames : Number of ODMI frames available. Each frame - provides a number of events. - -- reg : List of register definitions, one for each - ODMI frame. - -- marvell,spi-base : List of GIC base SPI interrupts, one for each - ODMI frame. Those SPI interrupts are 0-based, - i.e marvell,spi-base = <128> will use SPI #96. - See Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml - for details about the GIC Device Tree binding. - -Example: - - odmi: odmi@300000 { - compatible = "marvell,ap806-odmi-controller", - "marvell,odmi-controller"; - interrupt-controller; - msi-controller; - marvell,odmi-frames = <4>; - reg = <0x300000 0x4000>, - <0x304000 0x4000>, - <0x308000 0x4000>, - <0x30C000 0x4000>; - marvell,spi-base = <128>, <136>, <144>, <152>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,odmi-controller.yaml b/Documentation/devicetree/bindings/interrupt-controller/marvell,odmi-controller.yaml new file mode 100644 index 000000000000..9ec1ed4a5155 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/marvell,odmi-controller.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/marvell,odmi-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell ODMI controller + +maintainers: + - Thomas Petazzoni <thomas.petazzoni@free-electrons.com> + +description: + Some Marvell SoCs have an On-Die Message Interrupt (ODMI) controller which can + be used by on-board peripherals for MSI interrupts. + +properties: + compatible: + const: marvell,odmi-controller + + reg: + description: List of register definitions, one for each ODMI frame. + + msi-controller: true + + marvell,odmi-frames: + description: Number of ODMI frames available. Each frame provides a number of events. + $ref: /schemas/types.yaml#/definitions/uint32 + + marvell,spi-base: + description: > + List of GIC base SPI interrupts, one for each ODMI frame. Those SPI + interrupts are 0-based, i.e. marvell,spi-base = <128> will use SPI #96. + See Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml + for details. + $ref: /schemas/types.yaml#/definitions/uint32-array + +required: + - compatible + - reg + - msi-controller + - marvell,odmi-frames + - marvell,spi-base + +additionalProperties: false + +examples: + - | + msi-controller@300000 { + compatible = "marvell,odmi-controller"; + msi-controller; + marvell,odmi-frames = <4>; + reg = <0x300000 0x4000>, <0x304000 0x4000>, <0x308000 0x4000>, <0x30C000 0x4000>; + marvell,spi-base = <128>, <136>, <144>, <152>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,orion-bridge-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/marvell,orion-bridge-intc.yaml new file mode 100644 index 000000000000..e1310ec65382 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/marvell,orion-bridge-intc.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +--- +$id: http://devicetree.org/schemas/interrupt-controller/marvell,orion-bridge-intc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Orion SoC Bridge Interrupt Controller + +maintainers: + - Andrew Lunn <andrew@lunn.ch> + - Gregory Clement <gregory.clement@bootlin.com> + +properties: + compatible: + const: marvell,orion-bridge-intc + + reg: + minItems: 1 + maxItems: 2 + + interrupt-controller: true + + '#interrupt-cells': + const: 1 + + interrupts: + description: Bridge interrupt of the main interrupt controller + + marvell,#interrupts: + description: Number of interrupts provided by bridge interrupt controller. + $ref: /schemas/types.yaml#/definitions/uint32 + default: 32 + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + - interrupts + +additionalProperties: false + +examples: + - | + interrupt-controller@20110 { + compatible = "marvell,orion-bridge-intc"; + reg = <0x20110 0x8>; + interrupt-controller; + #interrupt-cells = <1>; + interrupts = <0>; + /* Dove bridge provides 5 interrupts */ + marvell,#interrupts = <5>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,orion-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/marvell,orion-intc.txt deleted file mode 100644 index 2c11ac76fac9..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/marvell,orion-intc.txt +++ /dev/null @@ -1,48 +0,0 @@ -Marvell Orion SoC interrupt controllers - -* Main interrupt controller - -Required properties: -- compatible: shall be "marvell,orion-intc" -- reg: base address(es) of interrupt registers starting with CAUSE register -- interrupt-controller: identifies the node as an interrupt controller -- #interrupt-cells: number of cells to encode an interrupt source, shall be 1 - -The interrupt sources map to the corresponding bits in the interrupt -registers, i.e. -- 0 maps to bit 0 of first base address, -- 1 maps to bit 1 of first base address, -- 32 maps to bit 0 of second base address, and so on. - -Example: - intc: interrupt-controller { - compatible = "marvell,orion-intc"; - interrupt-controller; - #interrupt-cells = <1>; - /* Dove has 64 first level interrupts */ - reg = <0x20200 0x10>, <0x20210 0x10>; - }; - -* Bridge interrupt controller - -Required properties: -- compatible: shall be "marvell,orion-bridge-intc" -- reg: base address of bridge interrupt registers starting with CAUSE register -- interrupts: bridge interrupt of the main interrupt controller -- interrupt-controller: identifies the node as an interrupt controller -- #interrupt-cells: number of cells to encode an interrupt source, shall be 1 - -Optional properties: -- marvell,#interrupts: number of interrupts provided by bridge interrupt - controller, defaults to 32 if not set - -Example: - bridge_intc: interrupt-controller { - compatible = "marvell,orion-bridge-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x20110 0x8>; - interrupts = <0>; - /* Dove bridge provides 5 interrupts */ - marvell,#interrupts = <5>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,sei.txt b/Documentation/devicetree/bindings/interrupt-controller/marvell,sei.txt deleted file mode 100644 index 0beafed502f5..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/marvell,sei.txt +++ /dev/null @@ -1,36 +0,0 @@ -Marvell SEI (System Error Interrupt) Controller ------------------------------------------------ - -Marvell SEI (System Error Interrupt) controller is an interrupt -aggregator. It receives interrupts from several sources and aggregates -them to a single interrupt line (an SPI) on the parent interrupt -controller. - -This interrupt controller can handle up to 64 SEIs, a set comes from the -AP and is wired while a second set comes from the CPs by the mean of -MSIs. - -Required properties: - -- compatible: should be one of: - * "marvell,ap806-sei" -- reg: SEI registers location and length. -- interrupts: identifies the parent IRQ that will be triggered. -- #interrupt-cells: number of cells to define an SEI wired interrupt - coming from the AP, should be 1. The cell is the IRQ - number. -- interrupt-controller: identifies the node as an interrupt controller - for AP interrupts. -- msi-controller: identifies the node as an MSI controller for the CPs - interrupts. - -Example: - - sei: interrupt-controller@3f0200 { - compatible = "marvell,ap806-sei"; - reg = <0x3f0200 0x40>; - interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; - #interrupt-cells = <1>; - interrupt-controller; - msi-controller; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/microchip,pic32-evic.txt b/Documentation/devicetree/bindings/interrupt-controller/microchip,pic32-evic.txt deleted file mode 100644 index c3a1b37c4c35..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/microchip,pic32-evic.txt +++ /dev/null @@ -1,67 +0,0 @@ -Microchip PIC32 Interrupt Controller -==================================== - -The Microchip PIC32 contains an Enhanced Vectored Interrupt Controller (EVIC). -It handles all internal and external interrupts. This controller exists outside -of the CPU and is the arbitrator of all interrupts (including interrupts from -the CPU itself) before they are presented to the CPU. - -External interrupts have a software configurable edge polarity. Non external -interrupts have a type and polarity that is determined by the source of the -interrupt. - -Required properties -------------------- - -- compatible: Should be "microchip,pic32mzda-evic" -- reg: Specifies physical base address and size of register range. -- interrupt-controller: Identifies the node as an interrupt controller. -- #interrupt cells: Specifies the number of cells used to encode an interrupt - source connected to this controller. The value shall be 2 and interrupt - descriptor shall have the following format: - - <hw_irq irq_type> - - hw_irq - represents the hardware interrupt number as in the data sheet. - irq_type - is used to describe the type and polarity of an interrupt. For - internal interrupts use IRQ_TYPE_EDGE_RISING for non persistent interrupts and - IRQ_TYPE_LEVEL_HIGH for persistent interrupts. For external interrupts use - IRQ_TYPE_EDGE_RISING or IRQ_TYPE_EDGE_FALLING to select the desired polarity. - -Optional properties -------------------- -- microchip,external-irqs: u32 array of external interrupts with software - polarity configuration. This array corresponds to the bits in the INTCON - SFR. - -Example -------- - -evic: interrupt-controller@1f810000 { - compatible = "microchip,pic32mzda-evic"; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1f810000 0x1000>; - microchip,external-irqs = <3 8 13 18 23>; -}; - -Each device/peripheral must request its interrupt line with the associated type -and polarity. - -Internal interrupt DTS snippet ------------------------------- - -device@1f800000 { - ... - interrupts = <113 IRQ_TYPE_LEVEL_HIGH>; - ... -}; - -External interrupt DTS snippet ------------------------------- - -device@1f800000 { - ... - interrupts = <3 IRQ_TYPE_EDGE_RISING>; - ... -}; diff --git a/Documentation/devicetree/bindings/interrupt-controller/microchip,pic32mzda-evic.yaml b/Documentation/devicetree/bindings/interrupt-controller/microchip,pic32mzda-evic.yaml new file mode 100644 index 000000000000..74bfc42693f0 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/microchip,pic32mzda-evic.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/microchip,pic32mzda-evic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PIC32 EVIC Interrupt Controller + +maintainers: + - Cristian Birsan <cristian.birsan@microchip.com> + +description: > + The Microchip PIC32 contains an Enhanced Vectored Interrupt Controller (EVIC). + It handles all internal and external interrupts. This controller exists + outside of the CPU and is the arbitrator of all interrupts (including + interrupts from the CPU itself) before they are presented to the CPU. + + External interrupts have a software configurable edge polarity. Non external + interrupts have a type and polarity that is determined by the source of the + interrupt. + +properties: + compatible: + items: + - const: microchip,pic32mzda-evic + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + interrupts: + maxItems: 1 + + microchip,external-irqs: + description: + External interrupts with software polarity configuration corresponding to + the INTCON SFR bits. + $ref: /schemas/types.yaml#/definitions/uint32-array + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + +additionalProperties: false + +examples: + - | + interrupt-controller@1f810000 { + compatible = "microchip,pic32mzda-evic"; + reg = <0x1f810000 0x1000>; + interrupt-controller; + #interrupt-cells = <2>; + microchip,external-irqs = <3 8 13 18 23>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.txt b/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.txt deleted file mode 100644 index 2ff356640100..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.txt +++ /dev/null @@ -1,41 +0,0 @@ -NVIDIA Legacy Interrupt Controller - -All Tegra SoCs contain a legacy interrupt controller that routes -interrupts to the GIC, and also serves as a wakeup source. It is also -referred to as "ictlr", hence the name of the binding. - -The HW block exposes a number of interrupt controllers, each -implementing a set of 32 interrupts. - -Required properties: - -- compatible : should be: "nvidia,tegra<chip>-ictlr". The LIC on - subsequent SoCs remained backwards-compatible with Tegra30, so on - Tegra generations later than Tegra30 the compatible value should - include "nvidia,tegra30-ictlr". -- reg : Specifies base physical address and size of the registers. - Each controller must be described separately (Tegra20 has 4 of them, - whereas Tegra30 and later have 5). -- interrupt-controller : Identifies the node as an interrupt controller. -- #interrupt-cells : Specifies the number of cells needed to encode an - interrupt source. The value must be 3. - -Notes: - -- Because this HW ultimately routes interrupts to the GIC, the - interrupt specifier must be that of the GIC. -- Only SPIs can use the ictlr as an interrupt parent. SGIs and PPIs - are explicitly forbidden. - -Example: - - ictlr: interrupt-controller@60004000 { - compatible = "nvidia,tegra20-ictlr", "nvidia,tegra-ictlr"; - reg = <0x60004000 64>, - <0x60004100 64>, - <0x60004200 64>, - <0x60004300 64>; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&intc>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.yaml b/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.yaml new file mode 100644 index 000000000000..074a873880e5 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/nvidia,tegra20-ictlr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra20 Legacy Interrupt Controller + +maintainers: + - Thierry Reding <treding@nvidia.com> + - Jonathan Hunter <jonathanh@nvidia.com> + +description: > + All Tegra SoCs contain a legacy interrupt controller that routes interrupts to + the GIC, and also serves as a wakeup source. It is also referred to as + "ictlr", hence the name of the binding. + + The HW block exposes a number of interrupt controllers, each implementing a + set of 32 interrupts. + + Notes: + - Because this HW ultimately routes interrupts to the GIC, the + interrupt specifier must be that of the GIC. + - Only SPIs can use the ictlr as an interrupt parent. SGIs and PPIs + are explicitly forbidden. + +properties: + compatible: + oneOf: + - items: + - enum: + - nvidia,tegra114-ictlr + - nvidia,tegra124-ictlr + - const: nvidia,tegra30-ictlr + - enum: + - nvidia,tegra20-ictlr + - nvidia,tegra30-ictlr + + reg: + description: Each entry is a block of 32 interrupts + minItems: 4 + maxItems: 5 + + interrupt-controller: true + + '#interrupt-cells': + const: 3 + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + +additionalProperties: false + +allOf: + - if: + properties: + compatible: + contains: + const: nvidia,tegra20-ictlr + then: + properties: + reg: + maxItems: 4 + else: + properties: + reg: + minItems: 5 + +examples: + - | + interrupt-controller@60004000 { + compatible = "nvidia,tegra20-ictlr"; + reg = <0x60004000 64>, + <0x60004100 64>, + <0x60004200 64>, + <0x60004300 64>; + interrupt-controller; + #interrupt-cells = <3>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/nxp,lpc3220-mic.txt b/Documentation/devicetree/bindings/interrupt-controller/nxp,lpc3220-mic.txt deleted file mode 100644 index 0bfb3ba55f4c..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/nxp,lpc3220-mic.txt +++ /dev/null @@ -1,58 +0,0 @@ -* NXP LPC32xx MIC, SIC1 and SIC2 Interrupt Controllers - -Required properties: -- compatible: "nxp,lpc3220-mic" or "nxp,lpc3220-sic". -- reg: should contain IC registers location and length. -- interrupt-controller: identifies the node as an interrupt controller. -- #interrupt-cells: the number of cells to define an interrupt, should be 2. - The first cell is the IRQ number, the second cell is used to specify - one of the supported IRQ types: - IRQ_TYPE_EDGE_RISING = low-to-high edge triggered, - IRQ_TYPE_EDGE_FALLING = high-to-low edge triggered, - IRQ_TYPE_LEVEL_HIGH = active high level-sensitive, - IRQ_TYPE_LEVEL_LOW = active low level-sensitive. - Reset value is IRQ_TYPE_LEVEL_LOW. - -Optional properties: -- interrupts: empty for MIC interrupt controller, cascaded MIC - hardware interrupts for SIC1 and SIC2 - -Examples: - - /* LPC32xx MIC, SIC1 and SIC2 interrupt controllers */ - mic: interrupt-controller@40008000 { - compatible = "nxp,lpc3220-mic"; - reg = <0x40008000 0x4000>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - sic1: interrupt-controller@4000c000 { - compatible = "nxp,lpc3220-sic"; - reg = <0x4000c000 0x4000>; - interrupt-controller; - #interrupt-cells = <2>; - - interrupt-parent = <&mic>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>, - <30 IRQ_TYPE_LEVEL_LOW>; - }; - - sic2: interrupt-controller@40010000 { - compatible = "nxp,lpc3220-sic"; - reg = <0x40010000 0x4000>; - interrupt-controller; - #interrupt-cells = <2>; - - interrupt-parent = <&mic>; - interrupts = <1 IRQ_TYPE_LEVEL_LOW>, - <31 IRQ_TYPE_LEVEL_LOW>; - }; - - /* ADC */ - adc@40048000 { - compatible = "nxp,lpc3220-adc"; - reg = <0x40048000 0x1000>; - interrupt-parent = <&sic1>; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/nxp,lpc3220-mic.yaml b/Documentation/devicetree/bindings/interrupt-controller/nxp,lpc3220-mic.yaml new file mode 100644 index 000000000000..724c869e3c40 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/nxp,lpc3220-mic.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/nxp,lpc3220-mic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP LPC32xx MIC, SIC1 and SIC2 Interrupt Controllers + +maintainers: + - Vladimir Zapolskiy <vz@mleia.com> + +properties: + compatible: + enum: + - nxp,lpc3220-mic + - nxp,lpc3220-sic + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + interrupts: + items: + - description: Regular interrupt request + - description: Fast interrupt request + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + +allOf: + - if: + properties: + compatible: + contains: + const: nxp,lpc3220-sic + then: + required: + - interrupts + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + mic: interrupt-controller@40008000 { + compatible = "nxp,lpc3220-mic"; + reg = <0x40008000 0x4000>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + interrupt-controller@4000c000 { + compatible = "nxp,lpc3220-sic"; + reg = <0x4000c000 0x4000>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&mic>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>, + <30 IRQ_TYPE_LEVEL_LOW>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/open-pic.txt b/Documentation/devicetree/bindings/interrupt-controller/open-pic.txt deleted file mode 100644 index ccbbfdc53c72..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/open-pic.txt +++ /dev/null @@ -1,97 +0,0 @@ -* Open PIC Binding - -This binding specifies what properties must be available in the device tree -representation of an Open PIC compliant interrupt controller. This binding is -based on the binding defined for Open PIC in [1] and is a superset of that -binding. - -Required properties: - - NOTE: Many of these descriptions were paraphrased here from [1] to aid - readability. - - - compatible: Specifies the compatibility list for the PIC. The type - shall be <string> and the value shall include "open-pic". - - - reg: Specifies the base physical address(s) and size(s) of this - PIC's addressable register space. The type shall be <prop-encoded-array>. - - - interrupt-controller: The presence of this property identifies the node - as an Open PIC. No property value shall be defined. - - - #interrupt-cells: Specifies the number of cells needed to encode an - interrupt source. The type shall be a <u32> and the value shall be 2. - - - #address-cells: Specifies the number of cells needed to encode an - address. The type shall be <u32> and the value shall be 0. As such, - 'interrupt-map' nodes do not have to specify a parent unit address. - -Optional properties: - - - pic-no-reset: The presence of this property indicates that the PIC - shall not be reset during runtime initialization. No property value shall - be defined. The presence of this property also mandates that any - initialization related to interrupt sources shall be limited to sources - explicitly referenced in the device tree. - -* Interrupt Specifier Definition - - Interrupt specifiers consists of 2 cells encoded as - follows: - - - <1st-cell>: The interrupt-number that identifies the interrupt source. - - - <2nd-cell>: The level-sense information, encoded as follows: - 0 = low-to-high edge triggered - 1 = active low level-sensitive - 2 = active high level-sensitive - 3 = high-to-low edge triggered - -* Examples - -Example 1: - - /* - * An Open PIC interrupt controller - */ - mpic: pic@40000 { - // This is an interrupt controller node. - interrupt-controller; - - // No address cells so that 'interrupt-map' nodes which reference - // this Open PIC node do not need a parent address specifier. - #address-cells = <0>; - - // Two cells to encode interrupt sources. - #interrupt-cells = <2>; - - // Offset address of 0x40000 and size of 0x40000. - reg = <0x40000 0x40000>; - - // Compatible with Open PIC. - compatible = "open-pic"; - - // The PIC shall not be reset. - pic-no-reset; - }; - -Example 2: - - /* - * An interrupt generating device that is wired to an Open PIC. - */ - serial0: serial@4500 { - // Interrupt source '42' that is active high level-sensitive. - // Note that there are only two cells as specified in the interrupt - // parent's '#interrupt-cells' property. - interrupts = <42 2>; - - // The interrupt controller that this device is wired to. - interrupt-parent = <&mpic>; - }; - -* References - -[1] Devicetree Specification - (https://www.devicetree.org/specifications/) - diff --git a/Documentation/devicetree/bindings/interrupt-controller/opencores,or1k-pic.txt b/Documentation/devicetree/bindings/interrupt-controller/opencores,or1k-pic.txt deleted file mode 100644 index 55c04faa3f3f..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/opencores,or1k-pic.txt +++ /dev/null @@ -1,23 +0,0 @@ -OpenRISC 1000 Programmable Interrupt Controller - -Required properties: - -- compatible : should be "opencores,or1k-pic-level" for variants with - level triggered interrupt lines, "opencores,or1k-pic-edge" for variants with - edge triggered interrupt lines or "opencores,or1200-pic" for machines - with the non-spec compliant or1200 type implementation. - - "opencores,or1k-pic" is also provided as an alias to "opencores,or1200-pic", - but this is only for backwards compatibility. - -- interrupt-controller : Identifies the node as an interrupt controller -- #interrupt-cells : Specifies the number of cells needed to encode an - interrupt source. The value shall be 1. - -Example: - -intc: interrupt-controller { - compatible = "opencores,or1k-pic-level"; - interrupt-controller; - #interrupt-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/interrupt-controller/opencores,or1k-pic.yaml b/Documentation/devicetree/bindings/interrupt-controller/opencores,or1k-pic.yaml new file mode 100644 index 000000000000..995b68c3aed4 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/opencores,or1k-pic.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/opencores,or1k-pic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: OpenRISC 1000 Programmable Interrupt Controller + +maintainers: + - Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> + +properties: + compatible: + enum: + - opencores,or1k-pic-level + - opencores,or1k-pic-edge + - opencores,or1200-pic + - opencores,or1k-pic + + interrupt-controller: true + + '#interrupt-cells': + const: 1 + +required: + - compatible + - interrupt-controller + - '#interrupt-cells' + +additionalProperties: false + +examples: + - | + interrupt-controller { + compatible = "opencores,or1k-pic-level"; + interrupt-controller; + #interrupt-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt b/Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt deleted file mode 100644 index caec07cc7149..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt +++ /dev/null @@ -1,22 +0,0 @@ -Open Multi-Processor Interrupt Controller - -Required properties: - -- compatible : This should be "openrisc,ompic" -- reg : Specifies base physical address and size of the register space. The - size is based on the number of cores the controller has been configured - to handle, this should be set to 8 bytes per cpu core. -- interrupt-controller : Identifies the node as an interrupt controller. -- #interrupt-cells : This should be set to 0 as this will not be an irq - parent. -- interrupts : Specifies the interrupt line to which the ompic is wired. - -Example: - -ompic: interrupt-controller@98000000 { - compatible = "openrisc,ompic"; - reg = <0x98000000 16>; - interrupt-controller; - #interrupt-cells = <0>; - interrupts = <1>; -}; diff --git a/Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.yaml b/Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.yaml new file mode 100644 index 000000000000..4efbfba3aa6b --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/openrisc,ompic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Open Multi-Processor Interrupt Controller + +maintainers: + - Stafford Horne <shorne@gmail.com> + +properties: + compatible: + items: + - const: openrisc,ompic + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 0 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + - interrupts + +additionalProperties: false + +examples: + - | + interrupt-controller@98000000 { + compatible = "openrisc,ompic"; + reg = <0x98000000 16>; + interrupt-controller; + #interrupt-cells = <0>; + interrupts = <1>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/qca,ar7100-cpu-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/qca,ar7100-cpu-intc.yaml new file mode 100644 index 000000000000..ab32a91af4c4 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/qca,ar7100-cpu-intc.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/qca,ar7100-cpu-intc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Atheros ath79 CPU interrupt controller + +maintainers: + - Alban Bedel <albeu@free.fr> + +description: + On most SoC the IRQ controller need to flush the DDR FIFO before running the + interrupt handler of some devices. This is configured using the + qca,ddr-wb-channels and qca,ddr-wb-channel-interrupts properties. + +properties: + compatible: + oneOf: + - items: + - const: qca,ar9132-cpu-intc + - const: qca,ar7100-cpu-intc + - items: + - const: qca,ar7100-cpu-intc + + interrupt-controller: true + + '#interrupt-cells': + const: 1 + + qca,ddr-wb-channel-interrupts: + description: List of interrupts needing a write buffer flush + $ref: /schemas/types.yaml#/definitions/uint32-array + + qca,ddr-wb-channels: + description: List of write buffer channel phandles for each interrupt + $ref: /schemas/types.yaml#/definitions/phandle-array + +required: + - compatible + - interrupt-controller + - '#interrupt-cells' + +additionalProperties: false + +examples: + - | + interrupt-controller { + compatible = "qca,ar9132-cpu-intc", "qca,ar7100-cpu-intc"; + + interrupt-controller; + #interrupt-cells = <1>; + + qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>; + qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>, + <&ddr_ctrl 0>, <&ddr_ctrl 1>; + }; + + ddr_ctrl: memory-controller { + #qca,ddr-wb-channel-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/qca,ar7100-misc-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/qca,ar7100-misc-intc.yaml new file mode 100644 index 000000000000..ae813189f5ab --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/qca,ar7100-misc-intc.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/qca,ar7100-misc-intc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Atheros AR7xxx/AR9XXX MISC interrupt controller + +maintainers: + - Alban Bedel <albeu@free.fr> + - Alexander Couzens <lynxis@fe80.eu> + +description: + The Qualcomm Atheros AR7xxx/AR9XXX MISC interrupt controller is a secondary + controller for lower priority interrupts. + +properties: + compatible: + oneOf: + - items: + - const: qca,ar9132-misc-intc + - const: qca,ar7100-misc-intc + - const: qca,ar7240-misc-intc + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 1 + +additionalProperties: false + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - "#interrupt-cells" + +examples: + - | + interrupt-controller@18060010 { + compatible = "qca,ar9132-misc-intc", "qca,ar7100-misc-intc"; + reg = <0x18060010 0x4>; + interrupts = <6>; + interrupt-controller; + #interrupt-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/qca,ath79-cpu-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/qca,ath79-cpu-intc.txt deleted file mode 100644 index aabce7810d29..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/qca,ath79-cpu-intc.txt +++ /dev/null @@ -1,44 +0,0 @@ -Binding for Qualcomm Atheros AR7xxx/AR9XXX CPU interrupt controller - -On most SoC the IRQ controller need to flush the DDR FIFO before running -the interrupt handler of some devices. This is configured using the -qca,ddr-wb-channels and qca,ddr-wb-channel-interrupts properties. - -Required Properties: - -- compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-cpu-intc" - as fallback -- interrupt-controller : Identifies the node as an interrupt controller -- #interrupt-cells : Specifies the number of cells needed to encode interrupt - source, should be 1 for intc - -Please refer to interrupts.txt in this directory for details of the common -Interrupt Controllers bindings used by client devices. - -Optional Properties: - -- qca,ddr-wb-channel-interrupts: List of the interrupts needing a write - buffer flush -- qca,ddr-wb-channels: List of phandles to the write buffer channels for - each interrupt. If qca,ddr-wb-channel-interrupts is not present the interrupt - default to the entry's index. - -Example: - - interrupt-controller { - compatible = "qca,ar9132-cpu-intc", "qca,ar7100-cpu-intc"; - - interrupt-controller; - #interrupt-cells = <1>; - - qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>; - qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>, - <&ddr_ctrl 0>, <&ddr_ctrl 1>; - }; - - ... - - ddr_ctrl: memory-controller@18000000 { - ... - #qca,ddr-wb-channel-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/qca,ath79-misc-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/qca,ath79-misc-intc.txt deleted file mode 100644 index ad70006c1848..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/qca,ath79-misc-intc.txt +++ /dev/null @@ -1,45 +0,0 @@ -Binding for Qualcomm Atheros AR7xxx/AR9XXX MISC interrupt controller - -The MISC interrupt controller is a secondary controller for lower priority -interrupt. - -Required Properties: -- compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-misc-intc" or - "qca,<soctype>-cpu-intc", "qca,ar7240-misc-intc" -- reg: Base address and size of the controllers memory area -- interrupts: Interrupt specifier for the controllers interrupt. -- interrupt-controller : Identifies the node as an interrupt controller -- #interrupt-cells : Specifies the number of cells needed to encode interrupt - source, should be 1 - -Compatible fallback depends on the SoC. Use ar7100 for ar71xx and ar913x, -use ar7240 for all other SoCs. - -Please refer to interrupts.txt in this directory for details of the common -Interrupt Controllers bindings used by client devices. - -Example: - - interrupt-controller@18060010 { - compatible = "qca,ar9132-misc-intc", "qca,ar7100-misc-intc"; - reg = <0x18060010 0x4>; - - interrupt-parent = <&cpuintc>; - interrupts = <6>; - - interrupt-controller; - #interrupt-cells = <1>; - }; - -Another example: - - interrupt-controller@18060010 { - compatible = "qca,ar9331-misc-intc", qca,ar7240-misc-intc"; - reg = <0x18060010 0x4>; - - interrupt-parent = <&cpuintc>; - interrupts = <6>; - - interrupt-controller; - #interrupt-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml index d7ef4f1323a7..3f99c8645767 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/interrupt-controller/renesas,rzv2h-icu.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Renesas RZ/V2H(P) Interrupt Control Unit +title: Renesas RZ/{G3E,V2H(P)} Interrupt Control Unit maintainers: - Fabrizio Castro <fabrizio.castro.jz@renesas.com> @@ -20,7 +20,9 @@ description: properties: compatible: - const: renesas,r9a09g057-icu # RZ/V2H(P) + enum: + - renesas,r9a09g047-icu # RZ/G3E + - renesas,r9a09g057-icu # RZ/V2H(P) '#interrupt-cells': description: The first cell is the SPI number of the NMI or the diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml index 190a6499c932..bef00521d5da 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml @@ -91,6 +91,14 @@ properties: Firmware must configure interrupt delegation registers based on interrupt delegation list. + riscv,hart-indexes: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 16384 + description: + A list of hart indexes that APLIC should use to address each hart + that is mentioned in the "interrupts-extended" + dependencies: riscv,delegation: [ "riscv,children" ] diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml index 3dfe425909d1..ffc4768bad06 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml @@ -70,6 +70,7 @@ properties: - sophgo,cv1812h-plic - sophgo,sg2002-plic - sophgo,sg2042-plic + - sophgo,sg2044-plic - thead,th1520-plic - const: thead,c900-plic - items: diff --git a/Documentation/devicetree/bindings/interrupt-controller/snps,arc700-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/snps,arc700-intc.txt deleted file mode 100644 index 9a5d562435ea..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/snps,arc700-intc.txt +++ /dev/null @@ -1,24 +0,0 @@ -* ARC700 incore Interrupt Controller - - The core interrupt controller provides 32 prioritised interrupts (2 levels) - to ARC700 core. - -Properties: - -- compatible: "snps,arc700-intc" -- interrupt-controller: This is an interrupt controller. -- #interrupt-cells: Must be <1>. - - Single Cell "interrupts" property of a device specifies the IRQ number - between 0 to 31 - - intc accessed via the special ARC AUX register interface, hence "reg" property - is not specified. - -Example: - - intc: interrupt-controller { - compatible = "snps,arc700-intc"; - interrupt-controller; - #interrupt-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/snps,arc700-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/snps,arc700-intc.yaml new file mode 100644 index 000000000000..000a734d997c --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/snps,arc700-intc.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/snps,arc700-intc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARC700 incore Interrupt Controller + +maintainers: + - Vineet Gupta <vgupta@kernel.org> + +description: > + The core interrupt controller provides 32 prioritized interrupts (2 levels) + to ARC700 core. + + intc accessed via the special ARC AUX register interface, hence "reg" property + is not specified. + +properties: + compatible: + const: snps,arc700-intc + + interrupt-controller: true + + '#interrupt-cells': + description: An interrupt number 0-31 + const: 1 + +required: + - compatible + - interrupt-controller + - '#interrupt-cells' + +additionalProperties: false + +examples: + - | + interrupt-controller { + compatible = "snps,arc700-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/snps,archs-idu-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/snps,archs-idu-intc.txt deleted file mode 100644 index a5c1db95b3ec..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/snps,archs-idu-intc.txt +++ /dev/null @@ -1,46 +0,0 @@ -* ARC-HS Interrupt Distribution Unit - - This optional 2nd level interrupt controller can be used in SMP configurations - for dynamic IRQ routing, load balancing of common/external IRQs towards core - intc. - -Properties: - -- compatible: "snps,archs-idu-intc" -- interrupt-controller: This is an interrupt controller. -- #interrupt-cells: Must be <1> or <2>. - - Value of the first cell specifies the "common" IRQ from peripheral to IDU. - Number N of the particular interrupt line of IDU corresponds to the line N+24 - of the core interrupt controller. - - The (optional) second cell specifies any of the following flags: - - bits[3:0] trigger type and level flags - 1 = low-to-high edge triggered - 2 = NOT SUPPORTED (high-to-low edge triggered) - 4 = active high level-sensitive <<< DEFAULT - 8 = NOT SUPPORTED (active low level-sensitive) - When no second cell is specified, the interrupt is assumed to be level - sensitive. - - The interrupt controller is accessed via the special ARC AUX register - interface, hence "reg" property is not specified. - -Example: - core_intc: core-interrupt-controller { - compatible = "snps,archs-intc"; - interrupt-controller; - #interrupt-cells = <1>; - }; - - idu_intc: idu-interrupt-controller { - compatible = "snps,archs-idu-intc"; - interrupt-controller; - interrupt-parent = <&core_intc>; - #interrupt-cells = <1>; - }; - - some_device: serial@c0fc1000 { - interrupt-parent = <&idu_intc>; - interrupts = <0>; /* upstream idu IRQ #24 */ - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/snps,archs-idu-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/snps,archs-idu-intc.yaml new file mode 100644 index 000000000000..286a964f23e1 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/snps,archs-idu-intc.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/snps,archs-idu-intc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARC-HS Interrupt Distribution Unit + +maintainers: + - Vineet Gupta <vgupta@kernel.org> + +description: > + ARC-HS Interrupt Distribution Unit is an optional 2nd level interrupt + controller which can be used in SMP configurations for dynamic IRQ routing, + load balancing of common/external IRQs towards core intc. + + The interrupt controller is accessed via the special ARC AUX register + interface, hence "reg" property is not specified. + +properties: + compatible: + const: snps,archs-idu-intc + + interrupt-controller: true + + '#interrupt-cells': + description: | + Number of interrupt specifier cells: + - 1: only a common IRQ is specified. + - 2: a second cell encodes trigger type and level flags: + 1 = low-to-high edge triggered + 4 = active high level-sensitive (default) + enum: [1, 2] + +required: + - compatible + - interrupt-controller + - '#interrupt-cells' + +additionalProperties: false + +examples: + - | + interrupt-controller { + compatible = "snps,archs-idu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/snps,archs-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/snps,archs-intc.txt deleted file mode 100644 index 69f326d6a5ad..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/snps,archs-intc.txt +++ /dev/null @@ -1,22 +0,0 @@ -* ARC-HS incore Interrupt Controller (Provided by cores implementing ARCv2 ISA) - -Properties: - -- compatible: "snps,archs-intc" -- interrupt-controller: This is an interrupt controller. -- #interrupt-cells: Must be <1>. - - Single Cell "interrupts" property of a device specifies the IRQ number - between 16 to 256 - - intc accessed via the special ARC AUX register interface, hence "reg" property - is not specified. - -Example: - - intc: interrupt-controller { - compatible = "snps,archs-intc"; - interrupt-controller; - #interrupt-cells = <1>; - interrupts = <16 17 18 19 20 21 22 23 24 25>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/snps,archs-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/snps,archs-intc.yaml new file mode 100644 index 000000000000..9d248ef7fe3d --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/snps,archs-intc.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/snps,archs-intc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARC-HS incore Interrupt Controller + +maintainers: + - Vineet Gupta <vgupta@kernel.org> + +description: + ARC-HS incore Interrupt Controller provided by cores implementing ARCv2 ISA. + intc accessed via the special ARC AUX register interface, hence "reg" property + is not specified. + +properties: + compatible: + const: snps,archs-intc + + interrupt-controller: true + + '#interrupt-cells': + const: 1 + + interrupts: + description: List of IRQ numbers between 16 and 256 + items: + items: + - minimum: 16 + maximum: 256 + +required: + - compatible + - interrupt-controller + - '#interrupt-cells' + - interrupts + +additionalProperties: false + +examples: + - | + interrupt-controller { + compatible = "snps,archs-intc"; + interrupt-controller; + #interrupt-cells = <1>; + interrupts = <16>, <17>, <18>, <19>, <20>, <21>, <22>, <23>, <24>, <25>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt b/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt deleted file mode 100644 index 2db59df9408f..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt +++ /dev/null @@ -1,43 +0,0 @@ -Synopsys DesignWare APB interrupt controller (dw_apb_ictl) - -Synopsys DesignWare provides interrupt controller IP for APB known as -dw_apb_ictl. The IP is used as secondary interrupt controller in some SoCs with -APB bus, e.g. Marvell Armada 1500. It can also be used as primary interrupt -controller in some SoCs, e.g. Hisilicon SD5203. - -Required properties: -- compatible: shall be "snps,dw-apb-ictl" -- reg: physical base address of the controller and length of memory mapped - region starting with ENABLE_LOW register -- interrupt-controller: identifies the node as an interrupt controller -- #interrupt-cells: number of cells to encode an interrupt-specifier, shall be 1 - -Additional required property when it's used as secondary interrupt controller: -- interrupts: interrupt reference to primary interrupt controller - -The interrupt sources map to the corresponding bits in the interrupt -registers, i.e. -- 0 maps to bit 0 of low interrupts, -- 1 maps to bit 1 of low interrupts, -- 32 maps to bit 0 of high interrupts, -- 33 maps to bit 1 of high interrupts, -- (optional) fast interrupts start at 64. - -Example: - /* dw_apb_ictl is used as secondary interrupt controller */ - aic: interrupt-controller@3000 { - compatible = "snps,dw-apb-ictl"; - reg = <0x3000 0xc00>; - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; - }; - - /* dw_apb_ictl is used as primary interrupt controller */ - vic: interrupt-controller@10130000 { - compatible = "snps,dw-apb-ictl"; - reg = <0x10130000 0x1000>; - interrupt-controller; - #interrupt-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.yaml b/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.yaml new file mode 100644 index 000000000000..6b59b600a037 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/snps,dw-apb-ictl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Synopsys DesignWare APB interrupt controller + +maintainers: + - Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> + - Zhen Lei <thunder.leizhen@huawei.com> + +description: + Synopsys DesignWare provides interrupt controller IP for APB known as + dw_apb_ictl. The IP is used as secondary interrupt controller in some SoCs + with APB bus, e.g. Marvell Armada 1500. It can also be used as primary + interrupt controller in some SoCs, e.g. Hisilicon SD5203. + +properties: + compatible: + const: snps,dw-apb-ictl + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 1 + + interrupts: + maxItems: 1 + description: > + Interrupt input connected to the primary interrupt controller when used + as a secondary controller. The interrupt specifier maps to bits in the + low and high interrupt registers (0⇒bit 0 low, 1⇒bit 1 low, 32⇒bit 0 high, + 33⇒bit 1 high, fast interrupts start at 64). + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + interrupt-controller@3000 { + compatible = "snps,dw-apb-ictl"; + reg = <0x3000 0xc00>; + interrupt-controller; + #interrupt-cells = <1>; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + }; + - | + interrupt-controller@10130000 { + compatible = "snps,dw-apb-ictl"; + reg = <0x10130000 0x1000>; + interrupt-controller; + #interrupt-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-msi.yaml b/Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-msi.yaml new file mode 100644 index 000000000000..f6b8b1d92f79 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-msi.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/sophgo,sg2042-msi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo SG2042 MSI Controller + +maintainers: + - Chen Wang <unicorn_wang@outlook.com> + +description: + This interrupt controller is in Sophgo SG2042 for transforming interrupts from + PCIe MSI to PLIC interrupts. + +allOf: + - $ref: /schemas/interrupt-controller/msi-controller.yaml# + +properties: + compatible: + enum: + - sophgo,sg2042-msi + - sophgo,sg2044-msi + + reg: + items: + - description: clear register + - description: msi doorbell address + + reg-names: + items: + - const: clr + - const: doorbell + + msi-controller: true + + msi-ranges: + maxItems: 1 + + "#msi-cells": + const: 0 + +required: + - compatible + - reg + - reg-names + - msi-controller + - msi-ranges + - "#msi-cells" + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + msi-controller@30000000 { + compatible = "sophgo,sg2042-msi"; + reg = <0x30000000 0x4>, <0x30000008 0x4>; + reg-names = "clr", "doorbell"; + msi-controller; + #msi-cells = <0>; + msi-ranges = <&plic 64 IRQ_TYPE_LEVEL_HIGH 32>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/st,spear300-shirq.yaml b/Documentation/devicetree/bindings/interrupt-controller/st,spear300-shirq.yaml new file mode 100644 index 000000000000..27d36173366a --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/st,spear300-shirq.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/st,spear300-shirq.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SPEAr3xx Shared IRQ controller + +maintainers: + - Viresh Kumar <vireshk@kernel.org> + - Shiraz Hashim <shiraz.linux.kernel@gmail.com> + +description: | + SPEAr3xx architecture includes shared/multiplexed irqs for certain set of + devices. The multiplexor provides a single interrupt to parent interrupt + controller (VIC) on behalf of a group of devices. + + There can be multiple groups available on SPEAr3xx variants but not exceeding + 4. The number of devices in a group can differ, further they may share same + set of status/mask registers spanning across different bit masks. Also in some + cases the group may not have enable or other registers. This makes software + little complex. + + A single node in the device tree is used to describe the shared interrupt + multiplexer (one node for all groups). A group in the interrupt controller + shares config/control registers with other groups. For example, a 32-bit + interrupt enable/disable config register can accommodate up to 4 interrupt + groups. + +properties: + compatible: + enum: + - st,spear300-shirq + - st,spear310-shirq + - st,spear320-shirq + + reg: + maxItems: 1 + + '#interrupt-cells': + const: 1 + + interrupt-controller: true + + interrupts: + description: Interrupt specifier array for SHIRQ groups + minItems: 1 + maxItems: 4 + +required: + - compatible + - reg + - '#interrupt-cells' + - interrupt-controller + - interrupts + +additionalProperties: false + +examples: + - | + interrupt-controller@b3000000 { + compatible = "st,spear320-shirq"; + reg = <0xb3000000 0x1000>; + interrupts = <28 29 30 1>; + #interrupt-cells = <1>; + interrupt-controller; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/st,spear3xx-shirq.txt b/Documentation/devicetree/bindings/interrupt-controller/st,spear3xx-shirq.txt deleted file mode 100644 index a407c499b3cc..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/st,spear3xx-shirq.txt +++ /dev/null @@ -1,44 +0,0 @@ -* SPEAr Shared IRQ layer (shirq) - -SPEAr3xx architecture includes shared/multiplexed irqs for certain set -of devices. The multiplexor provides a single interrupt to parent -interrupt controller (VIC) on behalf of a group of devices. - -There can be multiple groups available on SPEAr3xx variants but not -exceeding 4. The number of devices in a group can differ, further they -may share same set of status/mask registers spanning across different -bit masks. Also in some cases the group may not have enable or other -registers. This makes software little complex. - -A single node in the device tree is used to describe the shared -interrupt multiplexor (one node for all groups). A group in the -interrupt controller shares config/control registers with other groups. -For example, a 32-bit interrupt enable/disable config register can -accommodate up to 4 interrupt groups. - -Required properties: - - compatible: should be, either of - - "st,spear300-shirq" - - "st,spear310-shirq" - - "st,spear320-shirq" - - interrupt-controller: Identifies the node as an interrupt controller. - - #interrupt-cells: should be <1> which basically contains the offset - (starting from 0) of interrupts for all the groups. - - reg: Base address and size of shirq registers. - - interrupts: The list of interrupts generated by the groups which are - then connected to a parent interrupt controller. Each group is - associated with one of the interrupts, hence number of interrupts (to - parent) is equal to number of groups. The format of the interrupt - specifier depends in the interrupt parent controller. - -Example: - -The following is an example from the SPEAr320 SoC dtsi file. - -shirq: interrupt-controller@b3000000 { - compatible = "st,spear320-shirq"; - reg = <0xb3000000 0x1000>; - interrupts = <28 29 30 1>; - #interrupt-cells = <1>; - interrupt-controller; -}; diff --git a/Documentation/devicetree/bindings/interrupt-controller/technologic,ts4800-irqc.yaml b/Documentation/devicetree/bindings/interrupt-controller/technologic,ts4800-irqc.yaml new file mode 100644 index 000000000000..f1a15d725cd6 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/technologic,ts4800-irqc.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/technologic,ts4800-irqc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TS-4800 FPGA Interrupt Controller + +maintainers: + - Damien Riegel <damien.riegel@savoirfairelinux.com> + +description: + TS-4800 FPGA has an internal interrupt controller. When one of the interrupts + is triggered, the SoC is notified, usually using a GPIO as parent interrupt + source. + +properties: + compatible: + const: technologic,ts4800-irqc + + reg: + maxItems: 1 + + '#interrupt-cells': + const: 1 + + interrupt-controller: true + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + - interrupts + +additionalProperties: false + +examples: + - | + interrupt-controller@1000 { + compatible = "technologic,ts4800-irqc"; + reg = <0x1000 0x80>; + interrupt-controller; + #interrupt-cells = <1>; + interrupts = <10>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/technologic,ts4800.txt b/Documentation/devicetree/bindings/interrupt-controller/technologic,ts4800.txt deleted file mode 100644 index 341ae5909333..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/technologic,ts4800.txt +++ /dev/null @@ -1,14 +0,0 @@ -TS-4800 FPGA interrupt controller - -TS-4800 FPGA has an internal interrupt controller. When one of the -interrupts is triggered, the SoC is notified, usually using a GPIO as -parent interrupt source. - -Required properties: -- compatible: should be "technologic,ts4800-irqc" -- interrupt-controller: identifies the node as an interrupt controller -- reg: physical base address of the controller and length of memory mapped - region -- #interrupt-cells: specifies the number of cells needed to encode an interrupt - source, should be 1. -- interrupts: specifies the interrupt line in the interrupt-parent controller diff --git a/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-mswi.yaml b/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-mswi.yaml index 065f2544b63b..d6fb08a54167 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-mswi.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-mswi.yaml @@ -14,6 +14,7 @@ properties: items: - enum: - sophgo,sg2042-aclint-mswi + - sophgo,sg2044-aclint-mswi - const: thead,c900-aclint-mswi reg: diff --git a/Documentation/devicetree/bindings/interrupt-controller/ti,cp-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/ti,cp-intc.txt deleted file mode 100644 index 597e8a089fe4..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/ti,cp-intc.txt +++ /dev/null @@ -1,27 +0,0 @@ -* TI Common Platform Interrupt Controller - -Common Platform Interrupt Controller (cp_intc) is used on -OMAP-L1x SoCs and can support several configurable number -of interrupts. - -Main node required properties: - -- compatible : should be: - "ti,cp-intc" -- interrupt-controller : Identifies the node as an interrupt controller -- #interrupt-cells : Specifies the number of cells needed to encode an - interrupt source. The type shall be a <u32> and the value shall be 1. - - The cell contains the interrupt number in the range [0-128]. -- ti,intc-size: Number of interrupts handled by the interrupt controller. -- reg: physical base address and size of the intc registers map. - -Example: - - intc: interrupt-controller@1 { - compatible = "ti,cp-intc"; - interrupt-controller; - #interrupt-cells = <1>; - ti,intc-size = <101>; - reg = <0xfffee000 0x2000>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/ti,cp-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/ti,cp-intc.yaml new file mode 100644 index 000000000000..77d018d20f9f --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/ti,cp-intc.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/ti,cp-intc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI Common Platform Interrupt Controller + +maintainers: + - Bartosz Golaszewski <brgl@bgdev.pl> + +description: + Common Platform Interrupt Controller (cp_intc) is used on OMAP-L1x SoCs and + can support several configurable number of interrupts. + +properties: + compatible: + const: ti,cp-intc + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 1 + description: Encodes an interrupt number in the range 0–128. + + ti,intc-size: + description: Number of interrupts handled by the interrupt controller. + $ref: /schemas/types.yaml#/definitions/uint32 + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + - ti,intc-size + +additionalProperties: false + +examples: + - | + interrupt-controller@fffee000 { + compatible = "ti,cp-intc"; + reg = <0xfffee000 0x2000>; + interrupt-controller; + #interrupt-cells = <1>; + ti,intc-size = <101>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/ti,keystone-irq.txt b/Documentation/devicetree/bindings/interrupt-controller/ti,keystone-irq.txt deleted file mode 100644 index 5f94d7739d8d..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/ti,keystone-irq.txt +++ /dev/null @@ -1,36 +0,0 @@ -Keystone 2 IRQ controller IP - -On Keystone SOCs, DSP cores can send interrupts to ARM -host using the IRQ controller IP. It provides 28 IRQ signals to ARM. -The IRQ handler running on HOST OS can identify DSP signal source by -analyzing SRCCx bits in IPCARx registers. This is one of the component -used by the IPC mechanism used on Keystone SOCs. - -Required Properties: -- compatible: should be "ti,keystone-irq" -- ti,syscon-dev : phandle and offset pair. The phandle to syscon used to - access device control registers and the offset inside - device control registers range. -- interrupt-controller : Identifies the node as an interrupt controller -- #interrupt-cells : Specifies the number of cells needed to encode interrupt - source should be 1. -- interrupts: interrupt reference to primary interrupt controller - -Please refer to interrupts.txt in this directory for details of the common -Interrupt Controllers bindings used by client devices. - -Example: - kirq0: keystone_irq0@26202a0 { - compatible = "ti,keystone-irq"; - ti,syscon-dev = <&devctrl 0x2a0>; - interrupts = <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>; - interrupt-controller; - #interrupt-cells = <1>; - }; - - dsp0: dsp0 { - compatible = "linux,rproc-user"; - ... - interrupt-parent = <&kirq0>; - interrupts = <10 2>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/ti,keystone-irq.yaml b/Documentation/devicetree/bindings/interrupt-controller/ti,keystone-irq.yaml new file mode 100644 index 000000000000..27d448d1786a --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/ti,keystone-irq.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ti,keystone-irq.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Keystone 2 IRQ controller IP + +maintainers: + - Grygorii Strashko <grygorii.strashko@ti.com> + +description: + On Keystone SOCs, DSP cores can send interrupts to ARM host using the IRQ + controller IP. It provides 28 IRQ signals to ARM. The IRQ handler running on + HOST OS can identify DSP signal source by analyzing SRCCx bits in IPCARx + registers. This is one of the component used by the IPC mechanism used on + Keystone SOCs. + +properties: + compatible: + const: ti,keystone-irq + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 1 + + interrupts: + maxItems: 1 + + ti,syscon-dev: + description: Phandle and offset to syscon device + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: Phandle to syscon device control registers + - description: Offset to control register + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + - interrupts + - ti,syscon-dev + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + interrupt-controller@2a0 { + compatible = "ti,keystone-irq"; + reg = <0x2a0 0x4>; + ti,syscon-dev = <&devctrl 0x2a0>; + interrupts = <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>; + interrupt-controller; + #interrupt-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/ti,omap-intc-irq.txt b/Documentation/devicetree/bindings/interrupt-controller/ti,omap-intc-irq.txt deleted file mode 100644 index 38ce5d037722..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/ti,omap-intc-irq.txt +++ /dev/null @@ -1,28 +0,0 @@ -Omap2/3 intc controller - -On TI omap2 and 3 the intc interrupt controller can provide -96 or 128 IRQ signals to the ARM host depending on the SoC. - -Required Properties: -- compatible: should be one of - "ti,omap2-intc" - "ti,omap3-intc" - "ti,dm814-intc" - "ti,dm816-intc" - "ti,am33xx-intc" - -- interrupt-controller : Identifies the node as an interrupt controller -- #interrupt-cells : Specifies the number of cells needed to encode interrupt - source, should be 1 for intc -- interrupts: interrupt reference to primary interrupt controller - -Please refer to interrupts.txt in this directory for details of the common -Interrupt Controllers bindings used by client devices. - -Example: - intc: interrupt-controller@48200000 { - compatible = "ti,omap3-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x48200000 0x1000>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/ti,omap-intc-irq.yaml b/Documentation/devicetree/bindings/interrupt-controller/ti,omap-intc-irq.yaml new file mode 100644 index 000000000000..cb118180621f --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/ti,omap-intc-irq.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/ti,omap-intc-irq.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI OMAP Interrupt Controller + +maintainers: + - Tony Lindgren <tony@atomide.com> + +description: + On TI omap2 and 3 the intc interrupt controller can provide 96 or 128 IRQ + signals to the ARM host depending on the SoC. + +properties: + compatible: + enum: + - ti,omap2-intc + - ti,omap3-intc + - ti,dm814-intc + - ti,dm816-intc + - ti,am33xx-intc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 1 + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + +additionalProperties: false + +examples: + - | + interrupt-controller@48200000 { + compatible = "ti,omap3-intc"; + reg = <0x48200000 0x1000>; + interrupts = <32>; + interrupt-controller; + #interrupt-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/ti,omap2-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/ti,omap2-intc.txt deleted file mode 100644 index f2583e6ec060..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/ti,omap2-intc.txt +++ /dev/null @@ -1,27 +0,0 @@ -* OMAP Interrupt Controller - -OMAP2/3 are using a TI interrupt controller that can support several -configurable number of interrupts. - -Main node required properties: - -- compatible : should be: - "ti,omap2-intc" -- interrupt-controller : Identifies the node as an interrupt controller -- #interrupt-cells : Specifies the number of cells needed to encode an - interrupt source. The type shall be a <u32> and the value shall be 1. - - The cell contains the interrupt number in the range [0-128]. -- ti,intc-size: Number of interrupts handled by the interrupt controller. -- reg: physical base address and size of the intc registers map. - -Example: - - intc: interrupt-controller@1 { - compatible = "ti,omap2-intc"; - interrupt-controller; - #interrupt-cells = <1>; - ti,intc-size = <96>; - reg = <0x48200000 0x1000>; - }; - diff --git a/Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu.txt b/Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu.txt deleted file mode 100644 index 422d6908f8b2..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu.txt +++ /dev/null @@ -1,31 +0,0 @@ -TI OMAP4 Wake-up Generator - -All TI OMAP4/5 (and their derivatives) an interrupt controller that -routes interrupts to the GIC, and also serves as a wakeup source. It -is also referred to as "WUGEN-MPU", hence the name of the binding. - -Required properties: - -- compatible : should contain at least "ti,omap4-wugen-mpu" or - "ti,omap5-wugen-mpu" -- reg : Specifies base physical address and size of the registers. -- interrupt-controller : Identifies the node as an interrupt controller. -- #interrupt-cells : Specifies the number of cells needed to encode an - interrupt source. The value must be 3. - -Notes: - -- Because this HW ultimately routes interrupts to the GIC, the - interrupt specifier must be that of the GIC. -- Only SPIs can use the WUGEN as an interrupt parent. SGIs and PPIs - are explicitly forbidden. - -Example: - - wakeupgen: interrupt-controller@48281000 { - compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x48281000 0x1000>; - interrupt-parent = <&gic>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu.yaml b/Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu.yaml new file mode 100644 index 000000000000..6e3d6e6d9e07 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/ti,omap4-wugen-mpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI OMAP4 Wake-up Generator + +maintainers: + - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> + +description: > + All TI OMAP4/5 (and their derivatives) are interrupt controllers that route + interrupts to the GIC, and also serve as wakeup sources. They are also + referred to as "WUGEN-MPU", hence the name of the binding. + + Notes: + + - Because this HW ultimately routes interrupts to the GIC, the interrupt + specifier must be that of the GIC. + - Only SPIs can use the WUGEN as an interrupt parent. SGIs and PPIs are + explicitly forbidden. + +properties: + compatible: + oneOf: + - items: + - const: ti,omap5-wugen-mpu + - const: ti,omap4-wugen-mpu + - const: ti,omap4-wugen-mpu + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 3 + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + +additionalProperties: false + +examples: + - | + interrupt-controller@48281000 { + compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu"; + reg = <0x48281000 0x1000>; + interrupt-controller; + #interrupt-cells = <3>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/via,vt8500-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/via,vt8500-intc.txt deleted file mode 100644 index 0a4ce1051b02..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/via,vt8500-intc.txt +++ /dev/null @@ -1,16 +0,0 @@ -VIA/Wondermedia VT8500 Interrupt Controller ------------------------------------------------------ - -Required properties: -- compatible : "via,vt8500-intc" -- reg : Should contain 1 register ranges(address and length) -- #interrupt-cells : should be <1> - -Example: - - intc: interrupt-controller@d8140000 { - compatible = "via,vt8500-intc"; - interrupt-controller; - reg = <0xd8140000 0x10000>; - #interrupt-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/via,vt8500-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/via,vt8500-intc.yaml new file mode 100644 index 000000000000..bc14c74bf7d5 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/via,vt8500-intc.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/via,vt8500-intc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: VIA and WonderMedia SoCs Interrupt Controller + +description: + This is the interrupt controller used in single-core ARM SoCs made by + VIA and WonderMedia (up to and including WM8950). Each block handles + up to 64 interrupt sources (level or edge triggered) and can generate + up to 8 interrupts to its parent when used in a chained configuration. + +maintainers: + - Alexey Charkov <alchark@gmail.com> + +allOf: + - $ref: /schemas/interrupt-controller.yaml# + +properties: + compatible: + const: via,vt8500-intc + + reg: + maxItems: 1 + + interrupts: + items: + - description: + Interrupt number raised by the IRQ0 output of this controller + Only used if this controller is chained + - description: + Interrupt number raised by the IRQ1 output of this controller + Only used if this controller is chained + - description: + Interrupt number raised by the IRQ2 output of this controller + Only used if this controller is chained + - description: + Interrupt number raised by the IRQ3 output of this controller + Only used if this controller is chained + - description: + Interrupt number raised by the IRQ4 output of this controller + Only used if this controller is chained + - description: + Interrupt number raised by the IRQ5 output of this controller + Only used if this controller is chained + - description: + Interrupt number raised by the IRQ6 output of this controller + Only used if this controller is chained + - description: + Interrupt number raised by the IRQ7 output of this controller + Only used if this controller is chained + + interrupt-controller: true + + '#interrupt-cells': + const: 1 + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + +additionalProperties: false + +examples: + - | + interrupt-controller@d8140000 { + compatible = "via,vt8500-intc"; + interrupt-controller; + reg = <0xd8140000 0x10000>; + #interrupt-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index 032fdc27127b..7b9d5507d6cc 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -90,6 +90,7 @@ properties: - enum: - qcom,qcm2290-smmu-500 - qcom,qcs615-smmu-500 + - qcom,qcs8300-smmu-500 - qcom,sa8255p-smmu-500 - qcom,sa8775p-smmu-500 - qcom,sar2130p-smmu-500 @@ -397,6 +398,7 @@ allOf: compatible: contains: enum: + - qcom,qcs8300-smmu-500 - qcom,sa8775p-smmu-500 - qcom,sc7280-smmu-500 - qcom,sc8280xp-smmu-500 @@ -581,7 +583,6 @@ allOf: - cavium,smmu-v2 - marvell,ap806-smmu-500 - nvidia,smmu-500 - - qcom,qcs8300-smmu-500 - qcom,qdu1000-smmu-500 - qcom,sa8255p-smmu-500 - qcom,sc7180-smmu-500 diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml index ea6b0f5f24de..75750c64157c 100644 --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml @@ -74,6 +74,7 @@ properties: - mediatek,mt2712-m4u # generation two - mediatek,mt6779-m4u # generation two - mediatek,mt6795-m4u # generation two + - mediatek,mt6893-iommu-mm # generation two - mediatek,mt8167-m4u # generation two - mediatek,mt8173-m4u # generation two - mediatek,mt8183-m4u # generation two @@ -131,6 +132,7 @@ properties: dt-binding/memory/mt2712-larb-port.h for mt2712, dt-binding/memory/mt6779-larb-port.h for mt6779, dt-binding/memory/mt6795-larb-port.h for mt6795, + dt-binding/memory/mediatek,mt6893-memory-port.h for mt6893, dt-binding/memory/mt8167-larb-port.h for mt8167, dt-binding/memory/mt8173-larb-port.h for mt8173, dt-binding/memory/mt8183-larb-port.h for mt8183, @@ -157,6 +159,7 @@ allOf: - mediatek,mt2701-m4u - mediatek,mt2712-m4u - mediatek,mt6795-m4u + - mediatek,mt6893-iommu-mm - mediatek,mt8173-m4u - mediatek,mt8186-iommu-mm - mediatek,mt8188-iommu-vdo @@ -173,6 +176,7 @@ allOf: properties: compatible: enum: + - mediatek,mt6893-iommu-mm - mediatek,mt8186-iommu-mm - mediatek,mt8188-iommu-vdo - mediatek,mt8188-iommu-vpp diff --git a/Documentation/devicetree/bindings/iommu/qcom,iommu.yaml b/Documentation/devicetree/bindings/iommu/qcom,iommu.yaml index 5ae9a628261f..3e5623edd207 100644 --- a/Documentation/devicetree/bindings/iommu/qcom,iommu.yaml +++ b/Documentation/devicetree/bindings/iommu/qcom,iommu.yaml @@ -22,6 +22,7 @@ properties: - enum: - qcom,msm8916-iommu - qcom,msm8917-iommu + - qcom,msm8937-iommu - qcom,msm8953-iommu - const: qcom,msm-iommu-v1 - items: diff --git a/Documentation/devicetree/bindings/leds/backlight/apple,dwi-bl.yaml b/Documentation/devicetree/bindings/leds/backlight/apple,dwi-bl.yaml new file mode 100644 index 000000000000..29caeb356e6f --- /dev/null +++ b/Documentation/devicetree/bindings/leds/backlight/apple,dwi-bl.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/leds/backlight/apple,dwi-bl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Apple DWI 2-Wire Interface Backlight Controller + +maintainers: + - Nick Chan <towinchenmi@gmail.com> + +description: + Apple SoCs contain a 2-wire interface called DWI. On some Apple iPhones, + iPads and iPod touches with a LCD display, 1-2 backlight controllers + are connected via DWI. Interfacing with DWI controls all backlight + controllers at the same time. As such, the backlight controllers are + treated as a single controller regardless of the underlying + configuration. + +allOf: + - $ref: common.yaml# + +properties: + compatible: + items: + - enum: + - apple,s5l8960x-dwi-bl + - apple,t7000-dwi-bl + - apple,s8000-dwi-bl + - apple,t8010-dwi-bl + - apple,t8015-dwi-bl + - const: apple,dwi-bl + + reg: + maxItems: 1 + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + dwi_bl: backlight@20e200010 { + compatible = "apple,s5l8960x-dwi-bl", "apple,dwi-bl"; + reg = <0x2 0x0e200010 0x0 0x8>; + power-domains = <&ps_dwi>; + }; + }; diff --git a/Documentation/devicetree/bindings/leds/backlight/ti,lp8864.yaml b/Documentation/devicetree/bindings/leds/backlight/ti,lp8864.yaml new file mode 100644 index 000000000000..d44232d462bd --- /dev/null +++ b/Documentation/devicetree/bindings/leds/backlight/ti,lp8864.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/leds/backlight/ti,lp8864.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments - LP8864/LP8866 4/6-Channel LED Driver family + +maintainers: + - Andrew Davis <afd@ti.com> + - Alexander Sverdlin <alexander.sverdlin@siemens.com> + +description: | + LP8866-Q1, LP8866S-Q1, LP8864-Q1, LP8864S-Q1 are display LED-backlight drivers + with 4/6 channels. LED brightness can be controlled globally through the I2C + interface or PWM input. + + For more product information please see the links below: + https://www.ti.com/product/LP8864-Q1 + https://www.ti.com/product/LP8864S-Q1 + https://www.ti.com/product/LP8866-Q1 + https://www.ti.com/product/LP8866S-Q1 + +properties: + compatible: + const: ti,lp8864 + + reg: + maxItems: 1 + description: I2C slave address + + enable-gpios: + maxItems: 1 + description: GPIO pin to enable (active high) / disable the device + + vled-supply: + description: LED supply + + led: + type: object + $ref: common.yaml# + properties: + function: true + color: true + label: true + linux,default-trigger: true + + additionalProperties: false + +required: + - compatible + - reg + - led + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/leds/common.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + led-controller@3a { + compatible = "ti,lp8864"; + reg = <0x3a>; + enable-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; + vled-supply = <&vbatt>; + + led { + function = LED_FUNCTION_BACKLIGHT; + color = <LED_COLOR_ID_WHITE>; + linux,default-trigger = "backlight"; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/leds/leds-qcom-lpg.yaml b/Documentation/devicetree/bindings/leds/leds-qcom-lpg.yaml index 8b82c45d1a48..841a0229c472 100644 --- a/Documentation/devicetree/bindings/leds/leds-qcom-lpg.yaml +++ b/Documentation/devicetree/bindings/leds/leds-qcom-lpg.yaml @@ -39,6 +39,10 @@ properties: - enum: - qcom,pm8550-pwm - const: qcom,pm8350c-pwm + - items: + - enum: + - qcom,pm8937-pwm + - const: qcom,pm8916-pwm "#pwm-cells": const: 2 diff --git a/Documentation/devicetree/bindings/leds/leds-tlc591xx.txt b/Documentation/devicetree/bindings/leds/leds-tlc591xx.txt deleted file mode 100644 index 3bbbf7024411..000000000000 --- a/Documentation/devicetree/bindings/leds/leds-tlc591xx.txt +++ /dev/null @@ -1,40 +0,0 @@ -LEDs connected to tlc59116 or tlc59108 - -Required properties -- compatible: should be "ti,tlc59116" or "ti,tlc59108" -- #address-cells: must be 1 -- #size-cells: must be 0 -- reg: typically 0x68 - -Each led is represented as a sub-node of the ti,tlc59116. -See Documentation/devicetree/bindings/leds/common.txt - -LED sub-node properties: -- reg: number of LED line, 0 to 15 or 0 to 7 -- label: (optional) name of LED -- linux,default-trigger : (optional) - -Examples: - -tlc59116@68 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "ti,tlc59116"; - reg = <0x68>; - - wan@0 { - label = "wrt1900ac:amber:wan"; - reg = <0x0>; - }; - - 2g@2 { - label = "wrt1900ac:white:2g"; - reg = <0x2>; - }; - - alive@9 { - label = "wrt1900ac:green:alive"; - reg = <0x9>; - linux,default_trigger = "heartbeat"; - }; -}; diff --git a/Documentation/devicetree/bindings/leds/ti,tlc59116.yaml b/Documentation/devicetree/bindings/leds/ti,tlc59116.yaml new file mode 100644 index 000000000000..ce9713793908 --- /dev/null +++ b/Documentation/devicetree/bindings/leds/ti,tlc59116.yaml @@ -0,0 +1,90 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/leds/ti,tlc59116.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: LEDs connected to tlc59116 or tlc59108 + +maintainers: + - Andrew Lunn <andrew@lunn.ch> + +properties: + compatible: + enum: + - ti,tlc59108 + - ti,tlc59116 + + reg: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +patternProperties: + "^led@[0-9a-f]$": + type: object + $ref: common.yaml# + properties: + reg: + items: + minimum: 0 + maximum: 15 + + unevaluatedProperties: false + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + +allOf: + - if: + properties: + compatible: + contains: + const: ti,tlc59108 + then: + patternProperties: + "^led@[0-9a-f]$": + properties: + reg: + items: + maximum: 7 + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + led-controller@68 { + compatible = "ti,tlc59116"; + reg = <0x68>; + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0x0>; + label = "wrt1900ac:amber:wan"; + }; + + led@2 { + reg = <0x2>; + label = "wrt1900ac:white:2g"; + }; + + led@9 { + reg = <0x9>; + label = "wrt1900ac:green:alive"; + linux,default-trigger = "heartbeat"; + }; + }; + }; + diff --git a/Documentation/devicetree/bindings/leds/ti,tps61310.yaml b/Documentation/devicetree/bindings/leds/ti,tps61310.yaml new file mode 100644 index 000000000000..118f9c8bfdf7 --- /dev/null +++ b/Documentation/devicetree/bindings/leds/ti,tps61310.yaml @@ -0,0 +1,120 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/leds/ti,tps61310.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments TPS6131X flash LED driver + +maintainers: + - Matthias Fend <matthias.fend@emfend.at> + +description: | + The TPS61310/TPS61311 is a flash LED driver with I2C interface. + Its power stage is capable of supplying a maximum total current of roughly 1500mA. + The TPS6131x provides three constant-current sinks, capable of sinking + up to 2 x 400mA (LED1 and LED3) and 800mA (LED2) in flash mode. + In torch mode, each sink (LED1, LED2, LED3) supports currents up to 175mA. + Since the three current sinks share most of the control components such as + flash timer, control logic, safety timer and the operating mode, they cannot + be used completely independently of each other. Therefore, only one LED is + supported, but the current sinks can be combined accordingly. + + The data sheet can be found at: + https://www.ti.com/lit/ds/symlink/tps61310.pdf + +properties: + compatible: + oneOf: + - items: + - enum: + - ti,tps61311 + - const: ti,tps61310 + - items: + - const: ti,tps61310 + + reg: + maxItems: 1 + + reset-gpios: + maxItems: 1 + description: GPIO connected to NRESET pin + + ti,valley-current-limit: + type: boolean + description: + Reduce the valley peak current limit from 1750mA to 1250mA (TPS61310) or + from 2480mA to 1800mA (TPS61311). + + led: + type: object + $ref: common.yaml# + unevaluatedProperties: false + + properties: + led-sources: + minItems: 1 + maxItems: 3 + items: + enum: [1, 2, 3] + + led-max-microamp: + oneOf: + - minimum: 50000 + maximum: 350000 + multipleOf: 50000 + - minimum: 25000 + maximum: 525000 + multipleOf: 25000 + + flash-max-microamp: + oneOf: + - minimum: 50000 + maximum: 800000 + multipleOf: 50000 + - minimum: 25000 + maximum: 1500000 + multipleOf: 25000 + + flash-max-timeout-us: + enum: [ 5300, 10700, 16000, 21300, 26600, 32000, 37300, 68200, 71500, + 102200, 136300, 170400, 204500, 340800, 579300, 852000 ] + + required: + - led-sources + - led-max-microamp + - flash-max-microamp + - flash-max-timeout-us + +required: + - compatible + - reg + - led + +additionalProperties: false + +examples: + - | + #include <dt-bindings/leds/common.h> + #include <dt-bindings/gpio/gpio.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + led-controller@33 { + compatible = "ti,tps61311", "ti,tps61310"; + reg = <0x33>; + + reset-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + + led { + function = LED_FUNCTION_FLASH; + color = <LED_COLOR_ID_WHITE>; + led-sources = <1>, <2>, <3>; + led-max-microamp = <525000>; + flash-max-microamp = <1500000>; + flash-max-timeout-us = <852000>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml b/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml index 00631afcd51d..581425aacdcc 100644 --- a/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml +++ b/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml @@ -54,6 +54,10 @@ properties: - fsl,imx8qm-mu - fsl,imx8qxp-mu - const: fsl,imx6sx-mu + - items: + - enum: + - fsl,imx94-mu + - const: fsl,imx95-mu reg: maxItems: 1 @@ -142,7 +146,8 @@ allOf: not: properties: compatible: - const: fsl,imx95-mu + contains: + const: fsl,imx95-mu then: patternProperties: "^sram@[a-f0-9]+": false diff --git a/Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml index cef9d7601398..73d6db34d64a 100644 --- a/Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml +++ b/Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml @@ -25,6 +25,7 @@ properties: - mediatek,mt8188-gce - mediatek,mt8192-gce - mediatek,mt8195-gce + - mediatek,mt8196-gce - items: - const: mediatek,mt6795-gce - const: mediatek,mt8173-gce @@ -49,6 +50,9 @@ properties: items: - const: gce + iommus: + maxItems: 1 + required: - compatible - "#mbox-cells" diff --git a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml index 78f68dacd028..ac726136f7e5 100644 --- a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml +++ b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml @@ -26,6 +26,7 @@ properties: - const: qcom,ipq6018-apcs-apps-global - items: - enum: + - qcom,msm8226-apcs-kpss-global - qcom,qcs404-apcs-apps-global - const: qcom,msm8916-apcs-kpss-global - const: syscon @@ -48,6 +49,7 @@ properties: - qcom,qcs615-apss-shared - qcom,sc7180-apss-shared - qcom,sc8180x-apss-shared + - qcom,sm7150-apss-shared - qcom,sm8150-apss-shared - const: qcom,sdm845-apss-shared - items: @@ -71,6 +73,7 @@ properties: description: phandles to the parent clocks of the clock driver minItems: 2 maxItems: 3 + deprecated: true '#mbox-cells': const: 1 @@ -81,6 +84,23 @@ properties: clock-names: minItems: 2 maxItems: 3 + deprecated: true + + clock-controller: + type: object + additionalProperties: false + properties: + clocks: + description: phandles to the parent clocks of the clock driver + minItems: 2 + maxItems: 3 + + '#clock-cells': + enum: [0, 1] + + clock-names: + minItems: 2 + maxItems: 3 required: - compatible @@ -89,6 +109,76 @@ required: additionalProperties: false +# Clocks should be specified either on the parent node or on the child node +oneOf: + - required: + - clock-controller + properties: + clocks: false + clock-names: false + '#clock-cells': false + - properties: + clock-controller: false + +$defs: + msm8916-apcs-clock-controller: + properties: + clocks: + items: + - description: primary pll parent of the clock driver + - description: auxiliary parent + clock-names: + items: + - const: pll + - const: aux + '#clock-cells': + const: 0 + + msm8939-apcs-clock-controller: + properties: + clocks: + items: + - description: primary pll parent of the clock driver + - description: auxiliary parent + - description: reference clock + clock-names: + items: + - const: pll + - const: aux + - const: ref + '#clock-cells': + const: 0 + + sdx55-apcs-clock-controller: + properties: + clocks: + items: + - description: reference clock + - description: primary pll parent of the clock driver + - description: auxiliary parent + clock-names: + items: + - const: ref + - const: pll + - const: aux + '#clock-cells': + const: 0 + + ipq6018-apcs-clock-controller: + properties: + clocks: + items: + - description: primary pll parent of the clock driver + - description: XO clock + - description: GCC GPLL0 clock source + clock-names: + items: + - const: pll + - const: xo + - const: gpll0 + '#clock-cells': + const: 1 + allOf: - if: properties: @@ -97,15 +187,10 @@ allOf: enum: - qcom,msm8916-apcs-kpss-global then: + $ref: "#/$defs/msm8916-apcs-clock-controller" properties: - clocks: - items: - - description: primary pll parent of the clock driver - - description: auxiliary parent - clock-names: - items: - - const: pll - - const: aux + clock-controller: + $ref: "#/$defs/msm8916-apcs-clock-controller" - if: properties: @@ -114,17 +199,10 @@ allOf: enum: - qcom,msm8939-apcs-kpss-global then: + $ref: "#/$defs/msm8939-apcs-clock-controller" properties: - clocks: - items: - - description: primary pll parent of the clock driver - - description: auxiliary parent - - description: reference clock - clock-names: - items: - - const: pll - - const: aux - - const: ref + clock-controller: + $ref: "#/$defs/msm8939-apcs-clock-controller" - if: properties: @@ -133,17 +211,10 @@ allOf: enum: - qcom,sdx55-apcs-gcc then: + $ref: "#/$defs/sdx55-apcs-clock-controller" properties: - clocks: - items: - - description: reference clock - - description: primary pll parent of the clock driver - - description: auxiliary parent - clock-names: - items: - - const: ref - - const: pll - - const: aux + clock-controller: + $ref: "#/$defs/sdx55-apcs-clock-controller" - if: properties: @@ -152,17 +223,10 @@ allOf: enum: - qcom,ipq6018-apcs-apps-global then: + $ref: "#/$defs/ipq6018-apcs-clock-controller" properties: - clocks: - items: - - description: primary pll parent of the clock driver - - description: XO clock - - description: GCC GPLL0 clock source - clock-names: - items: - - const: pll - - const: xo - - const: gpll0 + clock-controller: + $ref: "#/$defs/ipq6018-apcs-clock-controller" - if: properties: @@ -178,19 +242,7 @@ allOf: properties: clocks: false clock-names: false - - - if: - properties: - compatible: - contains: - enum: - - qcom,ipq6018-apcs-apps-global - then: - properties: - '#clock-cells': - const: 1 - else: - properties: + clock-controller: false '#clock-cells': const: 0 @@ -218,6 +270,23 @@ examples: - | #define GCC_APSS_AHB_CLK_SRC 1 #define GCC_GPLL0_AO_OUT_MAIN 123 + mailbox@b011000 { + compatible = "qcom,qcs404-apcs-apps-global", + "qcom,msm8916-apcs-kpss-global", "syscon"; + reg = <0x0b011000 0x1000>; + #mbox-cells = <1>; + + apcs_clk: clock-controller { + clocks = <&apcs_hfpll>, <&gcc GCC_GPLL0_AO_OUT_MAIN>; + clock-names = "pll", "aux"; + #clock-cells = <0>; + }; + }; + + # Example apcs with qcs404 (deprecated: use clock-controller subnode) + - | + #define GCC_APSS_AHB_CLK_SRC 1 + #define GCC_GPLL0_AO_OUT_MAIN 123 apcs: mailbox@b011000 { compatible = "qcom,qcs404-apcs-apps-global", "qcom,msm8916-apcs-kpss-global", "syscon"; diff --git a/Documentation/devicetree/bindings/mailbox/sophgo,cv1800b-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/sophgo,cv1800b-mailbox.yaml new file mode 100644 index 000000000000..24e126bd3a20 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/sophgo,cv1800b-mailbox.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/sophgo,cv1800b-mailbox.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo CV1800/SG2000 mailbox controller + +maintainers: + - Yuntao Dai <d1581209858@live.com> + - Junhui Liu <junhui.liu@pigmoral.tech> + +description: + Mailboxes integrated in Sophgo CV1800/SG2000 SoCs have 8 channels, each + shipping an 8-byte FIFO. Any processor can write to an arbitrary channel + and raise interrupts to receivers. Sending messages to itself is also + supported. + +properties: + compatible: + const: sophgo,cv1800b-mailbox + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + "#mbox-cells": + const: 2 + description: | + <&phandle channel target> + phandle : Label name of mailbox controller + channel : 0-7, Channel index + target : 0-3, Target processor ID + + Sophgo CV1800/SG2000 SoCs include the following processors, numbered as: + <0> Cortex-A53 (Only available on CV181X/SG200X) + <1> C906B + <2> C906L + <3> 8051 + +required: + - compatible + - reg + - interrupts + - "#mbox-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + mailbox@1900000 { + compatible = "sophgo,cv1800b-mailbox"; + reg = <0x01900000 0x1000>; + interrupts = <101 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; + }; diff --git a/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml index b3d6db922693..1aa5775ba2bc 100644 --- a/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml +++ b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml @@ -110,7 +110,7 @@ examples: reg = <0x01cb4000 0x1000>; interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_CSI>, - <&ccu CLK_CSI1_SCLK>, + <&ccu CLK_CSI_SCLK>, <&ccu CLK_DRAM_CSI>; clock-names = "bus", "mod", diff --git a/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-isp.yaml b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-isp.yaml index a61a76bb611c..3ea4a4290f23 100644 --- a/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-isp.yaml +++ b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-isp.yaml @@ -79,7 +79,7 @@ examples: reg = <0x01cb8000 0x1000>; interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_CSI>, - <&ccu CLK_CSI1_SCLK>, + <&ccu CLK_CSI_SCLK>, <&ccu CLK_DRAM_CSI>; clock-names = "bus", "mod", "ram"; resets = <&ccu RST_BUS_CSI>; diff --git a/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml index 54e15ab8a7f5..627b28e94354 100644 --- a/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml +++ b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml @@ -103,7 +103,7 @@ examples: reg = <0x01cb1000 0x1000>; interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_CSI>, - <&ccu CLK_CSI1_SCLK>; + <&ccu CLK_CSI_SCLK>; clock-names = "bus", "mod"; resets = <&ccu RST_BUS_CSI>; diff --git a/Documentation/devicetree/bindings/media/amlogic,c3-isp.yaml b/Documentation/devicetree/bindings/media/amlogic,c3-isp.yaml new file mode 100644 index 000000000000..123bf462f098 --- /dev/null +++ b/Documentation/devicetree/bindings/media/amlogic,c3-isp.yaml @@ -0,0 +1,88 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/amlogic,c3-isp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic C3 Image Signal Processing Unit + +maintainers: + - Keke Li <keke.li@amlogic.com> + +description: + Amlogic ISP is the RAW image processing module + and supports three channels image output. + +properties: + compatible: + enum: + - amlogic,c3-isp + + reg: + maxItems: 1 + + reg-names: + items: + - const: isp + + power-domains: + maxItems: 1 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: vapb + - const: isp0 + + interrupts: + maxItems: 1 + + port: + $ref: /schemas/graph.yaml#/properties/port + description: input port node. + +required: + - compatible + - reg + - reg-names + - power-domains + - clocks + - clock-names + - interrupts + - port + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/amlogic,c3-peripherals-clkc.h> + #include <dt-bindings/power/amlogic,c3-pwrc.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + isp: isp@ff000000 { + compatible = "amlogic,c3-isp"; + reg = <0x0 0xff000000 0x0 0xf000>; + reg-names = "isp"; + power-domains = <&pwrc PWRC_C3_ISP_TOP_ID>; + clocks = <&clkc_periphs CLKID_VAPB>, + <&clkc_periphs CLKID_ISP0>; + clock-names = "vapb", "isp0"; + assigned-clocks = <&clkc_periphs CLKID_VAPB>, + <&clkc_periphs CLKID_ISP0>; + assigned-clock-rates = <0>, <400000000>; + interrupts = <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>; + + port { + c3_isp_in: endpoint { + remote-endpoint = <&c3_adap_out>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/media/amlogic,c3-mipi-adapter.yaml b/Documentation/devicetree/bindings/media/amlogic,c3-mipi-adapter.yaml new file mode 100644 index 000000000000..ba43bc6709a0 --- /dev/null +++ b/Documentation/devicetree/bindings/media/amlogic,c3-mipi-adapter.yaml @@ -0,0 +1,111 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/amlogic,c3-mipi-adapter.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic C3 MIPI adapter receiver + +maintainers: + - Keke Li <keke.li@amlogic.com> + +description: + MIPI adapter is used to convert the MIPI CSI-2 data + into an ISP supported data format. + +properties: + compatible: + enum: + - amlogic,c3-mipi-adapter + + reg: + maxItems: 3 + + reg-names: + items: + - const: top + - const: fd + - const: rd + + power-domains: + maxItems: 1 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: vapb + - const: isp0 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: input port node. + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: output port node. + + required: + - port@0 + - port@1 + +required: + - compatible + - reg + - reg-names + - power-domains + - clocks + - clock-names + - ports + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/amlogic,c3-peripherals-clkc.h> + #include <dt-bindings/power/amlogic,c3-pwrc.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + adap: adap@ff010000 { + compatible = "amlogic,c3-mipi-adapter"; + reg = <0x0 0xff010000 0x0 0x100>, + <0x0 0xff01b000 0x0 0x100>, + <0x0 0xff01d000 0x0 0x200>; + reg-names = "top", "fd", "rd"; + power-domains = <&pwrc PWRC_C3_ISP_TOP_ID>; + clocks = <&clkc_periphs CLKID_VAPB>, + <&clkc_periphs CLKID_ISP0>; + clock-names = "vapb", "isp0"; + assigned-clocks = <&clkc_periphs CLKID_VAPB>, + <&clkc_periphs CLKID_ISP0>; + assigned-clock-rates = <0>, <400000000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + c3_adap_in: endpoint { + remote-endpoint = <&c3_mipi_csi_out>; + }; + }; + + port@1 { + reg = <1>; + c3_adap_out: endpoint { + remote-endpoint = <&c3_isp_in>; + }; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/media/amlogic,c3-mipi-csi2.yaml b/Documentation/devicetree/bindings/media/amlogic,c3-mipi-csi2.yaml new file mode 100644 index 000000000000..b0129beab0c3 --- /dev/null +++ b/Documentation/devicetree/bindings/media/amlogic,c3-mipi-csi2.yaml @@ -0,0 +1,127 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/amlogic,c3-mipi-csi2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic C3 MIPI CSI-2 receiver + +maintainers: + - Keke Li <keke.li@amlogic.com> + +description: + MIPI CSI-2 receiver contains CSI-2 RX PHY and host controller. + It receives the MIPI data from the image sensor and sends MIPI data + to MIPI adapter. + +properties: + compatible: + enum: + - amlogic,c3-mipi-csi2 + + reg: + maxItems: 3 + + reg-names: + items: + - const: aphy + - const: dphy + - const: host + + power-domains: + maxItems: 1 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: vapb + - const: phy0 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: input port node, connected to sensor. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - data-lanes + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: output port node + + required: + - port@0 + - port@1 + +required: + - compatible + - reg + - reg-names + - power-domains + - clocks + - clock-names + - ports + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/amlogic,c3-peripherals-clkc.h> + #include <dt-bindings/power/amlogic,c3-pwrc.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + csi: csi@ff018000 { + compatible = "amlogic,c3-mipi-csi2"; + reg = <0x0 0xff018000 0x0 0x400>, + <0x0 0xff019000 0x0 0x300>, + <0x0 0xff01a000 0x0 0x100>; + reg-names = "aphy", "dphy", "host"; + power-domains = <&pwrc PWRC_C3_MIPI_ISP_WRAP_ID>; + clocks = <&clkc_periphs CLKID_VAPB>, + <&clkc_periphs CLKID_CSI_PHY0>; + clock-names = "vapb", "phy0"; + assigned-clocks = <&clkc_periphs CLKID_VAPB>, + <&clkc_periphs CLKID_CSI_PHY0>; + assigned-clock-rates = <0>, <200000000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + c3_mipi_csi_in: endpoint { + remote-endpoint = <&imx290_out>; + data-lanes = <1 2 3 4>; + }; + }; + + port@1 { + reg = <1>; + c3_mipi_csi_out: endpoint { + remote-endpoint = <&c3_adap_in>; + }; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/media/aspeed,video-engine.yaml b/Documentation/devicetree/bindings/media/aspeed,video-engine.yaml new file mode 100644 index 000000000000..682bba20778c --- /dev/null +++ b/Documentation/devicetree/bindings/media/aspeed,video-engine.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/aspeed,video-engine.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ASPEED Video Engine + +maintainers: + - Eddie James <eajames@linux.ibm.com> + +description: + The Video Engine (VE) embedded in the ASPEED SOCs can be configured to + capture and compress video data from digital or analog sources. + +properties: + compatible: + enum: + - aspeed,ast2400-video-engine + - aspeed,ast2500-video-engine + - aspeed,ast2600-video-engine + + reg: + maxItems: 1 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: vclk + - const: eclk + + resets: + maxItems: 1 + + interrupts: + maxItems: 1 + + memory-region: + maxItems: 1 + description: | + Phandle to the reserved memory nodes to be associated with the + VE. VE will acquires memory space for 3 purposes: + 1. JPEG header + 2. Compressed result + 3. Temporary transformed image data + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/ast2600-clock.h> + + video@1e700000 { + compatible = "aspeed,ast2600-video-engine"; + reg = <0x1e700000 0x1000>; + clocks = <&syscon ASPEED_CLK_GATE_VCLK>, + <&syscon ASPEED_CLK_GATE_ECLK>; + clock-names = "vclk", "eclk"; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + }; diff --git a/Documentation/devicetree/bindings/media/aspeed-video.txt b/Documentation/devicetree/bindings/media/aspeed-video.txt deleted file mode 100644 index d2ca32512272..000000000000 --- a/Documentation/devicetree/bindings/media/aspeed-video.txt +++ /dev/null @@ -1,33 +0,0 @@ -* Device tree bindings for Aspeed Video Engine - -The Video Engine (VE) embedded in the Aspeed AST2400/2500/2600 SOCs can -capture and compress video data from digital or analog sources. - -Required properties: - - compatible: "aspeed,ast2400-video-engine" or - "aspeed,ast2500-video-engine" or - "aspeed,ast2600-video-engine" - - reg: contains the offset and length of the VE memory region - - clocks: clock specifiers for the syscon clocks associated with - the VE (ordering must match the clock-names property) - - clock-names: "vclk" and "eclk" - - resets: reset specifier for the syscon reset associated with - the VE - - interrupts: the interrupt associated with the VE on this platform - -Optional properties: - - memory-region: - phandle to a memory region to allocate from, as defined in - Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt - -Example: - -video-engine@1e700000 { - compatible = "aspeed,ast2500-video-engine"; - reg = <0x1e700000 0x20000>; - clocks = <&syscon ASPEED_CLK_GATE_VCLK>, <&syscon ASPEED_CLK_GATE_ECLK>; - clock-names = "vclk", "eclk"; - resets = <&syscon ASPEED_RESET_VIDEO>; - interrupts = <7>; - memory-region = <&video_engine_memory>; -}; diff --git a/Documentation/devicetree/bindings/media/cec/nvidia,tegra114-cec.yaml b/Documentation/devicetree/bindings/media/cec/nvidia,tegra114-cec.yaml index a6b73498bc21..4b46aa755ccd 100644 --- a/Documentation/devicetree/bindings/media/cec/nvidia,tegra114-cec.yaml +++ b/Documentation/devicetree/bindings/media/cec/nvidia,tegra114-cec.yaml @@ -14,10 +14,16 @@ allOf: properties: compatible: - enum: - - nvidia,tegra114-cec - - nvidia,tegra124-cec - - nvidia,tegra210-cec + oneOf: + - enum: + - nvidia,tegra114-cec + - nvidia,tegra124-cec + - nvidia,tegra210-cec + - items: + - enum: + - nvidia,tegra186-cec + - nvidia,tegra194-cec + - const: nvidia,tegra210-cec clocks: maxItems: 1 diff --git a/Documentation/devicetree/bindings/media/fsl,imx-capture-subsystem.yaml b/Documentation/devicetree/bindings/media/fsl,imx-capture-subsystem.yaml new file mode 100644 index 000000000000..25e65a344a0a --- /dev/null +++ b/Documentation/devicetree/bindings/media/fsl,imx-capture-subsystem.yaml @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/fsl,imx-capture-subsystem.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX Media Video Device + +description: + This is the media controller node for video capture support. It is a + virtual device that lists the camera serial interface nodes that the + media device will control + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +properties: + compatible: + const: fsl,imx-capture-subsystem + + ports: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + Should contain a list of phandles pointing to camera + sensor interface ports of IPU devices. + +required: + - compatible + +additionalProperties: false + +examples: + - | + capture-subsystem { + compatible = "fsl,imx-capture-subsystem"; + ports = <&ipu1_csi0>, <&ipu1_csi1>; + }; diff --git a/Documentation/devicetree/bindings/media/fsl,imx6-mipi-csi2.yaml b/Documentation/devicetree/bindings/media/fsl,imx6-mipi-csi2.yaml new file mode 100644 index 000000000000..65255f576f26 --- /dev/null +++ b/Documentation/devicetree/bindings/media/fsl,imx6-mipi-csi2.yaml @@ -0,0 +1,143 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/fsl,imx6-mipi-csi2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MIPI CSI-2 Receiver core in the i.MX SoC + +description: + This is the device node for the MIPI CSI-2 Receiver core in the i.MX + SoC. This is a Synopsys Designware MIPI CSI-2 host controller core + combined with a D-PHY core mixed into the same register block. In + addition this device consists of an i.MX-specific "CSI2IPU gasket" + glue logic, also controlled from the same register block. The CSI2IPU + gasket demultiplexes the four virtual channel streams from the host + controller's 32-bit output image bus onto four 16-bit parallel busses + to the i.MX IPU CSIs. + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +properties: + compatible: + const: fsl,imx6-mipi-csi2 + + reg: + maxItems: 1 + + clocks: + items: + - description: hsi_tx (the D-PHY clock) + - description: video_27m (D-PHY PLL reference clock) + - description: eim_podf; + + clock-names: + items: + - const: dphy + - const: ref + - const: pix + + interrupts: + items: + - description: CSI-2 ERR1 irq + - description: CSI-2 ERR2 irq + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port node, single endpoint describing the CSI-2 transmitter. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + const: 0 + + data-lanes: + minItems: 1 + items: + - const: 1 + - const: 2 + - const: 3 + - const: 4 + + required: + - data-lanes + +patternProperties: + '^port@[1-4]$': + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + ports 1 through 4 are output ports connecting with parallel bus sink + endpoint nodes and correspond to the four MIPI CSI-2 virtual channel + outputs. + + properties: + endpoint@0: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + endpoint@1: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + +required: + - compatible + - reg + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/imx6qdl-clock.h> + + mipi@21dc000 { + compatible = "fsl,imx6-mipi-csi2"; + reg = <0x021dc000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clks IMX6QDL_CLK_HSI_TX>, + <&clks IMX6QDL_CLK_VIDEO_27M>, + <&clks IMX6QDL_CLK_EIM_PODF>; + clock-names = "dphy", "ref", "pix"; + + port@0 { + reg = <0>; + + endpoint { + remote-endpoint = <&ov5640_to_mipi_csi2>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + endpoint@0 { + reg = <0>; + remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>; + }; + + endpoint@1 { + reg = <1>; + remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc0>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/media/i2c/ad5820.txt b/Documentation/devicetree/bindings/media/i2c/ad5820.txt deleted file mode 100644 index 5764cbedf9b7..000000000000 --- a/Documentation/devicetree/bindings/media/i2c/ad5820.txt +++ /dev/null @@ -1,28 +0,0 @@ -* Analog Devices AD5820 autofocus coil - -Required Properties: - - - compatible: Must contain one of: - - "adi,ad5820" - - "adi,ad5821" - - "adi,ad5823" - - - reg: I2C slave address - - - VANA-supply: supply of voltage for VANA pin - -Optional properties: - - - enable-gpios : GPIO spec for the XSHUTDOWN pin. The XSHUTDOWN signal is -active low, a high level on the pin enables the device. - -Example: - - ad5820: coil@c { - compatible = "adi,ad5820"; - reg = <0x0c>; - - VANA-supply = <&vaux4>; - enable-gpios = <&msmgpio 26 GPIO_ACTIVE_HIGH>; - }; - diff --git a/Documentation/devicetree/bindings/media/i2c/adi,ad5820.yaml b/Documentation/devicetree/bindings/media/i2c/adi,ad5820.yaml new file mode 100644 index 000000000000..0c8f24f692ca --- /dev/null +++ b/Documentation/devicetree/bindings/media/i2c/adi,ad5820.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/i2c/adi,ad5820.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices AD5820 autofocus coil + +maintainers: + - Pavel Machek <pavel@ucw.cz> + +description: + The AD5820 is a current sink driver designed for precise control of + voice coil motors (VCMs) in camera autofocus systems. + +properties: + compatible: + enum: + - adi,ad5820 + - adi,ad5821 + - adi,ad5823 + + reg: + maxItems: 1 + + enable-gpios: + maxItems: 1 + description: + GPIO spec for the XSHUTDOWN pin. The XSHUTDOWN signal is active low, + a high level on the pin enables the device. + + VANA-supply: + description: supply of voltage for VANA pin + +required: + - compatible + - reg + - VANA-supply + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + coil@c { + compatible = "adi,ad5820"; + reg = <0x0c>; + + enable-gpios = <&msmgpio 26 GPIO_ACTIVE_HIGH>; + VANA-supply = <&vaux4>; + }; + }; diff --git a/Documentation/devicetree/bindings/media/i2c/adp1653.txt b/Documentation/devicetree/bindings/media/i2c/adi,adp1653.txt index 4cce0de40ee9..4cce0de40ee9 100644 --- a/Documentation/devicetree/bindings/media/i2c/adp1653.txt +++ b/Documentation/devicetree/bindings/media/i2c/adi,adp1653.txt diff --git a/Documentation/devicetree/bindings/media/i2c/adv7180.yaml b/Documentation/devicetree/bindings/media/i2c/adi,adv7180.yaml index 4371a0ef2761..dee8ce7cb7ba 100644 --- a/Documentation/devicetree/bindings/media/i2c/adv7180.yaml +++ b/Documentation/devicetree/bindings/media/i2c/adi,adv7180.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/media/i2c/adv7180.yaml# +$id: http://devicetree.org/schemas/media/i2c/adi,adv7180.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Analog Devices ADV7180 analog video decoder family @@ -49,6 +49,10 @@ properties: Indicates that the output is a BT.656-4 compatible stream. type: boolean + interrupts: + items: + - description: The GPIO connected to the INTRQ pin. + port: $ref: /schemas/graph.yaml#/$defs/port-base unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/media/i2c/adv7343.txt b/Documentation/devicetree/bindings/media/i2c/adi,adv7343.txt index 5653bc2428b8..5653bc2428b8 100644 --- a/Documentation/devicetree/bindings/media/i2c/adv7343.txt +++ b/Documentation/devicetree/bindings/media/i2c/adi,adv7343.txt diff --git a/Documentation/devicetree/bindings/media/i2c/adv748x.yaml b/Documentation/devicetree/bindings/media/i2c/adi,adv748x.yaml index d6353081402b..254987350321 100644 --- a/Documentation/devicetree/bindings/media/i2c/adv748x.yaml +++ b/Documentation/devicetree/bindings/media/i2c/adi,adv748x.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/media/i2c/adv748x.yaml# +$id: http://devicetree.org/schemas/media/i2c/adi,adv748x.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Analog Devices ADV748X video decoder with HDMI receiver diff --git a/Documentation/devicetree/bindings/media/i2c/adv7604.yaml b/Documentation/devicetree/bindings/media/i2c/adi,adv7604.yaml index 7589d377c686..6c403003cdda 100644 --- a/Documentation/devicetree/bindings/media/i2c/adv7604.yaml +++ b/Documentation/devicetree/bindings/media/i2c/adi,adv7604.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/media/i2c/adv7604.yaml# +$id: http://devicetree.org/schemas/media/i2c/adi,adv7604.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Analog Devices ADV7604/10/11/12 video decoder with HDMI receiver diff --git a/Documentation/devicetree/bindings/media/i2c/mt9v032.txt b/Documentation/devicetree/bindings/media/i2c/aptina,mt9v032.txt index 100f0ae43269..100f0ae43269 100644 --- a/Documentation/devicetree/bindings/media/i2c/mt9v032.txt +++ b/Documentation/devicetree/bindings/media/i2c/aptina,mt9v032.txt diff --git a/Documentation/devicetree/bindings/media/i2c/max2175.txt b/Documentation/devicetree/bindings/media/i2c/maxim,max2175.txt index 02b4e9cd7b1b..02b4e9cd7b1b 100644 --- a/Documentation/devicetree/bindings/media/i2c/max2175.txt +++ b/Documentation/devicetree/bindings/media/i2c/maxim,max2175.txt diff --git a/Documentation/devicetree/bindings/media/i2c/mt9m111.txt b/Documentation/devicetree/bindings/media/i2c/micron,mt9m111.txt index d0bed6fa901a..d0bed6fa901a 100644 --- a/Documentation/devicetree/bindings/media/i2c/mt9m111.txt +++ b/Documentation/devicetree/bindings/media/i2c/micron,mt9m111.txt diff --git a/Documentation/devicetree/bindings/media/i2c/tda1997x.txt b/Documentation/devicetree/bindings/media/i2c/nxp,tda1997x.txt index e76167999d76..e76167999d76 100644 --- a/Documentation/devicetree/bindings/media/i2c/tda1997x.txt +++ b/Documentation/devicetree/bindings/media/i2c/nxp,tda1997x.txt diff --git a/Documentation/devicetree/bindings/media/i2c/mt9m001.txt b/Documentation/devicetree/bindings/media/i2c/onnn,mt9m001.txt index c920552b03ef..c920552b03ef 100644 --- a/Documentation/devicetree/bindings/media/i2c/mt9m001.txt +++ b/Documentation/devicetree/bindings/media/i2c/onnn,mt9m001.txt diff --git a/Documentation/devicetree/bindings/media/i2c/ovti,ov02e10.yaml b/Documentation/devicetree/bindings/media/i2c/ovti,ov02e10.yaml new file mode 100644 index 000000000000..03d476bcf805 --- /dev/null +++ b/Documentation/devicetree/bindings/media/i2c/ovti,ov02e10.yaml @@ -0,0 +1,152 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright (c) 2025 Linaro Ltd. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/i2c/ovti,ov02e10.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Omnivision OV02E10 CMOS Sensor + +maintainers: + - Bryan O'Donoghue <bryan.odonoghue@linaro.org> + +description: | + The Omnivision OV02E10 and OV02C10 sensors are 2 megapixel, CMOS image sensors which support: + - Automatic black level calibration (ABLC) + - Programmable controls for frame rate, mirror and flip, binning, cropping + and windowing + - OVO2C10 + - 10 bit RAW Bayer 1920x1080 60 fps 2-lane @ 800 Mbps/lane + - 10 bit RAW Bayer 1920x1080 60 fps 1-lane @ 1500 Mbps/lane + - 10 bit RAW Bayer 1280x720 60 fps cropped 1-lane @ 960 Mbps/lane + - 10 bit RGB/BW 640x480 60 fps bin2 or skip2 1-lane @ 800 Mbps/lane + - 10 bit RGB/BW 480x270 60 fps bin4 or skip4 1-lane @ 800 Mbps/lane + - OV02E10 + - 10 bit RAW Bayer 1920x1088 60 fps 2-lane @ 720 Mbps/lane + - 10 bit RAW Bayer 1280x1080 60 fps 2-lane @ 720 Mbps/lane + - 10 bit Quad Bayer 960x540 60 fps 2-lane 360 Mbps/lane + - 8 bit Quad Bayer 480x270 1/3/5/10 fps sub2 288 Mbps/lane + - 8 bit Quad Bayer 232x132 1/3/5/10 fps sub4 144 Mbps/lane + - Dynamic defect pixel cancellation + - Standard SCCB command interface + +allOf: + - $ref: /schemas/media/video-interface-devices.yaml# + +properties: + compatible: + enum: + - ovti,ov02c10 + - ovti,ov02e10 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + avdd-supply: + description: Analogue circuit voltage supply. + + dovdd-supply: + description: I/O circuit voltage supply. + + dvdd-supply: + description: Digital circuit voltage supply. + + reset-gpios: + description: Active low GPIO connected to XSHUTDOWN pad of the sensor. + + port: + $ref: /schemas/graph.yaml#/$defs/port-base + additionalProperties: false + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + additionalProperties: false + + properties: + data-lanes: + items: + - const: 1 + - const: 2 + link-frequencies: true + remote-endpoint: true + + required: + - data-lanes + - link-frequencies + - remote-endpoint + +required: + - compatible + - reg + - clocks + - port + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + ov02e10: camera@10 { + compatible = "ovti,ov02e10"; + reg = <0x10>; + + reset-gpios = <&tlmm 237 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_rgb_defaultt>; + + clocks = <&ov02e10_clk>; + + assigned-clocks = <&ov02e10_clk>; + assigned-clock-parents = <&ov02e10_clk_parent>; + assigned-clock-rates = <19200000>; + + avdd-supply = <&vreg_l7b_2p8>; + dvdd-supply = <&vreg_l7b_1p8>; + dovdd-supply = <&vreg_l3m_1p8>; + + port { + ov02e10_ep: endpoint { + remote-endpoint = <&csiphy4_ep>; + data-lanes = <1 2>; + link-frequencies = /bits/ 64 <400000000>; + }; + }; + }; + + ov02c10: camera@36 { + compatible = "ovti,ov02c10"; + reg = <0x36>; + + reset-gpios = <&tlmm 237 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_rgb_defaultt>; + + clocks = <&ov02c10_clk>; + + assigned-clocks = <&ov02c10_clk>; + assigned-clock-parents = <&ov02c10_clk_parent>; + assigned-clock-rates = <19200000>; + + avdd-supply = <&vreg_l7b_2p8>; + dvdd-supply = <&vreg_l7b_1p8>; + dovdd-supply = <&vreg_l3m_1p8>; + + port { + ov02c10_ep: endpoint { + remote-endpoint = <&csiphy4_ep>; + data-lanes = <1 2>; + link-frequencies = /bits/ 64 <400000000>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/media/i2c/ov2640.txt b/Documentation/devicetree/bindings/media/i2c/ovti,ov2640.txt index 989ce6cb6ac3..989ce6cb6ac3 100644 --- a/Documentation/devicetree/bindings/media/i2c/ov2640.txt +++ b/Documentation/devicetree/bindings/media/i2c/ovti,ov2640.txt diff --git a/Documentation/devicetree/bindings/media/i2c/ov2659.txt b/Documentation/devicetree/bindings/media/i2c/ovti,ov2659.txt index 92989a619f29..92989a619f29 100644 --- a/Documentation/devicetree/bindings/media/i2c/ov2659.txt +++ b/Documentation/devicetree/bindings/media/i2c/ovti,ov2659.txt diff --git a/Documentation/devicetree/bindings/media/i2c/ov7670.txt b/Documentation/devicetree/bindings/media/i2c/ovti,ov7670.txt index 2c972a56f3cb..2c972a56f3cb 100644 --- a/Documentation/devicetree/bindings/media/i2c/ov7670.txt +++ b/Documentation/devicetree/bindings/media/i2c/ovti,ov7670.txt diff --git a/Documentation/devicetree/bindings/media/i2c/ov7740.txt b/Documentation/devicetree/bindings/media/i2c/ovti,ov7740.txt index af781c3a5f0e..af781c3a5f0e 100644 --- a/Documentation/devicetree/bindings/media/i2c/ov7740.txt +++ b/Documentation/devicetree/bindings/media/i2c/ovti,ov7740.txt diff --git a/Documentation/devicetree/bindings/media/i2c/ov9650.txt b/Documentation/devicetree/bindings/media/i2c/ovti,ov9650.txt index 506dfc52872a..506dfc52872a 100644 --- a/Documentation/devicetree/bindings/media/i2c/ov9650.txt +++ b/Documentation/devicetree/bindings/media/i2c/ovti,ov9650.txt diff --git a/Documentation/devicetree/bindings/media/i2c/imx219.yaml b/Documentation/devicetree/bindings/media/i2c/sony,imx219.yaml index 07d088cf66e0..38c3759bcd9f 100644 --- a/Documentation/devicetree/bindings/media/i2c/imx219.yaml +++ b/Documentation/devicetree/bindings/media/i2c/sony,imx219.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/media/i2c/imx219.yaml# +$id: http://devicetree.org/schemas/media/i2c/sony,imx219.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Sony 1/4.0-Inch 8Mpixel CMOS Digital Image Sensor @@ -16,6 +16,9 @@ description: |- Image data is sent through MIPI CSI-2, which is configured as either 2 or 4 data lanes. +allOf: + - $ref: /schemas/media/video-interface-devices.yaml# + properties: compatible: const: sony,imx219 @@ -79,7 +82,7 @@ required: - VDDL-supply - port -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/media/i2c/sony,imx290.yaml b/Documentation/devicetree/bindings/media/i2c/sony,imx290.yaml index fa69bd21c8da..990acf89af8f 100644 --- a/Documentation/devicetree/bindings/media/i2c/sony,imx290.yaml +++ b/Documentation/devicetree/bindings/media/i2c/sony,imx290.yaml @@ -136,7 +136,7 @@ examples: port { imx290_ep: endpoint { data-lanes = <1 2 3 4>; - link-frequencies = /bits/ 64 <445500000>; + link-frequencies = /bits/ 64 <222750000 148500000>; remote-endpoint = <&csiphy0_ep>; }; }; diff --git a/Documentation/devicetree/bindings/media/i2c/sony,imx415.yaml b/Documentation/devicetree/bindings/media/i2c/sony,imx415.yaml index 34962c5c7006..7c11e871dca6 100644 --- a/Documentation/devicetree/bindings/media/i2c/sony,imx415.yaml +++ b/Documentation/devicetree/bindings/media/i2c/sony,imx415.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Sony IMX415 CMOS Image Sensor maintainers: - - Michael Riesch <michael.riesch@wolfvision.net> + - Michael Riesch <michael.riesch@collabora.com> description: |- The Sony IMX415 is a diagonal 6.4 mm (Type 1/2.8) CMOS active pixel type diff --git a/Documentation/devicetree/bindings/media/i2c/st,vd55g1.yaml b/Documentation/devicetree/bindings/media/i2c/st,vd55g1.yaml new file mode 100644 index 000000000000..3c071e6fbea6 --- /dev/null +++ b/Documentation/devicetree/bindings/media/i2c/st,vd55g1.yaml @@ -0,0 +1,133 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright (c) 2025 STMicroelectronics SA. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/i2c/st,vd55g1.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics VD55G1 Global Shutter Image Sensor + +maintainers: + - Benjamin Mugnier <benjamin.mugnier@foss.st.com> + - Sylvain Petinot <sylvain.petinot@foss.st.com> + +description: |- + The STMicroelectronics VD55G1 is a global shutter image sensor with an active + array size of 804H x 704V. It is programmable through I2C interface. The I2C + address is fixed to 0x10. + + Image data is sent through MIPI CSI-2, which is configured as only 1 data + lane. The sensor provides 4 GPIOS that can be used for external LED signal + (synchronized with sensor integration periods). + +allOf: + - $ref: /schemas/media/video-interface-devices.yaml# + +properties: + compatible: + const: st,vd55g1 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + vcore-supply: + description: Digital core power supply (1.15V) + + vddio-supply: + description: Digital IO power supply (1.8V) + + vana-supply: + description: Analog power supply (2.8V) + + reset-gpios: + description: Sensor reset active low GPIO (XSHUTDOWN) + maxItems: 1 + + st,leds: + description: + List sensor's GPIOs used to control strobe light sources during exposure + time. The numbers identify the sensor pin on which the illumination + system is connected. GPIOs are active-high. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 4 + items: + minimum: 0 + maximum: 3 + + port: + $ref: /schemas/graph.yaml#/$defs/port-base + additionalProperties: false + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + items: + - const: 1 + + link-frequencies: + maxItems: 1 + items: + minimum: 125000000 + maximum: 600000000 + + lane-polarities: + minItems: 1 + maxItems: 2 + + required: + - data-lanes + - link-frequencies + +required: + - compatible + - reg + - clocks + - vcore-supply + - vddio-supply + - vana-supply + - reset-gpios + - port + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + camera-sensor@10 { + compatible = "st,vd55g1"; + reg = <0x10>; + + clocks = <&camera_clk_12M>; + + vcore-supply = <&camera_vcore_v1v15>; + vddio-supply = <&camera_vddio_v1v8>; + vana-supply = <&camera_vana_v2v8>; + + reset-gpios = <&gpio 5 GPIO_ACTIVE_LOW>; + st,leds = <2>; + + orientation = <2>; + rotation = <0>; + + port { + endpoint { + data-lanes = <1>; + link-frequencies = /bits/ 64 <600000000>; + remote-endpoint = <&csiphy0_ep>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/media/i2c/st,vd56g3.yaml b/Documentation/devicetree/bindings/media/i2c/st,vd56g3.yaml new file mode 100644 index 000000000000..c6673b8539db --- /dev/null +++ b/Documentation/devicetree/bindings/media/i2c/st,vd56g3.yaml @@ -0,0 +1,139 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright (c) 2024 STMicroelectronics SA. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/i2c/st,vd56g3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics VD56G3 Global Shutter Image Sensor + +maintainers: + - Benjamin Mugnier <benjamin.mugnier@foss.st.com> + - Sylvain Petinot <sylvain.petinot@foss.st.com> + +description: |- + The STMicroelectronics VD56G3 is a 1.5 M pixel global shutter image sensor + with an active array size of 1124 x 1364 (portrait orientation). It is + programmable through I2C, the address is fixed to 0x10. The sensor output is + available via CSI-2, which is configured as either 1 or 2 data lanes. The + sensor provides 8 GPIOS that can be used for external LED signal + (synchronized with sensor integration periods) + +allOf: + - $ref: /schemas/media/video-interface-devices.yaml# + +properties: + compatible: + enum: + - st,vd56g3 + - st,vd66gy + description: + Two variants are availables; VD56G3 is a monochrome sensor while VD66GY + is a colour variant. + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + vcore-supply: + description: Digital core power supply (1.15V) + + vddio-supply: + description: Digital IO power supply (1.8V) + + vana-supply: + description: Analog power supply (2.8V) + + reset-gpios: + description: Sensor reset active low GPIO (XSHUTDOWN) + maxItems: 1 + + st,leds: + description: + List sensor's GPIOs used to control strobe light sources during exposure + time. The numbers identify the sensor pin on which the illumination system + is connected. GPIOs are active-high. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 8 + items: + minimum: 0 + maximum: 7 + + port: + $ref: /schemas/graph.yaml#/$defs/port-base + additionalProperties: false + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + minItems: 1 + maxItems: 2 + items: + enum: [1, 2] + + link-frequencies: + maxItems: 1 + items: + enum: [402000000, 750000000] + + lane-polarities: + minItems: 1 + maxItems: 3 + description: Any lane can be inverted or not. + + required: + - data-lanes + - link-frequencies + +required: + - compatible + - reg + - clocks + - vcore-supply + - vddio-supply + - vana-supply + - reset-gpios + - port + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + camera-sensor@10 { + compatible = "st,vd56g3"; + reg = <0x10>; + + clocks = <&camera_clk_12M>; + + vcore-supply = <&camera_vcore_v1v15>; + vddio-supply = <&camera_vddio_v1v8>; + vana-supply = <&camera_vana_v2v8>; + + reset-gpios = <&gpio 5 GPIO_ACTIVE_LOW>; + st,leds = <6>; + + orientation = <2>; + rotation = <0>; + + port { + endpoint { + data-lanes = <1 2>; + link-frequencies = /bits/ 64 <402000000>; + remote-endpoint = <&csiphy0_ep>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/media/i2c/ti,ds90ub953.yaml b/Documentation/devicetree/bindings/media/i2c/ti,ds90ub953.yaml index 2030366994d1..2e129bf573b7 100644 --- a/Documentation/devicetree/bindings/media/i2c/ti,ds90ub953.yaml +++ b/Documentation/devicetree/bindings/media/i2c/ti,ds90ub953.yaml @@ -38,6 +38,13 @@ properties: '#clock-cells': const: 0 + reg: + maxItems: 1 + description: + The strap I2C address of the serializer. Can be used by the deserializer + to communicate over back-channel when the forward-channel is not yet + active. + ports: $ref: /schemas/graph.yaml#/properties/ports @@ -81,51 +88,57 @@ examples: - | #include <dt-bindings/gpio/gpio.h> - serializer { - compatible = "ti,ds90ub953-q1"; + link { + #address-cells = <1>; + #size-cells = <0>; + + serializer@18 { + compatible = "ti,ds90ub953-q1"; + reg = <0x18>; - gpio-controller; - #gpio-cells = <2>; + gpio-controller; + #gpio-cells = <2>; - #clock-cells = <0>; + #clock-cells = <0>; - ports { - #address-cells = <1>; - #size-cells = <0>; + ports { + #address-cells = <1>; + #size-cells = <0>; - port@0 { - reg = <0>; - ub953_in: endpoint { - clock-lanes = <0>; - data-lanes = <1 2 3 4>; - remote-endpoint = <&sensor_out>; + port@0 { + reg = <0>; + ub953_in: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&sensor_out>; + }; }; - }; - port@1 { - reg = <1>; - endpoint { - remote-endpoint = <&deser_fpd_in>; + port@1 { + reg = <1>; + endpoint { + remote-endpoint = <&deser_fpd_in>; + }; }; }; - }; - i2c { - #address-cells = <1>; - #size-cells = <0>; + i2c { + #address-cells = <1>; + #size-cells = <0>; - sensor@1a { - compatible = "sony,imx274"; - reg = <0x1a>; + sensor@1a { + compatible = "sony,imx274"; + reg = <0x1a>; - reset-gpios = <&serializer 0 GPIO_ACTIVE_LOW>; + reset-gpios = <&serializer 0 GPIO_ACTIVE_LOW>; - clocks = <&serializer>; - clock-names = "inck"; + clocks = <&serializer>; + clock-names = "inck"; - port { - sensor_out: endpoint { - remote-endpoint = <&ub953_in>; + port { + sensor_out: endpoint { + remote-endpoint = <&ub953_in>; + }; }; }; }; diff --git a/Documentation/devicetree/bindings/media/i2c/ti,ds90ub960.yaml b/Documentation/devicetree/bindings/media/i2c/ti,ds90ub960.yaml index 0b71e6f911a8..4dcbd2b039a5 100644 --- a/Documentation/devicetree/bindings/media/i2c/ti,ds90ub960.yaml +++ b/Documentation/devicetree/bindings/media/i2c/ti,ds90ub960.yaml @@ -68,6 +68,12 @@ properties: description: The link number maxItems: 1 + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + i2c-alias: $ref: /schemas/types.yaml#/definitions/uint32 description: @@ -107,7 +113,8 @@ properties: maximum: 14 description: Manual EQ level - serializer: + patternProperties: + '^serializer(@[0-9a-f]+)*$': type: object description: FPD-Link Serializer node @@ -115,7 +122,6 @@ properties: - reg - i2c-alias - ti,rx-mode - - serializer ports: $ref: /schemas/graph.yaml#/properties/ports @@ -309,13 +315,17 @@ examples: /* Link 0 has DS90UB953 serializer and IMX274 sensor */ link@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; i2c-alias = <0x44>; ti,rx-mode = <3>; - serializer1: serializer { + serializer1: serializer@30 { compatible = "ti,ds90ub953-q1"; + reg = <0x30>; gpio-controller; #gpio-cells = <2>; diff --git a/Documentation/devicetree/bindings/media/i2c/ths8200.txt b/Documentation/devicetree/bindings/media/i2c/ti,ths8200.txt index 285f6ae7dfa9..285f6ae7dfa9 100644 --- a/Documentation/devicetree/bindings/media/i2c/ths8200.txt +++ b/Documentation/devicetree/bindings/media/i2c/ti,ths8200.txt diff --git a/Documentation/devicetree/bindings/media/i2c/tvp514x.txt b/Documentation/devicetree/bindings/media/i2c/ti,tvp514x.txt index 46752cc71f2e..46752cc71f2e 100644 --- a/Documentation/devicetree/bindings/media/i2c/tvp514x.txt +++ b/Documentation/devicetree/bindings/media/i2c/ti,tvp514x.txt diff --git a/Documentation/devicetree/bindings/media/i2c/tvp5150.txt b/Documentation/devicetree/bindings/media/i2c/ti,tvp5150.txt index 94b908ace53c..94b908ace53c 100644 --- a/Documentation/devicetree/bindings/media/i2c/tvp5150.txt +++ b/Documentation/devicetree/bindings/media/i2c/ti,tvp5150.txt diff --git a/Documentation/devicetree/bindings/media/i2c/tvp7002.txt b/Documentation/devicetree/bindings/media/i2c/ti,tvp7002.txt index 5f28b5d9abcc..5f28b5d9abcc 100644 --- a/Documentation/devicetree/bindings/media/i2c/tvp7002.txt +++ b/Documentation/devicetree/bindings/media/i2c/ti,tvp7002.txt diff --git a/Documentation/devicetree/bindings/media/i2c/tc358743.txt b/Documentation/devicetree/bindings/media/i2c/toshiba,tc358743.txt index 59102edcf01e..59102edcf01e 100644 --- a/Documentation/devicetree/bindings/media/i2c/tc358743.txt +++ b/Documentation/devicetree/bindings/media/i2c/toshiba,tc358743.txt diff --git a/Documentation/devicetree/bindings/media/imx.txt b/Documentation/devicetree/bindings/media/imx.txt deleted file mode 100644 index 77f4b0a7fd2b..000000000000 --- a/Documentation/devicetree/bindings/media/imx.txt +++ /dev/null @@ -1,53 +0,0 @@ -Freescale i.MX Media Video Device -================================= - -Video Media Controller node ---------------------------- - -This is the media controller node for video capture support. It is a -virtual device that lists the camera serial interface nodes that the -media device will control. - -Required properties: -- compatible : "fsl,imx-capture-subsystem"; -- ports : Should contain a list of phandles pointing to camera - sensor interface ports of IPU devices - -example: - -capture-subsystem { - compatible = "fsl,imx-capture-subsystem"; - ports = <&ipu1_csi0>, <&ipu1_csi1>; -}; - - -mipi_csi2 node --------------- - -This is the device node for the MIPI CSI-2 Receiver core in the i.MX -SoC. This is a Synopsys Designware MIPI CSI-2 host controller core -combined with a D-PHY core mixed into the same register block. In -addition this device consists of an i.MX-specific "CSI2IPU gasket" -glue logic, also controlled from the same register block. The CSI2IPU -gasket demultiplexes the four virtual channel streams from the host -controller's 32-bit output image bus onto four 16-bit parallel busses -to the i.MX IPU CSIs. - -Required properties: -- compatible : "fsl,imx6-mipi-csi2"; -- reg : physical base address and length of the register set; -- clocks : the MIPI CSI-2 receiver requires three clocks: hsi_tx - (the D-PHY clock), video_27m (D-PHY PLL reference - clock), and eim_podf; -- clock-names : must contain "dphy", "ref", "pix"; -- port@* : five port nodes must exist, containing endpoints - connecting to the source and sink devices according to - of_graph bindings. The first port is an input port, - connecting with a MIPI CSI-2 source, and ports 1 - through 4 are output ports connecting with parallel - bus sink endpoint nodes and correspond to the four - MIPI CSI-2 virtual channel outputs. - -Optional properties: -- interrupts : must contain two level-triggered interrupts, - in order: 100 and 101; diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-fg.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-fg.yaml index 03f31b009085..40fda59fa8a8 100644 --- a/Documentation/devicetree/bindings/media/mediatek,mdp3-fg.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-fg.yaml @@ -16,8 +16,12 @@ description: properties: compatible: - enum: - - mediatek,mt8195-mdp3-fg + oneOf: + - enum: + - mediatek,mt8195-mdp3-fg + - items: + - const: mediatek,mt8188-mdp3-fg + - const: mediatek,mt8195-mdp3-fg reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-hdr.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-hdr.yaml index d4609bba6578..d9f926c20220 100644 --- a/Documentation/devicetree/bindings/media/mediatek,mdp3-hdr.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-hdr.yaml @@ -16,8 +16,12 @@ description: properties: compatible: - enum: - - mediatek,mt8195-mdp3-hdr + oneOf: + - enum: + - mediatek,mt8195-mdp3-hdr + - items: + - const: mediatek,mt8188-mdp3-hdr + - const: mediatek,mt8195-mdp3-hdr reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml index f5676bec4326..8124c39d73e9 100644 --- a/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml @@ -20,6 +20,7 @@ properties: - mediatek,mt8183-mdp3-rsz - items: - enum: + - mediatek,mt8188-mdp3-rsz - mediatek,mt8195-mdp3-rsz - const: mediatek,mt8183-mdp3-rsz diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-stitch.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-stitch.yaml index d815bea29154..1d8e7e202c42 100644 --- a/Documentation/devicetree/bindings/media/mediatek,mdp3-stitch.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-stitch.yaml @@ -16,8 +16,12 @@ description: properties: compatible: - enum: - - mediatek,mt8195-mdp3-stitch + oneOf: + - enum: + - mediatek,mt8195-mdp3-stitch + - items: + - const: mediatek,mt8188-mdp3-stitch + - const: mediatek,mt8195-mdp3-stitch reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml index 14ea556d4f82..6cff7c073ce4 100644 --- a/Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml @@ -17,8 +17,12 @@ description: properties: compatible: - enum: - - mediatek,mt8195-mdp3-tcc + oneOf: + - enum: + - mediatek,mt8195-mdp3-tcc + - items: + - const: mediatek,mt8188-mdp3-tcc + - const: mediatek,mt8195-mdp3-tcc reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-tdshp.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-tdshp.yaml index 8ab7f2d8e148..cdfa27324738 100644 --- a/Documentation/devicetree/bindings/media/mediatek,mdp3-tdshp.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-tdshp.yaml @@ -16,8 +16,12 @@ description: properties: compatible: - enum: - - mediatek,mt8195-mdp3-tdshp + oneOf: + - enum: + - mediatek,mt8195-mdp3-tdshp + - items: + - const: mediatek,mt8188-mdp3-tdshp + - const: mediatek,mt8195-mdp3-tdshp reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml index 53a679338402..b6269f4f9fd6 100644 --- a/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml @@ -20,6 +20,7 @@ properties: - mediatek,mt8183-mdp3-wrot - items: - enum: + - mediatek,mt8188-mdp3-wrot - mediatek,mt8195-mdp3-wrot - const: mediatek,mt8183-mdp3-wrot diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml index 110e8f5f1f9e..ebc615584f92 100644 --- a/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml @@ -41,10 +41,6 @@ properties: minItems: 1 maxItems: 5 - assigned-clocks: true - - assigned-clock-parents: true - iommus: minItems: 1 maxItems: 32 @@ -78,8 +74,6 @@ required: - clocks - clock-names - iommus - - assigned-clocks - - assigned-clock-parents allOf: - if: diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml index 5865e6f0be89..bf8082d87ac0 100644 --- a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml @@ -4,52 +4,70 @@ $id: http://devicetree.org/schemas/media/mediatek,vcodec-subdev-decoder.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Mediatek Video Decode Accelerator With Multi Hardware +title: MediaTek Video Decode Accelerator With Multi Hardware maintainers: - Yunfei Dong <yunfei.dong@mediatek.com> description: | - Mediatek Video Decode is the video decode hardware present in Mediatek - SoCs which supports high resolution decoding functionalities. Required - parent and child device node. - - About the Decoder Hardware Block Diagram, please check below: - - +------------------------------------------------+-------------------------------------+ - | | | - | input -> lat soc HW -> lat HW -> lat buffer --|--> lat buffer -> core HW -> output | - | || || | || | - +------------||-------------||-------------------+---------------------||--------------+ - || lat || | core workqueue <parent> - -------------||-------------||-------------------|---------------------||--------------- - ||<------------||----------------HW index---------------->|| <child> - \/ \/ \/ - +-------------------------------------------------------------+ - | enable/disable | - | clk power irq iommu | - | (lat/lat soc/core0/core1) | - +-------------------------------------------------------------+ - - As above, there are parent and child devices, child mean each hardware. The child device - controls the information of each hardware independent which include clk/power/irq. - - There are two workqueues in parent device: lat workqueue and core workqueue. They are used - to lat and core hardware decoder. Lat workqueue need to get input bitstream and lat buffer, - then enable lat to decode, writing the result to lat buffer, dislabe hardware when lat decode - done. Core workqueue need to get lat buffer and output buffer, then enable core to decode, - writing the result to output buffer, disable hardware when core decode done. These two - hardwares will decode each frame cyclically. - - For the smi common may not the same for each hardware, can't combine all hardware in one node, - or leading to iommu fault when access dram data. - - Lat soc is a hardware which is related with some larb(local arbiter) ports. For mt8195 - platform, there are some ports like RDMA, UFO in lat soc larb, need to enable its power and - clock when lat start to work, don't have interrupt. - - mt8195: lat soc HW + lat HW + core HW - mt8192: lat HW + core HW + MediaTek Video Decode Accelerator is the video decoding hardware present in + MediaTek SoCs that supports high-resolution decoding functionalities. + It consists of parent and child nodes. + + The decoder hardware block diagram is shown below: + + +------------------------------------------------+------------------------------+ + | | | + | input -> LAT-SoC HW -> LAT HW -> LAT buffer --|--> Core HW -> output buffer | + | || || | || | + +--------------||-----------||-------------------+-------||---------------------+ + LAT Workqueue | Core Workqueue <parent> + ---------------||-----------||-------------------|-------||---------------------- + ||<----------||---------HW index--------->|| <child> + \/ \/ \/ + +-------------------------------------------------------------+ + | enable/disable | + | clk power irq iommu | + | (lat/lat-soc/core0/core1) | + +-------------------------------------------------------------+ + + The child nodes represent the individual hardware blocks within the decoding + pipeline, such as LAT-SoC, LAT and Core. + Each child node is responsible for managing the dedicated resources of the + hardware, such as clocks, power domains, interrupts and IOMMUs. + + The parent node is a central point of control for the child nodes. + It identifies the specific video decoding pipeline architecture used by the + SoC, manages the shared resources like workqueues and platform data, and + handles V4L2 API calls on behalf of the underlying hardware. + + The parent utilizes two workqueues to manage the decoding process. + 1. LAT Workqueue, for LAT-SoC and LAT decoder: + Its workers take input bitstream and LAT buffer, enable the hardware for + decoding tasks, write the result to LAT buffer, and disable the hardware + after the LAT decoding is done. + 2. Core Workqueue, for Core decoder: + Its workers take LAT buffer and output buffer, enable the hardware for + decoding tasks, write the result to output buffer, and disable the hardware + after the Core decoding is done. + + These hardware decode each frame cyclically. + + The hardware might be associated with different SMI-common devices. + To prevent IOMMU faults during DRAM access in such cases, each hardware with + the unique SMI-common device must be placed under a separate parent node in + the device tree. + + LAT-SoC refers to another hardware block that connected to additional LARB + (local arbiter) ports, such as RDMA and UFO. + It requires independent power and clock control to work with LAT decoder, and + it doesn't have a dedicated interrupt. + + The used video decoding pipeline architecture across various Mediatek SoC: + MT8195: LAT-SoC + LAT + Core + MT8192: LAT + Core + MT8188: LAT + Core + MT8186: Core properties: compatible: diff --git a/Documentation/devicetree/bindings/media/mediatek-jpeg-decoder.yaml b/Documentation/devicetree/bindings/media/mediatek-jpeg-decoder.yaml index cfabf360f278..a4aacd3eb189 100644 --- a/Documentation/devicetree/bindings/media/mediatek-jpeg-decoder.yaml +++ b/Documentation/devicetree/bindings/media/mediatek-jpeg-decoder.yaml @@ -44,7 +44,8 @@ properties: maxItems: 1 iommus: - maxItems: 2 + minItems: 2 + maxItems: 32 description: | Points to the respective IOMMU block with master port as argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details. diff --git a/Documentation/devicetree/bindings/media/mediatek-jpeg-encoder.yaml b/Documentation/devicetree/bindings/media/mediatek-jpeg-encoder.yaml index 83c020a673d6..5b15f8977f67 100644 --- a/Documentation/devicetree/bindings/media/mediatek-jpeg-encoder.yaml +++ b/Documentation/devicetree/bindings/media/mediatek-jpeg-encoder.yaml @@ -39,7 +39,7 @@ properties: iommus: minItems: 2 - maxItems: 4 + maxItems: 32 description: | Points to the respective IOMMU block with master port as argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details. diff --git a/Documentation/devicetree/bindings/media/qcom,msm8916-camss.yaml b/Documentation/devicetree/bindings/media/qcom,msm8916-camss.yaml index 3469a43f00d4..7c8e0a905d89 100644 --- a/Documentation/devicetree/bindings/media/qcom,msm8916-camss.yaml +++ b/Documentation/devicetree/bindings/media/qcom,msm8916-camss.yaml @@ -93,6 +93,10 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - data-lanes @@ -112,6 +116,10 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - data-lanes diff --git a/Documentation/devicetree/bindings/media/qcom,msm8953-camss.yaml b/Documentation/devicetree/bindings/media/qcom,msm8953-camss.yaml index 8856fba385b1..6d776b0ca711 100644 --- a/Documentation/devicetree/bindings/media/qcom,msm8953-camss.yaml +++ b/Documentation/devicetree/bindings/media/qcom,msm8953-camss.yaml @@ -112,6 +112,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - data-lanes @@ -131,6 +136,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - data-lanes @@ -150,6 +160,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - data-lanes diff --git a/Documentation/devicetree/bindings/media/qcom,msm8996-camss.yaml b/Documentation/devicetree/bindings/media/qcom,msm8996-camss.yaml index 644646de338a..a2025952fe95 100644 --- a/Documentation/devicetree/bindings/media/qcom,msm8996-camss.yaml +++ b/Documentation/devicetree/bindings/media/qcom,msm8996-camss.yaml @@ -115,6 +115,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - data-lanes @@ -134,6 +139,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - data-lanes @@ -153,6 +163,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - data-lanes @@ -172,6 +187,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - data-lanes diff --git a/Documentation/devicetree/bindings/media/qcom,sc7180-venus.yaml b/Documentation/devicetree/bindings/media/qcom,sc7180-venus.yaml index 83c4a5d95f02..bfd8b1ad4731 100644 --- a/Documentation/devicetree/bindings/media/qcom,sc7180-venus.yaml +++ b/Documentation/devicetree/bindings/media/qcom,sc7180-venus.yaml @@ -18,7 +18,12 @@ allOf: properties: compatible: - const: qcom,sc7180-venus + oneOf: + - items: + - enum: + - qcom,qcs615-venus + - const: qcom,sc7180-venus + - const: qcom,sc7180-venus power-domains: minItems: 2 diff --git a/Documentation/devicetree/bindings/media/qcom,sc7280-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sc7280-camss.yaml index e11141b812a0..ee35e3bc97ff 100644 --- a/Documentation/devicetree/bindings/media/qcom,sc7280-camss.yaml +++ b/Documentation/devicetree/bindings/media/qcom,sc7280-camss.yaml @@ -55,8 +55,8 @@ properties: - const: csiphy3_timer - const: csiphy4 - const: csiphy4_timer - - const: gcc_camera_ahb - - const: gcc_cam_hf_axi + - const: gcc_axi_hf + - const: gcc_axi_sf - const: icp_ahb - const: vfe0 - const: vfe0_axi @@ -310,8 +310,8 @@ examples: <&camcc CAM_CC_CSI3PHYTIMER_CLK>, <&camcc CAM_CC_CSIPHY4_CLK>, <&camcc CAM_CC_CSI4PHYTIMER_CLK>, - <&gcc GCC_CAMERA_AHB_CLK>, <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&gcc GCC_CAMERA_SF_AXI_CLK>, <&camcc CAM_CC_ICP_AHB_CLK>, <&camcc CAM_CC_IFE_0_CLK>, <&camcc CAM_CC_IFE_0_AXI_CLK>, @@ -343,8 +343,8 @@ examples: "csiphy3_timer", "csiphy4", "csiphy4_timer", - "gcc_camera_ahb", - "gcc_cam_hf_axi", + "gcc_axi_hf", + "gcc_axi_sf", "icp_ahb", "vfe0", "vfe0_axi", diff --git a/Documentation/devicetree/bindings/media/qcom,sc8280xp-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sc8280xp-camss.yaml index 9936f0132417..d195f1bfb23d 100644 --- a/Documentation/devicetree/bindings/media/qcom,sc8280xp-camss.yaml +++ b/Documentation/devicetree/bindings/media/qcom,sc8280xp-camss.yaml @@ -143,6 +143,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - clock-lanes - data-lanes @@ -166,6 +171,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - clock-lanes - data-lanes @@ -189,6 +199,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - clock-lanes - data-lanes @@ -212,6 +227,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - clock-lanes - data-lanes diff --git a/Documentation/devicetree/bindings/media/qcom,sdm660-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sdm660-camss.yaml index 68d8670557f5..6e6ad8390e44 100644 --- a/Documentation/devicetree/bindings/media/qcom,sdm660-camss.yaml +++ b/Documentation/devicetree/bindings/media/qcom,sdm660-camss.yaml @@ -121,6 +121,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - data-lanes @@ -140,6 +145,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - data-lanes @@ -159,6 +169,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - data-lanes @@ -178,6 +193,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - data-lanes diff --git a/Documentation/devicetree/bindings/media/qcom,sdm670-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sdm670-camss.yaml new file mode 100644 index 000000000000..35c40fe22376 --- /dev/null +++ b/Documentation/devicetree/bindings/media/qcom,sdm670-camss.yaml @@ -0,0 +1,318 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,sdm670-camss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SDM670 Camera Subsystem (CAMSS) + +maintainers: + - Richard Acayan <mailingradian@gmail.com> + +description: + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms. + +properties: + compatible: + const: qcom,sdm670-camss + + reg: + maxItems: 9 + + reg-names: + items: + - const: csid0 + - const: csid1 + - const: csid2 + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: vfe0 + - const: vfe1 + - const: vfe_lite + + interrupts: + maxItems: 9 + + interrupt-names: + items: + - const: csid0 + - const: csid1 + - const: csid2 + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: vfe0 + - const: vfe1 + - const: vfe_lite + + clocks: + maxItems: 22 + + clock-names: + items: + - const: camnoc_axi + - const: cpas_ahb + - const: csi0 + - const: csi1 + - const: csi2 + - const: csiphy0 + - const: csiphy0_timer + - const: csiphy1 + - const: csiphy1_timer + - const: csiphy2 + - const: csiphy2_timer + - const: gcc_camera_ahb + - const: gcc_camera_axi + - const: soc_ahb + - const: vfe0 + - const: vfe0_axi + - const: vfe0_cphy_rx + - const: vfe1 + - const: vfe1_axi + - const: vfe1_cphy_rx + - const: vfe_lite + - const: vfe_lite_cphy_rx + + iommus: + maxItems: 4 + + power-domains: + items: + - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller. + - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller. + - description: Titan Top GDSC - Titan ISP Block, Global Distributed Switch Controller. + + power-domain-names: + items: + - const: ife0 + - const: ife1 + - const: top + + vdda-phy-supply: + description: + Phandle to a regulator supply to PHY core block. + + vdda-pll-supply: + description: + Phandle to 1.8V regulator supply to PHY refclk pll block. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + description: + CSI input ports. + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data from CSIPHY0. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - clock-lanes + - data-lanes + + port@1: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data from CSIPHY1. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - clock-lanes + - data-lanes + + port@2: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data from CSIPHY2. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - clock-lanes + - data-lanes + +required: + - compatible + - reg + - reg-names + - interrupts + - interrupt-names + - clocks + - clock-names + - iommus + - power-domains + - power-domain-names + - vdda-phy-supply + - vdda-pll-supply + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,camcc-sdm845.h> + #include <dt-bindings/clock/qcom,gcc-sdm845.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + isp@acb3000 { + compatible = "qcom,sdm670-camss"; + + reg = <0 0x0acb3000 0 0x1000>, + <0 0x0acba000 0 0x1000>, + <0 0x0acc8000 0 0x1000>, + <0 0x0ac65000 0 0x1000>, + <0 0x0ac66000 0 0x1000>, + <0 0x0ac67000 0 0x1000>, + <0 0x0acaf000 0 0x4000>, + <0 0x0acb6000 0 0x4000>, + <0 0x0acc4000 0 0x4000>; + reg-names = "csid0", + "csid1", + "csid2", + "csiphy0", + "csiphy1", + "csiphy2", + "vfe0", + "vfe1", + "vfe_lite"; + + interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "csid0", + "csid1", + "csid2", + "csiphy0", + "csiphy1", + "csiphy2", + "vfe0", + "vfe1", + "vfe_lite"; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_IFE_0_CSID_CLK>, + <&camcc CAM_CC_IFE_1_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, + <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_AXI_CLK>, + <&camcc CAM_CC_SOC_AHB_CLK>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_AXI_CLK>, + <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_AXI_CLK>, + <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>; + clock-names = "camnoc_axi", + "cpas_ahb", + "csi0", + "csi1", + "csi2", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "gcc_camera_ahb", + "gcc_camera_axi", + "soc_ahb", + "vfe0", + "vfe0_axi", + "vfe0_cphy_rx", + "vfe1", + "vfe1_axi", + "vfe1_cphy_rx", + "vfe_lite", + "vfe_lite_cphy_rx"; + + iommus = <&apps_smmu 0x808 0x0>, + <&apps_smmu 0x810 0x8>, + <&apps_smmu 0xc08 0x0>, + <&apps_smmu 0xc10 0x8>; + + power-domains = <&camcc IFE_0_GDSC>, + <&camcc IFE_1_GDSC>, + <&camcc TITAN_TOP_GDSC>; + power-domain-names = "ife0", + "ife1", + "top"; + + vdda-phy-supply = <&vreg_l1a_1p225>; + vdda-pll-supply = <&vreg_l8a_1p8>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + csiphy_ep0: endpoint { + clock-lanes = <7>; + data-lanes = <0 1 2 3>; + remote-endpoint = <&front_sensor_ep>; + }; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/media/qcom,sdm845-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sdm845-camss.yaml index 289494f561e5..82bf4689d330 100644 --- a/Documentation/devicetree/bindings/media/qcom,sdm845-camss.yaml +++ b/Documentation/devicetree/bindings/media/qcom,sdm845-camss.yaml @@ -108,6 +108,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - data-lanes @@ -127,6 +132,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - data-lanes @@ -146,6 +156,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - data-lanes @@ -165,6 +180,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - data-lanes diff --git a/Documentation/devicetree/bindings/media/qcom,sm8250-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sm8250-camss.yaml index a372d991e652..ebf68ff4ab96 100644 --- a/Documentation/devicetree/bindings/media/qcom,sm8250-camss.yaml +++ b/Documentation/devicetree/bindings/media/qcom,sm8250-camss.yaml @@ -128,6 +128,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - clock-lanes - data-lanes @@ -151,6 +156,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - clock-lanes - data-lanes @@ -174,6 +184,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - clock-lanes - data-lanes @@ -197,6 +212,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - clock-lanes - data-lanes @@ -220,6 +240,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - clock-lanes - data-lanes @@ -243,6 +268,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - clock-lanes - data-lanes diff --git a/Documentation/devicetree/bindings/media/qcom,sm8550-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sm8550-camss.yaml new file mode 100644 index 000000000000..cd34f14916b4 --- /dev/null +++ b/Documentation/devicetree/bindings/media/qcom,sm8550-camss.yaml @@ -0,0 +1,597 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,sm8550-camss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8550 Camera Subsystem (CAMSS) + +maintainers: + - Depeng Shao <quic_depengs@quicinc.com> + +description: + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms. + +properties: + compatible: + const: qcom,sm8550-camss + + reg: + maxItems: 19 + + reg-names: + items: + - const: csid0 + - const: csid1 + - const: csid2 + - const: csid_lite0 + - const: csid_lite1 + - const: csid_wrapper + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: csiphy3 + - const: csiphy4 + - const: csiphy5 + - const: csiphy6 + - const: csiphy7 + - const: vfe0 + - const: vfe1 + - const: vfe2 + - const: vfe_lite0 + - const: vfe_lite1 + + clocks: + maxItems: 36 + + clock-names: + items: + - const: camnoc_axi + - const: cpas_ahb + - const: cpas_fast_ahb_clk + - const: cpas_ife_lite + - const: cpas_vfe0 + - const: cpas_vfe1 + - const: cpas_vfe2 + - const: csid + - const: csiphy0 + - const: csiphy0_timer + - const: csiphy1 + - const: csiphy1_timer + - const: csiphy2 + - const: csiphy2_timer + - const: csiphy3 + - const: csiphy3_timer + - const: csiphy4 + - const: csiphy4_timer + - const: csiphy5 + - const: csiphy5_timer + - const: csiphy6 + - const: csiphy6_timer + - const: csiphy7 + - const: csiphy7_timer + - const: csiphy_rx + - const: gcc_axi_hf + - const: vfe0 + - const: vfe0_fast_ahb + - const: vfe1 + - const: vfe1_fast_ahb + - const: vfe2 + - const: vfe2_fast_ahb + - const: vfe_lite + - const: vfe_lite_ahb + - const: vfe_lite_cphy_rx + - const: vfe_lite_csid + + interrupts: + maxItems: 18 + + interrupt-names: + items: + - const: csid0 + - const: csid1 + - const: csid2 + - const: csid_lite0 + - const: csid_lite1 + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: csiphy3 + - const: csiphy4 + - const: csiphy5 + - const: csiphy6 + - const: csiphy7 + - const: vfe0 + - const: vfe1 + - const: vfe2 + - const: vfe_lite0 + - const: vfe_lite1 + + interconnects: + maxItems: 2 + + interconnect-names: + items: + - const: ahb + - const: hf_0_mnoc + + iommus: + maxItems: 1 + + power-domains: + items: + - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller. + - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller. + - description: IFE2 GDSC - Image Front End, Global Distributed Switch Controller. + - description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller. + + power-domain-names: + items: + - const: ife0 + - const: ife1 + - const: ife2 + - const: top + + vdda-phy-supply: + description: + Phandle to a regulator supply to PHY core block. + + vdda-pll-supply: + description: + Phandle to 1.2V regulator supply to PHY refclk pll block. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + description: + CSI input ports. + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data on CSI0. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + + required: + - clock-lanes + - data-lanes + + port@1: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data on CSI1. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + + required: + - clock-lanes + - data-lanes + + port@2: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data on CSI2. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + + required: + - clock-lanes + - data-lanes + + port@3: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data on CSI3. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + + required: + - clock-lanes + - data-lanes + + port@4: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data on CSI4. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + + required: + - clock-lanes + - data-lanes + + port@5: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data on CSI5. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + + required: + - clock-lanes + - data-lanes + + port@6: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data on CSI6. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + + required: + - clock-lanes + - data-lanes + + port@7: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data on CSI7. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + + required: + - clock-lanes + - data-lanes + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - interrupts + - interrupt-names + - interconnects + - interconnect-names + - iommus + - power-domains + - power-domain-names + - vdda-phy-supply + - vdda-pll-supply + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/clock/qcom,sm8550-camcc.h> + #include <dt-bindings/clock/qcom,sm8550-gcc.h> + #include <dt-bindings/interconnect/qcom,icc.h> + #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + isp@acb7000 { + compatible = "qcom,sm8550-camss"; + + reg = <0 0x0acb7000 0 0xd00>, + <0 0x0acb9000 0 0xd00>, + <0 0x0acbb000 0 0xd00>, + <0 0x0acca000 0 0xa00>, + <0 0x0acce000 0 0xa00>, + <0 0x0acb6000 0 0x1000>, + <0 0x0ace4000 0 0x2000>, + <0 0x0ace6000 0 0x2000>, + <0 0x0ace8000 0 0x2000>, + <0 0x0acea000 0 0x2000>, + <0 0x0acec000 0 0x2000>, + <0 0x0acee000 0 0x2000>, + <0 0x0acf0000 0 0x2000>, + <0 0x0acf2000 0 0x2000>, + <0 0x0ac62000 0 0xf000>, + <0 0x0ac71000 0 0xf000>, + <0 0x0ac80000 0 0xf000>, + <0 0x0accb000 0 0x1800>, + <0 0x0accf000 0 0x1800>; + reg-names = "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csid_wrapper", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "csiphy4", + "csiphy5", + "csiphy6", + "csiphy7", + "vfe0", + "vfe1", + "vfe2", + "vfe_lite0", + "vfe_lite1"; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, + <&camcc CAM_CC_CPAS_IFE_0_CLK>, + <&camcc CAM_CC_CPAS_IFE_1_CLK>, + <&camcc CAM_CC_CPAS_IFE_2_CLK>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY3_CLK>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY4_CLK>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY5_CLK>, + <&camcc CAM_CC_CSI5PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY6_CLK>, + <&camcc CAM_CC_CSI6PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY7_CLK>, + <&camcc CAM_CC_CSI7PHYTIMER_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_2_CLK>, + <&camcc CAM_CC_IFE_2_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>; + clock-names = "camnoc_axi", + "cpas_ahb", + "cpas_fast_ahb_clk", + "cpas_ife_lite", + "cpas_vfe0", + "cpas_vfe1", + "cpas_vfe2", + "csid", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "csiphy3", + "csiphy3_timer", + "csiphy4", + "csiphy4_timer", + "csiphy5", + "csiphy5_timer", + "csiphy6", + "csiphy6_timer", + "csiphy7", + "csiphy7_timer", + "csiphy_rx", + "gcc_axi_hf", + "vfe0", + "vfe0_fast_ahb", + "vfe1", + "vfe1_fast_ahb", + "vfe2", + "vfe2_fast_ahb", + "vfe_lite", + "vfe_lite_ahb", + "vfe_lite_cphy_rx", + "vfe_lite_csid"; + + interrupts = <GIC_SPI 601 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 603 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 431 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 605 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 278 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 602 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 604 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 688 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 606 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "csiphy4", + "csiphy5", + "csiphy6", + "csiphy7", + "vfe0", + "vfe1", + "vfe2", + "vfe_lite0", + "vfe_lite1"; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "ahb", + "hf_0_mnoc"; + + iommus = <&apps_smmu 0x800 0x20>; + + power-domains = <&camcc CAM_CC_IFE_0_GDSC>, + <&camcc CAM_CC_IFE_1_GDSC>, + <&camcc CAM_CC_IFE_2_GDSC>, + <&camcc CAM_CC_TITAN_TOP_GDSC>; + power-domain-names = "ife0", + "ife1", + "ife2", + "top"; + + vdda-phy-supply = <&vreg_l1e_0p88>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + csiphy_ep0: endpoint@0 { + reg = <0>; + clock-lanes = <7>; + data-lanes = <0 1>; + remote-endpoint = <&sensor_ep>; + }; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml b/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml new file mode 100644 index 000000000000..c79bf2101812 --- /dev/null +++ b/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml @@ -0,0 +1,187 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,sm8550-iris.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm iris video encode and decode accelerators + +maintainers: + - Vikash Garodia <quic_vgarodia@quicinc.com> + - Dikshita Agarwal <quic_dikshita@quicinc.com> + +description: + The iris video processing unit is a video encode and decode accelerator + present on Qualcomm platforms. + +properties: + compatible: + oneOf: + - items: + - enum: + - qcom,sa8775p-iris + - const: qcom,sm8550-iris + - enum: + - qcom,qcs8300-iris + - qcom,sm8550-iris + - qcom,sm8650-iris + + power-domains: + maxItems: 4 + + power-domain-names: + items: + - const: venus + - const: vcodec0 + - const: mxc + - const: mmcx + + clocks: + maxItems: 3 + + clock-names: + items: + - const: iface + - const: core + - const: vcodec0_core + + interconnects: + maxItems: 2 + + interconnect-names: + items: + - const: cpu-cfg + - const: video-mem + + resets: + minItems: 1 + maxItems: 3 + + reset-names: + minItems: 1 + items: + - const: bus + - const: xo + - const: core + + iommus: + maxItems: 2 + + dma-coherent: true + + operating-points-v2: true + + opp-table: + type: object + +required: + - compatible + - power-domain-names + - interconnects + - interconnect-names + - resets + - reset-names + - iommus + - dma-coherent + +allOf: + - $ref: qcom,venus-common.yaml# + - if: + properties: + compatible: + enum: + - qcom,sm8650-iris + then: + properties: + resets: + minItems: 3 + reset-names: + minItems: 3 + else: + properties: + resets: + maxItems: 1 + reset-names: + maxItems: 1 + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/clock/qcom,sm8550-gcc.h> + #include <dt-bindings/clock/qcom,sm8450-videocc.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interconnect/qcom,icc.h> + #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h> + #include <dt-bindings/power/qcom-rpmpd.h> + #include <dt-bindings/power/qcom,rpmhpd.h> + + video-codec@aa00000 { + compatible = "qcom,sm8550-iris"; + reg = <0x0aa00000 0xf0000>; + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; + + power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>, + <&videocc VIDEO_CC_MVS0_GDSC>, + <&rpmhpd RPMHPD_MXC>, + <&rpmhpd RPMHPD_MMCX>; + power-domain-names = "venus", "vcodec0", "mxc", "mmcx"; + + clocks = <&gcc GCC_VIDEO_AXI0_CLK>, + <&videocc VIDEO_CC_MVS0C_CLK>, + <&videocc VIDEO_CC_MVS0_CLK>; + clock-names = "iface", "core", "vcodec0_core"; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc MASTER_VIDEO QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "cpu-cfg", "video-mem"; + + memory-region = <&video_mem>; + + resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>; + reset-names = "bus"; + + iommus = <&apps_smmu 0x1940 0x0000>, + <&apps_smmu 0x1947 0x0000>; + dma-coherent; + + operating-points-v2 = <&iris_opp_table>; + + iris_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-240000000 { + opp-hz = /bits/ 64 <240000000>; + required-opps = <&rpmhpd_opp_svs>, + <&rpmhpd_opp_low_svs>; + }; + + opp-338000000 { + opp-hz = /bits/ 64 <338000000>; + required-opps = <&rpmhpd_opp_svs>, + <&rpmhpd_opp_svs>; + }; + + opp-366000000 { + opp-hz = /bits/ 64 <366000000>; + required-opps = <&rpmhpd_opp_svs_l1>, + <&rpmhpd_opp_svs_l1>; + }; + + opp-444000000 { + opp-hz = /bits/ 64 <444000000>; + required-opps = <&rpmhpd_opp_turbo>, + <&rpmhpd_opp_turbo>; + }; + + opp-533333334 { + opp-hz = /bits/ 64 <533333334>; + required-opps = <&rpmhpd_opp_turbo_l1>, + <&rpmhpd_opp_turbo_l1>; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/media/qcom,x1e80100-camss.yaml b/Documentation/devicetree/bindings/media/qcom,x1e80100-camss.yaml new file mode 100644 index 000000000000..113565cf2a99 --- /dev/null +++ b/Documentation/devicetree/bindings/media/qcom,x1e80100-camss.yaml @@ -0,0 +1,367 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,x1e80100-camss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm X1E80100 Camera Subsystem (CAMSS) + +maintainers: + - Bryan O'Donoghue <bryan.odonoghue@linaro.org> + +description: + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms. + +properties: + compatible: + const: qcom,x1e80100-camss + + reg: + maxItems: 17 + + reg-names: + items: + - const: csid0 + - const: csid1 + - const: csid2 + - const: csid_lite0 + - const: csid_lite1 + - const: csid_wrapper + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: csiphy4 + - const: csitpg0 + - const: csitpg1 + - const: csitpg2 + - const: vfe0 + - const: vfe1 + - const: vfe_lite0 + - const: vfe_lite1 + + clocks: + maxItems: 29 + + clock-names: + items: + - const: camnoc_nrt_axi + - const: camnoc_rt_axi + - const: core_ahb + - const: cpas_ahb + - const: cpas_fast_ahb + - const: cpas_vfe0 + - const: cpas_vfe1 + - const: cpas_vfe_lite + - const: cphy_rx_clk_src + - const: csid + - const: csid_csiphy_rx + - const: csiphy0 + - const: csiphy0_timer + - const: csiphy1 + - const: csiphy1_timer + - const: csiphy2 + - const: csiphy2_timer + - const: csiphy4 + - const: csiphy4_timer + - const: gcc_axi_hf + - const: gcc_axi_sf + - const: vfe0 + - const: vfe0_fast_ahb + - const: vfe1 + - const: vfe1_fast_ahb + - const: vfe_lite + - const: vfe_lite_ahb + - const: vfe_lite_cphy_rx + - const: vfe_lite_csid + + interrupts: + maxItems: 13 + + interrupt-names: + items: + - const: csid0 + - const: csid1 + - const: csid2 + - const: csid_lite0 + - const: csid_lite1 + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: csiphy4 + - const: vfe0 + - const: vfe1 + - const: vfe_lite0 + - const: vfe_lite1 + + interconnects: + maxItems: 4 + + interconnect-names: + items: + - const: ahb + - const: hf_mnoc + - const: sf_mnoc + - const: sf_icp_mnoc + + iommus: + maxItems: 8 + + power-domains: + items: + - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller. + - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller. + - description: Titan Top GDSC - Titan ISP Block, Global Distributed Switch Controller. + + power-domain-names: + items: + - const: ife0 + - const: ife1 + - const: top + + vdd-csiphy-0p8-supply: + description: + Phandle to a 0.8V regulator supply to a PHY. + + vdd-csiphy-1p2-supply: + description: + Phandle to 1.8V regulator supply to a PHY. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + description: + CSI input ports. + + patternProperties: + "^port@[0-3]+$": + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + + description: + Input port for receiving CSI data from a CSIPHY. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - clock-lanes + - data-lanes + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - interrupts + - interrupt-names + - interconnects + - interconnect-names + - iommus + - power-domains + - power-domain-names + - vdd-csiphy-0p8-supply + - vdd-csiphy-1p2-supply + - ports + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/qcom,x1e80100-gcc.h> + #include <dt-bindings/clock/qcom,x1e80100-camcc.h> + #include <dt-bindings/interconnect/qcom,icc.h> + #include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + camss: isp@acb6000 { + compatible = "qcom,x1e80100-camss"; + + reg = <0 0x0acb7000 0 0x2000>, + <0 0x0acb9000 0 0x2000>, + <0 0x0acbb000 0 0x2000>, + <0 0x0acc6000 0 0x1000>, + <0 0x0acca000 0 0x1000>, + <0 0x0acb6000 0 0x1000>, + <0 0x0ace4000 0 0x1000>, + <0 0x0ace6000 0 0x1000>, + <0 0x0ace8000 0 0x1000>, + <0 0x0acec000 0 0x4000>, + <0 0x0acf6000 0 0x1000>, + <0 0x0acf7000 0 0x1000>, + <0 0x0acf8000 0 0x1000>, + <0 0x0ac62000 0 0x4000>, + <0 0x0ac71000 0 0x4000>, + <0 0x0acc7000 0 0x2000>, + <0 0x0accb000 0 0x2000>; + + reg-names = "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csid_wrapper", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy4", + "csitpg0", + "csitpg1", + "csitpg2", + "vfe0", + "vfe1", + "vfe_lite0", + "vfe_lite1"; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, + <&camcc CAM_CC_CORE_AHB_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, + <&camcc CAM_CC_CPAS_IFE_0_CLK>, + <&camcc CAM_CC_CPAS_IFE_1_CLK>, + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY4_CLK>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&gcc GCC_CAMERA_SF_AXI_CLK>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>; + + clock-names = "camnoc_nrt_axi", + "camnoc_rt_axi", + "core_ahb", + "cpas_ahb", + "cpas_fast_ahb", + "cpas_vfe0", + "cpas_vfe1", + "cpas_vfe_lite", + "cphy_rx_clk_src", + "csid", + "csid_csiphy_rx", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "csiphy4", + "csiphy4_timer", + "gcc_axi_hf", + "gcc_axi_sf", + "vfe0", + "vfe0_fast_ahb", + "vfe1", + "vfe1_fast_ahb", + "vfe_lite", + "vfe_lite_ahb", + "vfe_lite_cphy_rx", + "vfe_lite_csid"; + + interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 431 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>; + + interrupt-names = "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy4", + "vfe0", + "vfe1", + "vfe_lite0", + "vfe_lite1"; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc MASTER_CAMNOC_ICP QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + + interconnect-names = "ahb", + "hf_mnoc", + "sf_mnoc", + "sf_icp_mnoc"; + + iommus = <&apps_smmu 0x800 0x60>, + <&apps_smmu 0x860 0x60>, + <&apps_smmu 0x1800 0x60>, + <&apps_smmu 0x1860 0x60>, + <&apps_smmu 0x18e0 0x00>, + <&apps_smmu 0x1980 0x20>, + <&apps_smmu 0x1900 0x00>, + <&apps_smmu 0x19a0 0x20>; + + power-domains = <&camcc CAM_CC_IFE_0_GDSC>, + <&camcc CAM_CC_IFE_1_GDSC>, + <&camcc CAM_CC_TITAN_TOP_GDSC>; + + power-domain-names = "ife0", + "ife1", + "top"; + + vdd-csiphy-0p8-supply = <&csiphy_0p8_supply>; + vdd-csiphy-1p2-supply = <&csiphy_1p2_supply>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + csiphy_ep0: endpoint { + clock-lanes = <7>; + data-lanes = <0 1>; + remote-endpoint = <&sensor_ep>; + }; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/media/renesas,fcp.yaml b/Documentation/devicetree/bindings/media/renesas,fcp.yaml index f94dacd96278..7bf1266223e8 100644 --- a/Documentation/devicetree/bindings/media/renesas,fcp.yaml +++ b/Documentation/devicetree/bindings/media/renesas,fcp.yaml @@ -30,14 +30,24 @@ properties: - renesas,r9a07g043u-fcpvd # RZ/G2UL - renesas,r9a07g044-fcpvd # RZ/G2{L,LC} - renesas,r9a07g054-fcpvd # RZ/V2L + - renesas,r9a09g057-fcpvd # RZ/V2H(P) - const: renesas,fcpv # Generic FCP for VSP fallback reg: maxItems: 1 - clocks: true + clocks: + minItems: 1 + items: + - description: Main clock + - description: Register access clock + - description: Video clock - clock-names: true + clock-names: + items: + - const: aclk + - const: pclk + - const: vclk iommus: maxItems: 1 @@ -66,18 +76,11 @@ allOf: - renesas,r9a07g043u-fcpvd - renesas,r9a07g044-fcpvd - renesas,r9a07g054-fcpvd + - renesas,r9a09g057-fcpvd then: properties: clocks: - items: - - description: Main clock - - description: Register access clock - - description: Video clock - clock-names: - items: - - const: aclk - - const: pclk - - const: vclk + minItems: 3 required: - clock-names else: diff --git a/Documentation/devicetree/bindings/media/renesas,isp.yaml b/Documentation/devicetree/bindings/media/renesas,isp.yaml index c4de4555b753..d25e020f5e5e 100644 --- a/Documentation/devicetree/bindings/media/renesas,isp.yaml +++ b/Documentation/devicetree/bindings/media/renesas,isp.yaml @@ -25,19 +25,55 @@ properties: - renesas,r8a779h0-isp # V4M - const: renesas,rcar-gen4-isp # Generic R-Car Gen4 reg: - maxItems: 1 + minItems: 1 + maxItems: 2 + + reg-names: + minItems: 1 + items: + - const: cs + - const: core interrupts: - maxItems: 1 + minItems: 1 + maxItems: 2 + + interrupt-names: + minItems: 1 + items: + - const: cs + - const: core clocks: - maxItems: 1 + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + items: + - const: cs + - const: core power-domains: maxItems: 1 resets: - maxItems: 1 + minItems: 1 + maxItems: 2 + + reset-names: + minItems: 1 + items: + - const: cs + - const: core + + renesas,vspx: + $ref: /schemas/types.yaml#/definitions/phandle + description: + A phandle to the companion VSPX responsible for the Streaming Bridge + functionality. The Streaming Bridge is responsible for feeding image + and configuration data to the ISP when operating in memory-to-memory + mode. ports: $ref: /schemas/graph.yaml#/properties/ports @@ -103,10 +139,14 @@ properties: required: - compatible - reg + - reg-names - interrupts + - interrupt-names - clocks + - clock-names - power-domains - resets + - reset-names - ports additionalProperties: false @@ -119,11 +159,18 @@ examples: isp1: isp@fed20000 { compatible = "renesas,r8a779a0-isp", "renesas,rcar-gen4-isp"; - reg = <0xfed20000 0x10000>; - interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 613>; + reg = <0xfed20000 0x10000>, <0xfee00000 0x100000>; + reg-names = "cs", "core"; + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cs", "core"; + clocks = <&cpg CPG_MOD 613>, <&cpg CPG_MOD 17>; + clock-names = "cs", "core"; power-domains = <&sysc R8A779A0_PD_A3ISP01>; - resets = <&cpg 613>; + resets = <&cpg 613>, <&cpg 17>; + reset-names = "cs", "core"; + + renesas,vspx = <&vspx1>; ports { #address-cells = <1>; diff --git a/Documentation/devicetree/bindings/media/renesas,rzg2l-cru.yaml b/Documentation/devicetree/bindings/media/renesas,rzg2l-cru.yaml index bc1245127025..47e18690fa57 100644 --- a/Documentation/devicetree/bindings/media/renesas,rzg2l-cru.yaml +++ b/Documentation/devicetree/bindings/media/renesas,rzg2l-cru.yaml @@ -17,24 +17,43 @@ description: properties: compatible: - items: - - enum: - - renesas,r9a07g043-cru # RZ/G2UL - - renesas,r9a07g044-cru # RZ/G2{L,LC} - - renesas,r9a07g054-cru # RZ/V2L - - const: renesas,rzg2l-cru + oneOf: + - items: + - enum: + - renesas,r9a07g043-cru # RZ/G2UL + - renesas,r9a07g044-cru # RZ/G2{L,LC} + - renesas,r9a07g054-cru # RZ/V2L + - const: renesas,rzg2l-cru + - const: renesas,r9a09g047-cru # RZ/G3E reg: maxItems: 1 interrupts: - maxItems: 3 + oneOf: + - items: + - description: CRU Interrupt for image_conv + - description: CRU Interrupt for image_conv_err + - description: CRU AXI master error interrupt + - items: + - description: CRU Interrupt for image_conv + - description: CRU AXI master error interrupt + - description: CRU Video Data AXI Master Address 0 Write End interrupt + - description: CRU Statistics data AXI master addr 0 write end interrupt + - description: CRU Video statistics data AXI master addr 0 write end interrupt interrupt-names: - items: - - const: image_conv - - const: image_conv_err - - const: axi_mst_err + oneOf: + - items: + - const: image_conv + - const: image_conv_err + - const: axi_mst_err + - items: + - const: image_conv + - const: axi_mst_err + - const: vd_addr_wend + - const: sd_addr_wend + - const: vsd_addr_wend clocks: items: @@ -109,6 +128,10 @@ allOf: - renesas,r9a07g054-cru then: properties: + interrupts: + maxItems: 3 + interrupt-names: + maxItems: 3 ports: required: - port@0 @@ -122,10 +145,30 @@ allOf: - renesas,r9a07g043-cru then: properties: + interrupts: + maxItems: 3 + interrupt-names: + maxItems: 3 ports: properties: port@0: false + required: + - port@1 + - if: + properties: + compatible: + contains: + const: renesas,r9a09g047-cru + then: + properties: + interrupts: + minItems: 5 + interrupt-names: + minItems: 5 + ports: + properties: + port@0: false required: - port@1 diff --git a/Documentation/devicetree/bindings/media/renesas,rzg2l-csi2.yaml b/Documentation/devicetree/bindings/media/renesas,rzg2l-csi2.yaml index 7faa12fecd5b..c5c511c9f0db 100644 --- a/Documentation/devicetree/bindings/media/renesas,rzg2l-csi2.yaml +++ b/Documentation/devicetree/bindings/media/renesas,rzg2l-csi2.yaml @@ -17,12 +17,17 @@ description: properties: compatible: - items: - - enum: - - renesas,r9a07g043-csi2 # RZ/G2UL - - renesas,r9a07g044-csi2 # RZ/G2{L,LC} - - renesas,r9a07g054-csi2 # RZ/V2L - - const: renesas,rzg2l-csi2 + oneOf: + - items: + - enum: + - renesas,r9a07g043-csi2 # RZ/G2UL + - renesas,r9a07g044-csi2 # RZ/G2{L,LC} + - renesas,r9a07g054-csi2 # RZ/V2L + - const: renesas,rzg2l-csi2 + - items: + - const: renesas,r9a09g047-csi2 # RZ/G3E + - const: renesas,r9a09g057-csi2 + - const: renesas,r9a09g057-csi2 # RZ/V2H(P) reg: maxItems: 1 @@ -31,16 +36,24 @@ properties: maxItems: 1 clocks: - items: - - description: Internal clock for connecting CRU and MIPI - - description: CRU Main clock - - description: CRU Register access clock + oneOf: + - items: + - description: Internal clock for connecting CRU and MIPI + - description: CRU Main clock + - description: CRU Register access clock + - items: + - description: CRU Main clock + - description: CRU Register access clock clock-names: - items: - - const: system - - const: video - - const: apb + oneOf: + - items: + - const: system + - const: video + - const: apb + - items: + - const: video + - const: apb power-domains: maxItems: 1 @@ -48,7 +61,7 @@ properties: resets: items: - description: CRU_PRESETN reset terminal - - description: CRU_CMN_RSTB reset terminal + - description: D-PHY reset (CRU_CMN_RSTB or CRU_n_S_RESETN) reset-names: items: @@ -101,6 +114,25 @@ required: - reset-names - ports +allOf: + - if: + properties: + compatible: + contains: + const: renesas,r9a09g057-csi2 + then: + properties: + clocks: + maxItems: 2 + clock-names: + maxItems: 2 + else: + properties: + clocks: + minItems: 3 + clock-names: + minItems: 3 + additionalProperties: false examples: diff --git a/Documentation/devicetree/bindings/media/renesas,vsp1.yaml b/Documentation/devicetree/bindings/media/renesas,vsp1.yaml index 1a03e67462a4..fcf7219b1f40 100644 --- a/Documentation/devicetree/bindings/media/renesas,vsp1.yaml +++ b/Documentation/devicetree/bindings/media/renesas,vsp1.yaml @@ -25,6 +25,7 @@ properties: - enum: - renesas,r9a07g043u-vsp2 # RZ/G2UL - renesas,r9a07g054-vsp2 # RZ/V2L + - renesas,r9a09g057-vsp2 # RZ/V2H(P) - const: renesas,r9a07g044-vsp2 # RZ/G2L fallback reg: @@ -33,8 +34,18 @@ properties: interrupts: maxItems: 1 - clocks: true - clock-names: true + clocks: + minItems: 1 + items: + - description: Main clock + - description: Register access clock + - description: Video clock + + clock-names: + items: + - const: aclk + - const: pclk + - const: vclk power-domains: maxItems: 1 @@ -78,15 +89,7 @@ allOf: then: properties: clocks: - items: - - description: Main clock - - description: Register access clock - - description: Video clock - clock-names: - items: - - const: aclk - - const: pclk - - const: vclk + minItems: 3 required: - clock-names else: diff --git a/Documentation/devicetree/bindings/media/snps,dw-hdmi-rx.yaml b/Documentation/devicetree/bindings/media/snps,dw-hdmi-rx.yaml new file mode 100644 index 000000000000..510e94e9ca3a --- /dev/null +++ b/Documentation/devicetree/bindings/media/snps,dw-hdmi-rx.yaml @@ -0,0 +1,132 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Device Tree bindings for Synopsys DesignWare HDMI RX Controller + +--- +$id: http://devicetree.org/schemas/media/snps,dw-hdmi-rx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Synopsys DesignWare HDMI RX Controller + +maintainers: + - Shreeya Patel <shreeya.patel@collabora.com> + +description: + Synopsys DesignWare HDMI Input Controller preset on RK3588 SoCs + allowing devices to receive and decode high-resolution video streams + from external sources like media players, cameras, laptops, etc. + +properties: + compatible: + items: + - const: rockchip,rk3588-hdmirx-ctrler + - const: snps,dw-hdmi-rx + + reg: + maxItems: 1 + + interrupts: + maxItems: 3 + + interrupt-names: + items: + - const: cec + - const: hdmi + - const: dma + + clocks: + maxItems: 7 + + clock-names: + items: + - const: aclk + - const: audio + - const: cr_para + - const: pclk + - const: ref + - const: hclk_s_hdmirx + - const: hclk_vo1 + + power-domains: + maxItems: 1 + + resets: + maxItems: 4 + + reset-names: + items: + - const: axi + - const: apb + - const: ref + - const: biu + + memory-region: + maxItems: 1 + + hpd-gpios: + description: GPIO specifier for HPD. + maxItems: 1 + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + The phandle of the syscon node for the general register file + containing HDMIRX PHY status bits. + + rockchip,vo1-grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + The phandle of the syscon node for the Video Output GRF register + to enable EDID transfer through SDAIN and SCLIN. + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - clock-names + - power-domains + - resets + - pinctrl-0 + - hpd-gpios + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/rockchip,rk3588-cru.h> + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/power/rk3588-power.h> + #include <dt-bindings/reset/rockchip,rk3588-cru.h> + hdmi_receiver: hdmi-receiver@fdee0000 { + compatible = "rockchip,rk3588-hdmirx-ctrler", "snps,dw-hdmi-rx"; + reg = <0xfdee0000 0x6000>; + interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "cec", "hdmi", "dma"; + clocks = <&cru ACLK_HDMIRX>, + <&cru CLK_HDMIRX_AUD>, + <&cru CLK_CR_PARA>, + <&cru PCLK_HDMIRX>, + <&cru CLK_HDMIRX_REF>, + <&cru PCLK_S_HDMIRX>, + <&cru HCLK_VO1>; + clock-names = "aclk", + "audio", + "cr_para", + "pclk", + "ref", + "hclk_s_hdmirx", + "hclk_vo1"; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_A_HDMIRX>, <&cru SRST_P_HDMIRX>, + <&cru SRST_HDMIRX_REF>, <&cru SRST_A_HDMIRX_BIU>; + reset-names = "axi", "apb", "ref", "biu"; + memory-region = <&hdmi_receiver_cma>; + pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_5v_detection>; + pinctrl-names = "default"; + hpd-gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; + }; diff --git a/Documentation/devicetree/bindings/media/st,stm32mp25-csi.yaml b/Documentation/devicetree/bindings/media/st,stm32mp25-csi.yaml index 33bedfe41924..e9fa3cfea5d2 100644 --- a/Documentation/devicetree/bindings/media/st,stm32mp25-csi.yaml +++ b/Documentation/devicetree/bindings/media/st,stm32mp25-csi.yaml @@ -7,8 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 CSI controller description: - The STM32 CSI controller allows connecting a CSI based - camera to the DCMIPP camera pipeline. + The STM32 CSI controller, coupled with a D-PHY allows connecting a CSI-2 + based camera to the DCMIPP camera pipeline. maintainers: - Alain Volmat <alain.volmat@foss.st.com> @@ -109,7 +109,6 @@ examples: endpoint { remote-endpoint = <&imx335_ep>; data-lanes = <1 2>; - bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>; }; }; diff --git a/Documentation/devicetree/bindings/memory-controllers/exynos-srom.yaml b/Documentation/devicetree/bindings/memory-controllers/exynos-srom.yaml index a5598ade399f..1578514ec58d 100644 --- a/Documentation/devicetree/bindings/memory-controllers/exynos-srom.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/exynos-srom.yaml @@ -38,50 +38,16 @@ properties: patternProperties: "^.*@[0-3],[a-f0-9]+$": type: object + $ref: mc-peripheral-props.yaml# additionalProperties: true - description: - The actual device nodes should be added as subnodes to the SROMc node. - These subnodes, in addition to regular device specification, should - contain the following properties, describing configuration - of the relevant SROM bank. properties: - reg: - description: - Bank number, base address (relative to start of the bank) and size - of the memory mapped for the device. Note that base address will be - typically 0 as this is the start of the bank. - maxItems: 1 - reg-io-width: enum: [1, 2] description: Data width in bytes (1 or 2). If omitted, default of 1 is used. - samsung,srom-page-mode: - description: - If page mode is set, 4 data page mode will be configured, - else normal (1 data) page mode will be set. - type: boolean - - samsung,srom-timing: - $ref: /schemas/types.yaml#/definitions/uint32-array - minItems: 6 - maxItems: 6 - description: | - Array of 6 integers, specifying bank timings in the following order: - Tacp, Tcah, Tcoh, Tacc, Tcos, Tacs. - Each value is specified in cycles and has the following meaning - and valid range: - Tacp: Page mode access cycle at Page mode (0 - 15) - Tcah: Address holding time after CSn (0 - 15) - Tcoh: Chip selection hold on OEn (0 - 15) - Tacc: Access cycle (0 - 31, the actual time is N + 1) - Tcos: Chip selection set-up before OEn (0 - 15) - Tacs: Address set-up before CSn (0 - 15) - required: - - reg - samsung,srom-timing required: diff --git a/Documentation/devicetree/bindings/memory-controllers/mc-peripheral-props.yaml b/Documentation/devicetree/bindings/memory-controllers/mc-peripheral-props.yaml index 00deeb09f87d..73a6dac946b7 100644 --- a/Documentation/devicetree/bindings/memory-controllers/mc-peripheral-props.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/mc-peripheral-props.yaml @@ -36,6 +36,8 @@ allOf: - $ref: st,stm32-fmc2-ebi-props.yaml# - $ref: ingenic,nemc-peripherals.yaml# - $ref: intel,ixp4xx-expansion-peripheral-props.yaml# + - $ref: qcom,ebi2-peripheral-props.yaml# + - $ref: samsung,exynos4210-srom-peripheral-props.yaml# - $ref: ti,gpmc-child.yaml# - $ref: fsl/fsl,imx-weim-peripherals.yaml diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml index 2f36ac23604c..0762e0ff66ef 100644 --- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml @@ -33,6 +33,7 @@ properties: - mediatek,mt2712-smi-common - mediatek,mt6779-smi-common - mediatek,mt6795-smi-common + - mediatek,mt6893-smi-common - mediatek,mt8167-smi-common - mediatek,mt8173-smi-common - mediatek,mt8183-smi-common diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml index 2381660b324c..2e7fac4b5094 100644 --- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml @@ -21,6 +21,7 @@ properties: - mediatek,mt2712-smi-larb - mediatek,mt6779-smi-larb - mediatek,mt6795-smi-larb + - mediatek,mt6893-smi-larb - mediatek,mt8167-smi-larb - mediatek,mt8173-smi-larb - mediatek,mt8183-smi-larb diff --git a/Documentation/devicetree/bindings/memory-controllers/qcom,ebi2-peripheral-props.yaml b/Documentation/devicetree/bindings/memory-controllers/qcom,ebi2-peripheral-props.yaml new file mode 100644 index 000000000000..29f8c30e8a88 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/qcom,ebi2-peripheral-props.yaml @@ -0,0 +1,91 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/qcom,ebi2-peripheral-props.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Peripheral Properties for Qualcomm External Bus Interface 2 (EBI2) + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + +properties: + # SLOW chip selects + qcom,xmem-recovery-cycles: + $ref: /schemas/types.yaml#/definitions/uint32 + description: > + The time the memory continues to drive the data bus after OE + is de-asserted, in order to avoid contention on the data bus. + They are inserted when reading one CS and switching to another + CS or read followed by write on the same CS. Minimum value is + actually 1, so a value of 0 will still yield 1 recovery cycle. + minimum: 0 + maximum: 15 + + qcom,xmem-write-hold-cycles: + $ref: /schemas/types.yaml#/definitions/uint32 + description: > + The extra cycles inserted after every write minimum 1. The + data out is driven from the time WE is asserted until CS is + asserted. With a hold of 1 (value = 0), the CS stays active + for 1 extra cycle, etc. + minimum: 0 + maximum: 15 + + qcom,xmem-write-delta-cycles: + $ref: /schemas/types.yaml#/definitions/uint32 + description: > + The initial latency for write cycles inserted for the first + write to a page or burst memory. + minimum: 0 + maximum: 255 + + qcom,xmem-read-delta-cycles: + $ref: /schemas/types.yaml#/definitions/uint32 + description: > + The initial latency for read cycles inserted for the first + read to a page or burst memory. + minimum: 0 + maximum: 255 + + qcom,xmem-write-wait-cycles: + $ref: /schemas/types.yaml#/definitions/uint32 + description: > + The number of wait cycles for every write access. + minimum: 0 + maximum: 15 + + qcom,xmem-read-wait-cycles: + $ref: /schemas/types.yaml#/definitions/uint32 + description: > + The number of wait cycles for every read access. + minimum: 0 + maximum: 15 + + + # FAST chip selects + qcom,xmem-address-hold-enable: + $ref: /schemas/types.yaml#/definitions/uint32 + description: > + Holds the address for an extra cycle to meet hold time + requirements with ADV assertion, when set to 1. + enum: [ 0, 1 ] + + qcom,xmem-adv-to-oe-recovery-cycles: + $ref: /schemas/types.yaml#/definitions/uint32 + description: > + The number of cycles elapsed before an OE assertion, with + respect to the cycle where ADV (address valid) is asserted. + minimum: 0 + maximum: 3 + + qcom,xmem-read-hold-cycles: + $ref: /schemas/types.yaml#/definitions/uint32 + description: > + The length in cycles of the first segment of a read transfer. + For a single read transfer this will be the time from CS + assertion to OE assertion. + minimum: 0 + maximum: 15 + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/bus/qcom,ebi2.yaml b/Documentation/devicetree/bindings/memory-controllers/qcom,ebi2.yaml index 1b1fb3538e6e..423d7a75134f 100644 --- a/Documentation/devicetree/bindings/bus/qcom,ebi2.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/qcom,ebi2.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/bus/qcom,ebi2.yaml# +$id: http://devicetree.org/schemas/memory-controllers/qcom,ebi2.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm External Bus Interface 2 (EBI2) @@ -104,91 +104,8 @@ required: patternProperties: "^.*@[0-5],[0-9a-f]+$": type: object + $ref: mc-peripheral-props.yaml# additionalProperties: true - properties: - reg: - maxItems: 1 - - # SLOW chip selects - qcom,xmem-recovery-cycles: - $ref: /schemas/types.yaml#/definitions/uint32 - description: > - The time the memory continues to drive the data bus after OE - is de-asserted, in order to avoid contention on the data bus. - They are inserted when reading one CS and switching to another - CS or read followed by write on the same CS. Minimum value is - actually 1, so a value of 0 will still yield 1 recovery cycle. - minimum: 0 - maximum: 15 - - qcom,xmem-write-hold-cycles: - $ref: /schemas/types.yaml#/definitions/uint32 - description: > - The extra cycles inserted after every write minimum 1. The - data out is driven from the time WE is asserted until CS is - asserted. With a hold of 1 (value = 0), the CS stays active - for 1 extra cycle, etc. - minimum: 0 - maximum: 15 - - qcom,xmem-write-delta-cycles: - $ref: /schemas/types.yaml#/definitions/uint32 - description: > - The initial latency for write cycles inserted for the first - write to a page or burst memory. - minimum: 0 - maximum: 255 - - qcom,xmem-read-delta-cycles: - $ref: /schemas/types.yaml#/definitions/uint32 - description: > - The initial latency for read cycles inserted for the first - read to a page or burst memory. - minimum: 0 - maximum: 255 - - qcom,xmem-write-wait-cycles: - $ref: /schemas/types.yaml#/definitions/uint32 - description: > - The number of wait cycles for every write access. - minimum: 0 - maximum: 15 - - qcom,xmem-read-wait-cycles: - $ref: /schemas/types.yaml#/definitions/uint32 - description: > - The number of wait cycles for every read access. - minimum: 0 - maximum: 15 - - - # FAST chip selects - qcom,xmem-address-hold-enable: - $ref: /schemas/types.yaml#/definitions/uint32 - description: > - Holds the address for an extra cycle to meet hold time - requirements with ADV assertion, when set to 1. - enum: [ 0, 1 ] - - qcom,xmem-adv-to-oe-recovery-cycles: - $ref: /schemas/types.yaml#/definitions/uint32 - description: > - The number of cycles elapsed before an OE assertion, with - respect to the cycle where ADV (address valid) is asserted. - minimum: 0 - maximum: 3 - - qcom,xmem-read-hold-cycles: - $ref: /schemas/types.yaml#/definitions/uint32 - description: > - The length in cycles of the first segment of a read transfer. - For a single read transfer this will be the time from CS - assertion to OE assertion. - minimum: 0 - maximum: 15 - - required: - - reg additionalProperties: false diff --git a/Documentation/devicetree/bindings/memory-controllers/renesas,rzg3e-xspi.yaml b/Documentation/devicetree/bindings/memory-controllers/renesas,rzg3e-xspi.yaml new file mode 100644 index 000000000000..2bfe63ec62dc --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/renesas,rzg3e-xspi.yaml @@ -0,0 +1,135 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/renesas,rzg3e-xspi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas Expanded Serial Peripheral Interface (xSPI) + +maintainers: + - Biju Das <biju.das.jz@bp.renesas.com> + +description: | + Renesas xSPI allows a SPI flash connected to the SoC to be accessed via + the memory-mapping or the manual command mode. + + The flash chip itself should be represented by a subnode of the XSPI node. + The flash interface is selected based on the "compatible" property of this + subnode: + - "jedec,spi-nor"; + +allOf: + - $ref: /schemas/spi/spi-controller.yaml# + +properties: + compatible: + const: renesas,r9a09g047-xspi # RZ/G3E + + reg: + items: + - description: xSPI registers + - description: direct mapping area + + reg-names: + items: + - const: regs + - const: dirmap + + interrupts: + items: + - description: Interrupt pulse signal by factors excluding errors + - description: Interrupt pulse signal by error factors + + interrupt-names: + items: + - const: pulse + - const: err_pulse + + clocks: + items: + - description: AHB clock + - description: AXI clock + - description: SPI clock + - description: Double speed SPI clock + + clock-names: + items: + - const: ahb + - const: axi + - const: spi + - const: spix2 + + power-domains: + maxItems: 1 + + resets: + items: + - description: Hardware reset + - description: AXI reset + + reset-names: + items: + - const: hresetn + - const: aresetn + + renesas,xspi-cs-addr-sys: + $ref: /schemas/types.yaml#/definitions/phandle + description: | + Phandle to the system controller (sys) that allows to configure + xSPI CS0 and CS1 addresses. + +patternProperties: + "flash@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + contains: + const: jedec,spi-nor + +required: + - compatible + - reg + - reg-names + - interrupts + - interrupt-names + - clocks + - clock-names + - power-domains + - resets + - reset-names + - '#address-cells' + - '#size-cells' + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/renesas,r9a09g047-cpg.h> + + spi@11030000 { + compatible = "renesas,r9a09g047-xspi"; + reg = <0x11030000 0x10000>, <0x20000000 0x10000000>; + reg-names = "regs", "dirmap"; + interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "pulse", "err_pulse"; + clocks = <&cpg CPG_MOD 0x9f>, <&cpg CPG_MOD 0xa0>, + <&cpg CPG_CORE 9>, <&cpg CPG_MOD 0xa1>; + clock-names = "ahb", "axi", "spi", "spix2"; + power-domains = <&cpg>; + resets = <&cpg 0xa3>, <&cpg 0xa4>; + reset-names = "hresetn", "aresetn"; + #address-cells = <1>; + #size-cells = <0>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + }; + }; diff --git a/Documentation/devicetree/bindings/memory-controllers/samsung,exynos4210-srom-peripheral-props.yaml b/Documentation/devicetree/bindings/memory-controllers/samsung,exynos4210-srom-peripheral-props.yaml new file mode 100644 index 000000000000..c474f90846e5 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/samsung,exynos4210-srom-peripheral-props.yaml @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/samsung,exynos4210-srom-peripheral-props.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Peripheral Properties for Samsung Exynos SoC SROM Controller + +maintainers: + - Krzysztof Kozlowski <krzk@kernel.org> + +properties: + samsung,srom-page-mode: + description: + If page mode is set, 4 data page mode will be configured, + else normal (1 data) page mode will be set. + type: boolean + + samsung,srom-timing: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 6 + maxItems: 6 + description: | + Array of 6 integers, specifying bank timings in the following order: + Tacp, Tcah, Tcoh, Tacc, Tcos, Tacs. + Each value is specified in cycles and has the following meaning + and valid range: + Tacp: Page mode access cycle at Page mode (0 - 15) + Tcah: Address holding time after CSn (0 - 15) + Tcoh: Chip selection hold on OEn (0 - 15) + Tacc: Access cycle (0 - 31, the actual time is N + 1) + Tcos: Chip selection set-up before OEn (0 - 15) + Tacs: Address set-up before CSn (0 - 15) + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/memory-controllers/st,stm32mp25-omm.yaml b/Documentation/devicetree/bindings/memory-controllers/st,stm32mp25-omm.yaml new file mode 100644 index 000000000000..344878db8818 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/st,stm32mp25-omm.yaml @@ -0,0 +1,226 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/st,stm32mp25-omm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STM32 Octo Memory Manager (OMM) + +maintainers: + - Patrice Chotard <patrice.chotard@foss.st.com> + +description: | + The STM32 Octo Memory Manager is a low-level interface that enables an + efficient OCTOSPI pin assignment with a full I/O matrix (before alternate + function map) and multiplex of single/dual/quad/octal SPI interfaces over + the same bus. It Supports up to: + - Two single/dual/quad/octal SPI interfaces + - Two ports for pin assignment + +properties: + compatible: + const: st,stm32mp25-omm + + "#address-cells": + const: 2 + + "#size-cells": + const: 1 + + ranges: + description: | + Reflects the memory layout per OSPI instance. + Format: + <chip-select> 0 <registers base address> <size> + minItems: 2 + maxItems: 2 + + reg: + items: + - description: OMM registers + - description: OMM memory map area + + reg-names: + items: + - const: regs + - const: memory_map + + memory-region: + description: + Memory region shared between the 2 OCTOSPI instance. + One or two phandle to a node describing a memory mapped region + depending of child number. + minItems: 1 + maxItems: 2 + + memory-region-names: + description: + Identify to which OSPI instance the memory region belongs to. + items: + enum: [ospi1, ospi2] + minItems: 1 + maxItems: 2 + + clocks: + maxItems: 3 + + clock-names: + items: + - const: omm + - const: ospi1 + - const: ospi2 + + resets: + maxItems: 3 + + reset-names: + items: + - const: omm + - const: ospi1 + - const: ospi2 + + access-controllers: + maxItems: 1 + + power-domains: + maxItems: 1 + + st,syscfg-amcr: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: | + The Address Mapping Control Register (AMCR) is used to split the 256MB + memory map area shared between the 2 OSPI instance. The Octo Memory + Manager sets the AMCR depending of the memory-region configuration. + The memory split bitmask description is: + - 000: OCTOSPI1 (256 Mbytes), OCTOSPI2 unmapped + - 001: OCTOSPI1 (192 Mbytes), OCTOSPI2 (64 Mbytes) + - 010: OCTOSPI1 (128 Mbytes), OCTOSPI2 (128 Mbytes) + - 011: OCTOSPI1 (64 Mbytes), OCTOSPI2 (192 Mbytes) + - 1xx: OCTOSPI1 unmapped, OCTOSPI2 (256 Mbytes) + items: + - items: + - description: phandle to syscfg + - description: register offset within syscfg + - description: register bitmask for memory split + + st,omm-req2ack-ns: + description: + In multiplexed mode (MUXEN = 1), this field defines the time in + nanoseconds between two transactions. + default: 0 + + st,omm-cssel-ovr: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Configure the chip select selector override for the 2 OCTOSPIs. + - 0: OCTOSPI1 chip select send to NCS1 OCTOSPI2 chip select send to NCS1 + - 1: OCTOSPI1 chip select send to NCS2 OCTOSPI2 chip select send to NCS1 + - 2: OCTOSPI1 chip select send to NCS1 OCTOSPI2 chip select send to NCS2 + - 3: OCTOSPI1 chip select send to NCS2 OCTOSPI2 chip select send to NCS2 + minimum: 0 + maximum: 3 + default: 0 + + st,omm-mux: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Configure the muxing between the 2 OCTOSPIs busses and the 2 output ports. + - 0: direct mode + - 1: mux OCTOSPI1 and OCTOSPI2 to port 1 + - 2: swapped mode + - 3: mux OCTOSPI1 and OCTOSPI2 to port 2 + minimum: 0 + maximum: 3 + default: 0 + +patternProperties: + ^spi@[0-9]: + type: object + $ref: /schemas/spi/st,stm32mp25-ospi.yaml# + description: Required spi child node + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - clocks + - clock-names + - resets + - reset-names + - st,syscfg-amcr + - ranges + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/st,stm32mp25-rcc.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/reset/st,stm32mp25-rcc.h> + ommanager@40500000 { + compatible = "st,stm32mp25-omm"; + reg = <0x40500000 0x400>, <0x60000000 0x10000000>; + reg-names = "regs", "memory_map"; + ranges = <0 0 0x40430000 0x400>, + <1 0 0x40440000 0x400>; + memory-region = <&mm_ospi1>, <&mm_ospi2>; + memory-region-names = "ospi1", "ospi2"; + pinctrl-0 = <&ospi_port1_clk_pins_a + &ospi_port1_io03_pins_a + &ospi_port1_cs0_pins_a>; + pinctrl-1 = <&ospi_port1_clk_sleep_pins_a + &ospi_port1_io03_sleep_pins_a + &ospi_port1_cs0_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + clocks = <&rcc CK_BUS_OSPIIOM>, + <&scmi_clk CK_SCMI_OSPI1>, + <&scmi_clk CK_SCMI_OSPI2>; + clock-names = "omm", "ospi1", "ospi2"; + resets = <&rcc OSPIIOM_R>, + <&scmi_reset RST_SCMI_OSPI1>, + <&scmi_reset RST_SCMI_OSPI2>; + reset-names = "omm", "ospi1", "ospi2"; + access-controllers = <&rifsc 111>; + power-domains = <&CLUSTER_PD>; + #address-cells = <2>; + #size-cells = <1>; + st,syscfg-amcr = <&syscfg 0x2c00 0x7>; + st,omm-req2ack-ns = <0>; + st,omm-mux = <0>; + st,omm-cssel-ovr = <0>; + + spi@0 { + compatible = "st,stm32mp25-ospi"; + reg = <0 0 0x400>; + memory-region = <&mm_ospi1>; + interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&hpdma 2 0x62 0x00003121 0x0>, + <&hpdma 2 0x42 0x00003112 0x0>; + dma-names = "tx", "rx"; + clocks = <&scmi_clk CK_SCMI_OSPI1>; + resets = <&scmi_reset RST_SCMI_OSPI1>, <&scmi_reset RST_SCMI_OSPI1DLL>; + access-controllers = <&rifsc 74>; + power-domains = <&CLUSTER_PD>; + #address-cells = <1>; + #size-cells = <0>; + st,syscfg-dlyb = <&syscfg 0x1000>; + }; + + spi@1 { + compatible = "st,stm32mp25-ospi"; + reg = <1 0 0x400>; + memory-region = <&mm_ospi1>; + interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&hpdma 3 0x62 0x00003121 0x0>, + <&hpdma 3 0x42 0x00003112 0x0>; + dma-names = "tx", "rx"; + clocks = <&scmi_clk CK_KER_OSPI2>; + resets = <&scmi_reset RST_SCMI_OSPI2>, <&scmi_reset RST_SCMI_OSPI1DLL>; + access-controllers = <&rifsc 75>; + power-domains = <&CLUSTER_PD>; + #address-cells = <1>; + #size-cells = <0>; + st,syscfg-dlyb = <&syscfg 0x1000>; + }; + }; diff --git a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml index c800d5e53b65..5eccd10d95ce 100644 --- a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml +++ b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml @@ -66,8 +66,15 @@ patternProperties: - compatible '^interrupt-controller@[0-9a-f]+$': - description: See Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2xxx-scu-ic.txt type: object + additionalProperties: true + properties: + compatible: + contains: + enum: + - aspeed,ast2500-scu-ic + - aspeed,ast2600-scu-ic0 + - aspeed,ast2600-scu-ic1 '^silicon-id@[0-9a-f]+$': description: Unique hardware silicon identifiers within the SoC diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml b/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml index 5dfe77aca167..d88854e60b7f 100644 --- a/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml +++ b/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml @@ -1,5 +1,5 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -# # Copyright (c) 2021 Aspeed Tehchnology Inc. +# # Copyright (c) 2021 Aspeed Technology Inc. %YAML 1.2 --- $id: http://devicetree.org/schemas/mfd/aspeed-lpc.yaml# diff --git a/Documentation/devicetree/bindings/mfd/atmel,at91sam9260-gpbr.yaml b/Documentation/devicetree/bindings/mfd/atmel,at91sam9260-gpbr.yaml index f805545aa62a..f6f47999c6c1 100644 --- a/Documentation/devicetree/bindings/mfd/atmel,at91sam9260-gpbr.yaml +++ b/Documentation/devicetree/bindings/mfd/atmel,at91sam9260-gpbr.yaml @@ -19,6 +19,7 @@ properties: - items: - enum: - atmel,at91sam9260-gpbr + - microchip,sama7d65-gpbr - const: syscon - items: - enum: diff --git a/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml b/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml index 0dc6a40b63f4..c7d6cf96796c 100644 --- a/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml +++ b/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml @@ -19,12 +19,11 @@ properties: oneOf: - const: atmel,sama5d2-flexcom - items: - - const: microchip,sam9x7-flexcom + - enum: + - microchip,sam9x7-flexcom + - microchip,sama7d65-flexcom + - microchip,sama7g5-flexcom - const: atmel,sama5d2-flexcom - - items: - - const: microchip,sama7g5-flexcom - - const: atmel,sama5d2-flexcom - reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/mfd/brcm,bcm59056.txt b/Documentation/devicetree/bindings/mfd/brcm,bcm59056.txt deleted file mode 100644 index be51a15e05f9..000000000000 --- a/Documentation/devicetree/bindings/mfd/brcm,bcm59056.txt +++ /dev/null @@ -1,39 +0,0 @@ -------------------------------- -BCM590xx Power Management Units -------------------------------- - -Required properties: -- compatible: "brcm,bcm59056" -- reg: I2C slave address -- interrupts: interrupt for the PMU. Generic interrupt client node bindings - are described in interrupt-controller/interrupts.txt - ------------------- -Voltage Regulators ------------------- - -Optional child nodes: -- regulators: container node for regulators following the generic - regulator binding in regulator/regulator.txt - - The valid regulator node names for BCM59056 are: - rfldo, camldo1, camldo2, simldo1, simldo2, sdldo, sdxldo, - mmcldo1, mmcldo2, audldo, micldo, usbldo, vibldo, - csr, iosr1, iosr2, msr, sdsr1, sdsr2, vsr, - gpldo1, gpldo2, gpldo3, gpldo4, gpldo5, gpldo6, - vbus - -Example: - pmu: bcm59056@8 { - compatible = "brcm,bcm59056"; - reg = <0x08>; - interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; - regulators { - rfldo_reg: rfldo { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3300000>; - }; - - ... - }; - }; diff --git a/Documentation/devicetree/bindings/mfd/brcm,bcm59056.yaml b/Documentation/devicetree/bindings/mfd/brcm,bcm59056.yaml new file mode 100644 index 000000000000..b67d7a723fc2 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/brcm,bcm59056.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/brcm,bcm59056.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom BCM590xx Power Management Units + +maintainers: + - Artur Weber <aweber.kernel@gmail.com> + +properties: + compatible: + enum: + - brcm,bcm59054 + - brcm,bcm59056 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + regulators: + type: object + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +allOf: + - if: + properties: + compatible: + contains: + const: brcm,bcm59054 + then: + properties: + regulators: + $ref: /schemas/regulator/brcm,bcm59054.yaml# + + - if: + properties: + compatible: + contains: + const: brcm,bcm59056 + then: + properties: + regulators: + $ref: /schemas/regulator/brcm,bcm59056.yaml# + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + pmic@8 { + compatible = "brcm,bcm59056"; + reg = <0x08>; + interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; + + regulators { + rfldo { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/mfd/fsl,mcu-mpc8349emitx.yaml b/Documentation/devicetree/bindings/mfd/fsl,mcu-mpc8349emitx.yaml new file mode 100644 index 000000000000..8beb2ed9edb7 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/fsl,mcu-mpc8349emitx.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/fsl,mcu-mpc8349emitx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale MPC8349E-mITX-compatible Power Management Micro Controller Unit (MCU) + +maintainers: + - J. Neuschäfer <j.ne@posteo.net> + +properties: + compatible: + oneOf: + - items: + - enum: + - fsl,mc9s08qg8-mpc8315erdb + - fsl,mc9s08qg8-mpc8349emitx + - fsl,mc9s08qg8-mpc8377erdb + - fsl,mc9s08qg8-mpc8378erdb + - fsl,mc9s08qg8-mpc8379erdb + - const: fsl,mcu-mpc8349emitx + + reg: + maxItems: 1 + + "#gpio-cells": + const: 2 + + gpio-controller: true + +required: + - compatible + - reg + - "#gpio-cells" + - gpio-controller + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + mcu@a { + #gpio-cells = <2>; + compatible = "fsl,mc9s08qg8-mpc8349emitx", + "fsl,mcu-mpc8349emitx"; + reg = <0x0a>; + gpio-controller; + }; + }; diff --git a/Documentation/devicetree/bindings/mfd/iqs62x.yaml b/Documentation/devicetree/bindings/mfd/iqs62x.yaml index e79ce447a800..f242dd0e18fd 100644 --- a/Documentation/devicetree/bindings/mfd/iqs62x.yaml +++ b/Documentation/devicetree/bindings/mfd/iqs62x.yaml @@ -60,43 +60,34 @@ examples: #include <dt-bindings/interrupt-controller/irq.h> i2c { - #address-cells = <1>; - #size-cells = <0>; - - iqs620a@44 { - compatible = "azoteq,iqs620a"; - reg = <0x44>; - interrupt-parent = <&gpio>; - interrupts = <17 IRQ_TYPE_LEVEL_LOW>; - - keys { - compatible = "azoteq,iqs620a-keys"; - - linux,keycodes = <KEY_SELECT>, - <KEY_MENU>, - <KEY_OK>, - <KEY_MENU>; - - hall-switch-south { - linux,code = <SW_LID>; - azoteq,use-prox; - }; - }; - - iqs620a_pwm: pwm { - compatible = "azoteq,iqs620a-pwm"; - #pwm-cells = <2>; - }; + #address-cells = <1>; + #size-cells = <0>; + + iqs620a@44 { + compatible = "azoteq,iqs620a"; + reg = <0x44>; + interrupt-parent = <&gpio>; + interrupts = <17 IRQ_TYPE_LEVEL_LOW>; + + keys { + compatible = "azoteq,iqs620a-keys"; + + linux,keycodes = <KEY_SELECT>, + <KEY_MENU>, + <KEY_OK>, + <KEY_MENU>; + + hall-switch-south { + linux,code = <SW_LID>; + azoteq,use-prox; + }; }; - }; - - pwmleds { - compatible = "pwm-leds"; - led-1 { - pwms = <&iqs620a_pwm 0 1000000>; - max-brightness = <255>; + iqs620a_pwm: pwm { + compatible = "azoteq,iqs620a-pwm"; + #pwm-cells = <2>; }; + }; }; - | @@ -105,37 +96,37 @@ examples: #include <dt-bindings/interrupt-controller/irq.h> i2c { - #address-cells = <1>; - #size-cells = <0>; - - iqs620a@44 { - compatible = "azoteq,iqs620a"; - reg = <0x44>; - interrupt-parent = <&gpio>; - interrupts = <17 IRQ_TYPE_LEVEL_LOW>; - - firmware-name = "iqs620a_coil.bin"; - - keys { - compatible = "azoteq,iqs620a-keys"; - - linux,keycodes = <0>, - <0>, - <0>, - <0>, - <0>, - <0>, - <KEY_MUTE>; - - hall-switch-north { - linux,code = <SW_DOCK>; - }; - - hall-switch-south { - linux,code = <SW_TABLET_MODE>; - }; - }; + #address-cells = <1>; + #size-cells = <0>; + + iqs620a@44 { + compatible = "azoteq,iqs620a"; + reg = <0x44>; + interrupt-parent = <&gpio>; + interrupts = <17 IRQ_TYPE_LEVEL_LOW>; + + firmware-name = "iqs620a_coil.bin"; + + keys { + compatible = "azoteq,iqs620a-keys"; + + linux,keycodes = <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <KEY_MUTE>; + + hall-switch-north { + linux,code = <SW_DOCK>; + }; + + hall-switch-south { + linux,code = <SW_TABLET_MODE>; + }; }; + }; }; - | @@ -144,36 +135,36 @@ examples: #include <dt-bindings/interrupt-controller/irq.h> i2c { - #address-cells = <1>; - #size-cells = <0>; - - iqs624@44 { - compatible = "azoteq,iqs624"; - reg = <0x44>; - interrupt-parent = <&gpio>; - interrupts = <17 IRQ_TYPE_LEVEL_LOW>; - - keys { - compatible = "azoteq,iqs624-keys"; - - linux,keycodes = <BTN_0>, - <0>, - <BTN_1>, - <0>, - <0>, - <0>, - <0>, - <0>, - <0>, - <0>, - <0>, - <0>, - <0>, - <0>, - <KEY_VOLUMEUP>, - <KEY_VOLUMEDOWN>; - }; + #address-cells = <1>; + #size-cells = <0>; + + iqs624@44 { + compatible = "azoteq,iqs624"; + reg = <0x44>; + interrupt-parent = <&gpio>; + interrupts = <17 IRQ_TYPE_LEVEL_LOW>; + + keys { + compatible = "azoteq,iqs624-keys"; + + linux,keycodes = <BTN_0>, + <0>, + <BTN_1>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <KEY_VOLUMEUP>, + <KEY_VOLUMEDOWN>; }; + }; }; ... diff --git a/Documentation/devicetree/bindings/mfd/maxim,max77705.yaml b/Documentation/devicetree/bindings/mfd/maxim,max77705.yaml new file mode 100644 index 000000000000..0ec89f0adc64 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/maxim,max77705.yaml @@ -0,0 +1,158 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/maxim,max77705.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Maxim MAX77705 Companion Power Management and USB Type-C interface + +maintainers: + - Dzmitry Sankouski <dsankouski@gmail.com> + +description: | + This is a part of device tree bindings for Maxim MAX77705. + + Maxim MAX77705 is a Companion Power Management and Type-C + interface IC which includes charger, fuelgauge, LED, haptic motor driver and + Type-C management. + +properties: + compatible: + const: maxim,max77705 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + haptic: + type: object + additionalProperties: false + + properties: + compatible: + const: maxim,max77705-haptic + + haptic-supply: true + + pwms: + maxItems: 1 + + required: + - compatible + - haptic-supply + - pwms + + leds: + type: object + additionalProperties: false + description: + Up to 4 LED channels supported. + + properties: + compatible: + const: maxim,max77705-rgb + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + multi-led: + type: object + $ref: /schemas/leds/leds-class-multicolor.yaml# + unevaluatedProperties: false + + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + patternProperties: + "^led@[0-3]$": + type: object + $ref: /schemas/leds/common.yaml# + unevaluatedProperties: false + + properties: + reg: + maxItems: 1 + + required: + - reg + + patternProperties: + "^led@[0-3]$": + type: object + $ref: /schemas/leds/common.yaml# + unevaluatedProperties: false + + properties: + reg: + maxItems: 1 + + required: + - reg + + required: + - compatible + +required: + - compatible + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/leds/common.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + pmic@66 { + compatible = "maxim,max77705"; + reg = <0x66>; + interrupt-parent = <&pm8998_gpios>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&chg_int_default>; + pinctrl-names = "default"; + + leds { + compatible = "maxim,max77705-rgb"; + + multi-led { + color = <LED_COLOR_ID_RGB>; + function = LED_FUNCTION_STATUS; + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + reg = <1>; + color = <LED_COLOR_ID_RED>; + }; + + led@2 { + reg = <2>; + color = <LED_COLOR_ID_GREEN>; + }; + + led@3 { + reg = <3>; + color = <LED_COLOR_ID_BLUE>; + }; + }; + }; + + haptic { + compatible = "maxim,max77705-haptic"; + haptic-supply = <&vib_regulator>; + pwms = <&vib_pwm 0 50000>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/mfd/maxim,max77759.yaml b/Documentation/devicetree/bindings/mfd/maxim,max77759.yaml new file mode 100644 index 000000000000..525de9ab3c2b --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/maxim,max77759.yaml @@ -0,0 +1,99 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/maxim,max77759.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Maxim Integrated MAX77759 PMIC for USB Type-C applications + +maintainers: + - André Draszik <andre.draszik@linaro.org> + +description: | + This is a part of device tree bindings for the MAX77759 companion Power + Management IC for USB Type-C applications. + + The MAX77759 includes Battery Charger, Fuel Gauge, temperature sensors, USB + Type-C Port Controller (TCPC), NVMEM, and a GPIO expander. + +properties: + compatible: + const: maxim,max77759 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + reg: + maxItems: 1 + + gpio: + $ref: /schemas/gpio/maxim,max77759-gpio.yaml + + nvmem-0: + $ref: /schemas/nvmem/maxim,max77759-nvmem.yaml + +required: + - compatible + - interrupts + - reg + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + pmic@66 { + compatible = "maxim,max77759"; + reg = <0x66>; + interrupts-extended = <&gpa8 3 IRQ_TYPE_LEVEL_LOW>; + + interrupt-controller; + #interrupt-cells = <2>; + + gpio { + compatible = "maxim,max77759-gpio"; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + nvmem-0 { + compatible = "maxim,max77759-nvmem"; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + reboot-mode@0 { + reg = <0x0 0x4>; + }; + + boot-reason@4 { + reg = <0x4 0x4>; + }; + + shutdown-user-flag@8 { + reg = <0x8 0x1>; + }; + + rsoc@10 { + reg = <0xa 0x2>; + }; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml b/Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml index 768390b92682..0e1d43c96fb9 100644 --- a/Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml +++ b/Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml @@ -18,6 +18,7 @@ properties: compatible: items: - enum: + - mediatek,mt6893-scpsys - mediatek,mt8167-scpsys - mediatek,mt8173-scpsys - mediatek,mt8183-scpsys diff --git a/Documentation/devicetree/bindings/mfd/motorola-cpcap.txt b/Documentation/devicetree/bindings/mfd/motorola-cpcap.txt index 190230216de8..f00827c9b67f 100644 --- a/Documentation/devicetree/bindings/mfd/motorola-cpcap.txt +++ b/Documentation/devicetree/bindings/mfd/motorola-cpcap.txt @@ -31,6 +31,10 @@ node must be named "audio-codec". Required properties for the audio-codec subnode: - #sound-dai-cells = <1>; +- interrupts : should contain jack detection interrupts, with headset + detect interrupt matching "hs" and microphone bias 2 + detect interrupt matching "mb2" in interrupt-names. +- interrupt-names : Contains "hs", "mb2" The audio-codec provides two DAIs. The first one is connected to the Stereo HiFi DAC and the second one is connected to the Voice DAC. @@ -52,6 +56,8 @@ Example: audio-codec { #sound-dai-cells = <1>; + interrupts-extended = <&cpcap 9 0>, <&cpcap 10 0>; + interrupt-names = "hs", "mb2"; /* HiFi */ port@0 { diff --git a/Documentation/devicetree/bindings/mfd/mscc,ocelot.yaml b/Documentation/devicetree/bindings/mfd/mscc,ocelot.yaml index 8bd1abfc44d9..b613da83dca4 100644 --- a/Documentation/devicetree/bindings/mfd/mscc,ocelot.yaml +++ b/Documentation/devicetree/bindings/mfd/mscc,ocelot.yaml @@ -76,12 +76,6 @@ additionalProperties: false examples: - | - ocelot_clock: ocelot-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - }; - spi { #address-cells = <1>; #size-cells = <0>; diff --git a/Documentation/devicetree/bindings/mfd/netronix,ntxec.yaml b/Documentation/devicetree/bindings/mfd/netronix,ntxec.yaml index 59a630025f52..37fbb953ea12 100644 --- a/Documentation/devicetree/bindings/mfd/netronix,ntxec.yaml +++ b/Documentation/devicetree/bindings/mfd/netronix,ntxec.yaml @@ -48,29 +48,18 @@ examples: - | #include <dt-bindings/interrupt-controller/irq.h> i2c { - #address-cells = <1>; - #size-cells = <0>; - - ec: embedded-controller@43 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ntxec>; - - compatible = "netronix,ntxec"; - reg = <0x43>; - system-power-controller; - interrupt-parent = <&gpio4>; - interrupts = <11 IRQ_TYPE_EDGE_FALLING>; - #pwm-cells = <2>; - }; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&ec 0 50000>; - power-supply = <&backlight_regulator>; - }; - - backlight_regulator: regulator-dummy { - compatible = "regulator-fixed"; - regulator-name = "backlight"; + #address-cells = <1>; + #size-cells = <0>; + + ec: embedded-controller@43 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ntxec>; + + compatible = "netronix,ntxec"; + reg = <0x43>; + system-power-controller; + interrupt-parent = <&gpio4>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + #pwm-cells = <2>; + }; }; diff --git a/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml b/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml index a503b67f2dbe..14ae3f00ef7e 100644 --- a/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml +++ b/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml @@ -41,6 +41,7 @@ properties: - qcom,sm8450-tcsr - qcom,tcsr-apq8064 - qcom,tcsr-apq8084 + - qcom,tcsr-ipq5018 - qcom,tcsr-ipq5332 - qcom,tcsr-ipq5424 - qcom,tcsr-ipq6018 @@ -52,6 +53,7 @@ properties: - qcom,tcsr-msm8660 - qcom,tcsr-msm8916 - qcom,tcsr-msm8917 + - qcom,tcsr-msm8937 - qcom,tcsr-msm8953 - qcom,tcsr-msm8960 - qcom,tcsr-msm8974 diff --git a/Documentation/devicetree/bindings/mfd/rohm,bd9571mwv.yaml b/Documentation/devicetree/bindings/mfd/rohm,bd9571mwv.yaml index 534cf03f36bb..47611c2a982c 100644 --- a/Documentation/devicetree/bindings/mfd/rohm,bd9571mwv.yaml +++ b/Documentation/devicetree/bindings/mfd/rohm,bd9571mwv.yaml @@ -99,29 +99,29 @@ examples: #include <dt-bindings/interrupt-controller/irq.h> i2c { - #address-cells = <1>; - #size-cells = <0>; - - pmic: pmic@30 { - compatible = "rohm,bd9571mwv"; - reg = <0x30>; - interrupt-parent = <&gpio2>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - rohm,ddr-backup-power = <0xf>; - rohm,rstbmode-pulse; - - regulators { - dvfs: dvfs { - regulator-name = "dvfs"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1030000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; + #address-cells = <1>; + #size-cells = <0>; + + pmic: pmic@30 { + compatible = "rohm,bd9571mwv"; + reg = <0x30>; + interrupt-parent = <&gpio2>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + rohm,ddr-backup-power = <0xf>; + rohm,rstbmode-pulse; + + regulators { + dvfs: dvfs { + regulator-name = "dvfs"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1030000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; }; diff --git a/Documentation/devicetree/bindings/mfd/rohm,bd96801-pmic.yaml b/Documentation/devicetree/bindings/mfd/rohm,bd96801-pmic.yaml index efee3de0d9ad..0e06570483ae 100644 --- a/Documentation/devicetree/bindings/mfd/rohm,bd96801-pmic.yaml +++ b/Documentation/devicetree/bindings/mfd/rohm,bd96801-pmic.yaml @@ -4,19 +4,21 @@ $id: http://devicetree.org/schemas/mfd/rohm,bd96801-pmic.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: ROHM BD96801 Scalable Power Management Integrated Circuit +title: ROHM BD96801/BD96805 Scalable Power Management Integrated Circuit maintainers: - Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> description: - BD96801 is an automotive grade single-chip power management IC. - It integrates 4 buck converters and 3 LDOs with safety features like + BD96801 and BD96805 are automotive grade, single-chip power management ICs. + They both integrate 4 buck converters and 3 LDOs with safety features like over-/under voltage and over current detection and a watchdog. properties: compatible: - const: rohm,bd96801 + enum: + - rohm,bd96801 + - rohm,bd96805 reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/mfd/rohm,bd96802-pmic.yaml b/Documentation/devicetree/bindings/mfd/rohm,bd96802-pmic.yaml new file mode 100644 index 000000000000..6cbea796d12f --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/rohm,bd96802-pmic.yaml @@ -0,0 +1,101 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/rohm,bd96802-pmic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ROHM BD96802 / BD96806 Scalable Power Management Integrated Circuit + +maintainers: + - Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> + +description: | + BD96802Qxx-C and BD96806 are automotive grade configurable Power Management + Integrated Circuits supporting Functional Safety features for application + processors, SoCs and FPGAs + +properties: + compatible: + enum: + - rohm,bd96802 + - rohm,bd96806 + + reg: + maxItems: 1 + + interrupts: + description: + The PMIC provides intb and errb IRQ lines. The errb IRQ line is used + for fatal IRQs which will cause the PMIC to shut down power outputs. + In many systems this will shut down the SoC contolling the PMIC and + connecting/handling the errb can be omitted. However, there are cases + where the SoC is not powered by the PMIC or has a short time backup + energy to handle shutdown of critical hardware. In that case it may be + useful to connect the errb and handle errb events. + minItems: 1 + maxItems: 2 + + interrupt-names: + minItems: 1 + items: + - enum: [intb, errb] + - const: errb + + regulators: + $ref: ../regulator/rohm,bd96802-regulator.yaml + description: + List of child nodes that specify the regulators. + +required: + - compatible + - reg + - interrupts + - interrupt-names + - regulators + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/leds/common.h> + i2c { + #address-cells = <1>; + #size-cells = <0>; + pmic: pmic@62 { + reg = <0x62>; + compatible = "rohm,bd96802"; + interrupt-parent = <&gpio1>; + interrupts = <29 IRQ_TYPE_LEVEL_LOW>, <6 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "intb", "errb"; + + regulators { + buck1 { + regulator-name = "buck1"; + regulator-ramp-delay = <1250>; + /* 0.5V min INITIAL - 150 mV tune */ + regulator-min-microvolt = <350000>; + /* 3.3V + 150mV tune */ + regulator-max-microvolt = <3450000>; + + /* These can be set only when PMIC is in STBY */ + rohm,initial-voltage-microvolt = <500000>; + regulator-ov-error-microvolt = <230000>; + regulator-uv-error-microvolt = <230000>; + regulator-temp-protection-kelvin = <1>; + regulator-temp-warn-kelvin = <0>; + }; + buck2 { + regulator-name = "buck2"; + regulator-min-microvolt = <350000>; + regulator-max-microvolt = <3450000>; + + rohm,initial-voltage-microvolt = <3000000>; + regulator-ov-error-microvolt = <18000>; + regulator-uv-error-microvolt = <18000>; + regulator-temp-protection-kelvin = <1>; + regulator-temp-warn-kelvin = <1>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/mfd/samsung,s2mps11.yaml b/Documentation/devicetree/bindings/mfd/samsung,s2mps11.yaml index a4be642de33c..d6b9e2914796 100644 --- a/Documentation/devicetree/bindings/mfd/samsung,s2mps11.yaml +++ b/Documentation/devicetree/bindings/mfd/samsung,s2mps11.yaml @@ -20,11 +20,13 @@ description: | properties: compatible: enum: + - samsung,s2mpg10-pmic - samsung,s2mps11-pmic - samsung,s2mps13-pmic - samsung,s2mps14-pmic - samsung,s2mps15-pmic - samsung,s2mpu02-pmic + - samsung,s2mpu05-pmic clocks: $ref: /schemas/clock/samsung,s2mps11.yaml @@ -57,11 +59,12 @@ properties: reset (setting buck voltages to default values). type: boolean + system-power-controller: true + wakeup-source: true required: - compatible - - reg - regulators additionalProperties: false @@ -71,6 +74,28 @@ allOf: properties: compatible: contains: + const: samsung,s2mpg10-pmic + then: + properties: + reg: false + samsung,s2mps11-acokb-ground: false + samsung,s2mps11-wrstbi-ground: false + + oneOf: + - required: [interrupts] + - required: [interrupts-extended] + + else: + properties: + system-power-controller: false + + required: + - reg + + - if: + properties: + compatible: + contains: const: samsung,s2mps11-pmic then: properties: @@ -125,6 +150,18 @@ allOf: samsung,s2mps11-acokb-ground: false samsung,s2mps11-wrstbi-ground: false + - if: + properties: + compatible: + contains: + const: samsung,s2mpu05-pmic + then: + properties: + regulators: + $ref: /schemas/regulator/samsung,s2mpu05.yaml + samsung,s2mps11-acokb-ground: false + samsung,s2mps11-wrstbi-ground: false + examples: - | #include <dt-bindings/interrupt-controller/irq.h> diff --git a/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml b/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml index d41308856408..4eabafb8079d 100644 --- a/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml +++ b/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml @@ -21,7 +21,12 @@ maintainers: properties: compatible: - const: st,stm32-lptimer + oneOf: + - items: + - const: st,stm32mp25-lptimer + - const: st,stm32-lptimer + - items: + - const: st,stm32-lptimer reg: maxItems: 1 @@ -48,13 +53,21 @@ properties: minItems: 1 maxItems: 2 + power-domains: + maxItems: 1 + pwm: type: object additionalProperties: false properties: compatible: - const: st,stm32-pwm-lp + oneOf: + - items: + - const: st,stm32mp25-pwm-lp + - const: st,stm32-pwm-lp + - items: + - const: st,stm32-pwm-lp "#pwm-cells": const: 3 @@ -69,7 +82,12 @@ properties: properties: compatible: - const: st,stm32-lptimer-counter + oneOf: + - items: + - const: st,stm32mp25-lptimer-counter + - const: st,stm32-lptimer-counter + - items: + - const: st,stm32-lptimer-counter required: - compatible @@ -80,7 +98,12 @@ properties: properties: compatible: - const: st,stm32-lptimer-timer + oneOf: + - items: + - const: st,stm32mp25-lptimer-timer + - const: st,stm32-lptimer-timer + - items: + - const: st,stm32-lptimer-timer required: - compatible @@ -92,13 +115,18 @@ patternProperties: properties: compatible: - const: st,stm32-lptimer-trigger + oneOf: + - items: + - const: st,stm32mp25-lptimer-trigger + - const: st,stm32-lptimer-trigger + - items: + - const: st,stm32-lptimer-trigger reg: description: Identify trigger hardware block. items: minimum: 0 - maximum: 2 + maximum: 4 required: - compatible diff --git a/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml b/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml index b0e438ff4950..66aa1550a4e5 100644 --- a/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml +++ b/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml @@ -21,7 +21,9 @@ maintainers: properties: compatible: - const: st,stm32-timers + enum: + - st,stm32-timers + - st,stm32mp25-timers reg: maxItems: 1 @@ -36,6 +38,9 @@ properties: resets: maxItems: 1 + power-domains: + maxItems: 1 + dmas: minItems: 1 maxItems: 7 @@ -77,7 +82,9 @@ properties: properties: compatible: - const: st,stm32-pwm + enum: + - st,stm32-pwm + - st,stm32mp25-pwm "#pwm-cells": const: 3 @@ -113,7 +120,9 @@ properties: properties: compatible: - const: st,stm32-timer-counter + enum: + - st,stm32-timer-counter + - st,stm32mp25-timer-counter required: - compatible @@ -128,12 +137,13 @@ patternProperties: enum: - st,stm32-timer-trigger - st,stm32h7-timer-trigger + - st,stm32mp25-timer-trigger reg: description: Identify trigger hardware block. items: minimum: 0 - maximum: 16 + maximum: 19 required: - compatible diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml index 4d67ff26d445..27672adeb1fe 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -27,6 +27,7 @@ select: compatible: contains: enum: + - airoha,en7581-pbus-csr - al,alpine-sysfabric-service - allwinner,sun8i-a83t-system-controller - allwinner,sun8i-h3-system-controller @@ -83,6 +84,7 @@ select: - mediatek,mt2701-pctl-a-syscfg - mediatek,mt2712-pctl-a-syscfg - mediatek,mt6397-pctl-pmic-syscfg + - mediatek,mt7988-topmisc - mediatek,mt8135-pctl-a-syscfg - mediatek,mt8135-pctl-b-syscfg - mediatek,mt8173-pctl-a-syscfg @@ -90,11 +92,15 @@ select: - microchip,lan966x-cpu-syscon - microchip,mpfs-sysreg-scb - microchip,sam9x60-sfr + - microchip,sama7d65-ddr3phy + - microchip,sama7d65-sfrbu - microchip,sama7g5-ddr3phy - mscc,ocelot-cpu-syscon - mstar,msc313-pmsleep - nuvoton,ma35d1-sys - nuvoton,wpcm450-shm + - qcom,apq8064-mmss-sfpb + - qcom,apq8064-sps-sic - rockchip,px30-qos - rockchip,rk3036-qos - rockchip,rk3066-qos @@ -103,6 +109,7 @@ select: - rockchip,rk3288-qos - rockchip,rk3368-qos - rockchip,rk3399-qos + - rockchip,rk3528-qos - rockchip,rk3562-qos - rockchip,rk3568-qos - rockchip,rk3576-qos @@ -126,6 +133,7 @@ properties: compatible: items: - enum: + - airoha,en7581-pbus-csr - al,alpine-sysfabric-service - allwinner,sun8i-a83t-system-controller - allwinner,sun8i-h3-system-controller @@ -182,18 +190,24 @@ properties: - mediatek,mt2701-pctl-a-syscfg - mediatek,mt2712-pctl-a-syscfg - mediatek,mt6397-pctl-pmic-syscfg + - mediatek,mt7988-topmisc - mediatek,mt8135-pctl-a-syscfg - mediatek,mt8135-pctl-b-syscfg - mediatek,mt8173-pctl-a-syscfg + - mediatek,mt8365-infracfg-nao - mediatek,mt8365-syscfg - microchip,lan966x-cpu-syscon - microchip,mpfs-sysreg-scb - microchip,sam9x60-sfr + - microchip,sama7d65-ddr3phy + - microchip,sama7d65-sfrbu - microchip,sama7g5-ddr3phy - mscc,ocelot-cpu-syscon - mstar,msc313-pmsleep - nuvoton,ma35d1-sys - nuvoton,wpcm450-shm + - qcom,apq8064-mmss-sfpb + - qcom,apq8064-sps-sic - rockchip,px30-qos - rockchip,rk3036-qos - rockchip,rk3066-qos @@ -202,6 +216,7 @@ properties: - rockchip,rk3288-qos - rockchip,rk3368-qos - rockchip,rk3399-qos + - rockchip,rk3528-qos - rockchip,rk3562-qos - rockchip,rk3568-qos - rockchip,rk3576-qos diff --git a/Documentation/devicetree/bindings/mfd/x-powers,axp152.yaml b/Documentation/devicetree/bindings/mfd/x-powers,axp152.yaml index 3f7661bdd202..45f015d63df1 100644 --- a/Documentation/devicetree/bindings/mfd/x-powers,axp152.yaml +++ b/Documentation/devicetree/bindings/mfd/x-powers,axp152.yaml @@ -316,106 +316,106 @@ additionalProperties: false examples: - | - i2c { - #address-cells = <1>; - #size-cells = <0>; - - pmic@30 { - compatible = "x-powers,axp152"; - reg = <0x30>; - interrupts = <0>; - interrupt-controller; - #interrupt-cells = <1>; - }; - }; + i2c { + #address-cells = <1>; + #size-cells = <0>; + + pmic@30 { + compatible = "x-powers,axp152"; + reg = <0x30>; + interrupts = <0>; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; - | - #include <dt-bindings/interrupt-controller/irq.h> - - i2c { - #address-cells = <1>; - #size-cells = <0>; - - pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <1>; - - ac_power_supply: ac-power { - compatible = "x-powers,axp202-ac-power-supply"; - }; - - axp_adc: adc { - compatible = "x-powers,axp209-adc"; - #io-channel-cells = <1>; - }; - - axp_gpio: gpio { - compatible = "x-powers,axp209-gpio"; - gpio-controller; - #gpio-cells = <2>; - - gpio0-adc-pin { - pins = "GPIO0"; - function = "adc"; - }; - }; - - battery_power_supply: battery-power { - compatible = "x-powers,axp209-battery-power-supply"; - }; - - regulators { - /* Default work frequency for buck regulators */ - x-powers,dcdc-freq = <1500>; - - reg_dcdc2: dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1450000>; - regulator-name = "vdd-cpu"; - }; - - reg_dcdc3: dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-dll"; - }; - - reg_ldo1: ldo1 { - /* LDO1 is a fixed output regulator */ - regulator-always-on; - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - regulator-name = "vdd-rtc"; - }; - - reg_ldo2: ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; - }; - - reg_ldo3: ldo3 { - regulator-name = "ldo3"; - }; - - reg_ldo4: ldo4 { - regulator-name = "ldo4"; - }; - - reg_ldo5: ldo5 { - regulator-name = "ldo5"; - }; - }; - - usb_power_supply: usb-power { - compatible = "x-powers,axp202-usb-power-supply"; - }; - }; - }; + #include <dt-bindings/interrupt-controller/irq.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <1>; + + ac_power_supply: ac-power { + compatible = "x-powers,axp202-ac-power-supply"; + }; + + axp_adc: adc { + compatible = "x-powers,axp209-adc"; + #io-channel-cells = <1>; + }; + + axp_gpio: gpio { + compatible = "x-powers,axp209-gpio"; + gpio-controller; + #gpio-cells = <2>; + + gpio0-adc-pin { + pins = "GPIO0"; + function = "adc"; + }; + }; + + battery_power_supply: battery-power { + compatible = "x-powers,axp209-battery-power-supply"; + }; + + regulators { + /* Default work frequency for buck regulators */ + x-powers,dcdc-freq = <1500>; + + reg_dcdc2: dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1450000>; + regulator-name = "vdd-cpu"; + }; + + reg_dcdc3: dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-int-dll"; + }; + + reg_ldo1: ldo1 { + /* LDO1 is a fixed output regulator */ + regulator-always-on; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + regulator-name = "vdd-rtc"; + }; + + reg_ldo2: ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; + }; + + reg_ldo3: ldo3 { + regulator-name = "ldo3"; + }; + + reg_ldo4: ldo4 { + regulator-name = "ldo4"; + }; + + reg_ldo5: ldo5 { + regulator-name = "ldo5"; + }; + }; + + usb_power_supply: usb-power { + compatible = "x-powers,axp202-usb-power-supply"; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/mips/cpus.yaml b/Documentation/devicetree/bindings/mips/cpus.yaml index a85137add668..471373ad0cfb 100644 --- a/Documentation/devicetree/bindings/mips/cpus.yaml +++ b/Documentation/devicetree/bindings/mips/cpus.yaml @@ -50,6 +50,7 @@ properties: device_type: true allOf: + - $ref: /schemas/opp/opp-v1.yaml# - if: properties: compatible: @@ -68,7 +69,7 @@ required: - compatible - reg -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/mips/econet.yaml b/Documentation/devicetree/bindings/mips/econet.yaml new file mode 100644 index 000000000000..d8181b58c781 --- /dev/null +++ b/Documentation/devicetree/bindings/mips/econet.yaml @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mips/econet.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: EcoNet MIPS SoCs + +maintainers: + - Caleb James DeLisle <cjd@cjdns.fr> + +properties: + $nodename: + const: '/' + + compatible: + oneOf: + - description: Boards with EcoNet EN751221 family SoC + items: + - enum: + - smartfiber,xp8421-b + - const: econet,en751221 + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/mips/mti,mips-cm.yaml b/Documentation/devicetree/bindings/mips/mti,mips-cm.yaml new file mode 100644 index 000000000000..d129d6382847 --- /dev/null +++ b/Documentation/devicetree/bindings/mips/mti,mips-cm.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mips/mti,mips-cm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MIPS Coherence Manager + +description: + The Coherence Manager (CM) is responsible for establishing the + global ordering of requests from all elements of the system and + sending the correct data back to the requester. It supports Cache + to Cache transfers. + https://training.mips.com/cps_mips/PDF/CPS_Introduction.pdf + https://training.mips.com/cps_mips/PDF/Coherency_Manager.pdf + +maintainers: + - Jiaxun Yang <jiaxun.yang@flygoat.com> + +properties: + compatible: + oneOf: + - const: mti,mips-cm + - const: mobileye,eyeq6-cm + description: + On EyeQ6 the HCI (Hardware Cache Initialization) information for + the L2 cache in multi-cluster configuration is broken. + + reg: + description: + Base address and size of the Global Configuration Registers + referred to as CMGCR.They are the system programmer's interface + to the Coherency Manager. Their location in the memory map is + determined at core build time. In a functional system, the base + address is provided by the Coprocessor 0, but some + System-on-Chip (SoC) designs may not provide an accurate address + that needs to be described statically. + + maxItems: 1 + +required: + - compatible + +additionalProperties: false + +examples: + - | + coherency-manager@1fbf8000 { + compatible = "mti,mips-cm"; + reg = <0x1bde8000 0x8000>; + }; + + - | + coherency-manager { + compatible = "mobileye,eyeq6-cm"; + }; +... diff --git a/Documentation/devicetree/bindings/misc/atmel-ssc.txt b/Documentation/devicetree/bindings/misc/atmel-ssc.txt deleted file mode 100644 index f9fb412642fe..000000000000 --- a/Documentation/devicetree/bindings/misc/atmel-ssc.txt +++ /dev/null @@ -1,50 +0,0 @@ -* Atmel SSC driver. - -Required properties: -- compatible: "atmel,at91rm9200-ssc" or "atmel,at91sam9g45-ssc" - - atmel,at91rm9200-ssc: support pdc transfer - - atmel,at91sam9g45-ssc: support dma transfer -- reg: Should contain SSC registers location and length -- interrupts: Should contain SSC interrupt -- clock-names: tuple listing input clock names. - Required elements: "pclk" -- clocks: phandles to input clocks. - - -Required properties for devices compatible with "atmel,at91sam9g45-ssc": -- dmas: DMA specifier, consisting of a phandle to DMA controller node, - the memory interface and SSC DMA channel ID (for tx and rx). - See Documentation/devicetree/bindings/dma/atmel-dma.txt for details. -- dma-names: Must be "tx", "rx". - -Optional properties: - - atmel,clk-from-rk-pin: bool property. - - When SSC works in slave mode, according to the hardware design, the - clock can get from TK pin, and also can get from RK pin. So, add - this parameter to choose where the clock from. - - By default the clock is from TK pin, if the clock from RK pin, this - property is needed. - - #sound-dai-cells: Should contain <0>. - - This property makes the SSC into an automatically registered DAI. - -Examples: -- PDC transfer: -ssc0: ssc@fffbc000 { - compatible = "atmel,at91rm9200-ssc"; - reg = <0xfffbc000 0x4000>; - interrupts = <14 4 5>; - clocks = <&ssc0_clk>; - clock-names = "pclk"; -}; - -- DMA transfer: -ssc0: ssc@f0010000 { - compatible = "atmel,at91sam9g45-ssc"; - reg = <0xf0010000 0x4000>; - interrupts = <28 4 5>; - dmas = <&dma0 1 13>, - <&dma0 1 14>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; -}; diff --git a/Documentation/devicetree/bindings/misc/ti,fpc202.yaml b/Documentation/devicetree/bindings/misc/ti,fpc202.yaml new file mode 100644 index 000000000000..a8cb10f2d0df --- /dev/null +++ b/Documentation/devicetree/bindings/misc/ti,fpc202.yaml @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/misc/ti,fpc202.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI FPC202 dual port controller with expanded IOs + +maintainers: + - Romain Gantois <romain.gantois@bootlin.com> + +allOf: + - $ref: /schemas/i2c/i2c-atr.yaml# + +properties: + compatible: + const: ti,fpc202 + + reg: + maxItems: 1 + + gpio-controller: true + + "#gpio-cells": + const: 2 + + enable-gpios: + description: + Specifier for the GPIO connected to the EN pin. + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + +patternProperties: + "^i2c@[0-1]$": + $ref: /schemas/i2c/i2c-controller.yaml# + description: Downstream device ports 0 and 1 + + properties: + reg: + maxItems: 1 + description: + Downstream port ID + + required: + - "#address-cells" + - "#size-cells" + - reg + + unevaluatedProperties: false + +required: + - compatible + - reg + - gpio-controller + - "#gpio-cells" + - "#address-cells" + - "#size-cells" + +unevaluatedProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + i2c-atr@f { + compatible = "ti,fpc202"; + reg = <0xf>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml b/Documentation/devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml index 0ccd632d5620..9f3b1edacaa0 100644 --- a/Documentation/devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml +++ b/Documentation/devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml @@ -30,38 +30,34 @@ properties: - const: allwinner,sun50i-a100-emmc - const: allwinner,sun50i-a100-mmc - items: - - const: allwinner,sun8i-a83t-mmc + - enum: + - allwinner,sun8i-a83t-mmc + - allwinner,suniv-f1c100s-mmc - const: allwinner,sun7i-a20-mmc - items: - - const: allwinner,sun8i-r40-emmc + - enum: + - allwinner,sun8i-r40-emmc + - allwinner,sun50i-h5-emmc + - allwinner,sun50i-h6-emmc - const: allwinner,sun50i-a64-emmc - items: - - const: allwinner,sun8i-r40-mmc + - enum: + - allwinner,sun8i-r40-mmc + - allwinner,sun50i-h5-mmc + - allwinner,sun50i-h6-mmc - const: allwinner,sun50i-a64-mmc - items: - - const: allwinner,sun50i-h5-emmc - - const: allwinner,sun50i-a64-emmc - - items: - - const: allwinner,sun50i-h5-mmc - - const: allwinner,sun50i-a64-mmc - - items: - - const: allwinner,sun50i-h6-emmc - - const: allwinner,sun50i-a64-emmc - - items: - - const: allwinner,sun50i-h6-mmc - - const: allwinner,sun50i-a64-mmc - - items: - - const: allwinner,sun20i-d1-emmc - - const: allwinner,sun50i-a100-emmc - - items: - - const: allwinner,sun50i-h616-emmc + - enum: + - allwinner,sun20i-d1-emmc + - allwinner,sun50i-h616-emmc + - allwinner,sun55i-a523-emmc - const: allwinner,sun50i-a100-emmc - items: - const: allwinner,sun50i-h616-mmc - const: allwinner,sun50i-a100-mmc - items: - - const: allwinner,suniv-f1c100s-mmc - - const: allwinner,sun7i-a20-mmc + - const: allwinner,sun55i-a523-mmc + - const: allwinner,sun20i-d1-mmc reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/mmc/amlogic,meson-mx-sdio.yaml b/Documentation/devicetree/bindings/mmc/amlogic,meson-mx-sdio.yaml index 022682a977c6..0d4d9ca6a8d9 100644 --- a/Documentation/devicetree/bindings/mmc/amlogic,meson-mx-sdio.yaml +++ b/Documentation/devicetree/bindings/mmc/amlogic,meson-mx-sdio.yaml @@ -60,6 +60,9 @@ patternProperties: bus-width: enum: [1, 4] + required: + - compatible + unevaluatedProperties: false required: diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml b/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml index 9075add020bf..8e79de97b242 100644 --- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml +++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml @@ -38,6 +38,15 @@ allOf: - items: - const: clk_out_sd1 - const: clk_in_sd1 + - if: + properties: + compatible: + contains: + const: renesas,rzn1-sdhci + then: + properties: + interrupts: + minItems: 2 properties: compatible: @@ -46,6 +55,10 @@ properties: - const: arasan,sdhci-4.9a # generic Arasan SDHCI 4.9a PHY - const: arasan,sdhci-5.1 # generic Arasan SDHCI 5.1 PHY - items: + - const: renesas,r9a06g032-sdhci # Renesas RZ/N1D SoC + - const: renesas,rzn1-sdhci # Renesas RZ/N1 family + - const: arasan,sdhci-8.9a + - items: - const: rockchip,rk3399-sdhci-5.1 # rk3399 eMMC PHY - const: arasan,sdhci-5.1 description: @@ -109,7 +122,14 @@ properties: - const: gate interrupts: - maxItems: 1 + minItems: 1 + maxItems: 2 + + interrupt-names: + minItems: 1 + items: + - const: int + - const: wakeup phys: maxItems: 1 diff --git a/Documentation/devicetree/bindings/mmc/atmel,hsmci.yaml b/Documentation/devicetree/bindings/mmc/atmel,hsmci.yaml new file mode 100644 index 000000000000..151b414b9d27 --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/atmel,hsmci.yaml @@ -0,0 +1,106 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mmc/atmel,hsmci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Atmel High-Speed MultiMedia Card Interface (HSMCI) + +description: + The Atmel HSMCI controller provides an interface for MMC, SD, and SDIO memory + cards. + +maintainers: + - Nicolas Ferre <nicolas.ferre@microchip.com> + - Aubin Constans <aubin.constans@microchip.com> + +allOf: + - $ref: mmc-controller.yaml + +properties: + compatible: + const: atmel,hsmci + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + dmas: + maxItems: 1 + + dma-names: + const: rxtx + + clocks: + maxItems: 1 + + clock-names: + const: mci_clk + + "#address-cells": + const: 1 + description: Used for slot IDs. + + "#size-cells": + const: 0 + +patternProperties: + "slot@[0-2]$": + $ref: mmc-slot.yaml + description: A slot node representing an MMC, SD, or SDIO slot. + + properties: + reg: + enum: [0, 1] + + required: + - reg + - bus-width + + unevaluatedProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - "#address-cells" + - "#size-cells" + +anyOf: + - required: + - slot@0 + - required: + - slot@1 + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/clock/at91.h> + mmc@f0008000 { + compatible = "atmel,hsmci"; + reg = <0xf0008000 0x600>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mci0_clk>; + clock-names = "mci_clk"; + #address-cells = <1>; + #size-cells = <0>; + + slot@0 { + reg = <0>; + bus-width = <4>; + cd-gpios = <&pioD 15 0>; + cd-inverted; + }; + + slot@1 { + reg = <1>; + bus-width = <4>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/mmc/atmel-hsmci.txt b/Documentation/devicetree/bindings/mmc/atmel-hsmci.txt deleted file mode 100644 index 07ad02075a93..000000000000 --- a/Documentation/devicetree/bindings/mmc/atmel-hsmci.txt +++ /dev/null @@ -1,73 +0,0 @@ -* Atmel High Speed MultiMedia Card Interface - -This controller on atmel products provides an interface for MMC, SD and SDIO -types of memory cards. - -This file documents differences between the core properties described -by mmc.txt and the properties used by the atmel-mci driver. - -1) MCI node - -Required properties: -- compatible: should be "atmel,hsmci" -- #address-cells: should be one. The cell is the slot id. -- #size-cells: should be zero. -- at least one slot node -- clock-names: tuple listing input clock names. - Required elements: "mci_clk" -- clocks: phandles to input clocks. - -The node contains child nodes for each slot that the platform uses - -Example MCI node: - -mmc0: mmc@f0008000 { - compatible = "atmel,hsmci"; - reg = <0xf0008000 0x600>; - interrupts = <12 4>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "mci_clk"; - clocks = <&mci0_clk>; - - [ child node definitions...] -}; - -2) slot nodes - -Required properties: -- reg: should contain the slot id. -- bus-width: number of data lines connected to the controller - -Optional properties: -- cd-gpios: specify GPIOs for card detection -- cd-inverted: invert the value of external card detect gpio line -- wp-gpios: specify GPIOs for write protection - -Example slot node: - -slot@0 { - reg = <0>; - bus-width = <4>; - cd-gpios = <&pioD 15 0> - cd-inverted; -}; - -Example full MCI node: -mmc0: mmc@f0008000 { - compatible = "atmel,hsmci"; - reg = <0xf0008000 0x600>; - interrupts = <12 4>; - #address-cells = <1>; - #size-cells = <0>; - slot@0 { - reg = <0>; - bus-width = <4>; - cd-gpios = <&pioD 15 0> - cd-inverted; - }; - slot@1 { - reg = <1>; - bus-width = <4>; - }; -}; diff --git a/Documentation/devicetree/bindings/mmc/fsl,esdhc.yaml b/Documentation/devicetree/bindings/mmc/fsl,esdhc.yaml index b86ffb53b18b..62087cf920df 100644 --- a/Documentation/devicetree/bindings/mmc/fsl,esdhc.yaml +++ b/Documentation/devicetree/bindings/mmc/fsl,esdhc.yaml @@ -24,6 +24,7 @@ properties: - fsl,t1040-esdhc - fsl,t4240-esdhc - fsl,ls1012a-esdhc + - fsl,ls1021a-esdhc - fsl,ls1028a-esdhc - fsl,ls1088a-esdhc - fsl,ls1043a-esdhc diff --git a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml index b9b999570529..b98a84f93277 100644 --- a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml +++ b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml @@ -57,6 +57,7 @@ properties: - fsl,imx8mp-usdhc - fsl,imx8ulp-usdhc - fsl,imx93-usdhc + - fsl,imx94-usdhc - fsl,imx95-usdhc - const: fsl,imx8mm-usdhc - items: diff --git a/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.yaml b/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.yaml index 3f48d8292d5b..ee2ddef36369 100644 --- a/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.yaml +++ b/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.yaml @@ -52,9 +52,14 @@ properties: - const: core - const: axi + dma-coherent: true + interrupts: maxItems: 1 + iommus: + maxItems: 1 + marvell,pad-type: $ref: /schemas/types.yaml#/definitions/string enum: @@ -142,7 +147,7 @@ properties: This property provides the re-tuning counter. allOf: - - $ref: mmc-controller.yaml# + - $ref: sdhci-common.yaml# - if: properties: compatible: @@ -164,26 +169,6 @@ allOf: marvell,pad-type: false - - if: - properties: - compatible: - contains: - enum: - - marvell,armada-cp110-sdhci - - marvell,armada-ap807-sdhci - - marvell,armada-ap806-sdhci - - then: - properties: - clocks: - minItems: 2 - - clock-names: - items: - - const: core - - const: axi - - required: - compatible - reg diff --git a/Documentation/devicetree/bindings/mmc/microchip,sdhci-pic32.txt b/Documentation/devicetree/bindings/mmc/microchip,sdhci-pic32.txt deleted file mode 100644 index f064528effed..000000000000 --- a/Documentation/devicetree/bindings/mmc/microchip,sdhci-pic32.txt +++ /dev/null @@ -1,29 +0,0 @@ -* Microchip PIC32 SDHCI Controller - -This file documents differences between the core properties in mmc.txt -and the properties used by the sdhci-pic32 driver. - -Required properties: -- compatible: Should be "microchip,pic32mzda-sdhci" -- interrupts: Should contain interrupt -- clock-names: Should be "base_clk", "sys_clk". - See: Documentation/devicetree/bindings/resource-names.txt -- clocks: Phandle to the clock. - See: Documentation/devicetree/bindings/clock/clock-bindings.txt -- pinctrl-names: A pinctrl state names "default" must be defined. -- pinctrl-0: Phandle referencing pin configuration of the SDHCI controller. - See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt - -Example: - - sdhci@1f8ec000 { - compatible = "microchip,pic32mzda-sdhci"; - reg = <0x1f8ec000 0x100>; - interrupts = <191 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rootclk REF4CLK>, <&rootclk PB5CLK>; - clock-names = "base_clk", "sys_clk"; - bus-width = <4>; - cap-sd-highspeed; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdhc1>; - }; diff --git a/Documentation/devicetree/bindings/mmc/microchip,sdhci-pic32.yaml b/Documentation/devicetree/bindings/mmc/microchip,sdhci-pic32.yaml new file mode 100644 index 000000000000..ca0ca7df9ee9 --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/microchip,sdhci-pic32.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mmc/microchip,sdhci-pic32.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PIC32 SDHI Controller + +description: + The Microchip PIC32 family of microcontrollers (MCUs) includes models with + Secure Digital Host Controller Interface (SDHCI) controllers, allowing them + to interface with Secure Digital (SD) cards. This interface is used for reading, + writing, and managing data on SD cards, enabling storage and data transfer + capabilities in embedded systems. + +allOf: + - $ref: mmc-controller.yaml + +maintainers: + - Ulf Hansson <ulf.hansson@linaro.org> + +properties: + compatible: + const: microchip,pic32mzda-sdhci + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: base_clk + - const: sys_clk + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - pinctrl-names + - pinctrl-0 + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/clock/microchip,pic32-clock.h> + mmc@1f8ec000 { + compatible = "microchip,pic32mzda-sdhci"; + reg = <0x1f8ec000 0x100>; + interrupts = <191 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rootclk REF4CLK>, <&rootclk PB5CLK>; + clock-names = "base_clk", "sys_clk"; + bus-width = <4>; + cap-sd-highspeed; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhc1>; + }; +... diff --git a/Documentation/devicetree/bindings/mmc/mmc-controller.yaml b/Documentation/devicetree/bindings/mmc/mmc-controller.yaml index 9d7a1298c455..26e4f0f8dc1c 100644 --- a/Documentation/devicetree/bindings/mmc/mmc-controller.yaml +++ b/Documentation/devicetree/bindings/mmc/mmc-controller.yaml @@ -24,7 +24,7 @@ properties: $nodename: pattern: "^mmc(@.*)?$" -unevaluatedProperties: true +additionalProperties: true examples: - | diff --git a/Documentation/devicetree/bindings/mmc/mmc-slot.yaml b/Documentation/devicetree/bindings/mmc/mmc-slot.yaml index 1f0667828063..ca3d0114bfc6 100644 --- a/Documentation/devicetree/bindings/mmc/mmc-slot.yaml +++ b/Documentation/devicetree/bindings/mmc/mmc-slot.yaml @@ -29,7 +29,6 @@ properties: maxItems: 1 required: - - compatible - reg unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml index 0debccbd6519..6dd26ad31491 100644 --- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml @@ -32,6 +32,7 @@ properties: - const: mediatek,mt2701-mmc - items: - enum: + - mediatek,mt6893-mmc - mediatek,mt8186-mmc - mediatek,mt8188-mmc - mediatek,mt8192-mmc @@ -299,6 +300,7 @@ allOf: properties: compatible: enum: + - mediatek,mt6893-mmc - mediatek,mt8186-mmc - mediatek,mt8188-mmc - mediatek,mt8195-mmc diff --git a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml index af378b9ff3f4..7563623876fc 100644 --- a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml +++ b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml @@ -68,6 +68,11 @@ properties: - renesas,sdhi-r9a08g045 # RZ/G3S - renesas,sdhi-r9a09g011 # RZ/V2M - const: renesas,rzg2l-sdhi + - items: + - enum: + - renesas,sdhi-r9a09g047 # RZ/G3E + - renesas,sdhi-r9a09g056 # RZ/V2N + - const: renesas,sdhi-r9a09g057 # RZ/V2H(P) reg: maxItems: 1 @@ -211,6 +216,19 @@ allOf: sectioned off to be run by a separate second clock source to allow the main core clock to be turned off to save power. + - if: + properties: + compatible: + contains: + const: renesas,sdhi-r9a09g057 + then: + properties: + vqmmc-regulator: + type: object + description: VQMMC SD regulator + $ref: /schemas/regulator/regulator.yaml# + unevaluatedProperties: false + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml b/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml index 06df1269f247..bf273115235b 100644 --- a/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml +++ b/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml @@ -38,6 +38,8 @@ properties: - rockchip,rk3328-dw-mshc - rockchip,rk3368-dw-mshc - rockchip,rk3399-dw-mshc + - rockchip,rk3528-dw-mshc + - rockchip,rk3562-dw-mshc - rockchip,rk3568-dw-mshc - rockchip,rk3588-dw-mshc - rockchip,rv1108-dw-mshc diff --git a/Documentation/devicetree/bindings/mmc/samsung,exynos-dw-mshc.yaml b/Documentation/devicetree/bindings/mmc/samsung,exynos-dw-mshc.yaml index ef2d1d7c92fc..e8bd49d46794 100644 --- a/Documentation/devicetree/bindings/mmc/samsung,exynos-dw-mshc.yaml +++ b/Documentation/devicetree/bindings/mmc/samsung,exynos-dw-mshc.yaml @@ -24,6 +24,8 @@ properties: - samsung,exynos5420-dw-mshc-smu - samsung,exynos7-dw-mshc - samsung,exynos7-dw-mshc-smu + - samsung,exynos7870-dw-mshc + - samsung,exynos7870-dw-mshc-smu - items: - enum: - samsung,exynos5433-dw-mshc-smu diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml index eed9063e9bb3..2b2cbce2458b 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml @@ -60,6 +60,7 @@ properties: - qcom,sm6125-sdhci - qcom,sm6350-sdhci - qcom,sm6375-sdhci + - qcom,sm7150-sdhci - qcom,sm8150-sdhci - qcom,sm8250-sdhci - qcom,sm8350-sdhci diff --git a/Documentation/devicetree/bindings/mmc/sdhci.txt b/Documentation/devicetree/bindings/mmc/sdhci.txt deleted file mode 100644 index 0e9923a64024..000000000000 --- a/Documentation/devicetree/bindings/mmc/sdhci.txt +++ /dev/null @@ -1,13 +0,0 @@ -The properties specific for SD host controllers. For properties shared by MMC -host controllers refer to the mmc[1] bindings. - - [1] Documentation/devicetree/bindings/mmc/mmc.txt - -Optional properties: -- sdhci-caps-mask: The sdhci capabilities register is incorrect. This 64bit - property corresponds to the bits in the sdhci capability register. If the bit - is on in the mask then the bit is incorrect in the register and should be - turned off, before applying sdhci-caps. -- sdhci-caps: The sdhci capabilities register is incorrect. This 64bit - property corresponds to the bits in the sdhci capability register. If the - bit is on in the property then the bit should be turned on. diff --git a/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml b/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml index c3d5e0230af1..f882219a0a26 100644 --- a/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml +++ b/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml @@ -14,8 +14,14 @@ properties: compatible: oneOf: - items: - - const: rockchip,rk3576-dwcmshc + - enum: + - rockchip,rk3528-dwcmshc + - rockchip,rk3562-dwcmshc + - rockchip,rk3576-dwcmshc - const: rockchip,rk3588-dwcmshc + - items: + - const: sophgo,sg2044-dwcmshc + - const: sophgo,sg2042-dwcmshc - enum: - rockchip,rk3568-dwcmshc - rockchip,rk3588-dwcmshc @@ -114,10 +120,6 @@ allOf: required: - power-domains - else: - properties: - power-domains: false - unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml b/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml new file mode 100644 index 000000000000..13d9382058fb --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mmc/spacemit,sdhci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SpacemiT SDHCI Controller + +maintainers: + - Yixun Lan <dlan@gentoo.org> + +allOf: + - $ref: mmc-controller.yaml# + +properties: + compatible: + const: spacemit,k1-sdhci + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: core clock, used by internal controller + - description: io clock, output for SD, SDIO, eMMC device + + clock-names: + items: + - const: core + - const: io + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + mmc@d4281000 { + compatible = "spacemit,k1-sdhci"; + reg = <0xd4281000 0x200>; + interrupts = <101>; + interrupt-parent = <&plic>; + clocks = <&clk_apmu 10>, <&clk_apmu 13>; + clock-names = "core", "io"; + }; diff --git a/Documentation/devicetree/bindings/mmc/vt8500-sdmmc.txt b/Documentation/devicetree/bindings/mmc/vt8500-sdmmc.txt deleted file mode 100644 index d7fb6abb3eb8..000000000000 --- a/Documentation/devicetree/bindings/mmc/vt8500-sdmmc.txt +++ /dev/null @@ -1,23 +0,0 @@ -* Wondermedia WM8505/WM8650 SD/MMC Host Controller - -This file documents differences between the core properties described -by mmc.txt and the properties used by the wmt-sdmmc driver. - -Required properties: -- compatible: Should be "wm,wm8505-sdhc". -- interrupts: Two interrupts are required - regular irq and dma irq. - -Optional properties: -- sdon-inverted: SD_ON bit is inverted on the controller - -Examples: - -sdhc@d800a000 { - compatible = "wm,wm8505-sdhc"; - reg = <0xd800a000 0x1000>; - interrupts = <20 21>; - clocks = <&sdhc>; - bus-width = <4>; - sdon-inverted; -}; - diff --git a/Documentation/devicetree/bindings/mmc/wm,wm8505-sdhc.yaml b/Documentation/devicetree/bindings/mmc/wm,wm8505-sdhc.yaml new file mode 100644 index 000000000000..5b55174e9088 --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/wm,wm8505-sdhc.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mmc/wm,wm8505-sdhc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: WonderMedia SoC SDHCI Controller + +maintainers: + - Alexey Charkov <alchark@gmail.com> + +allOf: + - $ref: mmc-controller.yaml# + +properties: + compatible: + oneOf: + - const: wm,wm8505-sdhc + - items: + - const: wm,wm8650-sdhc + - const: wm,wm8505-sdhc + - items: + - const: wm,wm8750-sdhc + - const: wm,wm8505-sdhc + - items: + - const: wm,wm8850-sdhc + - const: wm,wm8505-sdhc + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + interrupts: + items: + - description: SDMMC controller interrupt + - description: SDMMC controller DMA interrupt + + sdon-inverted: + type: boolean + description: All chips before (not including) WM8505 rev. A2 treated their + "clock stop" bit (register offset 0x08 a.k.a. SDMMC_BUSMODE, bit 0x10) + as "set 1 to disable SD clock", while all the later versions treated it + as "set 0 to disable SD clock". Set this property for later versions of + wm,wm8505-sdhc. On wm,wm8650-sdhc and later this property is implied and + does not need to be set explicitly + +required: + - compatible + - reg + - interrupts + - clocks + +unevaluatedProperties: false + +examples: + - | + mmc@d800a000 { + compatible = "wm,wm8505-sdhc"; + reg = <0xd800a000 0x1000>; + interrupts = <20>, <21>; + clocks = <&sdhc>; + bus-width = <4>; + sdon-inverted; + }; diff --git a/Documentation/devicetree/bindings/mtd/arasan,nand-controller.yaml b/Documentation/devicetree/bindings/mtd/arasan,nand-controller.yaml index 15b63bbb82a2..b90d3b48c2f2 100644 --- a/Documentation/devicetree/bindings/mtd/arasan,nand-controller.yaml +++ b/Documentation/devicetree/bindings/mtd/arasan,nand-controller.yaml @@ -42,7 +42,7 @@ required: - clock-names - interrupts -unevaluatedProperties: true +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/mtd/atmel,dataflash.yaml b/Documentation/devicetree/bindings/mtd/atmel,dataflash.yaml new file mode 100644 index 000000000000..8c72fa346e36 --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/atmel,dataflash.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/atmel,dataflash.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Atmel DataFlash + +maintainers: + - Nayab Sayed <nayabbasha.sayed@microchip.com> + +description: + The Atmel DataFlash is a low pin-count serial interface sequential access + Flash memory, compatible with SPI standard. The device tree may optionally + contain sub-nodes describing partitions of the address space. + +properties: + compatible: + oneOf: + - items: + - enum: + - atmel,at45db321d + - atmel,at45db041e + - atmel,at45db642d + - atmel,at45db021d + - const: atmel,at45 + - const: atmel,dataflash + - items: + - const: atmel,at45 + - const: atmel,dataflash + + reg: + maxItems: 1 + +required: + - compatible + - reg + +allOf: + - $ref: mtd.yaml# + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false + +examples: + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + + flash@1 { + compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash"; + reg = <1>; + }; + }; diff --git a/Documentation/devicetree/bindings/mtd/atmel-dataflash.txt b/Documentation/devicetree/bindings/mtd/atmel-dataflash.txt deleted file mode 100644 index 1889a4db5b7c..000000000000 --- a/Documentation/devicetree/bindings/mtd/atmel-dataflash.txt +++ /dev/null @@ -1,17 +0,0 @@ -* Atmel Data Flash - -Required properties: -- compatible : "atmel,<model>", "atmel,<series>", "atmel,dataflash". - -The device tree may optionally contain sub-nodes describing partitions of the -address space. See partition.txt for more detail. - -Example: - -flash@1 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash"; - spi-max-frequency = <25000000>; - reg = <1>; -}; diff --git a/Documentation/devicetree/bindings/mtd/fsl,vf610-nfc.yaml b/Documentation/devicetree/bindings/mtd/fsl,vf610-nfc.yaml new file mode 100644 index 000000000000..480a5c87859d --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/fsl,vf610-nfc.yaml @@ -0,0 +1,89 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/fsl,vf610-nfc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale's NAND flash controller (NFC) + +description: + This variant of the Freescale NAND flash controller (NFC) can be found on + Vybrid (vf610), MPC5125, MCF54418 and Kinetis K70. + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +properties: + compatible: + enum: + - fsl,vf610-nfc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: nfc + +patternProperties: + "^nand@[a-f0-9]$": + type: object + $ref: raw-nand-chip.yaml + + properties: + compatible: + const: fsl,vf610-nfc-nandcs + + reg: + const: 0 + + nand-ecc-strength: + enum: [24, 32] + + nand-ecc-step-size: + const: 2048 + + unevaluatedProperties: false + +required: + - compatible + - reg + - interrupts + +allOf: + - $ref: nand-controller.yaml + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/vf610-clock.h> + + nand-controller@400e0000 { + compatible = "fsl,vf610-nfc"; + reg = <0x400e0000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks VF610_CLK_NFC>; + clock-names = "nfc"; + assigned-clocks = <&clks VF610_CLK_NFC>; + assigned-clock-rates = <33000000>; + + nand@0 { + compatible = "fsl,vf610-nfc-nandcs"; + reg = <0>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <32>; + nand-ecc-step-size = <2048>; + nand-on-flash-bbt; + }; + }; diff --git a/Documentation/devicetree/bindings/mtd/gpmi-nand.yaml b/Documentation/devicetree/bindings/mtd/gpmi-nand.yaml index f9eb1868ca1f..0badb2e978c7 100644 --- a/Documentation/devicetree/bindings/mtd/gpmi-nand.yaml +++ b/Documentation/devicetree/bindings/mtd/gpmi-nand.yaml @@ -29,7 +29,14 @@ properties: - enum: - fsl,imx8mm-gpmi-nand - fsl,imx8mn-gpmi-nand + - fsl,imx8mp-gpmi-nand + - fsl,imx8mq-gpmi-nand - const: fsl,imx7d-gpmi-nand + - items: + - enum: + - fsl,imx8dxl-gpmi-nand + - fsl,imx8qm-gpmi-nand + - const: fsl,imx8qxp-gpmi-nand reg: items: diff --git a/Documentation/devicetree/bindings/mtd/loongson,ls1b-nand-controller.yaml b/Documentation/devicetree/bindings/mtd/loongson,ls1b-nand-controller.yaml new file mode 100644 index 000000000000..a09e92e416c4 --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/loongson,ls1b-nand-controller.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/loongson,ls1b-nand-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Loongson-1 NAND Controller + +maintainers: + - Keguang Zhang <keguang.zhang@gmail.com> + +description: + The Loongson-1 NAND controller abstracts all supported operations, + meaning it does not support low-level access to raw NAND flash chips. + Moreover, the controller is paired with the DMA engine to perform + READ and PROGRAM functions. + +allOf: + - $ref: nand-controller.yaml + +properties: + compatible: + oneOf: + - enum: + - loongson,ls1b-nand-controller + - loongson,ls1c-nand-controller + - items: + - enum: + - loongson,ls1a-nand-controller + - const: loongson,ls1b-nand-controller + + reg: + maxItems: 2 + + reg-names: + items: + - const: nand + - const: nand-dma + + dmas: + maxItems: 1 + + dma-names: + const: rxtx + +required: + - compatible + - reg + - reg-names + - dmas + - dma-names + +unevaluatedProperties: false + +examples: + - | + nand-controller@1fe78000 { + compatible = "loongson,ls1b-nand-controller"; + reg = <0x1fe78000 0x24>, <0x1fe78040 0x4>; + reg-names = "nand", "nand-dma"; + dmas = <&dma 0>; + dma-names = "rxtx"; + #address-cells = <1>; + #size-cells = <0>; + + nand@0 { + reg = <0>; + label = "ls1x-nand"; + nand-use-soft-ecc-engine; + nand-ecc-algo = "hamming"; + }; + }; diff --git a/Documentation/devicetree/bindings/mtd/mtd-physmap.yaml b/Documentation/devicetree/bindings/mtd/mtd-physmap.yaml index 18f6733408b4..1b375dee83b0 100644 --- a/Documentation/devicetree/bindings/mtd/mtd-physmap.yaml +++ b/Documentation/devicetree/bindings/mtd/mtd-physmap.yaml @@ -122,6 +122,8 @@ properties: '#size-cells': const: 1 + ranges: true + big-endian: true little-endian: true @@ -143,8 +145,7 @@ then: required: - syscon -# FIXME: A parent bus may define timing properties -additionalProperties: true +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/mtd/mxc-nand.yaml b/Documentation/devicetree/bindings/mtd/mxc-nand.yaml index cf4198e43d7f..bd8f7b683953 100644 --- a/Documentation/devicetree/bindings/mtd/mxc-nand.yaml +++ b/Documentation/devicetree/bindings/mtd/mxc-nand.yaml @@ -14,8 +14,12 @@ allOf: properties: compatible: - const: fsl,imx27-nand - + oneOf: + - const: fsl,imx27-nand + - items: + - enum: + - fsl,imx31-nand + - const: fsl,imx27-nand reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/mtd/qcom,nandc.yaml b/Documentation/devicetree/bindings/mtd/qcom,nandc.yaml index 35b4206ea918..5511389960f0 100644 --- a/Documentation/devicetree/bindings/mtd/qcom,nandc.yaml +++ b/Documentation/devicetree/bindings/mtd/qcom,nandc.yaml @@ -11,12 +11,18 @@ maintainers: properties: compatible: - enum: - - qcom,ipq806x-nand - - qcom,ipq4019-nand - - qcom,ipq6018-nand - - qcom,ipq8074-nand - - qcom,sdx55-nand + oneOf: + - items: + - enum: + - qcom,sdx75-nand + - const: qcom,sdx55-nand + - items: + - enum: + - qcom,ipq806x-nand + - qcom,ipq4019-nand + - qcom,ipq6018-nand + - qcom,ipq8074-nand + - qcom,sdx55-nand reg: maxItems: 1 @@ -100,6 +106,18 @@ allOf: compatible: contains: enum: + - qcom,sdx75-nand + + then: + properties: + iommus: + maxItems: 1 + + - if: + properties: + compatible: + contains: + enum: - qcom,ipq4019-nand - qcom,ipq6018-nand - qcom,ipq8074-nand diff --git a/Documentation/devicetree/bindings/mtd/vf610-nfc.txt b/Documentation/devicetree/bindings/mtd/vf610-nfc.txt deleted file mode 100644 index 7db5e6e609df..000000000000 --- a/Documentation/devicetree/bindings/mtd/vf610-nfc.txt +++ /dev/null @@ -1,59 +0,0 @@ -Freescale's NAND flash controller (NFC) - -This variant of the Freescale NAND flash controller (NFC) can be found on -Vybrid (vf610), MPC5125, MCF54418 and Kinetis K70. - -Required properties: -- compatible: Should be set to "fsl,vf610-nfc". -- reg: address range of the NFC. -- interrupts: interrupt of the NFC. -- #address-cells: shall be set to 1. Encode the nand CS. -- #size-cells : shall be set to 0. -- assigned-clocks: main clock from the SoC, for Vybrid <&clks VF610_CLK_NFC>; -- assigned-clock-rates: The NAND bus timing is derived from this clock - rate and should not exceed maximum timing for any NAND memory chip - in a board stuffing. Typical NAND memory timings derived from this - clock are found in the SoC hardware reference manual. Furthermore, - there might be restrictions on maximum rates when using hardware ECC. - -- #address-cells, #size-cells : Must be present if the device has sub-nodes - representing partitions. - -Required children nodes: -Children nodes represent the available nand chips. Currently the driver can -only handle one NAND chip. - -Required properties: -- compatible: Should be set to "fsl,vf610-nfc-cs". -- nand-bus-width: see nand-controller.yaml -- nand-ecc-mode: see nand-controller.yaml - -Required properties for hardware ECC: -- nand-ecc-strength: supported strengths are 24 and 32 bit (see nand-controller.yaml) -- nand-ecc-step-size: step size equals page size, currently only 2k pages are - supported -- nand-on-flash-bbt: see nand-controller.yaml - -Example: - - nfc: nand@400e0000 { - compatible = "fsl,vf610-nfc"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x400e0000 0x4000>; - interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_NFC>; - clock-names = "nfc"; - assigned-clocks = <&clks VF610_CLK_NFC>; - assigned-clock-rates = <33000000>; - - nand@0 { - compatible = "fsl,vf610-nfc-nandcs"; - reg = <0>; - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-ecc-strength = <32>; - nand-ecc-step-size = <2048>; - nand-on-flash-bbt; - }; - }; diff --git a/Documentation/devicetree/bindings/mux/gpio-mux.yaml b/Documentation/devicetree/bindings/mux/gpio-mux.yaml index b597c1f2c577..ef7e33ec85d4 100644 --- a/Documentation/devicetree/bindings/mux/gpio-mux.yaml +++ b/Documentation/devicetree/bindings/mux/gpio-mux.yaml @@ -25,6 +25,10 @@ properties: description: List of gpios used to control the multiplexer, least significant bit first. + mux-supply: + description: + Regulator to power on the multiplexer. + '#mux-control-cells': enum: [ 0, 1 ] diff --git a/Documentation/devicetree/bindings/net/aeonsemi,as21xxx.yaml b/Documentation/devicetree/bindings/net/aeonsemi,as21xxx.yaml new file mode 100644 index 000000000000..69eb29dc4d7b --- /dev/null +++ b/Documentation/devicetree/bindings/net/aeonsemi,as21xxx.yaml @@ -0,0 +1,122 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/aeonsemi,as21xxx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Aeonsemi AS21XXX Ethernet PHY + +maintainers: + - Christian Marangi <ansuelsmth@gmail.com> + +description: | + Aeonsemi AS21xxx Ethernet PHYs requires a firmware to be loaded to actually + work. The same firmware is compatible with various PHYs of the same family. + + A PHY with not firmware loaded will be exposed on the MDIO bus with ID + 0x7500 0x7500 or 0x7500 0x9410 on C45 registers. + + This can be done and is implemented by OEM in 2 different way: + - Attached SPI flash directly to the PHY with the firmware. The PHY + will self load the firmware in the presence of this configuration. + - Manually provided firmware loaded from a file in the filesystem. + + Each PHY can support up to 5 LEDs. + + AS2xxx PHY Name logic: + + AS21x1xxB1 + ^ ^^ + | |J: Supports SyncE/PTP + | |P: No SyncE/PTP support + | 1: Supports 2nd Serdes + | 2: Not 2nd Serdes support + 0: 10G, 5G, 2.5G + 5: 5G, 2.5G + 2: 2.5G + +allOf: + - $ref: ethernet-phy.yaml# + +select: + properties: + compatible: + contains: + enum: + - ethernet-phy-id7500.9410 + - ethernet-phy-id7500.9402 + - ethernet-phy-id7500.9412 + - ethernet-phy-id7500.9422 + - ethernet-phy-id7500.9432 + - ethernet-phy-id7500.9442 + - ethernet-phy-id7500.9452 + - ethernet-phy-id7500.9462 + - ethernet-phy-id7500.9472 + - ethernet-phy-id7500.9482 + - ethernet-phy-id7500.9492 + required: + - compatible + +properties: + reg: + maxItems: 1 + + firmware-name: + description: specify the name of PHY firmware to load + maxItems: 1 + +required: + - compatible + - reg + +if: + properties: + compatible: + contains: + const: ethernet-phy-id7500.9410 +then: + required: + - firmware-name +else: + properties: + firmware-name: false + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/leds/common.h> + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethernet-phy@1f { + compatible = "ethernet-phy-id7500.9410", + "ethernet-phy-ieee802.3-c45"; + + reg = <31>; + firmware-name = "as21x1x_fw.bin"; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_LAN; + function-enumerator = <0>; + default-state = "keep"; + }; + + led@1 { + reg = <1>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_LAN; + function-enumerator = <1>; + default-state = "keep"; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml b/Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml index c578637c5826..6d22131ac2f9 100644 --- a/Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml +++ b/Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml @@ -57,12 +57,30 @@ properties: - const: hsi-mac - const: xfp-mac + memory-region: + items: + - description: QDMA0 buffer memory + - description: QDMA1 buffer memory + + memory-region-names: + items: + - const: qdma0-buf + - const: qdma1-buf + "#address-cells": const: 1 "#size-cells": const: 0 + airoha,npu: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the node used to configure the NPU module. + The Airoha Network Processor Unit (NPU) provides a configuration + interface to implement hardware flow offloading programming Packet + Processor Engine (PPE) flow table. + patternProperties: "^ethernet@[1-4]$": type: object @@ -132,6 +150,11 @@ examples: <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; + memory-region = <&qdma0_buf>, <&qdma1_buf>; + memory-region-names = "qdma0-buf", "qdma1-buf"; + + airoha,npu = <&npu>; + #address-cells = <1>; #size-cells = <0>; diff --git a/Documentation/devicetree/bindings/net/airoha,en7581-npu.yaml b/Documentation/devicetree/bindings/net/airoha,en7581-npu.yaml new file mode 100644 index 000000000000..76dd97c3fb40 --- /dev/null +++ b/Documentation/devicetree/bindings/net/airoha,en7581-npu.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/airoha,en7581-npu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Airoha Network Processor Unit for EN7581 SoC + +maintainers: + - Lorenzo Bianconi <lorenzo@kernel.org> + +description: + The Airoha Network Processor Unit (NPU) provides a configuration interface + to implement wired and wireless hardware flow offloading programming Packet + Processor Engine (PPE) flow table. + +properties: + compatible: + enum: + - airoha,en7581-npu + + reg: + maxItems: 1 + + interrupts: + items: + - description: mbox host irq line + - description: watchdog0 irq line + - description: watchdog1 irq line + - description: watchdog2 irq line + - description: watchdog3 irq line + - description: watchdog4 irq line + - description: watchdog5 irq line + - description: watchdog6 irq line + - description: watchdog7 irq line + - description: wlan irq line0 + - description: wlan irq line1 + - description: wlan irq line2 + - description: wlan irq line3 + - description: wlan irq line4 + - description: wlan irq line5 + + memory-region: + maxItems: 1 + description: + Memory used to store NPU firmware binary. + +required: + - compatible + - reg + - interrupts + - memory-region + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + soc { + #address-cells = <2>; + #size-cells = <2>; + + npu@1e900000 { + compatible = "airoha,en7581-npu"; + reg = <0 0x1e900000 0 0x313000>; + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; + memory-region = <&npu_binary>; + }; + }; diff --git a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml index 7fe0352dff0f..19934d5c24e5 100644 --- a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml +++ b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml @@ -23,6 +23,7 @@ properties: - allwinner,sun20i-d1-emac - allwinner,sun50i-h6-emac - allwinner,sun50i-h616-emac0 + - allwinner,sun55i-a523-gmac0 - const: allwinner,sun50i-a64-emac reg: diff --git a/Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml b/Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml index 798a4c19f18c..0cd78d71768c 100644 --- a/Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml @@ -152,6 +152,12 @@ properties: The second range is is for the Amlogic specific configuration (for example the PRG_ETHERNET register range on Meson8b and newer) + interrupts: + maxItems: 1 + + interrupt-names: + const: macirq + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/net/bluetooth/nxp,88w8987-bt.yaml b/Documentation/devicetree/bindings/net/bluetooth/nxp,88w8987-bt.yaml index 0a2d7baf5db3..3ab60c70286f 100644 --- a/Documentation/devicetree/bindings/net/bluetooth/nxp,88w8987-bt.yaml +++ b/Documentation/devicetree/bindings/net/bluetooth/nxp,88w8987-bt.yaml @@ -17,6 +17,9 @@ description: maintainers: - Neeraj Sanjay Kale <neeraj.sanjaykale@nxp.com> +allOf: + - $ref: bluetooth-controller.yaml# + properties: compatible: enum: @@ -40,19 +43,49 @@ properties: Host-To-Chip power save mechanism is driven by this GPIO connected to BT_WAKE_IN pin of the NXP chipset. + nxp,wakein-pin: + $ref: /schemas/types.yaml#/definitions/uint8 + description: + The GPIO number of the NXP chipset used for BT_WAKE_IN. + + interrupts: + maxItems: 1 + description: + Host wakeup by falling edge interrupt on this pin which is + connected to BT_WAKE_OUT pin of the NXP chipset. + + interrupt-names: + items: + - const: wakeup + + wakeup-source: true + + nxp,wakeout-pin: + $ref: /schemas/types.yaml#/definitions/uint8 + description: + The GPIO number of the NXP chipset used for BT_WAKE_OUT. + required: - compatible -additionalProperties: false +unevaluatedProperties: false examples: - | #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interrupt-controller/irq.h> serial { bluetooth { compatible = "nxp,88w8987-bt"; fw-init-baudrate = <3000000>; firmware-name = "uartuart8987_bt_v0.bin"; device-wakeup-gpios = <&gpio 11 GPIO_ACTIVE_HIGH>; + nxp,wakein-pin = /bits/ 8 <18>; + nxp,wakeout-pin = /bits/ 8 <19>; + local-bd-address = [66 55 44 33 22 11]; + interrupt-parent = <&gpio>; + interrupts = <8 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "wakeup"; + wakeup-source; }; }; diff --git a/Documentation/devicetree/bindings/net/bluetooth/qualcomm-bluetooth.yaml b/Documentation/devicetree/bindings/net/bluetooth/qualcomm-bluetooth.yaml index a72152f7e29b..6353a336f382 100644 --- a/Documentation/devicetree/bindings/net/bluetooth/qualcomm-bluetooth.yaml +++ b/Documentation/devicetree/bindings/net/bluetooth/qualcomm-bluetooth.yaml @@ -19,6 +19,7 @@ properties: - qcom,qca2066-bt - qcom,qca6174-bt - qcom,qca9377-bt + - qcom,wcn3950-bt - qcom,wcn3988-bt - qcom,wcn3990-bt - qcom,wcn3991-bt @@ -138,6 +139,7 @@ allOf: compatible: contains: enum: + - qcom,wcn3950-bt - qcom,wcn3988-bt - qcom,wcn3990-bt - qcom,wcn3991-bt diff --git a/Documentation/devicetree/bindings/net/brcm,asp-v2.0.yaml b/Documentation/devicetree/bindings/net/brcm,asp-v2.0.yaml index 660e2ca42daf..a3db6d594c8c 100644 --- a/Documentation/devicetree/bindings/net/brcm,asp-v2.0.yaml +++ b/Documentation/devicetree/bindings/net/brcm,asp-v2.0.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/net/brcm,asp-v2.0.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Broadcom ASP 2.0 Ethernet controller +title: Broadcom ASP Ethernet controller maintainers: - Justin Chen <justin.chen@broadcom.com> @@ -17,16 +17,16 @@ properties: oneOf: - items: - enum: + - brcm,bcm74110-asp + - const: brcm,asp-v3.0 + - items: + - enum: - brcm,bcm74165b0-asp - const: brcm,asp-v2.2 - items: - enum: - brcm,bcm74165-asp - const: brcm,asp-v2.1 - - items: - - enum: - - brcm,bcm72165-asp - - const: brcm,asp-v2.0 "#address-cells": const: 1 @@ -39,11 +39,9 @@ properties: ranges: true interrupts: - minItems: 1 items: - description: RX/TX interrupt - - description: Port 0 Wake-on-LAN - - description: Port 1 Wake-on-LAN + - description: Wake-on-LAN interrupt clocks: maxItems: 1 @@ -106,16 +104,17 @@ examples: #include <dt-bindings/interrupt-controller/arm-gic.h> ethernet@9c00000 { - compatible = "brcm,bcm72165-asp", "brcm,asp-v2.0"; + compatible = "brcm,bcm74165-asp", "brcm,asp-v2.1"; reg = <0x9c00000 0x1fff14>; - interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; + interrupts-extended = <&intc GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, + <&aon_pm_l2_intc 14>; ranges = <0x0 0x9c00000 0x1fff14>; clocks = <&scmi 14>; #address-cells = <1>; #size-cells = <1>; mdio@c614 { - compatible = "brcm,asp-v2.0-mdio"; + compatible = "brcm,asp-v2.1-mdio"; reg = <0xc614 0x8>; reg-names = "mdio"; #address-cells = <1>; @@ -127,7 +126,7 @@ examples: }; mdio@ce14 { - compatible = "brcm,asp-v2.0-mdio"; + compatible = "brcm,asp-v2.1-mdio"; reg = <0xce14 0x8>; reg-names = "mdio"; #address-cells = <1>; diff --git a/Documentation/devicetree/bindings/net/brcm,unimac-mdio.yaml b/Documentation/devicetree/bindings/net/brcm,unimac-mdio.yaml index 63bee5b542f5..43516dd357b8 100644 --- a/Documentation/devicetree/bindings/net/brcm,unimac-mdio.yaml +++ b/Documentation/devicetree/bindings/net/brcm,unimac-mdio.yaml @@ -22,9 +22,9 @@ properties: - brcm,genet-mdio-v3 - brcm,genet-mdio-v4 - brcm,genet-mdio-v5 - - brcm,asp-v2.0-mdio - brcm,asp-v2.1-mdio - brcm,asp-v2.2-mdio + - brcm,asp-v3.0-mdio - brcm,unimac-mdio - brcm,bcm6846-mdio diff --git a/Documentation/devicetree/bindings/net/can/fsl,flexcan.yaml b/Documentation/devicetree/bindings/net/can/fsl,flexcan.yaml index 97dd1a7c5ed2..f81d56f7c12a 100644 --- a/Documentation/devicetree/bindings/net/can/fsl,flexcan.yaml +++ b/Documentation/devicetree/bindings/net/can/fsl,flexcan.yaml @@ -10,9 +10,6 @@ title: maintainers: - Marc Kleine-Budde <mkl@pengutronix.de> -allOf: - - $ref: can-controller.yaml# - properties: compatible: oneOf: @@ -28,6 +25,7 @@ properties: - fsl,vf610-flexcan - fsl,ls1021ar2-flexcan - fsl,lx2160ar1-flexcan + - nxp,s32g2-flexcan - items: - enum: - fsl,imx53-flexcan @@ -43,12 +41,25 @@ properties: - enum: - fsl,ls1028ar1-flexcan - const: fsl,lx2160ar1-flexcan + - items: + - enum: + - nxp,s32g3-flexcan + - const: nxp,s32g2-flexcan + - items: + - enum: + - fsl,imx94-flexcan + - const: fsl,imx95-flexcan reg: maxItems: 1 interrupts: - maxItems: 1 + minItems: 1 + maxItems: 4 + + interrupt-names: + minItems: 1 + maxItems: 4 clocks: maxItems: 2 @@ -70,6 +81,9 @@ properties: xceiver-supply: description: Regulator that powers the CAN transceiver. + phys: + maxItems: 1 + big-endian: $ref: /schemas/types.yaml#/definitions/flag description: | @@ -136,6 +150,41 @@ required: - reg - interrupts +allOf: + - $ref: can-controller.yaml# + - if: + properties: + compatible: + contains: + const: nxp,s32g2-flexcan + then: + properties: + interrupts: + items: + - description: Message Buffer interrupt for mailboxes 0-7 and Enhanced RX FIFO + - description: Device state change + - description: Bus Error detection + - description: Message Buffer interrupt for mailboxes 8-127 + interrupt-names: + items: + - const: mb-0 + - const: state + - const: berr + - const: mb-1 + required: + - interrupt-names + else: + properties: + interrupts: + maxItems: 1 + interrupt-names: false + - if: + required: + - xceiver-supply + then: + properties: + phys: false + additionalProperties: false examples: diff --git a/Documentation/devicetree/bindings/net/can/microchip,mcp2510.yaml b/Documentation/devicetree/bindings/net/can/microchip,mcp2510.yaml index e0ec53bc10c6..1525a50ded47 100644 --- a/Documentation/devicetree/bindings/net/can/microchip,mcp2510.yaml +++ b/Documentation/devicetree/bindings/net/can/microchip,mcp2510.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/can/microchip,mcp2510.yaml# +$id: http://devicetree.org/schemas/net/can/microchip,mcp2510.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Microchip MCP251X stand-alone CAN controller diff --git a/Documentation/devicetree/bindings/net/can/microchip,mcp251xfd.yaml b/Documentation/devicetree/bindings/net/can/microchip,mcp251xfd.yaml index 2a98b26630cb..c155c9c6db39 100644 --- a/Documentation/devicetree/bindings/net/can/microchip,mcp251xfd.yaml +++ b/Documentation/devicetree/bindings/net/can/microchip,mcp251xfd.yaml @@ -40,7 +40,7 @@ properties: microchip,rx-int-gpios: description: - GPIO phandle of GPIO connected to to INT1 pin of the MCP251XFD, which + GPIO phandle of GPIO connected to INT1 pin of the MCP251XFD, which signals a pending RX interrupt. maxItems: 1 diff --git a/Documentation/devicetree/bindings/net/can/nxp,sja1000.yaml b/Documentation/devicetree/bindings/net/can/nxp,sja1000.yaml index 144a3785132c..ec0c2168e4b9 100644 --- a/Documentation/devicetree/bindings/net/can/nxp,sja1000.yaml +++ b/Documentation/devicetree/bindings/net/can/nxp,sja1000.yaml @@ -16,9 +16,7 @@ properties: - nxp,sja1000 - technologic,sja1000 - items: - - enum: - - renesas,r9a06g032-sja1000 # RZ/N1D - - renesas,r9a06g033-sja1000 # RZ/N1S + - const: renesas,r9a06g032-sja1000 # RZ/N1D - const: renesas,rzn1-sja1000 # RZ/N1 reg: diff --git a/Documentation/devicetree/bindings/net/can/renesas,rcar-canfd.yaml b/Documentation/devicetree/bindings/net/can/renesas,rcar-canfd.yaml index f6884f6e59e7..f4ac21c68427 100644 --- a/Documentation/devicetree/bindings/net/can/renesas,rcar-canfd.yaml +++ b/Documentation/devicetree/bindings/net/can/renesas,rcar-canfd.yaml @@ -42,19 +42,80 @@ properties: - renesas,r9a07g054-canfd # RZ/V2L - const: renesas,rzg2l-canfd # RZ/G2L family + - const: renesas,r9a09g047-canfd # RZ/G3E + reg: maxItems: 1 - interrupts: true + interrupts: + oneOf: + - items: + - description: Channel interrupt + - description: Global interrupt + - items: + - description: CAN global error interrupt + - description: CAN receive FIFO interrupt + - description: CAN0 error interrupt + - description: CAN0 transmit interrupt + - description: CAN0 transmit/receive FIFO receive completion interrupt + - description: CAN1 error interrupt + - description: CAN1 transmit interrupt + - description: CAN1 transmit/receive FIFO receive completion interrupt + - description: CAN2 error interrupt + - description: CAN2 transmit interrupt + - description: CAN2 transmit/receive FIFO receive completion interrupt + - description: CAN3 error interrupt + - description: CAN3 transmit interrupt + - description: CAN3 transmit/receive FIFO receive completion interrupt + - description: CAN4 error interrupt + - description: CAN4 transmit interrupt + - description: CAN4 transmit/receive FIFO receive completion interrupt + - description: CAN5 error interrupt + - description: CAN5 transmit interrupt + - description: CAN5 transmit/receive FIFO receive completion interrupt + minItems: 8 + + interrupt-names: + oneOf: + - items: + - const: ch_int + - const: g_int + - items: + - const: g_err + - const: g_recc + - const: ch0_err + - const: ch0_rec + - const: ch0_trx + - const: ch1_err + - const: ch1_rec + - const: ch1_trx + - const: ch2_err + - const: ch2_rec + - const: ch2_trx + - const: ch3_err + - const: ch3_rec + - const: ch3_trx + - const: ch4_err + - const: ch4_rec + - const: ch4_trx + - const: ch5_err + - const: ch5_rec + - const: ch5_trx + minItems: 8 clocks: maxItems: 3 clock-names: - items: - - const: fck - - const: canfd - - const: can_clk + oneOf: + - items: + - const: fck + - const: canfd + - const: can_clk + - items: + - const: fck + - const: ram_clk + - const: can_clk power-domains: maxItems: 1 @@ -117,48 +178,38 @@ allOf: then: properties: interrupts: - items: - - description: CAN global error interrupt - - description: CAN receive FIFO interrupt - - description: CAN0 error interrupt - - description: CAN0 transmit interrupt - - description: CAN0 transmit/receive FIFO receive completion interrupt - - description: CAN1 error interrupt - - description: CAN1 transmit interrupt - - description: CAN1 transmit/receive FIFO receive completion interrupt + maxItems: 8 interrupt-names: - items: - - const: g_err - - const: g_recc - - const: ch0_err - - const: ch0_rec - - const: ch0_trx - - const: ch1_err - - const: ch1_rec - - const: ch1_trx + maxItems: 8 resets: + minItems: 2 maxItems: 2 reset-names: - items: - - const: rstp_n - - const: rstc_n + minItems: 2 + maxItems: 2 required: - reset-names - else: + + - if: + properties: + compatible: + contains: + enum: + - renesas,rcar-gen3-canfd + - renesas,rcar-gen4-canfd + then: properties: interrupts: - items: - - description: Channel interrupt - - description: Global interrupt + minItems: 2 + maxItems: 2 interrupt-names: - items: - - const: ch_int - - const: g_int + minItems: 2 + maxItems: 2 resets: maxItems: 1 @@ -167,20 +218,54 @@ allOf: properties: compatible: contains: + const: renesas,r9a09g047-canfd + then: + properties: + interrupts: + minItems: 20 + + interrupt-names: + minItems: 20 + + resets: + minItems: 2 + maxItems: 2 + + reset-names: + minItems: 2 + maxItems: 2 + + required: + - reset-names + + - if: + properties: + compatible: + contains: + enum: + - renesas,rcar-gen3-canfd + - renesas,rzg2l-canfd + then: + patternProperties: + "^channel[2-7]$": false + + - if: + properties: + compatible: + contains: const: renesas,r8a779h0-canfd then: patternProperties: "^channel[4-7]$": false - else: - if: - not: - properties: - compatible: - contains: - const: renesas,rcar-gen4-canfd - then: - patternProperties: - "^channel[2-7]$": false + + - if: + properties: + compatible: + contains: + const: renesas,r9a09g047-canfd + then: + patternProperties: + "^channel[6-7]$": false unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/net/cdns,macb.yaml b/Documentation/devicetree/bindings/net/cdns,macb.yaml index 3c30dd23cd4e..8d69846b2e09 100644 --- a/Documentation/devicetree/bindings/net/cdns,macb.yaml +++ b/Documentation/devicetree/bindings/net/cdns,macb.yaml @@ -197,7 +197,6 @@ examples: }; - | - #include <dt-bindings/clock/xlnx-zynqmp-clk.h> #include <dt-bindings/power/xlnx-zynqmp-power.h> #include <dt-bindings/reset/xlnx-zynqmp-resets.h> #include <dt-bindings/phy/phy.h> @@ -210,9 +209,9 @@ examples: interrupt-parent = <&gic>; interrupts = <0 59 4>, <0 59 4>; reg = <0x0 0xff0c0000 0x0 0x1000>; - clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>, - <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>, - <&zynqmp_clk GEM_TSU>; + clocks = <&zynqmp_clk 31>, <&zynqmp_clk 105>, + <&zynqmp_clk 51>, <&zynqmp_clk 50>, + <&zynqmp_clk 44>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; #size-cells = <0>; diff --git a/Documentation/devicetree/bindings/net/dsa/brcm,b53.yaml b/Documentation/devicetree/bindings/net/dsa/brcm,b53.yaml index 4c78c546343f..d6c957a33b48 100644 --- a/Documentation/devicetree/bindings/net/dsa/brcm,b53.yaml +++ b/Documentation/devicetree/bindings/net/dsa/brcm,b53.yaml @@ -16,6 +16,7 @@ properties: compatible: oneOf: - const: brcm,bcm5325 + - const: brcm,bcm53101 - const: brcm,bcm53115 - const: brcm,bcm53125 - const: brcm,bcm53128 @@ -77,6 +78,7 @@ allOf: contains: enum: - brcm,bcm5325 + - brcm,bcm53101 - brcm,bcm53115 - brcm,bcm53125 - brcm,bcm53128 diff --git a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml index ea979bcae1d6..51205f9f2985 100644 --- a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml +++ b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml @@ -96,6 +96,10 @@ properties: Built-in switch of the Airoha EN7581 SoC const: airoha,en7581-switch + - description: + Built-in switch of the Airoha AN7583 SoC + const: airoha,an7583-switch + reg: maxItems: 1 @@ -291,6 +295,7 @@ allOf: enum: - mediatek,mt7988-switch - airoha,en7581-switch + - airoha,an7583-switch then: $ref: "#/$defs/mt7530-dsa-port" properties: diff --git a/Documentation/devicetree/bindings/net/ethernet-controller.yaml b/Documentation/devicetree/bindings/net/ethernet-controller.yaml index 45819b235800..7cbf11bbe99c 100644 --- a/Documentation/devicetree/bindings/net/ethernet-controller.yaml +++ b/Documentation/devicetree/bindings/net/ethernet-controller.yaml @@ -16,30 +16,6 @@ properties: label: description: Human readable label on a port of a box. - local-mac-address: - description: - Specifies the MAC address that was assigned to the network device. - $ref: /schemas/types.yaml#/definitions/uint8-array - minItems: 6 - maxItems: 6 - - mac-address: - description: - Specifies the MAC address that was last used by the boot - program; should be used in cases where the MAC address assigned - to the device by the boot program is different from the - local-mac-address property. - $ref: /schemas/types.yaml#/definitions/uint8-array - minItems: 6 - maxItems: 6 - - max-frame-size: - $ref: /schemas/types.yaml#/definitions/uint32 - description: - Maximum transfer unit (IEEE defined MTU), rather than the - maximum frame size (there\'s contradiction in the Devicetree - Specification). - max-speed: $ref: /schemas/types.yaml#/definitions/uint32 description: @@ -74,19 +50,17 @@ properties: - rev-rmii - moca - # RX and TX delays are added by the MAC when required + # RX and TX delays are provided by the PCB. See below - rgmii - # RGMII with internal RX and TX delays provided by the PHY, - # the MAC should not add the RX or TX delays in this case + # RX and TX delays are not provided by the PCB. This is the most + # frequent case. See below - rgmii-id - # RGMII with internal RX delay provided by the PHY, the MAC - # should not add an RX delay in this case + # TX delay is provided by the PCB. See below - rgmii-rxid - # RGMII with internal TX delay provided by the PHY, the MAC - # should not add an TX delay in this case + # RX delay is provided by the PCB. See below - rgmii-txid - rtbi - smii @@ -197,7 +171,7 @@ properties: description: Link speed. $ref: /schemas/types.yaml#/definitions/uint32 - enum: [10, 100, 1000, 2500, 10000] + enum: [10, 100, 1000, 2500, 5000, 10000] full-duplex: $ref: /schemas/types.yaml#/definitions/flag @@ -262,6 +236,7 @@ dependencies: pcs-handle-names: [pcs-handle] allOf: + - $ref: /schemas/net/network-class.yaml# - if: properties: phy-mode: @@ -286,4 +261,89 @@ allOf: additionalProperties: true +# Informative +# =========== +# +# 'phy-modes' & 'phy-connection-type' properties 'rgmii', 'rgmii-id', +# 'rgmii-rxid', and 'rgmii-txid' are frequently used wrongly by +# developers. This informative section clarifies their usage. +# +# The RGMII specification requires a 2ns delay between the data and +# clock signals on the RGMII bus. How this delay is implemented is not +# specified. +# +# One option is to make the clock traces on the PCB longer than the +# data traces. A sufficiently difference in length can provide the 2ns +# delay. If both the RX and TX delays are implemented in this manner, +# 'rgmii' should be used, so indicating the PCB adds the delays. +# +# If the PCB does not add these delays via extra long traces, +# 'rgmii-id' should be used. Here, 'id' refers to 'internal delay', +# where either the MAC or PHY adds the delay. +# +# If only one of the two delays are implemented via extra long clock +# lines, either 'rgmii-rxid' or 'rgmii-txid' should be used, +# indicating the MAC or PHY should implement one of the delays +# internally, while the PCB implements the other delay. +# +# Device Tree describes hardware, and in this case, it describes the +# PCB between the MAC and the PHY, if the PCB implements delays or +# not. +# +# In practice, very few PCBs make use of extra long clock lines. Hence +# any RGMII phy mode other than 'rgmii-id' is probably wrong, and is +# unlikely to be accepted during review without details provided in +# the commit description and comments in the .dts file. +# +# When the PCB does not implement the delays, the MAC or PHY must. As +# such, this is software configuration, and so not described in Device +# Tree. +# +# The following describes how Linux implements the configuration of +# the MAC and PHY to add these delays when the PCB does not. As stated +# above, developers often get this wrong, and the aim of this section +# is reduce the frequency of these errors by Linux developers. Other +# users of the Device Tree may implement it differently, and still be +# consistent with both the normative and informative description +# above. +# +# By default in Linux, when using phylib/phylink, the MAC is expected +# to read the 'phy-mode' from Device Tree, not implement any delays, +# and pass the value to the PHY. The PHY will then implement delays as +# specified by the 'phy-mode'. The PHY should always be reconfigured +# to implement the needed delays, replacing any setting performed by +# strapping or the bootloader, etc. +# +# Experience to date is that all PHYs which implement RGMII also +# implement the ability to add or not add the needed delays. Hence +# this default is expected to work in all cases. Ignoring this default +# is likely to be questioned by Reviews, and require a strong argument +# to be accepted. +# +# There are a small number of cases where the MAC has hard coded +# delays which cannot be disabled. The 'phy-mode' only describes the +# PCB. The inability to disable the delays in the MAC does not change +# the meaning of 'phy-mode'. It does however mean that a 'phy-mode' of +# 'rgmii' is now invalid, it cannot be supported, since both the PCB +# and the MAC and PHY adding delays cannot result in a functional +# link. Thus the MAC should report a fatal error for any modes which +# cannot be supported. When the MAC implements the delay, it must +# ensure that the PHY does not also implement the same delay. So it +# must modify the phy-mode it passes to the PHY, removing the delay it +# has added. Failure to remove the delay will result in a +# non-functioning link. +# +# Sometimes there is a need to fine tune the delays. Often the MAC or +# PHY can perform this fine tuning. In the MAC node, the Device Tree +# properties 'rx-internal-delay-ps' and 'tx-internal-delay-ps' should +# be used to indicate fine tuning performed by the MAC. The values +# expected here are small. A value of 2000ps, i.e 2ns, and a phy-mode +# of 'rgmii' will not be accepted by Reviewers. +# +# If the PHY is to perform fine tuning, the properties +# 'rx-internal-delay-ps' and 'tx-internal-delay-ps' in the PHY node +# should be used. When the PHY is implementing delays, e.g. 'rgmii-id' +# these properties should have a value near to 2000ps. If the PCB is +# implementing delays, e.g. 'rgmii', a small value can be used to fine +# tune the delay added by the PCB. ... diff --git a/Documentation/devicetree/bindings/net/ethernet-phy.yaml b/Documentation/devicetree/bindings/net/ethernet-phy.yaml index 2c71454ae8e3..71e2cd32580f 100644 --- a/Documentation/devicetree/bindings/net/ethernet-phy.yaml +++ b/Documentation/devicetree/bindings/net/ethernet-phy.yaml @@ -232,6 +232,22 @@ properties: PHY's that have configurable TX internal delays. If this property is present then the PHY applies the TX delay. + tx-amplitude-100base-tx-percent: + description: + Transmit amplitude gain applied for 100BASE-TX. 100% matches 2V + peak-to-peak specified in ANSI X3.263. When omitted, the PHYs default + will be left as is. + + mac-termination-ohms: + maximum: 200 + description: + The xMII signals need series termination on the driver side to match both + the output driver impedance and the line characteristic impedance, to + prevent reflections and EMI problems. Select a resistance value which is + supported by the builtin resistors of the PHY, otherwise the resistors may + have to be placed on board. When omitted, the PHYs default will be left as + is. + leds: type: object diff --git a/Documentation/devicetree/bindings/net/faraday,ftgmac100.yaml b/Documentation/devicetree/bindings/net/faraday,ftgmac100.yaml index 9bcbacb6640d..55d6a8379025 100644 --- a/Documentation/devicetree/bindings/net/faraday,ftgmac100.yaml +++ b/Documentation/devicetree/bindings/net/faraday,ftgmac100.yaml @@ -44,6 +44,9 @@ properties: phy-mode: enum: - rgmii + - rgmii-id + - rgmii-rxid + - rgmii-txid - rmii phy-handle: true diff --git a/Documentation/devicetree/bindings/net/fsl,gianfar-mdio.yaml b/Documentation/devicetree/bindings/net/fsl,gianfar-mdio.yaml new file mode 100644 index 000000000000..03c819bc701b --- /dev/null +++ b/Documentation/devicetree/bindings/net/fsl,gianfar-mdio.yaml @@ -0,0 +1,112 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/fsl,gianfar-mdio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale Gianfar (TSEC) MDIO Device + +description: + This binding describes the MDIO is a bus to which the PHY devices are + connected. For each device that exists on this bus, a child node should be + created. + + Some TSECs are associated with an internal Ten-Bit Interface (TBI) PHY. This + PHY is accessed through the local MDIO bus. These buses are defined similarly + to the mdio buses, except they are compatible with "fsl,gianfar-tbi". The TBI + PHYs underneath them are similar to normal PHYs, but the reg property is + considered instructive, rather than descriptive. The reg property should be + chosen so it doesn't interfere with other PHYs on the bus. + +maintainers: + - J. Neuschäfer <j.ne@posteo.net> + +# This is needed to distinguish gianfar.yaml and gianfar-mdio.yaml, because +# both use compatible = "gianfar" (with different device_type values) +select: + oneOf: + - properties: + compatible: + contains: + const: gianfar + device_type: + const: mdio + required: + - device_type + + - properties: + compatible: + contains: + enum: + - fsl,gianfar-tbi + - fsl,gianfar-mdio + - fsl,etsec2-tbi + - fsl,etsec2-mdio + - fsl,ucc-mdio + - ucc_geth_phy + + required: + - compatible + +properties: + compatible: + enum: + - fsl,gianfar-tbi + - fsl,gianfar-mdio + - fsl,etsec2-tbi + - fsl,etsec2-mdio + - fsl,ucc-mdio + - gianfar + - ucc_geth_phy + + reg: + minItems: 1 + items: + - description: + Offset and length of the register set for the device + + - description: + Optionally, the offset and length of the TBIPA register (TBI PHY + address register). If TBIPA register is not specified, the driver + will attempt to infer it from the register set specified (your + mileage may vary). + + device_type: + const: mdio + +required: + - reg + - "#address-cells" + - "#size-cells" + +allOf: + - $ref: mdio.yaml# + + - if: + properties: + compatible: + contains: + const: ucc_geth_phy + then: + required: + - device_type + +unevaluatedProperties: false + +examples: + - | + soc { + #address-cells = <1>; + #size-cells = <1>; + + mdio@24520 { + reg = <0x24520 0x20>; + compatible = "fsl,gianfar-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethernet-phy@0 { + reg = <0>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/net/fsl,gianfar.yaml b/Documentation/devicetree/bindings/net/fsl,gianfar.yaml new file mode 100644 index 000000000000..f92f284aa05b --- /dev/null +++ b/Documentation/devicetree/bindings/net/fsl,gianfar.yaml @@ -0,0 +1,248 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/fsl,gianfar.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale Three-Speed Ethernet Controller (TSEC), "Gianfar" + +maintainers: + - J. Neuschäfer <j.ne@posteo.net> + +# This is needed to distinguish gianfar.yaml and gianfar-mdio.yaml, because +# both use compatible = "gianfar" (with different device_type values) +select: + oneOf: + - properties: + compatible: + contains: + const: gianfar + device_type: + const: network + required: + - device_type + + - properties: + compatible: + const: fsl,etsec2 + + required: + - compatible + +properties: + compatible: + enum: + - gianfar + - fsl,etsec2 + + device_type: + const: network + + model: + enum: + - FEC + - TSEC + - eTSEC + + reg: + maxItems: 1 + + ranges: true + + "#address-cells": + enum: [ 1, 2 ] + + "#size-cells": + enum: [ 1, 2 ] + + cell-index: + $ref: /schemas/types.yaml#/definitions/uint32 + + interrupts: + minItems: 1 + items: + - description: Transmit interrupt or single combined interrupt + - description: Receive interrupt + - description: Error interrupt + + dma-coherent: true + + fsl,magic-packet: + type: boolean + description: + If present, indicates that the hardware supports waking up via magic packet. + + fsl,wake-on-filer: + type: boolean + description: + If present, indicates that the hardware supports waking up by Filer + General Purpose Interrupt (FGPI) asserted on the Rx int line. This is + an advanced power management capability allowing certain packet types + (user) defined by filer rules to wake up the system. + + bd-stash: + type: boolean + description: + If present, indicates that the hardware supports stashing buffer + descriptors in the L2. + + rx-stash-len: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Denotes the number of bytes of a received buffer to stash in the L2. + + rx-stash-idx: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Denotes the index of the first byte from the received buffer to stash in + the L2. + + fsl,num_rx_queues: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Number of receive queues + const: 8 + + fsl,num_tx_queues: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Number of transmit queues + const: 8 + + tbi-handle: + $ref: /schemas/types.yaml#/definitions/phandle + description: Reference (phandle) to the TBI node + +required: + - compatible + - model + +patternProperties: + "^mdio@[0-9a-f]+$": + $ref: /schemas/net/fsl,gianfar-mdio.yaml# + +allOf: + - $ref: ethernet-controller.yaml# + + # eTSEC2 controller nodes have "queue group" subnodes and don't need a "reg" + # property. + - if: + properties: + compatible: + contains: + const: fsl,etsec2 + then: + patternProperties: + "^queue-group@[0-9a-f]+$": + type: object + + properties: + reg: + maxItems: 1 + + interrupts: + items: + - description: Transmit interrupt + - description: Receive interrupt + - description: Error interrupt + + required: + - reg + - interrupts + + additionalProperties: false + else: + required: + - reg + + # TSEC and eTSEC devices require three interrupts + - if: + properties: + model: + contains: + enum: [ TSEC, eTSEC ] + then: + properties: + interrupts: + items: + - description: Transmit interrupt + - description: Receive interrupt + - description: Error interrupt + + + +unevaluatedProperties: false + +examples: + - | + ethernet@24000 { + device_type = "network"; + model = "TSEC"; + compatible = "gianfar"; + reg = <0x24000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <29 2>, <30 2>, <34 2>; + interrupt-parent = <&mpic>; + phy-handle = <&phy0>; + }; + + - | + #include <dt-bindings/interrupt-controller/irq.h> + + ethernet@24000 { + compatible = "gianfar"; + reg = <0x24000 0x1000>; + ranges = <0x0 0x24000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + cell-index = <0>; + device_type = "network"; + model = "eTSEC"; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <32 IRQ_TYPE_LEVEL_LOW>, + <33 IRQ_TYPE_LEVEL_LOW>, + <34 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&ipic>; + + mdio@520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,gianfar-mdio"; + reg = <0x520 0x20>; + }; + }; + + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + bus { + #address-cells = <2>; + #size-cells = <2>; + + ethernet { + compatible = "fsl,etsec2"; + ranges; + device_type = "network"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic>; + model = "eTSEC"; + fsl,magic-packet; + dma-coherent; + + queue-group@2d10000 { + reg = <0x0 0x2d10000 0x0 0x1000>; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; + }; + + queue-group@2d14000 { + reg = <0x0 0x2d14000 0x0 0x1000>; + interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt index 9c9668c1b6a2..b18bb4c997ea 100644 --- a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt +++ b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt @@ -1,88 +1,14 @@ * MDIO IO device -The MDIO is a bus to which the PHY devices are connected. For each -device that exists on this bus, a child node should be created. See -the definition of the PHY node in booting-without-of.txt for an example -of how to define a PHY. - -Required properties: - - reg : Offset and length of the register set for the device, and optionally - the offset and length of the TBIPA register (TBI PHY address - register). If TBIPA register is not specified, the driver will - attempt to infer it from the register set specified (your mileage may - vary). - - compatible : Should define the compatible device type for the - mdio. Currently supported strings/devices are: - - "fsl,gianfar-tbi" - - "fsl,gianfar-mdio" - - "fsl,etsec2-tbi" - - "fsl,etsec2-mdio" - - "fsl,ucc-mdio" - - "fsl,fman-mdio" - When device_type is "mdio", the following strings are also considered: - - "gianfar" - - "ucc_geth_phy" - -Example: - - mdio@24520 { - reg = <24520 20>; - compatible = "fsl,gianfar-mdio"; - - ethernet-phy@0 { - ...... - }; - }; +Refer to Documentation/devicetree/bindings/net/fsl,gianfar-mdio.yaml * TBI Internal MDIO bus -As of this writing, every tsec is associated with an internal TBI PHY. -This PHY is accessed through the local MDIO bus. These buses are defined -similarly to the mdio buses, except they are compatible with "fsl,gianfar-tbi". -The TBI PHYs underneath them are similar to normal PHYs, but the reg property -is considered instructive, rather than descriptive. The reg property should -be chosen so it doesn't interfere with other PHYs on the bus. +Refer to Documentation/devicetree/bindings/net/fsl,gianfar-mdio.yaml * Gianfar-compatible ethernet nodes -Properties: - - - device_type : Should be "network" - - model : Model of the device. Can be "TSEC", "eTSEC", or "FEC" - - compatible : Should be "gianfar" - - reg : Offset and length of the register set for the device - - interrupts : For FEC devices, the first interrupt is the device's - interrupt. For TSEC and eTSEC devices, the first interrupt is - transmit, the second is receive, and the third is error. - - phy-handle : See ethernet.txt file in the same directory. - - fixed-link : See fixed-link.txt in the same directory. - - phy-connection-type : See ethernet.txt file in the same directory. - This property is only really needed if the connection is of type - "rgmii-id", as all other connection types are detected by hardware. - - fsl,magic-packet : If present, indicates that the hardware supports - waking up via magic packet. - - fsl,wake-on-filer : If present, indicates that the hardware supports - waking up by Filer General Purpose Interrupt (FGPI) asserted on the - Rx int line. This is an advanced power management capability allowing - certain packet types (user) defined by filer rules to wake up the system. - - bd-stash : If present, indicates that the hardware supports stashing - buffer descriptors in the L2. - - rx-stash-len : Denotes the number of bytes of a received buffer to stash - in the L2. - - rx-stash-idx : Denotes the index of the first byte from the received - buffer to stash in the L2. - -Example: - ethernet@24000 { - device_type = "network"; - model = "TSEC"; - compatible = "gianfar"; - reg = <0x24000 0x1000>; - local-mac-address = [ 00 E0 0C 00 73 00 ]; - interrupts = <29 2 30 2 34 2>; - interrupt-parent = <&mpic>; - phy-handle = <&phy0> - }; +Refer to Documentation/devicetree/bindings/net/fsl,gianfar.yaml * Gianfar PTP clock nodes diff --git a/Documentation/devicetree/bindings/net/ieee802154/ca8210.txt b/Documentation/devicetree/bindings/net/ieee802154/ca8210.txt index a1046e636fa1..f1bd07a0097d 100644 --- a/Documentation/devicetree/bindings/net/ieee802154/ca8210.txt +++ b/Documentation/devicetree/bindings/net/ieee802154/ca8210.txt @@ -20,7 +20,7 @@ Example: reg = <0>; spi-max-frequency = <3000000>; spi-cpol; - reset-gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>; + reset-gpio = <&gpio1 1 GPIO_ACTIVE_LOW>; irq-gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; extclock-enable; extclock-freq = 16000000; diff --git a/Documentation/devicetree/bindings/net/intel,dwmac-plat.yaml b/Documentation/devicetree/bindings/net/intel,dwmac-plat.yaml index 42a0bc94312c..62c1da36a2b5 100644 --- a/Documentation/devicetree/bindings/net/intel,dwmac-plat.yaml +++ b/Documentation/devicetree/bindings/net/intel,dwmac-plat.yaml @@ -41,6 +41,12 @@ properties: - const: ptp_ref - const: tx_clk + interrupts: + maxItems: 1 + + interrupt-names: + const: macirq + required: - compatible - clocks diff --git a/Documentation/devicetree/bindings/net/mediatek-dwmac.yaml b/Documentation/devicetree/bindings/net/mediatek-dwmac.yaml index ed9d845f6008..3aab21b8e8de 100644 --- a/Documentation/devicetree/bindings/net/mediatek-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/mediatek-dwmac.yaml @@ -64,6 +64,12 @@ properties: - const: rmii_internal - const: mac_cg + interrupts: + maxItems: 1 + + interrupt-names: + const: macirq + power-domains: maxItems: 1 diff --git a/Documentation/devicetree/bindings/net/network-class.yaml b/Documentation/devicetree/bindings/net/network-class.yaml new file mode 100644 index 000000000000..06461fb92eb8 --- /dev/null +++ b/Documentation/devicetree/bindings/net/network-class.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/network-class.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Network Class Common Properties + +maintainers: + - Devicetree Specification Mailing List <devicetree-spec@vger.kernel.org> + +properties: + address-bits: + description: + Specifies number of address bits required to address the device + described by this node, e.g. size of the MAC address. + default: 48 + const: 48 + + local-mac-address: + description: + Specifies MAC address that was assigned to the network device described by + the node containing this property. + $ref: /schemas/types.yaml#/definitions/uint8-array + minItems: 6 + maxItems: 6 + + mac-address: + description: + Specifies the MAC address that was last used by the boot program. This + property should be used in cases where the MAC address assigned to the + device by the boot program is different from the + local-mac-address property. This property shall be used only if the value + differs from local-mac-address property value. + $ref: /schemas/types.yaml#/definitions/uint8-array + minItems: 6 + maxItems: 6 + + max-frame-size: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Maximum transfer unit (IEEE defined MTU), rather than the + maximum frame size (there\'s contradiction in the Devicetree + Specification). + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/net/nxp,dwmac-imx.yaml b/Documentation/devicetree/bindings/net/nxp,dwmac-imx.yaml index 87bc4416eadf..e5db346beca9 100644 --- a/Documentation/devicetree/bindings/net/nxp,dwmac-imx.yaml +++ b/Documentation/devicetree/bindings/net/nxp,dwmac-imx.yaml @@ -56,6 +56,14 @@ properties: - tx - mem + interrupts: + maxItems: 2 + + interrupt-names: + items: + - const: macirq + - const: eth_wake_irq + intf_mode: $ref: /schemas/types.yaml#/definitions/phandle-array items: diff --git a/Documentation/devicetree/bindings/net/qcom,ipa.yaml b/Documentation/devicetree/bindings/net/qcom,ipa.yaml index 1a46d80a66e8..b4a79912d473 100644 --- a/Documentation/devicetree/bindings/net/qcom,ipa.yaml +++ b/Documentation/devicetree/bindings/net/qcom,ipa.yaml @@ -210,70 +210,70 @@ additionalProperties: false examples: - | - #include <dt-bindings/interrupt-controller/arm-gic.h> - #include <dt-bindings/clock/qcom,rpmh.h> - #include <dt-bindings/interconnect/qcom,sdm845.h> - - smp2p-mpss { - compatible = "qcom,smp2p"; - interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; - mboxes = <&apss_shared 6>; - qcom,smem = <94>, <432>; - qcom,local-pid = <0>; - qcom,remote-pid = <5>; - - ipa_smp2p_out: ipa-ap-to-modem { - qcom,entry-name = "ipa"; - #qcom,smem-state-cells = <1>; - }; - - ipa_smp2p_in: ipa-modem-to-ap { - qcom,entry-name = "ipa"; - interrupt-controller; - #interrupt-cells = <2>; - }; + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/interconnect/qcom,sdm845.h> + + smp2p-mpss { + compatible = "qcom,smp2p"; + interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; + mboxes = <&apss_shared 6>; + qcom,smem = <94>, <432>; + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + ipa_smp2p_out: ipa-ap-to-modem { + qcom,entry-name = "ipa"; + #qcom,smem-state-cells = <1>; }; - ipa@1e40000 { - compatible = "qcom,sc7180-ipa"; - - qcom,gsi-loader = "self"; - memory-region = <&ipa_fw_mem>; - firmware-name = "qcom/sc7180-trogdor/modem/modem.mbn"; - - iommus = <&apps_smmu 0x440 0x0>, - <&apps_smmu 0x442 0x0>; - reg = <0x1e40000 0x7000>, - <0x1e47000 0x2000>, - <0x1e04000 0x2c000>; - reg-names = "ipa-reg", - "ipa-shared", - "gsi"; - - interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>, - <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, - <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "ipa", - "gsi", - "ipa-clock-query", - "ipa-setup-ready"; - - clocks = <&rpmhcc RPMH_IPA_CLK>; - clock-names = "core"; - - interconnects = - <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, - <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; - interconnect-names = "memory", - "imem", - "config"; - - qcom,qmp = <&aoss_qmp>; - - qcom,smem-states = <&ipa_smp2p_out 0>, - <&ipa_smp2p_out 1>; - qcom,smem-state-names = "ipa-clock-enabled-valid", - "ipa-clock-enabled"; + ipa_smp2p_in: ipa-modem-to-ap { + qcom,entry-name = "ipa"; + interrupt-controller; + #interrupt-cells = <2>; }; + }; + + ipa@1e40000 { + compatible = "qcom,sc7180-ipa"; + + qcom,gsi-loader = "self"; + memory-region = <&ipa_fw_mem>; + firmware-name = "qcom/sc7180-trogdor/modem/modem.mbn"; + + iommus = <&apps_smmu 0x440 0x0>, + <&apps_smmu 0x442 0x0>; + reg = <0x1e40000 0x7000>, + <0x1e47000 0x2000>, + <0x1e04000 0x2c000>; + reg-names = "ipa-reg", + "ipa-shared", + "gsi"; + + interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, + <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ipa", + "gsi", + "ipa-clock-query", + "ipa-setup-ready"; + + clocks = <&rpmhcc RPMH_IPA_CLK>; + clock-names = "core"; + + interconnects = + <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, + <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; + interconnect-names = "memory", + "imem", + "config"; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&ipa_smp2p_out 0>, + <&ipa_smp2p_out 1>; + qcom,smem-state-names = "ipa-clock-enabled-valid", + "ipa-clock-enabled"; + }; diff --git a/Documentation/devicetree/bindings/net/realtek,rtl9301-mdio.yaml b/Documentation/devicetree/bindings/net/realtek,rtl9301-mdio.yaml new file mode 100644 index 000000000000..02e4e33e9969 --- /dev/null +++ b/Documentation/devicetree/bindings/net/realtek,rtl9301-mdio.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/realtek,rtl9301-mdio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Realtek RTL9300 MDIO Controller + +maintainers: + - Chris Packham <chris.packham@alliedtelesis.co.nz> + +properties: + compatible: + oneOf: + - items: + - enum: + - realtek,rtl9302b-mdio + - realtek,rtl9302c-mdio + - realtek,rtl9303-mdio + - const: realtek,rtl9301-mdio + - const: realtek,rtl9301-mdio + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + reg: + maxItems: 1 + +patternProperties: + '^mdio-bus@[0-3]$': + $ref: mdio.yaml# + + properties: + reg: + maxItems: 1 + + required: + - reg + + patternProperties: + '^ethernet-phy@[a-f0-9]+$': + type: object + $ref: ethernet-phy.yaml# + unevaluatedProperties: false + + unevaluatedProperties: false + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + mdio-controller@ca00 { + compatible = "realtek,rtl9301-mdio"; + reg = <0xca00 0x200>; + #address-cells = <1>; + #size-cells = <0>; + + mdio-bus@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0>; + }; + }; + + mdio-bus@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/mfd/realtek,rtl9301-switch.yaml b/Documentation/devicetree/bindings/net/realtek,rtl9301-switch.yaml index f053303ab1e6..80eabc170669 100644 --- a/Documentation/devicetree/bindings/mfd/realtek,rtl9301-switch.yaml +++ b/Documentation/devicetree/bindings/net/realtek,rtl9301-switch.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/mfd/realtek,rtl9301-switch.yaml# +$id: http://devicetree.org/schemas/net/realtek,rtl9301-switch.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Realtek Switch with Internal CPU @@ -14,6 +14,8 @@ description: number of different peripherals are accessed through a common register block, represented here as a syscon node. +$ref: ethernet-switch.yaml#/$defs/ethernet-ports + properties: compatible: items: @@ -28,12 +30,23 @@ properties: reg: maxItems: 1 + interrupts: + maxItems: 2 + + interrupt-names: + items: + - const: switch + - const: nic + '#address-cells': const: 1 '#size-cells': const: 1 + ethernet-ports: + type: object + patternProperties: 'reboot@[0-9a-f]+$': $ref: /schemas/power/reset/syscon-reboot.yaml# @@ -41,9 +54,14 @@ patternProperties: 'i2c@[0-9a-f]+$': $ref: /schemas/i2c/realtek,rtl9301-i2c.yaml# + 'mdio-controller@[0-9a-f]+$': + $ref: realtek,rtl9301-mdio.yaml# + required: - compatible - reg + - interrupts + - interrupt-names additionalProperties: false @@ -52,6 +70,9 @@ examples: ethernet-switch@1b000000 { compatible = "realtek,rtl9301-switch", "syscon", "simple-mfd"; reg = <0x1b000000 0x10000>; + interrupt-parent = <&intc>; + interrupts = <23>, <24>; + interrupt-names = "switch", "nic"; #address-cells = <1>; #size-cells = <1>; @@ -110,5 +131,45 @@ examples: }; }; }; + + mdio-controller@ca00 { + compatible = "realtek,rtl9301-mdio"; + reg = <0xca00 0x200>; + #address-cells = <1>; + #size-cells = <0>; + + mdio-bus@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + phy1: ethernet-phy@0 { + reg = <0>; + }; + }; + mdio-bus@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + phy2: ethernet-phy@0 { + reg = <0>; + }; + }; + }; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + phy-handle = <&phy1>; + }; + port@1 { + reg = <1>; + phy-handle = <&phy2>; + }; + }; }; diff --git a/Documentation/devicetree/bindings/net/renesas,r9a09g057-gbeth.yaml b/Documentation/devicetree/bindings/net/renesas,r9a09g057-gbeth.yaml new file mode 100644 index 000000000000..c498a9999289 --- /dev/null +++ b/Documentation/devicetree/bindings/net/renesas,r9a09g057-gbeth.yaml @@ -0,0 +1,203 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/renesas,r9a09g057-gbeth.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: GBETH glue layer for Renesas RZ/V2H(P) (and similar SoCs) + +maintainers: + - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> + +select: + properties: + compatible: + contains: + enum: + - renesas,r9a09g056-gbeth + - renesas,r9a09g057-gbeth + - renesas,rzv2h-gbeth + required: + - compatible + +properties: + compatible: + items: + - enum: + - renesas,r9a09g056-gbeth # RZ/V2N + - renesas,r9a09g057-gbeth # RZ/V2H(P) + - const: renesas,rzv2h-gbeth + - const: snps,dwmac-5.20 + + reg: + maxItems: 1 + + clocks: + items: + - description: CSR clock + - description: AXI system clock + - description: PTP clock + - description: TX clock + - description: RX clock + - description: TX clock phase-shifted by 180 degrees + - description: RX clock phase-shifted by 180 degrees + + clock-names: + items: + - const: stmmaceth + - const: pclk + - const: ptp_ref + - const: tx + - const: rx + - const: tx-180 + - const: rx-180 + + interrupts: + minItems: 11 + + interrupt-names: + items: + - const: macirq + - const: eth_wake_irq + - const: eth_lpi + - const: rx-queue-0 + - const: rx-queue-1 + - const: rx-queue-2 + - const: rx-queue-3 + - const: tx-queue-0 + - const: tx-queue-1 + - const: tx-queue-2 + - const: tx-queue-3 + + resets: + items: + - description: AXI power-on system reset + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - interrupt-names + - resets + +allOf: + - $ref: snps,dwmac.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/renesas-cpg-mssr.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + ethernet@15c30000 { + compatible = "renesas,r9a09g057-gbeth", "renesas,rzv2h-gbeth", "snps,dwmac-5.20"; + reg = <0x15c30000 0x10000>; + clocks = <&cpg CPG_MOD 0xbd>, <&cpg CPG_MOD 0xbc>, + <&ptp_clock>, <&cpg CPG_MOD 0xb8>, + <&cpg CPG_MOD 0xb9>, <&cpg CPG_MOD 0xba>, + <&cpg CPG_MOD 0xbb>; + clock-names = "stmmaceth", "pclk", "ptp_ref", + "tx", "rx", "tx-180", "rx-180"; + resets = <&cpg 0xb0>; + interrupts = <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 767 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 745 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi", + "rx-queue-0", "rx-queue-1", "rx-queue-2", + "rx-queue-3", "tx-queue-0", "tx-queue-1", + "tx-queue-2", "tx-queue-3"; + phy-mode = "rgmii-id"; + snps,multicast-filter-bins = <256>; + snps,perfect-filter-entries = <128>; + rx-fifo-depth = <8192>; + tx-fifo-depth = <8192>; + snps,fixed-burst; + snps,force_thresh_dma_mode; + snps,axi-config = <&stmmac_axi_setup>; + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; + snps,txpbl = <32>; + snps,rxpbl = <32>; + phy-handle = <&phy0>; + + stmmac_axi_setup: stmmac-axi-config { + snps,lpi_en; + snps,wr_osr_lmt = <0xf>; + snps,rd_osr_lmt = <0xf>; + snps,blen = <16 8 4 0 0 0 0>; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,priority = <0x1>; + snps,map-to-dma-channel = <0>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority = <0x2>; + snps,map-to-dma-channel = <1>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority = <0x4>; + snps,map-to-dma-channel = <2>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority = <0x8>; + snps,map-to-dma-channel = <3>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <4>; + + queue0 { + snps,dcb-algorithm; + snps,priority = <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority = <0x2>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority = <0x4>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority = <0x1>; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + phy0: ethernet-phy@0 { + reg = <0>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/net/rfkill-gpio.yaml b/Documentation/devicetree/bindings/net/rfkill-gpio.yaml index 9630c8466fac..4a706a41ab38 100644 --- a/Documentation/devicetree/bindings/net/rfkill-gpio.yaml +++ b/Documentation/devicetree/bindings/net/rfkill-gpio.yaml @@ -32,6 +32,10 @@ properties: shutdown-gpios: maxItems: 1 + default-blocked: + $ref: /schemas/types.yaml#/definitions/flag + description: configure rfkill state as blocked at boot + required: - compatible - radio-type @@ -48,4 +52,5 @@ examples: label = "rfkill-pcie-wlan"; radio-type = "wlan"; shutdown-gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>; + default-blocked; }; diff --git a/Documentation/devicetree/bindings/net/rockchip-dwmac.yaml b/Documentation/devicetree/bindings/net/rockchip-dwmac.yaml index f8a576611d6c..0ac7c4b47d6b 100644 --- a/Documentation/devicetree/bindings/net/rockchip-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/rockchip-dwmac.yaml @@ -24,6 +24,7 @@ select: - rockchip,rk3366-gmac - rockchip,rk3368-gmac - rockchip,rk3399-gmac + - rockchip,rk3528-gmac - rockchip,rk3568-gmac - rockchip,rk3576-gmac - rockchip,rk3588-gmac @@ -32,9 +33,6 @@ select: required: - compatible -allOf: - - $ref: snps,dwmac.yaml# - properties: compatible: oneOf: @@ -52,14 +50,25 @@ properties: - rockchip,rv1108-gmac - items: - enum: + - rockchip,rk3528-gmac - rockchip,rk3568-gmac - rockchip,rk3576-gmac - rockchip,rk3588-gmac - rockchip,rv1126-gmac - const: snps,dwmac-4.20a + interrupts: + minItems: 1 + maxItems: 2 + + interrupt-names: + minItems: 1 + items: + - const: macirq + - const: eth_wake_irq + clocks: - minItems: 5 + minItems: 4 maxItems: 8 clock-names: @@ -114,6 +123,36 @@ required: - compatible - clocks - clock-names + - rockchip,grf + +allOf: + - $ref: snps,dwmac.yaml# + + - if: + properties: + compatible: + contains: + enum: + - rockchip,rk3576-gmac + - rockchip,rk3588-gmac + then: + required: + - rockchip,php-grf + else: + properties: + rockchip,php-grf: false + + - if: + not: + properties: + compatible: + contains: + enum: + - rockchip,rk3528-gmac + then: + properties: + clocks: + minItems: 5 unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/net/smsc,lan9115.yaml b/Documentation/devicetree/bindings/net/smsc,lan9115.yaml index f86667cbcca8..42279ae8c2b9 100644 --- a/Documentation/devicetree/bindings/net/smsc,lan9115.yaml +++ b/Documentation/devicetree/bindings/net/smsc,lan9115.yaml @@ -11,6 +11,7 @@ maintainers: allOf: - $ref: ethernet-controller.yaml# + - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml# properties: compatible: @@ -89,10 +90,7 @@ required: - reg - interrupts -# There are lots of bus-specific properties ("qcom,*", "samsung,*", "fsl,*", -# "gpmc,*", ...) to be found, that actually depend on the compatible value of -# the parent node. -additionalProperties: true +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml index 91e75eb3f329..90b79283e228 100644 --- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml +++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml @@ -32,6 +32,7 @@ select: - snps,dwmac-4.20a - snps,dwmac-5.10a - snps,dwmac-5.20 + - snps,dwmac-5.30a - snps,dwxgmac - snps,dwxgmac-2.10 @@ -74,6 +75,7 @@ properties: - qcom,sm8150-ethqos - renesas,r9a06g032-gmac - renesas,rzn1-gmac + - renesas,rzv2h-gbeth - rockchip,px30-gmac - rockchip,rk3128-gmac - rockchip,rk3228-gmac @@ -98,10 +100,13 @@ properties: - snps,dwmac-4.20a - snps,dwmac-5.10a - snps,dwmac-5.20 + - snps,dwmac-5.30a - snps,dwxgmac - snps,dwxgmac-2.10 + - sophgo,sg2044-dwmac - starfive,jh7100-dwmac - starfive,jh7110-dwmac + - tesla,fsd-ethqos - thead,th1520-gmac reg: @@ -110,23 +115,29 @@ properties: interrupts: minItems: 1 - items: - - description: Combined signal for various interrupt events - - description: The interrupt to manage the remote wake-up packet detection - - description: The interrupt that occurs when Rx exits the LPI state - - description: The interrupt that occurs when HW safety error triggered + maxItems: 11 interrupt-names: minItems: 1 + maxItems: 11 items: - - const: macirq - - enum: [eth_wake_irq, eth_lpi, sfty] - - enum: [eth_wake_irq, eth_lpi, sfty] - - enum: [eth_wake_irq, eth_lpi, sfty] + oneOf: + - description: Combined signal for various interrupt events + const: macirq + - description: The interrupt to manage the remote wake-up packet detection + const: eth_wake_irq + - description: The interrupt that occurs when Rx exits the LPI state + const: eth_lpi + - description: The interrupt that occurs when HW safety error triggered + const: sfty + - description: Per channel receive completion interrupt + pattern: '^rx-queue-[0-3]$' + - description: Per channel transmit completion interrupt + pattern: '^tx-queue-[0-3]$' clocks: minItems: 1 - maxItems: 8 + maxItems: 10 additionalItems: true items: - description: GMAC main clock @@ -138,7 +149,7 @@ properties: clock-names: minItems: 1 - maxItems: 8 + maxItems: 10 additionalItems: true contains: enum: @@ -490,6 +501,7 @@ properties: snps,en-tx-lpi-clockgating: $ref: /schemas/types.yaml#/definitions/flag + deprecated: true description: Enable gating of the MAC TX clock during TX low-power mode @@ -631,6 +643,7 @@ allOf: - snps,dwmac-4.20a - snps,dwmac-5.10a - snps,dwmac-5.20 + - snps,dwmac-5.30a - snps,dwxgmac - snps,dwxgmac-2.10 - st,spear600-gmac @@ -697,7 +710,7 @@ examples: }; }; - mdio0 { + mdio { #address-cells = <1>; #size-cells = <0>; compatible = "snps,dwmac-mdio"; diff --git a/Documentation/devicetree/bindings/net/sophgo,sg2044-dwmac.yaml b/Documentation/devicetree/bindings/net/sophgo,sg2044-dwmac.yaml new file mode 100644 index 000000000000..8afbd9ebd73f --- /dev/null +++ b/Documentation/devicetree/bindings/net/sophgo,sg2044-dwmac.yaml @@ -0,0 +1,127 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/sophgo,sg2044-dwmac.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo SG2044 DWMAC glue layer + +maintainers: + - Inochi Amaoto <inochiama@gmail.com> + +select: + properties: + compatible: + contains: + enum: + - sophgo,sg2044-dwmac + required: + - compatible + +properties: + compatible: + items: + - const: sophgo,sg2044-dwmac + - const: snps,dwmac-5.30a + + reg: + maxItems: 1 + + clocks: + items: + - description: GMAC main clock + - description: PTP clock + - description: TX clock + + clock-names: + items: + - const: stmmaceth + - const: ptp_ref + - const: tx + + dma-noncoherent: true + + interrupts: + maxItems: 1 + + interrupt-names: + maxItems: 1 + + resets: + maxItems: 1 + + reset-names: + const: stmmaceth + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - interrupt-names + - resets + - reset-names + +allOf: + - $ref: snps,dwmac.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + ethernet@30006000 { + compatible = "sophgo,sg2044-dwmac", "snps,dwmac-5.30a"; + reg = <0x30006000 0x4000>; + clocks = <&clk 151>, <&clk 152>, <&clk 154>; + clock-names = "stmmaceth", "ptp_ref", "tx"; + interrupt-parent = <&intc>; + interrupts = <296 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + resets = <&rst 30>; + reset-names = "stmmaceth"; + snps,multicast-filter-bins = <0>; + snps,perfect-filter-entries = <1>; + snps,aal; + snps,tso; + snps,txpbl = <32>; + snps,rxpbl = <32>; + snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; + snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; + snps,axi-config = <&gmac0_stmmac_axi_setup>; + + gmac0_mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <8>; + snps,rx-sched-wsp; + queue0 {}; + queue1 {}; + queue2 {}; + queue3 {}; + queue4 {}; + queue5 {}; + queue6 {}; + queue7 {}; + }; + + gmac0_mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <8>; + queue0 {}; + queue1 {}; + queue2 {}; + queue3 {}; + queue4 {}; + queue5 {}; + queue6 {}; + queue7 {}; + }; + + gmac0_stmmac_axi_setup: stmmac-axi-config { + snps,blen = <16 8 4 0 0 0 0>; + snps,wr_osr_lmt = <1>; + snps,rd_osr_lmt = <2>; + }; + }; diff --git a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml index 85cea9966a27..987254900d0d 100644 --- a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml @@ -54,6 +54,16 @@ properties: items: - const: stmmaceth + interrupts: + minItems: 1 + maxItems: 2 + + interrupt-names: + minItems: 1 + items: + - const: macirq + - const: eth_wake_irq + clocks: minItems: 3 items: diff --git a/Documentation/devicetree/bindings/net/tesla,fsd-ethqos.yaml b/Documentation/devicetree/bindings/net/tesla,fsd-ethqos.yaml new file mode 100644 index 000000000000..dd7481bb16e5 --- /dev/null +++ b/Documentation/devicetree/bindings/net/tesla,fsd-ethqos.yaml @@ -0,0 +1,118 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/tesla,fsd-ethqos.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FSD Ethernet Quality of Service + +maintainers: + - Swathi K S <swathi.ks@samsung.com> + +description: + Tesla ethernet devices based on dwmmac support Gigabit ethernet. + +allOf: + - $ref: snps,dwmac.yaml# + +properties: + compatible: + const: tesla,fsd-ethqos + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-names: + items: + - const: macirq + + clocks: + minItems: 5 + items: + - description: PTP clock + - description: Master bus clock + - description: Slave bus clock + - description: MAC TX clock + - description: MAC RX clock + - description: Master2 bus clock + - description: Slave2 bus clock + - description: RX MUX clock + - description: PHY RX clock + - description: PERIC RGMII clock + + clock-names: + minItems: 5 + items: + - const: ptp_ref + - const: master_bus + - const: slave_bus + - const: tx + - const: rx + - const: master2_bus + - const: slave2_bus + - const: eqos_rxclk_mux + - const: eqos_phyrxclk + - const: dout_peric_rgmii_clk + + iommus: + maxItems: 1 + + phy-mode: + enum: + - rgmii + - rgmii-id + - rgmii-rxid + - rgmii-txid + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - iommus + - phy-mode + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/fsd-clk.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + soc { + #address-cells = <2>; + #size-cells = <2>; + ethernet1: ethernet@14300000 { + compatible = "tesla,fsd-ethqos"; + reg = <0x0 0x14300000 0x0 0x10000>; + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + clocks = <&clock_peric PERIC_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I>, + <&clock_peric PERIC_EQOS_TOP_IPCLKPORT_ACLK_I>, + <&clock_peric PERIC_EQOS_TOP_IPCLKPORT_HCLK_I>, + <&clock_peric PERIC_EQOS_TOP_IPCLKPORT_RGMII_CLK_I>, + <&clock_peric PERIC_EQOS_TOP_IPCLKPORT_CLK_RX_I>, + <&clock_peric PERIC_BUS_D_PERIC_IPCLKPORT_EQOSCLK>, + <&clock_peric PERIC_BUS_P_PERIC_IPCLKPORT_EQOSCLK>, + <&clock_peric PERIC_EQOS_PHYRXCLK_MUX>, + <&clock_peric PERIC_EQOS_PHYRXCLK>, + <&clock_peric PERIC_DOUT_RGMII_CLK>; + clock-names = "ptp_ref", "master_bus", "slave_bus","tx", + "rx", "master2_bus", "slave2_bus", "eqos_rxclk_mux", + "eqos_phyrxclk","dout_peric_rgmii_clk"; + assigned-clocks = <&clock_peric PERIC_EQOS_PHYRXCLK_MUX>, + <&clock_peric PERIC_EQOS_PHYRXCLK>; + assigned-clock-parents = <&clock_peric PERIC_EQOS_PHYRXCLK>; + pinctrl-names = "default"; + pinctrl-0 = <ð1_tx_clk>, <ð1_tx_data>, <ð1_tx_ctrl>, + <ð1_phy_intr>, <ð1_rx_clk>, <ð1_rx_data>, + <ð1_rx_ctrl>, <ð1_mdio>; + iommus = <&smmu_peric 0x0 0x1>; + phy-mode = "rgmii-id"; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/net/ti,dp83822.yaml b/Documentation/devicetree/bindings/net/ti,dp83822.yaml index 50c24248df26..28a0bddb9af9 100644 --- a/Documentation/devicetree/bindings/net/ti,dp83822.yaml +++ b/Documentation/devicetree/bindings/net/ti,dp83822.yaml @@ -122,6 +122,9 @@ properties: - free-running - recovered + mac-termination-ohms: + enum: [43, 44, 46, 48, 50, 53, 55, 58, 61, 65, 69, 73, 78, 84, 91, 99] + required: - reg @@ -137,6 +140,7 @@ examples: rx-internal-delay-ps = <1>; tx-internal-delay-ps = <1>; ti,gpio2-clk-out = "xi"; + mac-termination-ohms = <43>; }; }; diff --git a/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml b/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml index b11894fbaec4..7b3d948f187d 100644 --- a/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml +++ b/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml @@ -143,6 +143,8 @@ properties: label: description: label associated with this port + fixed-link: true + ti,mac-only: $ref: /schemas/types.yaml#/definitions/flag description: diff --git a/Documentation/devicetree/bindings/net/toshiba,visconti-dwmac.yaml b/Documentation/devicetree/bindings/net/toshiba,visconti-dwmac.yaml index 052f636158b3..f0f32e18fc85 100644 --- a/Documentation/devicetree/bindings/net/toshiba,visconti-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/toshiba,visconti-dwmac.yaml @@ -42,6 +42,12 @@ properties: - const: stmmaceth - const: phy_ref_clk + interrupts: + maxItems: 1 + + interrupt-names: + const: macirq + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/net/vertexcom-mse102x.yaml b/Documentation/devicetree/bindings/net/vertexcom-mse102x.yaml index 4158673f723c..8359de7ad272 100644 --- a/Documentation/devicetree/bindings/net/vertexcom-mse102x.yaml +++ b/Documentation/devicetree/bindings/net/vertexcom-mse102x.yaml @@ -63,7 +63,7 @@ examples: compatible = "vertexcom,mse1021"; reg = <0>; interrupt-parent = <&gpio>; - interrupts = <23 IRQ_TYPE_EDGE_RISING>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; spi-cpha; spi-cpol; spi-max-frequency = <7142857>; diff --git a/Documentation/devicetree/bindings/net/via,vt8500-rhine.yaml b/Documentation/devicetree/bindings/net/via,vt8500-rhine.yaml new file mode 100644 index 000000000000..e663d5a2f014 --- /dev/null +++ b/Documentation/devicetree/bindings/net/via,vt8500-rhine.yaml @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/via,vt8500-rhine.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: VIA Rhine 10/100 Network Controller + +description: + VIA's Ethernet controller integrated into VIA VT8500, + WonderMedia WM8950 and related SoCs + +maintainers: + - Alexey Charkov <alchark@gmail.com> + +allOf: + - $ref: ethernet-controller.yaml# + +properties: + compatible: + const: via,vt8500-rhine + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - reg + - interrupts + +unevaluatedProperties: false + +examples: + - | + ethernet@d8004000 { + compatible = "via,vt8500-rhine"; + reg = <0xd8004000 0x100>; + interrupts = <10>; + }; diff --git a/Documentation/devicetree/bindings/net/via-rhine.txt b/Documentation/devicetree/bindings/net/via-rhine.txt deleted file mode 100644 index 334eca2bf937..000000000000 --- a/Documentation/devicetree/bindings/net/via-rhine.txt +++ /dev/null @@ -1,17 +0,0 @@ -* VIA Rhine 10/100 Network Controller - -Required properties: -- compatible : Should be "via,vt8500-rhine" for integrated - Rhine controllers found in VIA VT8500, WonderMedia WM8950 - and similar. These are listed as 1106:3106 rev. 0x84 on the - virtual PCI bus under vendor-provided kernels -- reg : Address and length of the io space -- interrupts : Should contain the controller interrupt line - -Examples: - -ethernet@d8004000 { - compatible = "via,vt8500-rhine"; - reg = <0xd8004000 0x100>; - interrupts = <10>; -}; diff --git a/Documentation/devicetree/bindings/net/wireless/brcm,bcm4329-fmac.yaml b/Documentation/devicetree/bindings/net/wireless/brcm,bcm4329-fmac.yaml index a3607d55ef36..7c8100e59a6c 100644 --- a/Documentation/devicetree/bindings/net/wireless/brcm,bcm4329-fmac.yaml +++ b/Documentation/devicetree/bindings/net/wireless/brcm,bcm4329-fmac.yaml @@ -16,7 +16,7 @@ description: binding. allOf: - - $ref: ieee80211.yaml# + - $ref: /schemas/net/wireless/wireless-controller.yaml# properties: compatible: diff --git a/Documentation/devicetree/bindings/net/wireless/qcom,ath10k.yaml b/Documentation/devicetree/bindings/net/wireless/qcom,ath10k.yaml index aace072e2d52..f2440d39b7eb 100644 --- a/Documentation/devicetree/bindings/net/wireless/qcom,ath10k.yaml +++ b/Documentation/devicetree/bindings/net/wireless/qcom,ath10k.yaml @@ -92,20 +92,41 @@ properties: ieee80211-freq-limit: true + qcom,calibration-data: + $ref: /schemas/types.yaml#/definitions/uint8-array + description: + Calibration data + board-specific data as a byte array. The length + can vary between hardware versions. + qcom,ath10k-calibration-data: $ref: /schemas/types.yaml#/definitions/uint8-array + deprecated: true description: Calibration data + board-specific data as a byte array. The length can vary between hardware versions. + qcom,calibration-variant: + $ref: /schemas/types.yaml#/definitions/string + description: + Unique variant identifier of the calibration data in board-2.bin + for designs with colliding bus and device specific ids + qcom,ath10k-calibration-variant: $ref: /schemas/types.yaml#/definitions/string + deprecated: true description: Unique variant identifier of the calibration data in board-2.bin for designs with colliding bus and device specific ids + qcom,pre-calibration-data: + $ref: /schemas/types.yaml#/definitions/uint8-array + description: + Pre-calibration data as a byte array. The length can vary between + hardware versions. + qcom,ath10k-pre-calibration-data: $ref: /schemas/types.yaml#/definitions/uint8-array + deprecated: true description: Pre-calibration data as a byte array. The length can vary between hardware versions. diff --git a/Documentation/devicetree/bindings/net/wireless/qcom,ath11k-pci.yaml b/Documentation/devicetree/bindings/net/wireless/qcom,ath11k-pci.yaml index a4425cf196ab..653b319fee88 100644 --- a/Documentation/devicetree/bindings/net/wireless/qcom,ath11k-pci.yaml +++ b/Documentation/devicetree/bindings/net/wireless/qcom,ath11k-pci.yaml @@ -22,8 +22,15 @@ properties: reg: maxItems: 1 + qcom,calibration-variant: + $ref: /schemas/types.yaml#/definitions/string + description: | + string to uniquely identify variant of the calibration data for designs + with colliding bus and device ids + qcom,ath11k-calibration-variant: $ref: /schemas/types.yaml#/definitions/string + deprecated: true description: | string to uniquely identify variant of the calibration data for designs with colliding bus and device ids @@ -127,7 +134,7 @@ examples: vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>; - qcom,ath11k-calibration-variant = "LE_X13S"; + qcom,calibration-variant = "LE_X13S"; }; }; }; diff --git a/Documentation/devicetree/bindings/net/wireless/qcom,ath11k.yaml b/Documentation/devicetree/bindings/net/wireless/qcom,ath11k.yaml index a69ffb7b3cb8..c089677702cf 100644 --- a/Documentation/devicetree/bindings/net/wireless/qcom,ath11k.yaml +++ b/Documentation/devicetree/bindings/net/wireless/qcom,ath11k.yaml @@ -41,8 +41,15 @@ properties: * reg * reg-names + qcom,calibration-variant: + $ref: /schemas/types.yaml#/definitions/string + description: + string to uniquely identify variant of the calibration data in the + board-2.bin for designs with colliding bus and device specific ids + qcom,ath11k-calibration-variant: $ref: /schemas/types.yaml#/definitions/string + deprecated: true description: string to uniquely identify variant of the calibration data in the board-2.bin for designs with colliding bus and device specific ids diff --git a/Documentation/devicetree/bindings/net/wireless/qcom,ath12k-wsi.yaml b/Documentation/devicetree/bindings/net/wireless/qcom,ath12k-wsi.yaml index 318f305405e3..589960144fe1 100644 --- a/Documentation/devicetree/bindings/net/wireless/qcom,ath12k-wsi.yaml +++ b/Documentation/devicetree/bindings/net/wireless/qcom,ath12k-wsi.yaml @@ -52,8 +52,15 @@ properties: reg: maxItems: 1 + qcom,calibration-variant: + $ref: /schemas/types.yaml#/definitions/string + description: + String to uniquely identify variant of the calibration data for designs + with colliding bus and device ids + qcom,ath12k-calibration-variant: $ref: /schemas/types.yaml#/definitions/string + deprecated: true description: String to uniquely identify variant of the calibration data for designs with colliding bus and device ids @@ -103,7 +110,7 @@ examples: compatible = "pci17cb,1109"; reg = <0x0 0x0 0x0 0x0 0x0>; - qcom,ath12k-calibration-variant = "RDP433_1"; + qcom,calibration-variant = "RDP433_1"; ports { #address-cells = <1>; @@ -139,7 +146,7 @@ examples: compatible = "pci17cb,1109"; reg = <0x0 0x0 0x0 0x0 0x0>; - qcom,ath12k-calibration-variant = "RDP433_2"; + qcom,calibration-variant = "RDP433_2"; qcom,wsi-controller; ports { @@ -176,7 +183,7 @@ examples: compatible = "pci17cb,1109"; reg = <0x0 0x0 0x0 0x0 0x0>; - qcom,ath12k-calibration-variant = "RDP433_3"; + qcom,calibration-variant = "RDP433_3"; ports { #address-cells = <1>; diff --git a/Documentation/devicetree/bindings/net/wireless/qcom,ath12k.yaml b/Documentation/devicetree/bindings/net/wireless/qcom,ath12k.yaml index 9e557cb838c7..dc68dd59988f 100644 --- a/Documentation/devicetree/bindings/net/wireless/qcom,ath12k.yaml +++ b/Documentation/devicetree/bindings/net/wireless/qcom,ath12k.yaml @@ -21,6 +21,12 @@ properties: reg: maxItems: 1 + firmware-name: + maxItems: 1 + description: + If present, a board or platform specific string used to lookup + usecase-specific firmware files for the device. + vddaon-supply: description: VDD_AON supply regulator handle diff --git a/Documentation/devicetree/bindings/net/wireless/qcom,ipq5332-wifi.yaml b/Documentation/devicetree/bindings/net/wireless/qcom,ipq5332-wifi.yaml new file mode 100644 index 000000000000..363a0ecb6ad9 --- /dev/null +++ b/Documentation/devicetree/bindings/net/wireless/qcom,ipq5332-wifi.yaml @@ -0,0 +1,315 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/wireless/qcom,ipq5332-wifi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies ath12k wireless devices (AHB) + +maintainers: + - Jeff Johnson <jjohnson@kernel.org> + +description: + Qualcomm Technologies IEEE 802.11be AHB devices. + +properties: + compatible: + enum: + - qcom,ipq5332-wifi + + reg: + maxItems: 1 + + clocks: + items: + - description: XO clock used for copy engine + + clock-names: + items: + - const: xo + + interrupts: + items: + - description: Fatal interrupt + - description: Ready interrupt + - description: Spawn acknowledge interrupt + - description: Stop acknowledge interrupt + - description: misc-pulse1 interrupt events + - description: misc-latch interrupt events + - description: sw exception interrupt events + - description: interrupt event for ring CE0 + - description: interrupt event for ring CE1 + - description: interrupt event for ring CE2 + - description: interrupt event for ring CE3 + - description: interrupt event for ring CE4 + - description: interrupt event for ring CE5 + - description: interrupt event for ring CE6 + - description: interrupt event for ring CE7 + - description: interrupt event for ring CE8 + - description: interrupt event for ring CE9 + - description: interrupt event for ring CE10 + - description: interrupt event for ring CE11 + - description: interrupt event for ring host2wbm-desc-feed + - description: interrupt event for ring host2reo-re-injection + - description: interrupt event for ring host2reo-command + - description: interrupt event for ring host2rxdma-monitor-ring1 + - description: interrupt event for ring reo2ost-exception + - description: interrupt event for ring wbm2host-rx-release + - description: interrupt event for ring reo2host-status + - description: interrupt event for ring reo2host-destination-ring4 + - description: interrupt event for ring reo2host-destination-ring3 + - description: interrupt event for ring reo2host-destination-ring2 + - description: interrupt event for ring reo2host-destination-ring1 + - description: interrupt event for ring rxdma2host-monitor-destination-mac3 + - description: interrupt event for ring rxdma2host-monitor-destination-mac2 + - description: interrupt event for ring rxdma2host-monitor-destination-mac1 + - description: interrupt event for ring host2rxdma-host-buf-ring-mac3 + - description: interrupt event for ring host2rxdma-host-buf-ring-mac2 + - description: interrupt event for ring host2rxdma-host-buf-ring-mac1 + - description: interrupt event for ring host2tcl-input-ring4 + - description: interrupt event for ring host2tcl-input-ring3 + - description: interrupt event for ring host2tcl-input-ring2 + - description: interrupt event for ring host2tcl-input-ring1 + - description: interrupt event for ring wbm2host-tx-completions-ring4 + - description: interrupt event for ring wbm2host-tx-completions-ring3 + - description: interrupt event for ring wbm2host-tx-completions-ring2 + - description: interrupt event for ring wbm2host-tx-completions-ring1 + - description: interrupt event for ring host2tx-monitor-ring1 + - description: interrupt event for ring txmon2host-monitor-destination-mac3 + - description: interrupt event for ring txmon2host-monitor-destination-mac2 + - description: interrupt event for ring txmon2host-monitor-destination-mac1 + - description: interrupt event for umac-reset + + interrupt-names: + items: + - const: fatal + - const: ready + - const: spawn + - const: stop-ack + - const: misc-pulse1 + - const: misc-latch + - const: sw-exception + - const: ce0 + - const: ce1 + - const: ce2 + - const: ce3 + - const: ce4 + - const: ce5 + - const: ce6 + - const: ce7 + - const: ce8 + - const: ce9 + - const: ce10 + - const: ce11 + - const: host2wbm-desc-feed + - const: host2reo-re-injection + - const: host2reo-command + - const: host2rxdma-monitor-ring1 + - const: reo2ost-exception + - const: wbm2host-rx-release + - const: reo2host-status + - const: reo2host-destination-ring4 + - const: reo2host-destination-ring3 + - const: reo2host-destination-ring2 + - const: reo2host-destination-ring1 + - const: rxdma2host-monitor-destination-mac3 + - const: rxdma2host-monitor-destination-mac2 + - const: rxdma2host-monitor-destination-mac1 + - const: host2rxdma-host-buf-ring-mac3 + - const: host2rxdma-host-buf-ring-mac2 + - const: host2rxdma-host-buf-ring-mac1 + - const: host2tcl-input-ring4 + - const: host2tcl-input-ring3 + - const: host2tcl-input-ring2 + - const: host2tcl-input-ring1 + - const: wbm2host-tx-completions-ring4 + - const: wbm2host-tx-completions-ring3 + - const: wbm2host-tx-completions-ring2 + - const: wbm2host-tx-completions-ring1 + - const: host2tx-monitor-ring1 + - const: txmon2host-monitor-destination-mac3 + - const: txmon2host-monitor-destination-mac2 + - const: txmon2host-monitor-destination-mac1 + - const: umac-reset + + memory-region: + description: + Memory regions used by the ath12k firmware. + items: + - description: Q6 memory region + - description: m3 dump memory region + - description: Q6 caldata memory region + - description: Multi Link Operation (MLO) Global memory region + + memory-region-names: + items: + - const: q6-region + - const: m3-dump + - const: q6-caldb + - const: mlo-global-mem + + qcom,calibration-variant: + $ref: /schemas/types.yaml#/definitions/string + description: + String to uniquely identify variant of the calibration data for designs + with colliding bus and device ids + + qcom,rproc: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the Qualcomm Hexagon DSP(q6 remote processor), which is utilized + for offloading WiFi processing tasks, this q6 remote processor operates in + conjunction with WiFi. + + qcom,smem-states: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: States used by the AP to signal the remote processor + items: + - description: Shutdown WCSS pd + - description: Stop WCSS pd + - description: Spawn WCSS pd + + qcom,smem-state-names: + description: + Names of the states used by the AP to signal the remote processor + items: + - const: shutdown + - const: stop + - const: spawn + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - interrupt-names + - memory-region + - memory-region-names + - qcom,rproc + - qcom,smem-states + - qcom,smem-state-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/qcom,ipq5332-gcc.h> + + wifi0: wifi@c000000 { + compatible = "qcom,ipq5332-wifi"; + reg = <0x0c000000 0x1000000>; + clocks = <&gcc GCC_XO_CLK>; + clock-names = "xo"; + interrupts-extended = <&wcss_smp2p_in 8 IRQ_TYPE_NONE>, + <&wcss_smp2p_in 9 IRQ_TYPE_NONE>, + <&wcss_smp2p_in 12 IRQ_TYPE_NONE>, + <&wcss_smp2p_in 11 IRQ_TYPE_NONE>, + <&intc GIC_SPI 559 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 560 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 561 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 422 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 423 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 424 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 425 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 426 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 427 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 428 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 429 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 430 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 431 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 432 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 433 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 491 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 495 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 493 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 544 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 457 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 466 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 497 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 454 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 453 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 452 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 451 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 488 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 488 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 484 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 554 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 554 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 549 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 507 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 500 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 499 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 498 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 450 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 449 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 447 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 543 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 486 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 486 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 482 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 419 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "fatal", + "ready", + "spawn", + "stop-ack", + "misc-pulse1", + "misc-latch", + "sw-exception", + "ce0", + "ce1", + "ce2", + "ce3", + "ce4", + "ce5", + "ce6", + "ce7", + "ce8", + "ce9", + "ce10", + "ce11", + "host2wbm-desc-feed", + "host2reo-re-injection", + "host2reo-command", + "host2rxdma-monitor-ring1", + "reo2ost-exception", + "wbm2host-rx-release", + "reo2host-status", + "reo2host-destination-ring4", + "reo2host-destination-ring3", + "reo2host-destination-ring2", + "reo2host-destination-ring1", + "rxdma2host-monitor-destination-mac3", + "rxdma2host-monitor-destination-mac2", + "rxdma2host-monitor-destination-mac1", + "host2rxdma-host-buf-ring-mac3", + "host2rxdma-host-buf-ring-mac2", + "host2rxdma-host-buf-ring-mac1", + "host2tcl-input-ring4", + "host2tcl-input-ring3", + "host2tcl-input-ring2", + "host2tcl-input-ring1", + "wbm2host-tx-completions-ring4", + "wbm2host-tx-completions-ring3", + "wbm2host-tx-completions-ring2", + "wbm2host-tx-completions-ring1", + "host2tx-monitor-ring1", + "txmon2host-monitor-destination-mac3", + "txmon2host-monitor-destination-mac2", + "txmon2host-monitor-destination-mac1", + "umac-reset"; + + memory-region = <&q6_region>, <&m3_dump>, <&q6_caldb>, <&mlo_mem>; + memory-region-names = "q6-region", "m3-dump", "q6-caldb", "mlo-global-mem"; + qcom,calibration-variant = "RDP441_1"; + qcom,rproc = <&q6v5_wcss>; + qcom,smem-states = <&wcss_smp2p_out 8>, + <&wcss_smp2p_out 9>, + <&wcss_smp2p_out 10>; + qcom,smem-state-names = "shutdown", + "stop", + "spawn"; + }; diff --git a/Documentation/devicetree/bindings/net/wireless/realtek,rtl8188e.yaml b/Documentation/devicetree/bindings/net/wireless/realtek,rtl8188e.yaml new file mode 100644 index 000000000000..2769731e0708 --- /dev/null +++ b/Documentation/devicetree/bindings/net/wireless/realtek,rtl8188e.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/wireless/realtek,rtl8188e.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Realtek RTL8188E USB WiFi + +maintainers: + - J. Neuschäfer <j.ne@posteo.net> + +description: + Realtek RTL8188E is a family of USB-connected 2.4 GHz WiFi modules. + +allOf: + - $ref: /schemas/usb/usb-device.yaml# + +properties: + compatible: + const: usbbda,179 # RTL8188ETV + + reg: true + + vdd-supply: + description: + Regulator for the 3V3 supply. + +required: + - compatible + - reg + - vdd-supply + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + usb { + #address-cells = <1>; + #size-cells = <0>; + + wifi: wifi@1 { + compatible = "usbbda,179"; + reg = <1>; + vdd-supply = <&vcc3v3>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/net/wireless/silabs,wfx.yaml b/Documentation/devicetree/bindings/net/wireless/silabs,wfx.yaml index 84e5659e50ef..6c0888ae4c4e 100644 --- a/Documentation/devicetree/bindings/net/wireless/silabs,wfx.yaml +++ b/Documentation/devicetree/bindings/net/wireless/silabs,wfx.yaml @@ -71,15 +71,12 @@ properties: "Platform Data Set" in Silabs jargon). Default depends of "compatible" string. For "silabs,wf200", the default is 'wf200.pds'. - local-mac-address: true - - mac-address: true - required: - compatible - reg allOf: + - $ref: /schemas/net/wireless/wireless-controller.yaml# - $ref: /schemas/spi/spi-peripheral-props.yaml# unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/net/wireless/wireless-controller.yaml b/Documentation/devicetree/bindings/net/wireless/wireless-controller.yaml new file mode 100644 index 000000000000..7379f6c1aa05 --- /dev/null +++ b/Documentation/devicetree/bindings/net/wireless/wireless-controller.yaml @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/wireless/wireless-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Wireless Controller Common Properties + +maintainers: + - Lorenzo Bianconi <lorenzo@kernel.org> + +properties: + $nodename: + pattern: "^wifi(@.*)?$" + +allOf: + - $ref: ieee80211.yaml# + - $ref: /schemas/net/network-class.yaml# + +additionalProperties: true + +... + diff --git a/Documentation/devicetree/bindings/numa.txt b/Documentation/devicetree/bindings/numa.txt deleted file mode 100644 index 42f282c2f3cc..000000000000 --- a/Documentation/devicetree/bindings/numa.txt +++ /dev/null @@ -1,319 +0,0 @@ -============================================================================== -NUMA binding description. -============================================================================== - -============================================================================== -1 - Introduction -============================================================================== - -Systems employing a Non Uniform Memory Access (NUMA) architecture contain -collections of hardware resources including processors, memory, and I/O buses, -that comprise what is commonly known as a NUMA node. -Processor accesses to memory within the local NUMA node is generally faster -than processor accesses to memory outside of the local NUMA node. -DT defines interfaces that allow the platform to convey NUMA node -topology information to OS. - -============================================================================== -2 - numa-node-id -============================================================================== - -For the purpose of identification, each NUMA node is associated with a unique -token known as a node id. For the purpose of this binding -a node id is a 32-bit integer. - -A device node is associated with a NUMA node by the presence of a -numa-node-id property which contains the node id of the device. - -Example: - /* numa node 0 */ - numa-node-id = <0>; - - /* numa node 1 */ - numa-node-id = <1>; - -============================================================================== -3 - distance-map -============================================================================== - -The optional device tree node distance-map describes the relative -distance (memory latency) between all numa nodes. - -- compatible : Should at least contain "numa-distance-map-v1". - -- distance-matrix - This property defines a matrix to describe the relative distances - between all numa nodes. - It is represented as a list of node pairs and their relative distance. - - Note: - 1. Each entry represents distance from first node to second node. - The distances are equal in either direction. - 2. The distance from a node to self (local distance) is represented - with value 10 and all internode distance should be represented with - a value greater than 10. - 3. distance-matrix should have entries in lexicographical ascending - order of nodes. - 4. There must be only one device node distance-map which must - reside in the root node. - 5. If the distance-map node is not present, a default - distance-matrix is used. - -Example: - 4 nodes connected in mesh/ring topology as below, - - 0_______20______1 - | | - | | - 20 20 - | | - | | - |_______________| - 3 20 2 - - if relative distance for each hop is 20, - then internode distance would be, - 0 -> 1 = 20 - 1 -> 2 = 20 - 2 -> 3 = 20 - 3 -> 0 = 20 - 0 -> 2 = 40 - 1 -> 3 = 40 - - and dt presentation for this distance matrix is, - - distance-map { - compatible = "numa-distance-map-v1"; - distance-matrix = <0 0 10>, - <0 1 20>, - <0 2 40>, - <0 3 20>, - <1 0 20>, - <1 1 10>, - <1 2 20>, - <1 3 40>, - <2 0 40>, - <2 1 20>, - <2 2 10>, - <2 3 20>, - <3 0 20>, - <3 1 40>, - <3 2 20>, - <3 3 10>; - }; - -============================================================================== -4 - Empty memory nodes -============================================================================== - -Empty memory nodes, which no memory resides in, are allowed. There are no -device nodes for these empty memory nodes. However, the NUMA node IDs and -distance maps are still valid and memory may be added into them through -hotplug afterwards. - -Example: - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - numa-node-id = <0>; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x0 0x80000000 0x0 0x80000000>; - numa-node-id = <1>; - }; - - /* Empty memory node 2 and 3 */ - distance-map { - compatible = "numa-distance-map-v1"; - distance-matrix = <0 0 10>, - <0 1 20>, - <0 2 40>, - <0 3 20>, - <1 0 20>, - <1 1 10>, - <1 2 20>, - <1 3 40>, - <2 0 40>, - <2 1 20>, - <2 2 10>, - <2 3 20>, - <3 0 20>, - <3 1 40>, - <3 2 20>, - <3 3 10>; - }; - -============================================================================== -5 - Example dts -============================================================================== - -Dual socket system consists of 2 boards connected through ccn bus and -each board having one socket/soc of 8 cpus, memory and pci bus. - - memory@c00000 { - device_type = "memory"; - reg = <0x0 0xc00000 0x0 0x80000000>; - /* node 0 */ - numa-node-id = <0>; - }; - - memory@10000000000 { - device_type = "memory"; - reg = <0x100 0x0 0x0 0x80000000>; - /* node 1 */ - numa-node-id = <1>; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x0>; - enable-method = "psci"; - /* node 0 */ - numa-node-id = <0>; - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x1>; - enable-method = "psci"; - numa-node-id = <0>; - }; - cpu@2 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x2>; - enable-method = "psci"; - numa-node-id = <0>; - }; - cpu@3 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x3>; - enable-method = "psci"; - numa-node-id = <0>; - }; - cpu@4 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x4>; - enable-method = "psci"; - numa-node-id = <0>; - }; - cpu@5 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x5>; - enable-method = "psci"; - numa-node-id = <0>; - }; - cpu@6 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x6>; - enable-method = "psci"; - numa-node-id = <0>; - }; - cpu@7 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x7>; - enable-method = "psci"; - numa-node-id = <0>; - }; - cpu@8 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x8>; - enable-method = "psci"; - /* node 1 */ - numa-node-id = <1>; - }; - cpu@9 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x9>; - enable-method = "psci"; - numa-node-id = <1>; - }; - cpu@a { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0xa>; - enable-method = "psci"; - numa-node-id = <1>; - }; - cpu@b { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0xb>; - enable-method = "psci"; - numa-node-id = <1>; - }; - cpu@c { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0xc>; - enable-method = "psci"; - numa-node-id = <1>; - }; - cpu@d { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0xd>; - enable-method = "psci"; - numa-node-id = <1>; - }; - cpu@e { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0xe>; - enable-method = "psci"; - numa-node-id = <1>; - }; - cpu@f { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0xf>; - enable-method = "psci"; - numa-node-id = <1>; - }; - }; - - pcie0: pcie0@848000000000 { - compatible = "arm,armv8"; - device_type = "pci"; - bus-range = <0 255>; - #size-cells = <2>; - #address-cells = <3>; - reg = <0x8480 0x00000000 0 0x10000000>; /* Configuration space */ - ranges = <0x03000000 0x8010 0x00000000 0x8010 0x00000000 0x70 0x00000000>; - /* node 0 */ - numa-node-id = <0>; - }; - - pcie1: pcie1@948000000000 { - compatible = "arm,armv8"; - device_type = "pci"; - bus-range = <0 255>; - #size-cells = <2>; - #address-cells = <3>; - reg = <0x9480 0x00000000 0 0x10000000>; /* Configuration space */ - ranges = <0x03000000 0x9010 0x00000000 0x9010 0x00000000 0x70 0x00000000>; - /* node 1 */ - numa-node-id = <1>; - }; - - distance-map { - compatible = "numa-distance-map-v1"; - distance-matrix = <0 0 10>, - <0 1 20>, - <1 1 10>; - }; diff --git a/Documentation/devicetree/bindings/nvmem/apple,spmi-nvmem.yaml b/Documentation/devicetree/bindings/nvmem/apple,spmi-nvmem.yaml new file mode 100644 index 000000000000..80b5a6cdcec9 --- /dev/null +++ b/Documentation/devicetree/bindings/nvmem/apple,spmi-nvmem.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/nvmem/apple,spmi-nvmem.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Apple SPMI NVMEM + +description: Exports a series of SPMI registers as NVMEM cells + +maintainers: + - Sasha Finkelstein <fnkl.kernel@gmail.com> + +allOf: + - $ref: nvmem.yaml# + +properties: + compatible: + items: + - enum: + - apple,maverick-pmic + - apple,sera-pmic + - apple,stowe-pmic + - const: apple,spmi-nvmem + + reg: + maxItems: 1 + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/spmi/spmi.h> + + pmic@f { + compatible = "apple,maverick-pmic", "apple,spmi-nvmem"; + reg = <0xf SPMI_USID>; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + boot_stage: boot-stage@6001 { + reg = <0x6001 0x1>; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/nvmem/layouts/fixed-cell.yaml b/Documentation/devicetree/bindings/nvmem/layouts/fixed-cell.yaml index 8b3826243ddd..38e3ad50ff4f 100644 --- a/Documentation/devicetree/bindings/nvmem/layouts/fixed-cell.yaml +++ b/Documentation/devicetree/bindings/nvmem/layouts/fixed-cell.yaml @@ -27,7 +27,7 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32-array items: - minimum: 0 - maximum: 7 + maximum: 31 description: Offset in bit within the address range specified by reg. - minimum: 1 diff --git a/Documentation/devicetree/bindings/nvmem/maxim,max77759-nvmem.yaml b/Documentation/devicetree/bindings/nvmem/maxim,max77759-nvmem.yaml new file mode 100644 index 000000000000..1e3bd4433007 --- /dev/null +++ b/Documentation/devicetree/bindings/nvmem/maxim,max77759-nvmem.yaml @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/nvmem/maxim,max77759-nvmem.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Maxim Integrated MAX77759 Non Volatile Memory + +maintainers: + - André Draszik <andre.draszik@linaro.org> + +description: | + This module is part of the MAX77759 PMIC. For additional information, see + Documentation/devicetree/bindings/mfd/maxim,max77759.yaml. + + The MAX77759 is a PMIC integrating, amongst others, Non Volatile Memory + (NVMEM) with 30 bytes of storage which can be used by software to store + information or communicate with a boot loader. + +properties: + compatible: + const: maxim,max77759-nvmem + + wp-gpios: false + +required: + - compatible + +allOf: + - $ref: nvmem.yaml# + +unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml index 39c209249c9c..3f6dc6a3a9f1 100644 --- a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml +++ b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml @@ -19,6 +19,7 @@ properties: - enum: - qcom,apq8064-qfprom - qcom,apq8084-qfprom + - qcom,ipq5018-qfprom - qcom,ipq5332-qfprom - qcom,ipq5424-qfprom - qcom,ipq6018-qfprom @@ -28,6 +29,8 @@ properties: - qcom,msm8226-qfprom - qcom,msm8916-qfprom - qcom,msm8917-qfprom + - qcom,msm8937-qfprom + - qcom,msm8960-qfprom - qcom,msm8974-qfprom - qcom,msm8976-qfprom - qcom,msm8996-qfprom @@ -51,6 +54,7 @@ properties: - qcom,sm8450-qfprom - qcom,sm8550-qfprom - qcom,sm8650-qfprom + - qcom,x1e80100-qfprom - const: qcom,qfprom reg: diff --git a/Documentation/devicetree/bindings/nvmem/rockchip,otp.yaml b/Documentation/devicetree/bindings/nvmem/rockchip,otp.yaml index a44d44b32809..dc89020b0950 100644 --- a/Documentation/devicetree/bindings/nvmem/rockchip,otp.yaml +++ b/Documentation/devicetree/bindings/nvmem/rockchip,otp.yaml @@ -14,6 +14,7 @@ properties: enum: - rockchip,px30-otp - rockchip,rk3308-otp + - rockchip,rk3576-otp - rockchip,rk3588-otp reg: @@ -62,6 +63,8 @@ allOf: properties: clocks: maxItems: 3 + clock-names: + maxItems: 3 resets: maxItems: 1 reset-names: @@ -73,11 +76,33 @@ allOf: compatible: contains: enum: + - rockchip,rk3576-otp + then: + properties: + clocks: + maxItems: 3 + clock-names: + maxItems: 3 + resets: + minItems: 2 + maxItems: 2 + reset-names: + items: + - const: otp + - const: apb + + - if: + properties: + compatible: + contains: + enum: - rockchip,rk3588-otp then: properties: clocks: minItems: 4 + clock-names: + minItems: 4 resets: minItems: 3 reset-names: diff --git a/Documentation/devicetree/bindings/opp/opp-v1.yaml b/Documentation/devicetree/bindings/opp/opp-v1.yaml index 07e26c267815..61c080e50859 100644 --- a/Documentation/devicetree/bindings/opp/opp-v1.yaml +++ b/Documentation/devicetree/bindings/opp/opp-v1.yaml @@ -18,9 +18,21 @@ description: |+ This binding only supports voltage-frequency pairs. -select: true +deprecated: true properties: + clock-latency: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The latency in nanoseconds for clock changes. Use OPP tables for new + designs instead. + + voltage-tolerance: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 10 + description: + The voltage tolerance in percent. Use OPP tables for new designs instead. + operating-points: $ref: /schemas/types.yaml#/definitions/uint32-matrix items: @@ -28,8 +40,12 @@ properties: - description: Frequency in kHz - description: Voltage for OPP in uV +dependencies: + clock-latency: [ operating-points ] + voltage-tolerance: [ operating-points ] additionalProperties: true + examples: - | cpus { diff --git a/Documentation/devicetree/bindings/opp/opp-v2-qcom-adreno.yaml b/Documentation/devicetree/bindings/opp/opp-v2-qcom-adreno.yaml new file mode 100644 index 000000000000..a27ba7b663d4 --- /dev/null +++ b/Documentation/devicetree/bindings/opp/opp-v2-qcom-adreno.yaml @@ -0,0 +1,96 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/opp/opp-v2-qcom-adreno.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Adreno compatible OPP supply + +description: + Adreno GPUs present in Qualcomm's Snapdragon chipsets uses an OPP specific + ACD related information tailored for the specific chipset. This binding + provides the information needed to describe such a hardware value. + +maintainers: + - Rob Clark <robdclark@gmail.com> + +allOf: + - $ref: opp-v2-base.yaml# + +properties: + compatible: + contains: + const: operating-points-v2-adreno + +patternProperties: + '^opp-[0-9]+$': + type: object + additionalProperties: false + + properties: + opp-hz: true + + opp-level: true + + opp-peak-kBps: true + + opp-supported-hw: true + + qcom,opp-acd-level: + description: | + A positive value representing the ACD (Adaptive Clock Distribution, + a fancy name for clk throttling during voltage droop) level associated + with this OPP node. This value is shared to a co-processor inside GPU + (called Graphics Management Unit a.k.a GMU) during wake up. It may not + be present for some OPPs and GMU will disable ACD while transitioning + to that OPP. This value encodes a voltage threshold, delay cycles & + calibration margins which are identified by characterization of the + SoC. So, it doesn't have any unit. This data is passed to GMU firmware + via 'HFI_H2F_MSG_ACD' packet. + $ref: /schemas/types.yaml#/definitions/uint32 + + required: + - opp-hz + - opp-level + +required: + - compatible + +additionalProperties: false + +examples: + - | + #include <dt-bindings/power/qcom-rpmpd.h> + + gpu_opp_table: opp-table { + compatible = "operating-points-v2-adreno", "operating-points-v2"; + + opp-687000000 { + opp-hz = /bits/ 64 <687000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; + opp-peak-kBps = <8171875>; + qcom,opp-acd-level = <0x882e5ffd>; + }; + + opp-550000000 { + opp-hz = /bits/ 64 <550000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS>; + opp-peak-kBps = <6074219>; + qcom,opp-acd-level = <0xc0285ffd>; + }; + + opp-390000000 { + opp-hz = /bits/ 64 <390000000>; + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; + opp-peak-kBps = <3000000>; + qcom,opp-acd-level = <0xc0285ffd>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; + opp-peak-kBps = <2136719>; + /* Intentionally left out qcom,opp-acd-level property here */ + }; + + }; diff --git a/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml b/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml index 52533fccc134..5d3f48a001b7 100644 --- a/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml +++ b/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml @@ -12,9 +12,19 @@ maintainers: properties: compatible: + description: Each family of socfpga has its own implementation of the + PCI controller. The altr,pcie-root-port-1.0 is used for the Cyclone5 + family of chips. The Stratix10 family of chips is supported by the + altr,pcie-root-port-2.0. The Agilex family of chips has three, + non-register compatible, variants of PCIe Hard IP referred to as the + F-Tile, P-Tile, and R-Tile, depending on the specific chip instance. + enum: - altr,pcie-root-port-1.0 - altr,pcie-root-port-2.0 + - altr,pcie-root-port-3.0-f-tile + - altr,pcie-root-port-3.0-p-tile + - altr,pcie-root-port-3.0-r-tile reg: items: diff --git a/Documentation/devicetree/bindings/pci/amd,versal2-mdb-host.yaml b/Documentation/devicetree/bindings/pci/amd,versal2-mdb-host.yaml new file mode 100644 index 000000000000..43dc2585c237 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/amd,versal2-mdb-host.yaml @@ -0,0 +1,121 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/amd,versal2-mdb-host.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: AMD Versal2 MDB(Multimedia DMA Bridge) Host Controller + +maintainers: + - Thippeswamy Havalige <thippeswamy.havalige@amd.com> + +allOf: + - $ref: /schemas/pci/pci-host-bridge.yaml# + - $ref: /schemas/pci/snps,dw-pcie.yaml# + +properties: + compatible: + const: amd,versal2-mdb-host + + reg: + items: + - description: MDB System Level Control and Status Register (SLCR) Base + - description: configuration region + - description: data bus interface + - description: address translation unit register + + reg-names: + items: + - const: slcr + - const: config + - const: dbi + - const: atu + + ranges: + maxItems: 2 + + msi-map: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-map-mask: + items: + - const: 0 + - const: 0 + - const: 0 + - const: 7 + + interrupt-map: + maxItems: 4 + + "#interrupt-cells": + const: 1 + + interrupt-controller: + description: identifies the node as an interrupt controller + type: object + additionalProperties: false + properties: + interrupt-controller: true + + "#address-cells": + const: 0 + + "#interrupt-cells": + const: 1 + + required: + - interrupt-controller + - "#address-cells" + - "#interrupt-cells" + +required: + - reg + - reg-names + - interrupts + - interrupt-map + - interrupt-map-mask + - msi-map + - "#interrupt-cells" + - interrupt-controller + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + pcie@ed931000 { + compatible = "amd,versal2-mdb-host"; + reg = <0x0 0xed931000 0x0 0x2000>, + <0x1000 0x100000 0x0 0xff00000>, + <0x1000 0x0 0x0 0x1000>, + <0x0 0xed860000 0x0 0x2000>; + reg-names = "slcr", "config", "dbi", "atu"; + ranges = <0x2000000 0x00 0xa0000000 0x00 0xa0000000 0x00 0x10000000>, + <0x43000000 0x1100 0x00 0x1100 0x00 0x00 0x1000000>; + interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc_0 0>, + <0 0 0 2 &pcie_intc_0 1>, + <0 0 0 3 &pcie_intc_0 2>, + <0 0 0 4 &pcie_intc_0 3>; + msi-map = <0x0 &gic_its 0x00 0x10000>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + pcie_intc_0: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pci/apple,pcie.yaml b/Documentation/devicetree/bindings/pci/apple,pcie.yaml index c8775f9cb071..c0852be04f6d 100644 --- a/Documentation/devicetree/bindings/pci/apple,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/apple,pcie.yaml @@ -17,6 +17,10 @@ description: | implements its root ports. But the ATU found on most DesignWare PCIe host bridges is absent. + On systems derived from T602x, the PHY registers are in a region + separate from the port registers. In that case, there is one PHY + register range per port register range. + All root ports share a single ECAM space, but separate GPIOs are used to take the PCI devices on those ports out of reset. Therefore the standard "reset-gpios" and "max-link-speed" properties appear on @@ -30,16 +34,18 @@ description: | properties: compatible: - items: - - enum: - - apple,t8103-pcie - - apple,t8112-pcie - - apple,t6000-pcie - - const: apple,pcie + oneOf: + - items: + - enum: + - apple,t8103-pcie + - apple,t8112-pcie + - apple,t6000-pcie + - const: apple,pcie + - const: apple,t6020-pcie reg: minItems: 3 - maxItems: 6 + maxItems: 10 reg-names: minItems: 3 @@ -50,6 +56,10 @@ properties: - const: port1 - const: port2 - const: port3 + - const: phy0 + - const: phy1 + - const: phy2 + - const: phy3 ranges: minItems: 2 @@ -98,6 +108,15 @@ allOf: maxItems: 5 interrupts: maxItems: 3 + - if: + properties: + compatible: + contains: + const: apple,t6020-pcie + then: + properties: + reg-names: + minItems: 10 examples: - | diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml index 2ad1652c2584..c4f9674e8695 100644 --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml @@ -14,6 +14,7 @@ properties: items: - enum: - brcm,bcm2711-pcie # The Raspberry Pi 4 + - brcm,bcm2712-pcie # Raspberry Pi 5 - brcm,bcm4908-pcie - brcm,bcm7211-pcie # Broadcom STB version of RPi4 - brcm,bcm7216-pcie # Broadcom 7216 Arm @@ -101,7 +102,10 @@ properties: reset-names: minItems: 1 - maxItems: 3 + items: + - enum: [perst, rescal] + - const: bridge + - const: swinit required: - compatible @@ -182,49 +186,48 @@ examples: #include <dt-bindings/interrupt-controller/arm-gic.h> scb { - #address-cells = <2>; - #size-cells = <1>; - pcie0: pcie@7d500000 { - compatible = "brcm,bcm2711-pcie"; - reg = <0x0 0x7d500000 0x9310>; - device_type = "pci"; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "pcie", "msi"; - interrupt-map-mask = <0x0 0x0 0x0 0x7>; - interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH - 0 0 0 2 &gicv2 GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH - 0 0 0 3 &gicv2 GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH - 0 0 0 4 &gicv2 GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; - - msi-parent = <&pcie0>; - msi-controller; - ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000 0x0 0x04000000>; - dma-ranges = <0x42000000 0x1 0x00000000 0x0 0x40000000 0x0 0x80000000>, - <0x42000000 0x1 0x80000000 0x3 0x00000000 0x0 0x80000000>; - brcm,enable-ssc; - brcm,scb-sizes = <0x0000000080000000 0x0000000080000000>; - - /* PCIe bridge, Root Port */ - pci@0,0 { - #address-cells = <3>; - #size-cells = <2>; - reg = <0x0 0x0 0x0 0x0 0x0>; - compatible = "pciclass,0604"; - device_type = "pci"; - vpcie3v3-supply = <&vreg7>; - ranges; - - /* PCIe endpoint */ - pci-ep@0,0 { - assigned-addresses = - <0x82010000 0x0 0xf8000000 0x6 0x00000000 0x0 0x2000>; - reg = <0x0 0x0 0x0 0x0 0x0>; - compatible = "pci14e4,1688"; - }; - }; + #address-cells = <2>; + #size-cells = <1>; + pcie0: pcie@7d500000 { + compatible = "brcm,bcm2711-pcie"; + reg = <0x0 0x7d500000 0x9310>; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pcie", "msi"; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH + 0 0 0 2 &gicv2 GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH + 0 0 0 3 &gicv2 GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH + 0 0 0 4 &gicv2 GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; + + msi-parent = <&pcie0>; + msi-controller; + ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000 0x0 0x04000000>; + dma-ranges = <0x42000000 0x1 0x00000000 0x0 0x40000000 0x0 0x80000000>, + <0x42000000 0x1 0x80000000 0x3 0x00000000 0x0 0x80000000>; + brcm,enable-ssc; + brcm,scb-sizes = <0x0000000080000000 0x0000000080000000>; + + /* PCIe bridge, Root Port */ + pci@0,0 { + #address-cells = <3>; + #size-cells = <2>; + reg = <0x0 0x0 0x0 0x0 0x0>; + compatible = "pciclass,0604"; + device_type = "pci"; + vpcie3v3-supply = <&vreg7>; + ranges; + + /* PCIe endpoint */ + pci-ep@0,0 { + assigned-addresses = <0x82010000 0x0 0xf8000000 0x6 0x00000000 0x0 0x2000>; + reg = <0x0 0x0 0x0 0x0 0x0>; + compatible = "pci14e4,1688"; + }; }; + }; }; diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml index 98651ab22103..8735293962ee 100644 --- a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml @@ -37,14 +37,14 @@ examples: #size-cells = <2>; pcie-ep@fc000000 { - compatible = "cdns,cdns-pcie-ep"; - reg = <0x0 0xfc000000 0x0 0x01000000>, - <0x0 0x80000000 0x0 0x40000000>; - reg-names = "reg", "mem"; - cdns,max-outbound-regions = <16>; - max-functions = /bits/ 8 <8>; - phys = <&pcie_phy0>; - phy-names = "pcie-phy"; + compatible = "cdns,cdns-pcie-ep"; + reg = <0x0 0xfc000000 0x0 0x01000000>, + <0x0 0x80000000 0x0 0x40000000>; + reg-names = "reg", "mem"; + cdns,max-outbound-regions = <16>; + max-functions = /bits/ 8 <8>; + phys = <&pcie_phy0>; + phy-names = "pcie-phy"; }; }; ... diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml index 4c76cd3f98a9..ca5f2970f217 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml @@ -47,12 +47,16 @@ properties: maxItems: 5 interrupts: + minItems: 1 items: - description: builtin MSI controller. + - description: builtin DMA controller. interrupt-names: + minItems: 1 items: - const: msi + - const: dma reset-gpio: description: Should specify the GPIO for controlling the PCI bus device diff --git a/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml index 399efa7364c9..d78a6d1f7198 100644 --- a/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml @@ -94,9 +94,6 @@ examples: reg-names = "regs", "addr_space"; interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */ interrupt-names = "pme"; - num-ib-windows = <6>; - num-ob-windows = <8>; - status = "disabled"; }; }; ... diff --git a/Documentation/devicetree/bindings/pci/fsl,mpc8xxx-pci.yaml b/Documentation/devicetree/bindings/pci/fsl,mpc8xxx-pci.yaml new file mode 100644 index 000000000000..28759ab1caaa --- /dev/null +++ b/Documentation/devicetree/bindings/pci/fsl,mpc8xxx-pci.yaml @@ -0,0 +1,113 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- + +$id: http://devicetree.org/schemas/pci/fsl,mpc8xxx-pci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale MPC83xx PCI/PCI-X/PCIe controllers + +description: + Binding for the PCI/PCI-X/PCIe host bridges on MPC8xxx SoCs + +maintainers: + - J. Neuschäfer <j.neuschaefer@gmx.net> + +allOf: + - $ref: /schemas/pci/pci-host-bridge.yaml# + +properties: + compatible: + oneOf: + - enum: + - fsl,mpc8314-pcie + - fsl,mpc8349-pci + - fsl,mpc8540-pci + - fsl,mpc8548-pcie + - fsl,mpc8641-pcie + - items: + - enum: + - fsl,mpc8308-pcie + - fsl,mpc8315-pcie + - fsl,mpc8377-pcie + - fsl,mpc8378-pcie + - const: fsl,mpc8314-pcie + - items: + - const: fsl,mpc8360-pci + - const: fsl,mpc8349-pci + - items: + - const: fsl,mpc8540-pcix + - const: fsl,mpc8540-pci + + reg: + minItems: 1 + items: + - description: internal registers + - description: config space access registers + + clock-frequency: true + + interrupts: + items: + - description: Consolidated PCI interrupt + + fsl,pci-agent-force-enum: + type: boolean + description: + Typically any Freescale PCI-X bridge hardware strapped into Agent mode is + prevented from enumerating the bus. The PrPMC form-factor requires all + mezzanines to be PCI-X Agents, but one per system may still enumerate the + bus. + + This property allows a PCI-X bridge to be used for bus enumeration + despite being strapped into Agent mode. + +required: + - reg + - compatible + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + pcie@e0009000 { + compatible = "fsl,mpc8315-pcie", "fsl,mpc8314-pcie"; + reg = <0xe0009000 0x00001000>; + ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000 + 0x01000000 0 0x00000000 0xb1000000 0 0x00800000>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + bus-range = <0 255>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = <0 0 0 1 &ipic 1 IRQ_TYPE_LEVEL_LOW + 0 0 0 2 &ipic 1 IRQ_TYPE_LEVEL_LOW + 0 0 0 3 &ipic 1 IRQ_TYPE_LEVEL_LOW + 0 0 0 4 &ipic 1 IRQ_TYPE_LEVEL_LOW>; + clock-frequency = <0>; + }; + + - | + pci@ef008000 { + compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; + reg = <0xef008000 0x1000>; + ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000 + 0x01000000 0 0x00000000 0xd0000000 0 0x01000000>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + clock-frequency = <33333333>; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; + interrupt-map = </* IDSEL */ + 0xe000 0 0 1 &mpic 2 1 + 0xe000 0 0 2 &mpic 3 1>; + interrupts-extended = <&mpic 24 2>; + bus-range = <0 0>; + fsl,pci-agent-force-enum; + }; + +... diff --git a/Documentation/devicetree/bindings/pci/fsl,pci.txt b/Documentation/devicetree/bindings/pci/fsl,pci.txt deleted file mode 100644 index d8ac4a768e7e..000000000000 --- a/Documentation/devicetree/bindings/pci/fsl,pci.txt +++ /dev/null @@ -1,27 +0,0 @@ -* Bus Enumeration by Freescale PCI-X Agent - -Typically any Freescale PCI-X bridge hardware strapped into Agent mode -is prevented from enumerating the bus. The PrPMC form-factor requires -all mezzanines to be PCI-X Agents, but one per system may still -enumerate the bus. - -The property defined below will allow a PCI-X bridge to be used for bus -enumeration despite being strapped into Agent mode. - -Required properties: -- fsl,pci-agent-force-enum : There is no value associated with this - property. The property itself is treated as a boolean. - -Example: - - /* PCI-X bridge known to be PrPMC Monarch */ - pci0: pci@ef008000 { - fsl,pci-agent-force-enum; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; - device_type = "pci"; - ... - ... - }; diff --git a/Documentation/devicetree/bindings/pci/intel,keembay-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/intel,keembay-pcie-ep.yaml index 730e63fd7669..b19f61ae72fb 100644 --- a/Documentation/devicetree/bindings/pci/intel,keembay-pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/intel,keembay-pcie-ep.yaml @@ -53,17 +53,17 @@ examples: #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> pcie-ep@37000000 { - compatible = "intel,keembay-pcie-ep"; - reg = <0x37000000 0x00001000>, - <0x37100000 0x00001000>, - <0x37300000 0x00001000>, - <0x36000000 0x01000000>, - <0x37800000 0x00000200>; - reg-names = "dbi", "dbi2", "atu", "addr_space", "apb"; - interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 108 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "pcie", "pcie_ev", "pcie_err", "pcie_mem_access"; - num-lanes = <2>; + compatible = "intel,keembay-pcie-ep"; + reg = <0x37000000 0x00001000>, + <0x37100000 0x00001000>, + <0x37300000 0x00001000>, + <0x36000000 0x01000000>, + <0x37800000 0x00000200>; + reg-names = "dbi", "dbi2", "atu", "addr_space", "apb"; + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 108 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pcie", "pcie_ev", "pcie_err", "pcie_mem_access"; + num-lanes = <2>; }; diff --git a/Documentation/devicetree/bindings/pci/intel,keembay-pcie.yaml b/Documentation/devicetree/bindings/pci/intel,keembay-pcie.yaml index 1fd557504b10..dd71e3d6bf94 100644 --- a/Documentation/devicetree/bindings/pci/intel,keembay-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/intel,keembay-pcie.yaml @@ -75,23 +75,23 @@ examples: #define KEEM_BAY_A53_PCIE #define KEEM_BAY_A53_AUX_PCIE pcie@37000000 { - compatible = "intel,keembay-pcie"; - reg = <0x37000000 0x00001000>, - <0x37300000 0x00001000>, - <0x36e00000 0x00200000>, - <0x37800000 0x00000200>; - reg-names = "dbi", "atu", "config", "apb"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x02000000 0 0x36000000 0x36000000 0 0x00e00000>; - interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "pcie", "pcie_ev", "pcie_err"; - clocks = <&scmi_clk KEEM_BAY_A53_PCIE>, - <&scmi_clk KEEM_BAY_A53_AUX_PCIE>; - clock-names = "master", "aux"; - reset-gpios = <&pca2 9 GPIO_ACTIVE_LOW>; - num-lanes = <2>; + compatible = "intel,keembay-pcie"; + reg = <0x37000000 0x00001000>, + <0x37300000 0x00001000>, + <0x36e00000 0x00200000>, + <0x37800000 0x00000200>; + reg-names = "dbi", "atu", "config", "apb"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x02000000 0 0x36000000 0x36000000 0 0x00e00000>; + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pcie", "pcie_ev", "pcie_err"; + clocks = <&scmi_clk KEEM_BAY_A53_PCIE>, + <&scmi_clk KEEM_BAY_A53_AUX_PCIE>; + clock-names = "master", "aux"; + reset-gpios = <&pca2 9 GPIO_ACTIVE_LOW>; + num-lanes = <2>; }; diff --git a/Documentation/devicetree/bindings/pci/marvell,armada8k-pcie.yaml b/Documentation/devicetree/bindings/pci/marvell,armada8k-pcie.yaml new file mode 100644 index 000000000000..f3ba9230ce2a --- /dev/null +++ b/Documentation/devicetree/bindings/pci/marvell,armada8k-pcie.yaml @@ -0,0 +1,100 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/marvell,armada8k-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Armada 7K/8K PCIe interface + +maintainers: + - Thomas Petazzoni <thomas.petazzoni@bootlin.com> + +description: + This PCIe host controller is based on the Synopsys DesignWare PCIe IP. + +select: + properties: + compatible: + contains: + enum: + - marvell,armada8k-pcie + required: + - compatible + +allOf: + - $ref: snps,dw-pcie.yaml# + +properties: + compatible: + items: + - enum: + - marvell,armada8k-pcie + - const: snps,dw-pcie + + reg: + maxItems: 2 + + reg-names: + items: + - const: ctrl + - const: config + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + items: + - const: core + - const: reg + + interrupts: + maxItems: 1 + + msi-parent: + maxItems: 1 + + phys: + minItems: 1 + maxItems: 4 + + phy-names: + minItems: 1 + maxItems: 4 + + marvell,reset-gpio: + maxItems: 1 + deprecated: true + +required: + - interrupt-map + - clocks + - msi-parent + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + + pcie@f2600000 { + compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; + reg = <0xf2600000 0x10000>, <0xf6f00000 0x80000>; + reg-names = "ctrl", "config"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + dma-coherent; + msi-parent = <&gic_v2m0>; + + ranges = <0x81000000 0 0xf9000000 0xf9000000 0 0x10000>, /* downstream I/O */ + <0x82000000 0 0xf6000000 0xf6000000 0 0xf00000>; /* non-prefetchable memory */ + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + num-lanes = <1>; + clocks = <&cpm_syscon0 1 13>; + }; +... diff --git a/Documentation/devicetree/bindings/pci/marvell,kirkwood-pcie.yaml b/Documentation/devicetree/bindings/pci/marvell,kirkwood-pcie.yaml new file mode 100644 index 000000000000..7be695320ddf --- /dev/null +++ b/Documentation/devicetree/bindings/pci/marvell,kirkwood-pcie.yaml @@ -0,0 +1,277 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/marvell,kirkwood-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell EBU PCIe interfaces + +maintainers: + - Thomas Petazzoni <thomas.petazzoni@bootlin.com> + - Pali Rohár <pali@kernel.org> + +allOf: + - $ref: /schemas/pci/pci-host-bridge.yaml# + +properties: + compatible: + enum: + - marvell,armada-370-pcie + - marvell,armada-xp-pcie + - marvell,dove-pcie + - marvell,kirkwood-pcie + + ranges: + description: > + The ranges describing the MMIO registers have the following layout: + + 0x82000000 0 r MBUS_ID(0xf0, 0x01) r 0 s + + where: + + * r is a 32-bits value that gives the offset of the MMIO registers of + this PCIe interface, from the base of the internal registers. + + * s is a 32-bits value that give the size of this MMIO registers area. + This range entry translates the '0x82000000 0 r' PCI address into the + 'MBUS_ID(0xf0, 0x01) r' CPU address, which is part of the internal + register window (as identified by MBUS_ID(0xf0, 0x01)). + + The ranges describing the MBus windows have the following layout: + + 0x8t000000 s 0 MBUS_ID(w, a) 0 1 0 + + where: + + * t is the type of the MBus window (as defined by the standard PCI DT + bindings), 1 for I/O and 2 for memory. + + * s is the PCI slot that corresponds to this PCIe interface + + * w is the 'target ID' value for the MBus window + + * a the 'attribute' value for the MBus window. + + Since the location and size of the different MBus windows is not fixed in + hardware, and only determined in runtime, those ranges cover the full first + 4 GB of the physical address space, and do not translate into a valid CPU + address. + + msi-parent: + maxItems: 1 + +patternProperties: + '^pcie@': + type: object + allOf: + - $ref: /schemas/pci/pci-bus-common.yaml# + - $ref: /schemas/pci/pci-device.yaml# + unevaluatedProperties: false + + properties: + clocks: + maxItems: 1 + + interrupts: + minItems: 1 + maxItems: 2 + + interrupt-names: + minItems: 1 + items: + - const: intx + - const: error + + reset-delay-us: + default: 100000 + description: todo + + marvell,pcie-port: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 3 + description: todo + + marvell,pcie-lane: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 3 + description: todo + + interrupt-controller: + type: object + additionalProperties: false + + properties: + interrupt-controller: true + + '#interrupt-cells': + const: 1 + + required: + - assigned-addresses + - clocks + - interrupt-map + - marvell,pcie-port + +unevaluatedProperties: false + +examples: + - | + #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pcie@f001000000000000 { + compatible = "marvell,armada-xp-pcie"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + + bus-range = <0x00 0xff>; + msi-parent = <&mpic>; + + ranges = + <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ + 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */ + 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */ + 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ + 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */ + 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */ + 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */ + 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */ + 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */ + 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */ + 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ + 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ + 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */ + 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */ + 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */ + 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */ + 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */ + 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */ + + 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */ + 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */ + 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */ + 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */ + 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */ + 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */ + 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */ + 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */ + + 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */ + 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */ + + 0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */ + 0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>; + + pcie@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 58>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + num-lanes = <1>; + /* low-active PERST# reset on GPIO 25 */ + reset-gpios = <&gpio0 25 1>; + /* wait 20ms for device settle after reset deassertion */ + reset-delay-us = <20000>; + clocks = <&gateclk 5>; + }; + + pcie@2,0 { + device_type = "pci"; + assigned-addresses = <0x82001000 0 0x44000 0 0x2000>; + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 + 0x81000000 0 0 0x81000000 0x2 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 59>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <1>; + num-lanes = <1>; + clocks = <&gateclk 6>; + }; + + pcie@3,0 { + device_type = "pci"; + assigned-addresses = <0x82001800 0 0x48000 0 0x2000>; + reg = <0x1800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 + 0x81000000 0 0 0x81000000 0x3 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 60>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <2>; + num-lanes = <1>; + clocks = <&gateclk 7>; + }; + + pcie@4,0 { + device_type = "pci"; + assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>; + reg = <0x2000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 + 0x81000000 0 0 0x81000000 0x4 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 61>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <3>; + num-lanes = <1>; + clocks = <&gateclk 8>; + }; + + pcie@5,0 { + device_type = "pci"; + assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; + reg = <0x2800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 + 0x81000000 0 0 0x81000000 0x5 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 62>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <0>; + num-lanes = <1>; + clocks = <&gateclk 9>; + }; + + pcie@6,0 { + device_type = "pci"; + assigned-addresses = <0x82003000 0 0x84000 0 0x2000>; + reg = <0x3000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0 + 0x81000000 0 0 0x81000000 0x6 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 63>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <1>; + num-lanes = <1>; + clocks = <&gateclk 10>; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml index f05aab2b1add..162406e0691a 100644 --- a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml @@ -109,6 +109,17 @@ properties: power-domains: maxItems: 1 + mediatek,pbus-csr: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to pbus-csr syscon + - description: offset of pbus-csr base address register + - description: offset of pbus-csr base address mask register + description: + Phandle with two arguments to the syscon node used to detect if + a given address is accessible on PCIe controller. + '#interrupt-cells': const: 1 @@ -168,6 +179,8 @@ allOf: minItems: 1 maxItems: 2 + mediatek,pbus-csr: false + - if: properties: compatible: @@ -197,6 +210,8 @@ allOf: minItems: 1 maxItems: 2 + mediatek,pbus-csr: false + - if: properties: compatible: @@ -224,6 +239,8 @@ allOf: minItems: 1 maxItems: 2 + mediatek,pbus-csr: false + - if: properties: compatible: diff --git a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml index 103574d18dbc..47b0bad690d5 100644 --- a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml +++ b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml @@ -50,7 +50,7 @@ properties: items: pattern: '^fic[0-3]$' - dma-coherent: true + dma-noncoherent: true ranges: minItems: 1 @@ -65,33 +65,33 @@ unevaluatedProperties: false examples: - | soc { - #address-cells = <2>; + #address-cells = <2>; + #size-cells = <2>; + pcie0: pcie@2030000000 { + compatible = "microchip,pcie-host-1.0"; + reg = <0x0 0x70000000 0x0 0x08000000>, + <0x0 0x43008000 0x0 0x00002000>, + <0x0 0x4300a000 0x0 0x00002000>; + reg-names = "cfg", "bridge", "ctrl"; + device_type = "pci"; + #address-cells = <3>; #size-cells = <2>; - pcie0: pcie@2030000000 { - compatible = "microchip,pcie-host-1.0"; - reg = <0x0 0x70000000 0x0 0x08000000>, - <0x0 0x43008000 0x0 0x00002000>, - <0x0 0x4300a000 0x0 0x00002000>; - reg-names = "cfg", "bridge", "ctrl"; - device_type = "pci"; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - interrupts = <119>; - interrupt-map-mask = <0x0 0x0 0x0 0x7>; - interrupt-map = <0 0 0 1 &pcie_intc0 0>, - <0 0 0 2 &pcie_intc0 1>, - <0 0 0 3 &pcie_intc0 2>, - <0 0 0 4 &pcie_intc0 3>; - interrupt-parent = <&plic0>; - msi-parent = <&pcie0>; - msi-controller; - bus-range = <0x00 0x7f>; - ranges = <0x03000000 0x0 0x78000000 0x0 0x78000000 0x0 0x04000000>; - pcie_intc0: interrupt-controller { - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - }; + #interrupt-cells = <1>; + interrupts = <119>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0 0 0 1 &pcie_intc0 0>, + <0 0 0 2 &pcie_intc0 1>, + <0 0 0 3 &pcie_intc0 2>, + <0 0 0 4 &pcie_intc0 3>; + interrupt-parent = <&plic0>; + msi-parent = <&pcie0>; + msi-controller; + bus-range = <0x00 0x7f>; + ranges = <0x03000000 0x0 0x78000000 0x0 0x78000000 0x0 0x04000000>; + pcie_intc0: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; }; + }; }; diff --git a/Documentation/devicetree/bindings/pci/mvebu-pci.txt b/Documentation/devicetree/bindings/pci/mvebu-pci.txt deleted file mode 100644 index 6d022a9d36ee..000000000000 --- a/Documentation/devicetree/bindings/pci/mvebu-pci.txt +++ /dev/null @@ -1,310 +0,0 @@ -* Marvell EBU PCIe interfaces - -Mandatory properties: - -- compatible: one of the following values: - marvell,armada-370-pcie - marvell,armada-xp-pcie - marvell,dove-pcie - marvell,kirkwood-pcie -- #address-cells, set to <3> -- #size-cells, set to <2> -- #interrupt-cells, set to <1> -- bus-range: PCI bus numbers covered -- device_type, set to "pci" -- ranges: ranges describing the MMIO registers to control the PCIe - interfaces, and ranges describing the MBus windows needed to access - the memory and I/O regions of each PCIe interface. -- msi-parent: Link to the hardware entity that serves as the Message - Signaled Interrupt controller for this PCI controller. - -The ranges describing the MMIO registers have the following layout: - - 0x82000000 0 r MBUS_ID(0xf0, 0x01) r 0 s - -where: - - * r is a 32-bits value that gives the offset of the MMIO - registers of this PCIe interface, from the base of the internal - registers. - - * s is a 32-bits value that give the size of this MMIO - registers area. This range entry translates the '0x82000000 0 r' PCI - address into the 'MBUS_ID(0xf0, 0x01) r' CPU address, which is part - of the internal register window (as identified by MBUS_ID(0xf0, - 0x01)). - -The ranges describing the MBus windows have the following layout: - - 0x8t000000 s 0 MBUS_ID(w, a) 0 1 0 - -where: - - * t is the type of the MBus window (as defined by the standard PCI DT - bindings), 1 for I/O and 2 for memory. - - * s is the PCI slot that corresponds to this PCIe interface - - * w is the 'target ID' value for the MBus window - - * a the 'attribute' value for the MBus window. - -Since the location and size of the different MBus windows is not fixed in -hardware, and only determined in runtime, those ranges cover the full first -4 GB of the physical address space, and do not translate into a valid CPU -address. - -In addition, the device tree node must have sub-nodes describing each -PCIe interface, having the following mandatory properties: - -- reg: used only for interrupt mapping, so only the first four bytes - are used to refer to the correct bus number and device number. -- assigned-addresses: reference to the MMIO registers used to control - this PCIe interface. -- clocks: the clock associated to this PCIe interface -- marvell,pcie-port: the physical PCIe port number -- status: either "disabled" or "okay" -- device_type, set to "pci" -- #address-cells, set to <3> -- #size-cells, set to <2> -- #interrupt-cells, set to <1> -- ranges, translating the MBus windows ranges of the parent node into - standard PCI addresses. -- interrupt-map-mask and interrupt-map, standard PCI properties to - define the mapping of the PCIe interface to interrupt numbers. - -and the following optional properties: -- marvell,pcie-lane: the physical PCIe lane number, for ports having - multiple lanes. If this property is not found, we assume that the - value is 0. -- num-lanes: number of SerDes PCIe lanes for this link (1 or 4) -- reset-gpios: optional GPIO to PERST# -- reset-delay-us: delay in us to wait after reset de-assertion, if not - specified will default to 100ms, as required by the PCIe specification. -- interrupt-names: list of interrupt names, supported are: - - "intx" - interrupt line triggered by one of the legacy interrupt -- interrupts or interrupts-extended: List of the interrupt sources which - corresponding to the "interrupt-names". If non-empty then also additional - 'interrupt-controller' subnode must be defined. - -Example: - -pcie-controller { - compatible = "marvell,armada-xp-pcie"; - device_type = "pci"; - - #address-cells = <3>; - #size-cells = <2>; - - bus-range = <0x00 0xff>; - msi-parent = <&mpic>; - - ranges = - <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ - 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */ - 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */ - 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ - 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */ - 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */ - 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */ - 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */ - 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */ - 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */ - 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ - 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ - 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */ - 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */ - 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */ - 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */ - 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */ - 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */ - - 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */ - 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */ - 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */ - 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */ - 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */ - 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */ - 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */ - 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */ - - 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */ - 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */ - - 0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */ - 0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>; - - pcie@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 - 0x81000000 0 0 0x81000000 0x1 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 58>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <0>; - num-lanes = <1>; - /* low-active PERST# reset on GPIO 25 */ - reset-gpios = <&gpio0 25 1>; - /* wait 20ms for device settle after reset deassertion */ - reset-delay-us = <20000>; - clocks = <&gateclk 5>; - }; - - pcie@2,0 { - device_type = "pci"; - assigned-addresses = <0x82001000 0 0x44000 0 0x2000>; - reg = <0x1000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 - 0x81000000 0 0 0x81000000 0x2 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 59>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <1>; - num-lanes = <1>; - clocks = <&gateclk 6>; - }; - - pcie@3,0 { - device_type = "pci"; - assigned-addresses = <0x82001800 0 0x48000 0 0x2000>; - reg = <0x1800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 - 0x81000000 0 0 0x81000000 0x3 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 60>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <2>; - num-lanes = <1>; - clocks = <&gateclk 7>; - }; - - pcie@4,0 { - device_type = "pci"; - assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>; - reg = <0x2000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 - 0x81000000 0 0 0x81000000 0x4 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 61>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <3>; - num-lanes = <1>; - clocks = <&gateclk 8>; - }; - - pcie@5,0 { - device_type = "pci"; - assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; - reg = <0x2800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 - 0x81000000 0 0 0x81000000 0x5 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 62>; - marvell,pcie-port = <1>; - marvell,pcie-lane = <0>; - num-lanes = <1>; - clocks = <&gateclk 9>; - }; - - pcie@6,0 { - device_type = "pci"; - assigned-addresses = <0x82003000 0 0x84000 0 0x2000>; - reg = <0x3000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0 - 0x81000000 0 0 0x81000000 0x6 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 63>; - marvell,pcie-port = <1>; - marvell,pcie-lane = <1>; - num-lanes = <1>; - clocks = <&gateclk 10>; - }; - - pcie@7,0 { - device_type = "pci"; - assigned-addresses = <0x82003800 0 0x88000 0 0x2000>; - reg = <0x3800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0 - 0x81000000 0 0 0x81000000 0x7 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 64>; - marvell,pcie-port = <1>; - marvell,pcie-lane = <2>; - num-lanes = <1>; - clocks = <&gateclk 11>; - }; - - pcie@8,0 { - device_type = "pci"; - assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>; - reg = <0x4000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0 - 0x81000000 0 0 0x81000000 0x8 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 65>; - marvell,pcie-port = <1>; - marvell,pcie-lane = <3>; - num-lanes = <1>; - clocks = <&gateclk 12>; - }; - - pcie@9,0 { - device_type = "pci"; - assigned-addresses = <0x82004800 0 0x42000 0 0x2000>; - reg = <0x4800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0 - 0x81000000 0 0 0x81000000 0x9 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 99>; - marvell,pcie-port = <2>; - marvell,pcie-lane = <0>; - num-lanes = <1>; - clocks = <&gateclk 26>; - }; - - pcie@a,0 { - device_type = "pci"; - assigned-addresses = <0x82005000 0 0x82000 0 0x2000>; - reg = <0x5000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0 - 0x81000000 0 0 0x81000000 0xa 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 103>; - marvell,pcie-port = <3>; - marvell,pcie-lane = <0>; - num-lanes = <1>; - clocks = <&gateclk 27>; - }; -}; diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml index a24fb8307d29..6d6052a2748f 100644 --- a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml @@ -74,7 +74,7 @@ properties: reset-gpios: description: Must contain a phandle to a GPIO controller followed by GPIO - that is being used as PERST input signal. Please refer to pci.txt. + that is being used as PERST input signal. phys: minItems: 1 diff --git a/Documentation/devicetree/bindings/pci/pci-armada8k.txt b/Documentation/devicetree/bindings/pci/pci-armada8k.txt deleted file mode 100644 index ff25a134befa..000000000000 --- a/Documentation/devicetree/bindings/pci/pci-armada8k.txt +++ /dev/null @@ -1,48 +0,0 @@ -* Marvell Armada 7K/8K PCIe interface - -This PCIe host controller is based on the Synopsys DesignWare PCIe IP -and thus inherits all the common properties defined in snps,dw-pcie.yaml. - -Required properties: -- compatible: "marvell,armada8k-pcie" -- reg: must contain two register regions - - the control register region - - the config space region -- reg-names: - - "ctrl" for the control register region - - "config" for the config space region -- interrupts: Interrupt specifier for the PCIe controller -- clocks: reference to the PCIe controller clocks -- clock-names: mandatory if there is a second clock, in this case the - name must be "core" for the first clock and "reg" for the second - one - -Optional properties: -- phys: phandle(s) to PHY node(s) following the generic PHY bindings. - Either 1, 2 or 4 PHYs might be needed depending on the number of - PCIe lanes. -- phy-names: names of the PHYs corresponding to the number of lanes. - Must be "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy" for - 2 PHYs. - -Example: - - pcie@f2600000 { - compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; - reg = <0 0xf2600000 0 0x10000>, <0 0xf6f00000 0 0x80000>; - reg-names = "ctrl", "config"; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - device_type = "pci"; - dma-coherent; - - bus-range = <0 0xff>; - ranges = <0x81000000 0 0xf9000000 0 0xf9000000 0 0x10000 /* downstream I/O */ - 0x82000000 0 0xf6000000 0 0xf6000000 0 0xf00000>; /* non-prefetchable memory */ - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; - num-lanes = <1>; - clocks = <&cpm_syscon0 1 13>; - }; diff --git a/Documentation/devicetree/bindings/pci/pci-ep-bus.yaml b/Documentation/devicetree/bindings/pci/pci-ep-bus.yaml new file mode 100644 index 000000000000..a2cd7905f5bf --- /dev/null +++ b/Documentation/devicetree/bindings/pci/pci-ep-bus.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/pci-ep-bus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Common Properties for PCI MFD EP with Peripherals Addressable from BARs + +maintainers: + - A. della Porta <andrea.porta@suse.com> + +description: + Define a generic node representing a PCI endpoint which contains several sub- + peripherals. The peripherals can be accessed through one or more BARs. + This common schema is intended to be referenced from device tree bindings and + does not represent a device tree binding by itself. + +properties: + '#address-cells': + const: 3 + + '#size-cells': + const: 2 + + ranges: + minItems: 1 + maxItems: 6 + items: + maxItems: 8 + additionalItems: true + items: + - maximum: 5 # The BAR number + - const: 0 + - const: 0 + +patternProperties: + '^pci-ep-bus@[0-5]$': + type: object + description: + One node for each BAR used by peripherals contained in the PCI endpoint. + Each node represents a bus on which peripherals are connected. + This allows for some segmentation, e.g., one peripheral is accessible + through BAR0 and another through BAR1, and you don't want the two + peripherals to be able to act on the other BAR. Alternatively, when + different peripherals need to share BARs, you can define only one node + and use a 'ranges' property to map all the used BARs. + + additionalProperties: true + + properties: + compatible: + const: simple-bus + + required: + - compatible + +additionalProperties: true +... diff --git a/Documentation/devicetree/bindings/pci/pci-ep.yaml b/Documentation/devicetree/bindings/pci/pci-ep.yaml index f75000e3093d..214caa4ec3d5 100644 --- a/Documentation/devicetree/bindings/pci/pci-ep.yaml +++ b/Documentation/devicetree/bindings/pci/pci-ep.yaml @@ -17,6 +17,24 @@ properties: $nodename: pattern: "^pcie-ep@" + iommu-map: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + items: + items: + - description: Device ID (see msi-map) base + maximum: 0x7ffff + - description: phandle to IOMMU + - description: IOMMU specifier base (currently always 1 cell) + - description: Number of Device IDs + maximum: 0x80000 + + iommu-map-mask: + description: + A mask to be applied to each Device ID prior to being mapped to an + IOMMU specifier per the iommu-map property. + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 0x7ffff + max-functions: description: Maximum number of functions that can be configured $ref: /schemas/types.yaml#/definitions/uint8 @@ -35,6 +53,56 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32 enum: [ 1, 2, 3, 4 ] + msi-map: + description: | + Maps a Device ID to an MSI and associated MSI specifier data. + + A PCI Endpoint (EP) can use MSI as a doorbell function. This is achieved by + mapping the MSI controller's address into PCI BAR<n>. The PCI Root Complex + can write to this BAR<n>, triggering the EP to generate IRQ. This notifies + the EP-side driver of an event, eliminating the need for the driver to + continuously poll for status changes. + + However, the EP cannot rely on Requester ID (RID) because the RID is + determined by the PCI topology of the host system. Since the EP may be + connected to different PCI hosts, the RID can vary between systems and is + therefore not a reliable identifier. + + Each EP can support up to 8 physical functions and up to 65,536 virtual + functions. To uniquely identify each child device, a device ID is defined + as + - Bits [2:0] for the function number (func) + - Bits [18:3] for the virtual function index (vfunc) + + The resulting device ID is computed as: + + (func & 0x7) | (vfunc << 3) + + The property is an arbitrary number of tuples of + (device-id-base, msi, msi-base,length). + + Any Device ID id in the interval [id-base, id-base + length) is + associated with the listed MSI, with the MSI specifier + (id - id-base + msi-base). + $ref: /schemas/types.yaml#/definitions/uint32-matrix + items: + items: + - description: The Device ID base matched by the entry + maximum: 0x7ffff + - description: phandle to msi-controller node + - description: (optional) The msi-specifier produced for the first + Device ID matched by the entry. Currently, msi-specifier is 0 or + 1 cells. + - description: The length of consecutive Device IDs following the + Device ID base + maximum: 0x80000 + + msi-map-mask: + description: A mask to be applied to each Device ID prior to being + mapped to an msi-specifier per the msi-map property. + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 0x7ffff + num-lanes: description: maximum number of lanes $ref: /schemas/types.yaml#/definitions/uint32 diff --git a/Documentation/devicetree/bindings/pci/pci-iommu.txt b/Documentation/devicetree/bindings/pci/pci-iommu.txt deleted file mode 100644 index 0def586fdcdf..000000000000 --- a/Documentation/devicetree/bindings/pci/pci-iommu.txt +++ /dev/null @@ -1,171 +0,0 @@ -This document describes the generic device tree binding for describing the -relationship between PCI(e) devices and IOMMU(s). - -Each PCI(e) device under a root complex is uniquely identified by its Requester -ID (AKA RID). A Requester ID is a triplet of a Bus number, Device number, and -Function number. - -For the purpose of this document, when treated as a numeric value, a RID is -formatted such that: - -* Bits [15:8] are the Bus number. -* Bits [7:3] are the Device number. -* Bits [2:0] are the Function number. -* Any other bits required for padding must be zero. - -IOMMUs may distinguish PCI devices through sideband data derived from the -Requester ID. While a given PCI device can only master through one IOMMU, a -root complex may split masters across a set of IOMMUs (e.g. with one IOMMU per -bus). - -The generic 'iommus' property is insufficient to describe this relationship, -and a mechanism is required to map from a PCI device to its IOMMU and sideband -data. - -For generic IOMMU bindings, see -Documentation/devicetree/bindings/iommu/iommu.txt. - - -PCI root complex -================ - -Optional properties -------------------- - -- iommu-map: Maps a Requester ID to an IOMMU and associated IOMMU specifier - data. - - The property is an arbitrary number of tuples of - (rid-base,iommu,iommu-base,length). - - Any RID r in the interval [rid-base, rid-base + length) is associated with - the listed IOMMU, with the IOMMU specifier (r - rid-base + iommu-base). - -- iommu-map-mask: A mask to be applied to each Requester ID prior to being - mapped to an IOMMU specifier per the iommu-map property. - - -Example (1) -=========== - -/ { - #address-cells = <1>; - #size-cells = <1>; - - iommu: iommu@a { - reg = <0xa 0x1>; - compatible = "vendor,some-iommu"; - #iommu-cells = <1>; - }; - - pci: pci@f { - reg = <0xf 0x1>; - compatible = "vendor,pcie-root-complex"; - device_type = "pci"; - - /* - * The sideband data provided to the IOMMU is the RID, - * identity-mapped. - */ - iommu-map = <0x0 &iommu 0x0 0x10000>; - }; -}; - - -Example (2) -=========== - -/ { - #address-cells = <1>; - #size-cells = <1>; - - iommu: iommu@a { - reg = <0xa 0x1>; - compatible = "vendor,some-iommu"; - #iommu-cells = <1>; - }; - - pci: pci@f { - reg = <0xf 0x1>; - compatible = "vendor,pcie-root-complex"; - device_type = "pci"; - - /* - * The sideband data provided to the IOMMU is the RID with the - * function bits masked out. - */ - iommu-map = <0x0 &iommu 0x0 0x10000>; - iommu-map-mask = <0xfff8>; - }; -}; - - -Example (3) -=========== - -/ { - #address-cells = <1>; - #size-cells = <1>; - - iommu: iommu@a { - reg = <0xa 0x1>; - compatible = "vendor,some-iommu"; - #iommu-cells = <1>; - }; - - pci: pci@f { - reg = <0xf 0x1>; - compatible = "vendor,pcie-root-complex"; - device_type = "pci"; - - /* - * The sideband data provided to the IOMMU is the RID, - * but the high bits of the bus number are flipped. - */ - iommu-map = <0x0000 &iommu 0x8000 0x8000>, - <0x8000 &iommu 0x0000 0x8000>; - }; -}; - - -Example (4) -=========== - -/ { - #address-cells = <1>; - #size-cells = <1>; - - iommu_a: iommu@a { - reg = <0xa 0x1>; - compatible = "vendor,some-iommu"; - #iommu-cells = <1>; - }; - - iommu_b: iommu@b { - reg = <0xb 0x1>; - compatible = "vendor,some-iommu"; - #iommu-cells = <1>; - }; - - iommu_c: iommu@c { - reg = <0xc 0x1>; - compatible = "vendor,some-iommu"; - #iommu-cells = <1>; - }; - - pci: pci@f { - reg = <0xf 0x1>; - compatible = "vendor,pcie-root-complex"; - device_type = "pci"; - - /* - * Devices with bus number 0-127 are mastered via IOMMU - * a, with sideband data being RID[14:0]. - * Devices with bus number 128-255 are mastered via - * IOMMU b, with sideband data being RID[14:0]. - * No devices master via IOMMU c. - */ - iommu-map = <0x0000 &iommu_a 0x0000 0x8000>, - <0x8000 &iommu_b 0x0000 0x8000>; - }; -}; diff --git a/Documentation/devicetree/bindings/pci/pci-msi.txt b/Documentation/devicetree/bindings/pci/pci-msi.txt deleted file mode 100644 index b73d839657b6..000000000000 --- a/Documentation/devicetree/bindings/pci/pci-msi.txt +++ /dev/null @@ -1,220 +0,0 @@ -This document describes the generic device tree binding for describing the -relationship between PCI devices and MSI controllers. - -Each PCI device under a root complex is uniquely identified by its Requester ID -(AKA RID). A Requester ID is a triplet of a Bus number, Device number, and -Function number. - -For the purpose of this document, when treated as a numeric value, a RID is -formatted such that: - -* Bits [15:8] are the Bus number. -* Bits [7:3] are the Device number. -* Bits [2:0] are the Function number. -* Any other bits required for padding must be zero. - -MSIs may be distinguished in part through the use of sideband data accompanying -writes. In the case of PCI devices, this sideband data may be derived from the -Requester ID. A mechanism is required to associate a device with both the MSI -controllers it can address, and the sideband data that will be associated with -its writes to those controllers. - -For generic MSI bindings, see -Documentation/devicetree/bindings/interrupt-controller/msi.txt. - - -PCI root complex -================ - -Optional properties -------------------- - -- msi-map: Maps a Requester ID to an MSI controller and associated - msi-specifier data. The property is an arbitrary number of tuples of - (rid-base,msi-controller,msi-base,length), where: - - * rid-base is a single cell describing the first RID matched by the entry. - - * msi-controller is a single phandle to an MSI controller - - * msi-base is an msi-specifier describing the msi-specifier produced for the - first RID matched by the entry. - - * length is a single cell describing how many consecutive RIDs are matched - following the rid-base. - - Any RID r in the interval [rid-base, rid-base + length) is associated with - the listed msi-controller, with the msi-specifier (r - rid-base + msi-base). - -- msi-map-mask: A mask to be applied to each Requester ID prior to being mapped - to an msi-specifier per the msi-map property. - -- msi-parent: Describes the MSI parent of the root complex itself. Where - the root complex and MSI controller do not pass sideband data with MSI - writes, this property may be used to describe the MSI controller(s) - used by PCI devices under the root complex, if defined as such in the - binding for the root complex. - - -Example (1) -=========== - -/ { - #address-cells = <1>; - #size-cells = <1>; - - msi: msi-controller@a { - reg = <0xa 0x1>; - compatible = "vendor,some-controller"; - msi-controller; - #msi-cells = <1>; - }; - - pci: pci@f { - reg = <0xf 0x1>; - compatible = "vendor,pcie-root-complex"; - device_type = "pci"; - - /* - * The sideband data provided to the MSI controller is - * the RID, identity-mapped. - */ - msi-map = <0x0 &msi_a 0x0 0x10000>, - }; -}; - - -Example (2) -=========== - -/ { - #address-cells = <1>; - #size-cells = <1>; - - msi: msi-controller@a { - reg = <0xa 0x1>; - compatible = "vendor,some-controller"; - msi-controller; - #msi-cells = <1>; - }; - - pci: pci@f { - reg = <0xf 0x1>; - compatible = "vendor,pcie-root-complex"; - device_type = "pci"; - - /* - * The sideband data provided to the MSI controller is - * the RID, masked to only the device and function bits. - */ - msi-map = <0x0 &msi_a 0x0 0x100>, - msi-map-mask = <0xff> - }; -}; - - -Example (3) -=========== - -/ { - #address-cells = <1>; - #size-cells = <1>; - - msi: msi-controller@a { - reg = <0xa 0x1>; - compatible = "vendor,some-controller"; - msi-controller; - #msi-cells = <1>; - }; - - pci: pci@f { - reg = <0xf 0x1>; - compatible = "vendor,pcie-root-complex"; - device_type = "pci"; - - /* - * The sideband data provided to the MSI controller is - * the RID, but the high bit of the bus number is - * ignored. - */ - msi-map = <0x0000 &msi 0x0000 0x8000>, - <0x8000 &msi 0x0000 0x8000>; - }; -}; - - -Example (4) -=========== - -/ { - #address-cells = <1>; - #size-cells = <1>; - - msi: msi-controller@a { - reg = <0xa 0x1>; - compatible = "vendor,some-controller"; - msi-controller; - #msi-cells = <1>; - }; - - pci: pci@f { - reg = <0xf 0x1>; - compatible = "vendor,pcie-root-complex"; - device_type = "pci"; - - /* - * The sideband data provided to the MSI controller is - * the RID, but the high bit of the bus number is - * negated. - */ - msi-map = <0x0000 &msi 0x8000 0x8000>, - <0x8000 &msi 0x0000 0x8000>; - }; -}; - - -Example (5) -=========== - -/ { - #address-cells = <1>; - #size-cells = <1>; - - msi_a: msi-controller@a { - reg = <0xa 0x1>; - compatible = "vendor,some-controller"; - msi-controller; - #msi-cells = <1>; - }; - - msi_b: msi-controller@b { - reg = <0xb 0x1>; - compatible = "vendor,some-controller"; - msi-controller; - #msi-cells = <1>; - }; - - msi_c: msi-controller@c { - reg = <0xc 0x1>; - compatible = "vendor,some-controller"; - msi-controller; - #msi-cells = <1>; - }; - - pci: pci@f { - reg = <0xf 0x1>; - compatible = "vendor,pcie-root-complex"; - device_type = "pci"; - - /* - * The sideband data provided to MSI controller a is the - * RID, but the high bit of the bus number is negated. - * The sideband data provided to MSI controller b is the - * RID, identity-mapped. - * MSI controller c is not addressable. - */ - msi-map = <0x0000 &msi_a 0x8000 0x08000>, - <0x8000 &msi_a 0x0000 0x08000>, - <0x0000 &msi_b 0x0000 0x10000>; - }; -}; diff --git a/Documentation/devicetree/bindings/pci/pci.txt b/Documentation/devicetree/bindings/pci/pci.txt deleted file mode 100644 index 6a8f2874a24d..000000000000 --- a/Documentation/devicetree/bindings/pci/pci.txt +++ /dev/null @@ -1,84 +0,0 @@ -PCI bus bridges have standardized Device Tree bindings: - -PCI Bus Binding to: IEEE Std 1275-1994 -https://www.devicetree.org/open-firmware/bindings/pci/pci2_1.pdf - -And for the interrupt mapping part: - -Open Firmware Recommended Practice: Interrupt Mapping -https://www.devicetree.org/open-firmware/practice/imap/imap0_9d.pdf - -Additionally to the properties specified in the above standards a host bridge -driver implementation may support the following properties: - -- linux,pci-domain: - If present this property assigns a fixed PCI domain number to a host bridge, - otherwise an unstable (across boots) unique number will be assigned. - It is required to either not set this property at all or set it for all - host bridges in the system, otherwise potentially conflicting domain numbers - may be assigned to root buses behind different host bridges. The domain - number for each host bridge in the system must be unique. -- max-link-speed: - If present this property specifies PCI gen for link capability. Host - drivers could add this as a strategy to avoid unnecessary operation for - unsupported link speed, for instance, trying to do training for - unsupported link speed, etc. Must be '4' for gen4, '3' for gen3, '2' - for gen2, and '1' for gen1. Any other values are invalid. -- reset-gpios: - If present this property specifies PERST# GPIO. Host drivers can parse the - GPIO and apply fundamental reset to endpoints. -- supports-clkreq: - If present this property specifies that CLKREQ signal routing exists from - root port to downstream device and host bridge drivers can do programming - which depends on CLKREQ signal existence. For example, programming root port - not to advertise ASPM L1 Sub-States support if there is no CLKREQ signal. - -PCI-PCI Bridge properties -------------------------- - -PCIe root ports and switch ports may be described explicitly in the device -tree, as children of the host bridge node. Even though those devices are -discoverable by probing, it might be necessary to describe properties that -aren't provided by standard PCIe capabilities. - -Required properties: - -- reg: - Identifies the PCI-PCI bridge. As defined in the IEEE Std 1275-1994 - document, it is a five-cell address encoded as (phys.hi phys.mid - phys.lo size.hi size.lo). phys.hi should contain the device's BDF as - 0b00000000 bbbbbbbb dddddfff 00000000. The other cells should be zero. - - The bus number is defined by firmware, through the standard bridge - configuration mechanism. If this port is a switch port, then firmware - allocates the bus number and writes it into the Secondary Bus Number - register of the bridge directly above this port. Otherwise, the bus - number of a root port is the first number in the bus-range property, - defaulting to zero. - - If firmware leaves the ARI Forwarding Enable bit set in the bridge - above this port, then phys.hi contains the 8-bit function number as - 0b00000000 bbbbbbbb ffffffff 00000000. Note that the PCIe specification - recommends that firmware only leaves ARI enabled when it knows that the - OS is ARI-aware. - -Optional properties: - -- external-facing: - When present, the port is external-facing. All bridges and endpoints - downstream of this port are external to the machine. The OS can, for - example, use this information to identify devices that cannot be - trusted with relaxed DMA protection, as users could easily attach - malicious devices to this port. - -Example: - -pcie@10000000 { - compatible = "pci-host-ecam-generic"; - ... - pcie@0008 { - /* Root port 00:01.0 is external-facing */ - reg = <0x00000800 0 0 0 0>; - external-facing; - }; -}; diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml index 1226ee5d08d1..ac3414203d38 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml @@ -14,6 +14,7 @@ properties: oneOf: - enum: - qcom,sa8775p-pcie-ep + - qcom,sar2130p-pcie-ep - qcom,sdx55-pcie-ep - qcom,sm8450-pcie-ep - items: @@ -44,11 +45,11 @@ properties: clocks: minItems: 5 - maxItems: 8 + maxItems: 9 clock-names: minItems: 5 - maxItems: 8 + maxItems: 9 qcom,perst-regs: description: Reference to a syscon representing TCSR followed by the two @@ -75,6 +76,9 @@ properties: - const: doorbell - const: dma + iommus: + maxItems: 1 + reset-gpios: description: GPIO used as PERST# input signal maxItems: 1 @@ -91,6 +95,8 @@ properties: - const: pcie-mem - const: cpu-pcie + dma-coherent: true + resets: maxItems: 1 @@ -126,6 +132,38 @@ required: allOf: - $ref: pci-ep.yaml# + + - if: + properties: + compatible: + contains: + enum: + - qcom,sar2130p-pcie-ep + then: + properties: + clocks: + items: + - description: PCIe Auxiliary clock + - description: PCIe CFG AHB clock + - description: PCIe Master AXI clock + - description: PCIe Slave AXI clock + - description: PCIe Slave Q2A AXI clock + - description: PCIe DDRSS SF TBU clock + - description: PCIe AGGRE NOC AXI clock + - description: PCIe CFG NOC AXI clock + - description: PCIe QMIP AHB clock + clock-names: + items: + - const: aux + - const: cfg + - const: bus_master + - const: bus_slave + - const: slave_q2a + - const: ddrss_sf_tbu + - const: aggre_noc_axi + - const: cnoc_sf_axi + - const: qmip_pcie_ahb + - if: properties: compatible: @@ -135,9 +173,43 @@ allOf: then: properties: reg: + minItems: 6 maxItems: 6 reg-names: + minItems: 6 maxItems: 6 + interrupts: + minItems: 2 + maxItems: 2 + interrupt-names: + minItems: 2 + maxItems: 2 + iommus: false + else: + properties: + reg: + minItems: 7 + maxItems: 7 + reg-names: + minItems: 7 + maxItems: 7 + interrupts: + minItems: 3 + maxItems: 3 + interrupt-names: + minItems: 3 + maxItems: 3 + required: + - iommus + + - if: + properties: + compatible: + contains: + enum: + - qcom,sdx55-pcie-ep + then: + properties: clocks: items: - description: PCIe Auxiliary clock @@ -156,10 +228,6 @@ allOf: - const: slave_q2a - const: sleep - const: ref - interrupts: - maxItems: 2 - interrupt-names: - maxItems: 2 - if: properties: @@ -169,10 +237,6 @@ allOf: - qcom,sm8450-pcie-ep then: properties: - reg: - maxItems: 6 - reg-names: - maxItems: 6 clocks: items: - description: PCIe Auxiliary clock @@ -193,10 +257,6 @@ allOf: - const: ref - const: ddrss_sf_tbu - const: aggre_noc_axi - interrupts: - maxItems: 2 - interrupt-names: - maxItems: 2 - if: properties: @@ -206,12 +266,6 @@ allOf: - qcom,sa8775p-pcie-ep then: properties: - reg: - minItems: 7 - maxItems: 7 - reg-names: - minItems: 7 - maxItems: 7 clocks: items: - description: PCIe Auxiliary clock @@ -226,12 +280,6 @@ allOf: - const: bus_master - const: bus_slave - const: slave_q2a - interrupts: - minItems: 3 - maxItems: 3 - interrupt-names: - minItems: 3 - maxItems: 3 unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml index efde49d1bef8..e3fa232da2ca 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml @@ -45,9 +45,10 @@ properties: interrupts: minItems: 8 - maxItems: 8 + maxItems: 9 interrupt-names: + minItems: 8 items: - const: msi0 - const: msi1 @@ -57,6 +58,7 @@ properties: - const: msi5 - const: msi6 - const: msi7 + - const: global resets: maxItems: 1 @@ -129,7 +131,8 @@ examples: <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "msi0", "msi1", "msi2", @@ -137,7 +140,8 @@ examples: "msi4", "msi5", "msi6", - "msi7"; + "msi7", + "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml index 76cb9fbfd476..ff508f592a1a 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml @@ -54,9 +54,10 @@ properties: interrupts: minItems: 8 - maxItems: 8 + maxItems: 9 interrupt-names: + minItems: 8 items: - const: msi0 - const: msi1 @@ -66,6 +67,7 @@ properties: - const: msi5 - const: msi6 - const: msi7 + - const: global resets: maxItems: 1 @@ -149,9 +151,10 @@ examples: <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "msi0", "msi1", "msi2", "msi3", - "msi4", "msi5", "msi6", "msi7"; + "msi4", "msi5", "msi6", "msi7", "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sc8180x.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sc8180x.yaml index baf1813ec0ac..331fc25d7a17 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-sc8180x.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sc8180x.yaml @@ -49,9 +49,10 @@ properties: interrupts: minItems: 8 - maxItems: 8 + maxItems: 9 interrupt-names: + minItems: 8 items: - const: msi0 - const: msi1 @@ -61,6 +62,7 @@ properties: - const: msi5 - const: msi6 - const: msi7 + - const: global resets: maxItems: 1 @@ -136,7 +138,8 @@ examples: <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "msi0", "msi1", "msi2", @@ -144,7 +147,8 @@ examples: "msi4", "msi5", "msi6", - "msi7"; + "msi7", + "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8150.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8150.yaml index 9d569644fda9..a604f2a79de3 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8150.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8150.yaml @@ -49,9 +49,10 @@ properties: interrupts: minItems: 8 - maxItems: 8 + maxItems: 9 interrupt-names: + minItems: 8 items: - const: msi0 - const: msi1 @@ -61,6 +62,7 @@ properties: - const: msi5 - const: msi6 - const: msi7 + - const: global resets: maxItems: 1 @@ -128,9 +130,10 @@ examples: <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "msi0", "msi1", "msi2", "msi3", - "msi4", "msi5", "msi6", "msi7"; + "msi4", "msi5", "msi6", "msi7", "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8250.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8250.yaml index 4d060bce6f9d..af4dae68d508 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8250.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8250.yaml @@ -61,9 +61,10 @@ properties: interrupts: minItems: 8 - maxItems: 8 + maxItems: 9 interrupt-names: + minItems: 8 items: - const: msi0 - const: msi1 @@ -73,6 +74,7 @@ properties: - const: msi5 - const: msi6 - const: msi7 + - const: global resets: maxItems: 1 @@ -143,9 +145,10 @@ examples: <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "msi0", "msi1", "msi2", "msi3", - "msi4", "msi5", "msi6", "msi7"; + "msi4", "msi5", "msi6", "msi7", "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8350.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8350.yaml index 2a4cc41fc710..dde3079adbb3 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8350.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8350.yaml @@ -51,9 +51,10 @@ properties: interrupts: minItems: 8 - maxItems: 8 + maxItems: 9 interrupt-names: + minItems: 8 items: - const: msi0 - const: msi1 @@ -63,6 +64,7 @@ properties: - const: msi5 - const: msi6 - const: msi7 + - const: global resets: maxItems: 1 @@ -132,9 +134,10 @@ examples: <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "msi0", "msi1", "msi2", "msi3", - "msi4", "msi5", "msi6", "msi7"; + "msi4", "msi5", "msi6", "msi7", "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index 7235d6554cfb..0e1808105a81 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -21,6 +21,7 @@ properties: - qcom,pcie-apq8064 - qcom,pcie-apq8084 - qcom,pcie-ipq4019 + - qcom,pcie-ipq5018 - qcom,pcie-ipq6018 - qcom,pcie-ipq8064 - qcom,pcie-ipq8064-v2 @@ -33,6 +34,7 @@ properties: - qcom,pcie-sdx55 - items: - enum: + - qcom,pcie-ipq5332 - qcom,pcie-ipq5424 - const: qcom,pcie-ipq9574 - items: @@ -49,11 +51,11 @@ properties: interrupts: minItems: 1 - maxItems: 8 + maxItems: 9 interrupt-names: minItems: 1 - maxItems: 8 + maxItems: 9 iommu-map: minItems: 1 @@ -167,6 +169,7 @@ allOf: compatible: contains: enum: + - qcom,pcie-ipq5018 - qcom,pcie-ipq6018 - qcom,pcie-ipq8074-gen3 - qcom,pcie-ipq9574 @@ -174,14 +177,16 @@ allOf: properties: reg: minItems: 5 - maxItems: 5 + maxItems: 6 reg-names: + minItems: 5 items: - const: dbi # DesignWare PCIe registers - const: elbi # External local bus interface registers - const: atu # ATU address space - const: parf # Qualcomm specific registers - const: config # PCIe configuration space + - const: mhi # MHI registers - if: properties: @@ -326,6 +331,53 @@ allOf: compatible: contains: enum: + - qcom,pcie-ipq5018 + then: + properties: + clocks: + minItems: 6 + maxItems: 6 + clock-names: + items: + - const: iface # PCIe to SysNOC BIU clock + - const: axi_m # AXI Master clock + - const: axi_s # AXI Slave clock + - const: ahb # AHB clock + - const: aux # Auxiliary clock + - const: axi_bridge # AXI bridge clock + resets: + minItems: 8 + maxItems: 8 + reset-names: + items: + - const: pipe # PIPE reset + - const: sleep # Sleep reset + - const: sticky # Core sticky reset + - const: axi_m # AXI master reset + - const: axi_s # AXI slave reset + - const: ahb # AHB reset + - const: axi_m_sticky # AXI master sticky reset + - const: axi_s_sticky # AXI slave sticky reset + interrupts: + minItems: 9 + maxItems: 9 + interrupt-names: + items: + - const: msi0 + - const: msi1 + - const: msi2 + - const: msi3 + - const: msi4 + - const: msi5 + - const: msi6 + - const: msi7 + - const: global + + - if: + properties: + compatible: + contains: + enum: - qcom,pcie-msm8996 then: properties: @@ -443,6 +495,7 @@ allOf: interrupts: minItems: 8 interrupt-names: + minItems: 8 items: - const: msi0 - const: msi1 @@ -452,6 +505,7 @@ allOf: - const: msi5 - const: msi6 - const: msi7 + - const: global - if: properties: @@ -559,6 +613,7 @@ allOf: enum: - qcom,pcie-apq8064 - qcom,pcie-ipq4019 + - qcom,pcie-ipq5018 - qcom,pcie-ipq8064 - qcom,pcie-ipq8064v2 - qcom,pcie-ipq8074 @@ -586,7 +641,11 @@ allOf: compatible: contains: enum: + - qcom,pcie-ipq6018 + - qcom,pcie-ipq8074 + - qcom,pcie-ipq8074-gen3 - qcom,pcie-msm8996 + - qcom,pcie-msm8998 - qcom,pcie-sdm845 then: oneOf: @@ -599,7 +658,9 @@ allOf: - properties: interrupts: minItems: 8 + maxItems: 9 interrupt-names: + minItems: 8 items: - const: msi0 - const: msi1 @@ -609,6 +670,7 @@ allOf: - const: msi5 - const: msi6 - const: msi7 + - const: global - if: properties: @@ -618,11 +680,8 @@ allOf: - qcom,pcie-apq8064 - qcom,pcie-apq8084 - qcom,pcie-ipq4019 - - qcom,pcie-ipq6018 - qcom,pcie-ipq8064 - qcom,pcie-ipq8064-v2 - - qcom,pcie-ipq8074 - - qcom,pcie-ipq8074-gen3 - qcom,pcie-qcs404 then: properties: diff --git a/Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml b/Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml index 32a3b7665ff5..6b91581c30ae 100644 --- a/Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml +++ b/Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml @@ -73,21 +73,21 @@ examples: #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/power/r8a774c0-sysc.h> - pcie0_ep: pcie-ep@fe000000 { - compatible = "renesas,r8a774c0-pcie-ep", - "renesas,rcar-gen3-pcie-ep"; - reg = <0xfe000000 0x80000>, - <0xfe100000 0x100000>, - <0xfe200000 0x200000>, - <0x30000000 0x8000000>, - <0x38000000 0x8000000>; - reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; - interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; - resets = <&cpg 319>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - clocks = <&cpg CPG_MOD 319>; - clock-names = "pcie"; - max-functions = /bits/ 8 <1>; + pcie0_ep: pcie-ep@fe000000 { + compatible = "renesas,r8a774c0-pcie-ep", + "renesas,rcar-gen3-pcie-ep"; + reg = <0xfe000000 0x80000>, + <0xfe100000 0x100000>, + <0xfe200000 0x200000>, + <0x30000000 0x8000000>, + <0x38000000 0x8000000>; + reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; + resets = <&cpg 319>; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + clocks = <&cpg CPG_MOD 319>; + clock-names = "pcie"; + max-functions = /bits/ 8 <1>; }; diff --git a/Documentation/devicetree/bindings/pci/rcar-pci-host.yaml b/Documentation/devicetree/bindings/pci/rcar-pci-host.yaml index 666f013e3af8..7896576920aa 100644 --- a/Documentation/devicetree/bindings/pci/rcar-pci-host.yaml +++ b/Documentation/devicetree/bindings/pci/rcar-pci-host.yaml @@ -113,27 +113,27 @@ examples: pcie: pcie@fe000000 { compatible = "renesas,pcie-r8a7791", "renesas,pcie-rcar-gen2"; reg = <0 0xfe000000 0 0x80000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - device_type = "pci"; - ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, - <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, - <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, - <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>, - <0x42000000 2 0x00000000 2 0x00000000 0 0x40000000>; - interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; - clock-names = "pcie", "pcie_bus"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 319>; - vpcie3v3-supply = <&pcie_3v3>; - vpcie12v-supply = <&pcie_12v>; - }; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, + <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, + <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, + <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>, + <0x42000000 2 0x00000000 2 0x00000000 0 0x40000000>; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 319>; + vpcie3v3-supply = <&pcie_3v3>; + vpcie12v-supply = <&pcie_12v>; + }; }; diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml index cc9adfc7611c..fde9b87508b3 100644 --- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml @@ -65,7 +65,11 @@ properties: tx_cpl_timeout, cor_err_sent, nf_err_sent, f_err_sent, cor_err_rx, nf_err_rx, f_err_rx, radm_qoverflow - description: - eDMA write channel 0 interrupt + If the matching interrupt name is "msi", then this is the combined + MSI line interrupt, which is to support MSI interrupts output to GIC + controller via GIC SPI interrupt instead of GIC ITS interrupt. + If the matching interrupt name is "dma0", then this is the eDMA write + channel 0 interrupt. - description: eDMA write channel 1 interrupt - description: @@ -81,7 +85,9 @@ properties: - const: msg - const: legacy - const: err - - const: dma0 + - enum: + - msi + - dma0 - const: dma1 - const: dma2 - const: dma3 diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml index 550d8a684af3..6c6d828ce964 100644 --- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml @@ -16,16 +16,14 @@ description: |+ PCIe IP and thus inherits all the common properties defined in snps,dw-pcie.yaml. -allOf: - - $ref: /schemas/pci/snps,dw-pcie.yaml# - - $ref: /schemas/pci/rockchip-dw-pcie-common.yaml# - properties: compatible: oneOf: - const: rockchip,rk3568-pcie - items: - enum: + - rockchip,rk3562-pcie + - rockchip,rk3576-pcie - rockchip,rk3588-pcie - const: rockchip,rk3568-pcie @@ -71,8 +69,58 @@ properties: vpcie3v3-supply: true -required: - - msi-map +allOf: + - $ref: /schemas/pci/snps,dw-pcie.yaml# + - $ref: /schemas/pci/rockchip-dw-pcie-common.yaml# + - if: + not: + properties: + compatible: + contains: + enum: + - rockchip,rk3562-pcie + - rockchip,rk3576-pcie + then: + required: + - msi-map + + - if: + properties: + compatible: + contains: + enum: + - rockchip,rk3562-pcie + - rockchip,rk3576-pcie + then: + properties: + interrupts: + minItems: 6 + maxItems: 6 + interrupt-names: + items: + - const: sys + - const: pmc + - const: msg + - const: legacy + - const: err + - const: msi + else: + properties: + interrupts: + minItems: 5 + interrupt-names: + minItems: 5 + items: + - const: sys + - const: pmc + - const: msg + - const: legacy + - const: err + - const: dma0 + - const: dma1 + - const: dma2 + - const: dma3 + unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml b/Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml index 844fc7142302..d35ff807936b 100644 --- a/Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml @@ -81,10 +81,10 @@ unevaluatedProperties: false examples: - | + #include <dt-bindings/clock/sifive-fu740-prci.h> bus { #address-cells = <2>; #size-cells = <2>; - #include <dt-bindings/clock/sifive-fu740-prci.h> pcie@e00000000 { compatible = "sifive,fu740-pcie"; diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml index dc05761c5cf9..34594972d8db 100644 --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml @@ -115,7 +115,7 @@ properties: above for new bindings. oneOf: - description: See native 'dbi' clock for details - enum: [ pcie, pcie_apb_sys, aclk_dbi ] + enum: [ pcie, pcie_apb_sys, aclk_dbi, reg ] - description: See native 'mstr/slv' clock for details enum: [ pcie_bus, pcie_inbound_axi, pcie_aclk, aclk_mst, aclk_slv ] - description: See native 'pipe' clock for details @@ -201,6 +201,7 @@ properties: oneOf: - pattern: '^pcie(-?phy[0-9]*)?$' - pattern: '^p2u-[0-7]$' + - pattern: '^cp[01]-pcie[0-2]-x[124](-lane[0-3])?-phy$' # marvell,armada8k-pcie reset-gpio: deprecated: true diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml index 205326fb2d75..69e82f438f58 100644 --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml @@ -105,6 +105,8 @@ properties: Vendor-specific CSR names. Consider using the generic names above for new bindings. oneOf: + - description: See native 'dbi' CSR region for details. + enum: [ ctrl ] - description: See native 'elbi/app' CSR region for details. enum: [ apb, mgmt, link, ulreg, appl ] - description: See native 'atu' CSR region for details. @@ -113,9 +115,11 @@ properties: enum: [ smu, mpu ] - description: Tegra234 aperture enum: [ ecam ] + - description: AMD MDB PCIe SLCR region + const: slcr allOf: - contains: - const: dbi + enum: [ dbi, ctrl ] - contains: const: config diff --git a/Documentation/devicetree/bindings/pci/v3,v360epc-pci.yaml b/Documentation/devicetree/bindings/pci/v3,v360epc-pci.yaml new file mode 100644 index 000000000000..38cac88f17bf --- /dev/null +++ b/Documentation/devicetree/bindings/pci/v3,v360epc-pci.yaml @@ -0,0 +1,100 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/v3,v360epc-pci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: V3 Semiconductor V360 EPC PCI bridge + +maintainers: + - Linus Walleij <linus.walleij@linaro.org> + +description: + This bridge is found in the ARM Integrator/AP (Application Platform) + +allOf: + - $ref: /schemas/pci/pci-host-bridge.yaml# + +properties: + compatible: + items: + - const: arm,integrator-ap-pci + - const: v3,v360epc-pci + + reg: + items: + - description: V3 host bridge controller + - description: Configuration space + + clocks: + maxItems: 1 + + dma-ranges: + maxItems: 2 + description: + The inbound ranges must be aligned to a 1MB boundary, and may be 1MB, 2MB, + 4MB, 8MB, 16MB, 32MB, 64MB, 128MB, 256MB, 512MB, 1GB or 2GB in size. The + memory should be marked as pre-fetchable. + + interrupts: + description: Bus Error IRQ + maxItems: 1 + + ranges: + description: + The non-prefetchable and prefetchable memory windows must each be exactly + 256MB (0x10000000) in size. The prefetchable memory window must be + immediately adjacent to the non-prefetchable memory window. + +required: + - compatible + - reg + - clocks + - dma-ranges + - "#interrupt-cells" + - interrupt-map + - interrupt-map-mask + +unevaluatedProperties: false + +examples: + - | + pci@62000000 { + compatible = "arm,integrator-ap-pci", "v3,v360epc-pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <0x62000000 0x10000>, <0x61000000 0x01000000>; + device_type = "pci"; + interrupt-parent = <&pic>; + interrupts = <17>; /* Bus error IRQ */ + clocks = <&pciclk>; + ranges = <0x01000000 0 0x00000000 0x60000000 0 0x01000000>, /* 16 MiB @ LB 60000000 */ + <0x02000000 0 0x40000000 0x40000000 0 0x10000000>, /* 256 MiB @ LB 40000000 1:1 */ + <0x42000000 0 0x50000000 0x50000000 0 0x10000000>; /* 256 MiB @ LB 50000000 1:1 */ + dma-ranges = <0x02000000 0 0x20000000 0x20000000 0 0x20000000>, /* EBI: 512 MB @ LB 20000000 1:1 */ + <0x02000000 0 0x80000000 0x80000000 0 0x40000000>; /* CM alias: 1GB @ LB 80000000 */ + interrupt-map-mask = <0xf800 0 0 0x7>; + interrupt-map = + /* IDSEL 9 */ + <0x4800 0 0 1 &pic 13>, /* INT A on slot 9 is irq 13 */ + <0x4800 0 0 2 &pic 14>, /* INT B on slot 9 is irq 14 */ + <0x4800 0 0 3 &pic 15>, /* INT C on slot 9 is irq 15 */ + <0x4800 0 0 4 &pic 16>, /* INT D on slot 9 is irq 16 */ + /* IDSEL 10 */ + <0x5000 0 0 1 &pic 14>, /* INT A on slot 10 is irq 14 */ + <0x5000 0 0 2 &pic 15>, /* INT B on slot 10 is irq 15 */ + <0x5000 0 0 3 &pic 16>, /* INT C on slot 10 is irq 16 */ + <0x5000 0 0 4 &pic 13>, /* INT D on slot 10 is irq 13 */ + /* IDSEL 11 */ + <0x5800 0 0 1 &pic 15>, /* INT A on slot 11 is irq 15 */ + <0x5800 0 0 2 &pic 16>, /* INT B on slot 11 is irq 16 */ + <0x5800 0 0 3 &pic 13>, /* INT C on slot 11 is irq 13 */ + <0x5800 0 0 4 &pic 14>, /* INT D on slot 11 is irq 14 */ + /* IDSEL 12 */ + <0x6000 0 0 1 &pic 16>, /* INT A on slot 12 is irq 16 */ + <0x6000 0 0 2 &pic 13>, /* INT B on slot 12 is irq 13 */ + <0x6000 0 0 3 &pic 14>, /* INT C on slot 12 is irq 14 */ + <0x6000 0 0 4 &pic 15>; /* INT D on slot 12 is irq 15 */ + }; +... diff --git a/Documentation/devicetree/bindings/pci/v3-v360epc-pci.txt b/Documentation/devicetree/bindings/pci/v3-v360epc-pci.txt deleted file mode 100644 index 11063293f761..000000000000 --- a/Documentation/devicetree/bindings/pci/v3-v360epc-pci.txt +++ /dev/null @@ -1,76 +0,0 @@ -V3 Semiconductor V360 EPC PCI bridge - -This bridge is found in the ARM Integrator/AP (Application Platform) - -Required properties: -- compatible: should be one of: - "v3,v360epc-pci" - "arm,integrator-ap-pci", "v3,v360epc-pci" -- reg: should contain two register areas: - first the base address of the V3 host bridge controller, 64KB - second the configuration area register space, 16MB -- interrupts: should contain a reference to the V3 error interrupt - as routed on the system. -- bus-range: see pci.txt -- ranges: this follows the standard PCI bindings in the IEEE Std - 1275-1994 (see pci.txt) with the following restriction: - - The non-prefetchable and prefetchable memory windows must - each be exactly 256MB (0x10000000) in size. - - The prefetchable memory window must be immediately adjacent - to the non-prefetcable memory window -- dma-ranges: three ranges for the inbound memory region. The ranges must - be aligned to a 1MB boundary, and may be 1MB, 2MB, 4MB, 8MB, 16MB, 32MB, - 64MB, 128MB, 256MB, 512MB, 1GB or 2GB in size. The memory should be marked - as pre-fetchable. Two ranges are supported by the hardware. - -Integrator-specific required properties: -- syscon: should contain a link to the syscon device node, since - on the Integrator, some registers in the syscon are required to - operate the V3 host bridge. - -Example: - -pci: pciv3@62000000 { - compatible = "arm,integrator-ap-pci", "v3,v360epc-pci"; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - reg = <0x62000000 0x10000>, <0x61000000 0x01000000>; - interrupt-parent = <&pic>; - interrupts = <17>; /* Bus error IRQ */ - clocks = <&pciclk>; - bus-range = <0x00 0xff>; - ranges = 0x01000000 0 0x00000000 /* I/O space @00000000 */ - 0x60000000 0 0x01000000 /* 16 MiB @ LB 60000000 */ - 0x02000000 0 0x40000000 /* non-prefectable memory @40000000 */ - 0x40000000 0 0x10000000 /* 256 MiB @ LB 40000000 1:1 */ - 0x42000000 0 0x50000000 /* prefetchable memory @50000000 */ - 0x50000000 0 0x10000000>; /* 256 MiB @ LB 50000000 1:1 */ - dma-ranges = <0x02000000 0 0x20000000 /* EBI memory space */ - 0x20000000 0 0x20000000 /* 512 MB @ LB 20000000 1:1 */ - 0x02000000 0 0x80000000 /* Core module alias memory */ - 0x80000000 0 0x40000000>; /* 1GB @ LB 80000000 */ - interrupt-map-mask = <0xf800 0 0 0x7>; - interrupt-map = < - /* IDSEL 9 */ - 0x4800 0 0 1 &pic 13 /* INT A on slot 9 is irq 13 */ - 0x4800 0 0 2 &pic 14 /* INT B on slot 9 is irq 14 */ - 0x4800 0 0 3 &pic 15 /* INT C on slot 9 is irq 15 */ - 0x4800 0 0 4 &pic 16 /* INT D on slot 9 is irq 16 */ - /* IDSEL 10 */ - 0x5000 0 0 1 &pic 14 /* INT A on slot 10 is irq 14 */ - 0x5000 0 0 2 &pic 15 /* INT B on slot 10 is irq 15 */ - 0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */ - 0x5000 0 0 4 &pic 13 /* INT D on slot 10 is irq 13 */ - /* IDSEL 11 */ - 0x5800 0 0 1 &pic 15 /* INT A on slot 11 is irq 15 */ - 0x5800 0 0 2 &pic 16 /* INT B on slot 11 is irq 16 */ - 0x5800 0 0 3 &pic 13 /* INT C on slot 11 is irq 13 */ - 0x5800 0 0 4 &pic 14 /* INT D on slot 11 is irq 14 */ - /* IDSEL 12 */ - 0x6000 0 0 1 &pic 16 /* INT A on slot 12 is irq 16 */ - 0x6000 0 0 2 &pic 13 /* INT B on slot 12 is irq 13 */ - 0x6000 0 0 3 &pic 14 /* INT C on slot 12 is irq 14 */ - 0x6000 0 0 4 &pic 15 /* INT D on slot 12 is irq 15 */ - >; -}; diff --git a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml index b63a759ec2d7..9823456addea 100644 --- a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml +++ b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml @@ -18,6 +18,7 @@ properties: - xlnx,versal-cpm-host-1.00 - xlnx,versal-cpm5-host - xlnx,versal-cpm5-host1 + - xlnx,versal-cpm5nc-host reg: items: @@ -75,64 +76,62 @@ unevaluatedProperties: false examples: - | - versal { - #address-cells = <2>; - #size-cells = <2>; - cpm_pcie: pcie@fca10000 { - compatible = "xlnx,versal-cpm-host-1.00"; - device_type = "pci"; - #address-cells = <3>; - #interrupt-cells = <1>; - #size-cells = <2>; - interrupts = <0 72 4>; - interrupt-parent = <&gic>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc_0 0>, - <0 0 0 2 &pcie_intc_0 1>, - <0 0 0 3 &pcie_intc_0 2>, - <0 0 0 4 &pcie_intc_0 3>; - bus-range = <0x00 0xff>; - ranges = <0x02000000 0x0 0xe0010000 0x0 0xe0010000 0x0 0x10000000>, - <0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>; - msi-map = <0x0 &its_gic 0x0 0x10000>; - reg = <0x0 0xfca10000 0x0 0x1000>, - <0x6 0x00000000 0x0 0x10000000>; - reg-names = "cpm_slcr", "cfg"; - pcie_intc_0: interrupt-controller { - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - }; - }; - - cpm5_pcie: pcie@fcdd0000 { - compatible = "xlnx,versal-cpm5-host"; - device_type = "pci"; - #address-cells = <3>; - #interrupt-cells = <1>; - #size-cells = <2>; - interrupts = <0 72 4>; - interrupt-parent = <&gic>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc_1 0>, - <0 0 0 2 &pcie_intc_1 1>, - <0 0 0 3 &pcie_intc_1 2>, - <0 0 0 4 &pcie_intc_1 3>; - bus-range = <0x00 0xff>; - ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>, - <0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>; - msi-map = <0x0 &its_gic 0x0 0x10000>; - reg = <0x00 0xfcdd0000 0x00 0x1000>, - <0x06 0x00000000 0x00 0x1000000>, - <0x00 0xfce20000 0x00 0x1000000>; - reg-names = "cpm_slcr", "cfg", "cpm_csr"; - - pcie_intc_1: interrupt-controller { - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - }; - }; - + #address-cells = <2>; + #size-cells = <2>; + pcie@fca10000 { + compatible = "xlnx,versal-cpm-host-1.00"; + device_type = "pci"; + #address-cells = <3>; + #interrupt-cells = <1>; + #size-cells = <2>; + interrupts = <0 72 4>; + interrupt-parent = <&gic>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc_0 0>, + <0 0 0 2 &pcie_intc_0 1>, + <0 0 0 3 &pcie_intc_0 2>, + <0 0 0 4 &pcie_intc_0 3>; + bus-range = <0x00 0xff>; + ranges = <0x02000000 0x0 0xe0010000 0x0 0xe0010000 0x0 0x10000000>, + <0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>; + msi-map = <0x0 &its_gic 0x0 0x10000>; + reg = <0x0 0xfca10000 0x0 0x1000>, + <0x6 0x00000000 0x0 0x10000000>; + reg-names = "cpm_slcr", "cfg"; + pcie_intc_0: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + pcie@fcdd0000 { + compatible = "xlnx,versal-cpm5-host"; + device_type = "pci"; + #address-cells = <3>; + #interrupt-cells = <1>; + #size-cells = <2>; + interrupts = <0 72 4>; + interrupt-parent = <&gic>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc_1 0>, + <0 0 0 2 &pcie_intc_1 1>, + <0 0 0 3 &pcie_intc_1 2>, + <0 0 0 4 &pcie_intc_1 3>; + bus-range = <0x00 0xff>; + ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>, + <0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>; + msi-map = <0x0 &its_gic 0x0 0x10000>; + reg = <0x00 0xfcdd0000 0x00 0x1000>, + <0x06 0x00000000 0x00 0x1000000>, + <0x00 0xfce20000 0x00 0x1000000>; + reg-names = "cpm_slcr", "cfg", "cpm_csr"; + + pcie_intc_1: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; }; diff --git a/Documentation/devicetree/bindings/phy/allwinner,sun50i-a64-usb-phy.yaml b/Documentation/devicetree/bindings/phy/allwinner,sun50i-a64-usb-phy.yaml index 21209126ed00..580c3296a18d 100644 --- a/Documentation/devicetree/bindings/phy/allwinner,sun50i-a64-usb-phy.yaml +++ b/Documentation/devicetree/bindings/phy/allwinner,sun50i-a64-usb-phy.yaml @@ -20,7 +20,9 @@ properties: - allwinner,sun20i-d1-usb-phy - allwinner,sun50i-a64-usb-phy - items: - - const: allwinner,sun50i-a100-usb-phy + - enum: + - allwinner,sun50i-a100-usb-phy + - allwinner,sun55i-a523-usb-phy - const: allwinner,sun20i-d1-usb-phy reg: diff --git a/Documentation/devicetree/bindings/phy/brcm,brcmstb-usb-phy.yaml b/Documentation/devicetree/bindings/phy/brcm,brcmstb-usb-phy.yaml index 580fbe37b37f..843d04027c30 100644 --- a/Documentation/devicetree/bindings/phy/brcm,brcmstb-usb-phy.yaml +++ b/Documentation/devicetree/bindings/phy/brcm,brcmstb-usb-phy.yaml @@ -18,6 +18,7 @@ properties: - brcm,bcm4908-usb-phy - brcm,bcm7211-usb-phy - brcm,bcm7216-usb-phy + - brcm,bcm74110-usb-phy - brcm,brcmstb-usb-phy reg: @@ -139,7 +140,9 @@ allOf: properties: compatible: contains: - const: brcm,bcm7216-usb-phy + enum: + - brcm,bcm7216-usb-phy + - brcm,bcm74110-usb-phy then: properties: reg: diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.yaml b/Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.yaml index daee0c0fc915..22dd91591a09 100644 --- a/Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.yaml +++ b/Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.yaml @@ -43,15 +43,15 @@ properties: fsl,phy-tx-vref-tune-percent: description: Tunes the HS DC level relative to the nominal level - minimum: 94 + minimum: 90 maximum: 124 fsl,phy-tx-rise-tune-percent: description: Adjusts the rise/fall time duration of the HS waveform relative to its nominal value - minimum: 97 - maximum: 103 + minimum: 90 + maximum: 120 fsl,phy-tx-preemp-amp-tune-microamp: description: @@ -63,8 +63,7 @@ properties: fsl,phy-tx-vboost-level-microvolt: description: Adjust the boosted transmit launch pk-pk differential amplitude - minimum: 880 - maximum: 1120 + enum: [844, 1008, 1156] fsl,phy-comp-dis-tune-percent: description: @@ -113,6 +112,34 @@ allOf: maxItems: 1 - if: + properties: + compatible: + enum: + - fsl,imx8mq-usb-phy + - fsl,imx8mp-usb-phy + then: + properties: + fsl,phy-tx-vref-tune-percent: + minimum: 94 + fsl,phy-tx-rise-tune-percent: + minimum: 97 + maximum: 103 + + - if: + properties: + compatible: + contains: + enum: + - fsl,imx95-usb-phy + then: + properties: + fsl,phy-tx-vref-tune-percent: + maximum: 108 + fsl,phy-comp-dis-tune-percent: + minimum: 94 + maximum: 104 + + - if: required: - orientation-switch then: diff --git a/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml index f6e494d0d89b..acdbce937b0a 100644 --- a/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml +++ b/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml @@ -30,6 +30,7 @@ properties: - const: mediatek,mt8173-mipi-tx - items: - enum: + - mediatek,mt6893-mipi-tx - mediatek,mt8188-mipi-tx - mediatek,mt8195-mipi-tx - mediatek,mt8365-mipi-tx diff --git a/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml index 6be3aa4557e5..b2218c151939 100644 --- a/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml +++ b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml @@ -78,6 +78,7 @@ properties: - items: - enum: - mediatek,mt2712-tphy + - mediatek,mt6893-tphy - mediatek,mt7629-tphy - mediatek,mt7986-tphy - mediatek,mt8183-tphy diff --git a/Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml b/Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml index a9e3139fd421..0bed847bb4ad 100644 --- a/Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml +++ b/Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml @@ -49,6 +49,7 @@ properties: - enum: - mediatek,mt3611-xsphy - mediatek,mt3612-xsphy + - mediatek,mt7988-xsphy - const: mediatek,xsphy reg: @@ -150,6 +151,21 @@ patternProperties: minimum: 1 maximum: 31 + mediatek,syscon-type: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + A phandle to syscon used to access the register of type switch, + the field should always be 3 cells long. + items: + - items: + - description: + Phandle to phy type configuration system controller + - description: + Phy type configuration register offset + - description: + Index of config segment + enum: [0, 1, 2, 3] + required: - reg - clocks diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml index 15dc8efe6ffe..9af39b33646a 100644 --- a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml +++ b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml @@ -99,8 +99,7 @@ patternProperties: Specifies the type of PHY for which the group of PHY lanes is used. Refer include/dt-bindings/phy/phy.h. Constants from the header should be used. $ref: /schemas/types.yaml#/definitions/uint32 - minimum: 1 - maximum: 9 + enum: [1, 2, 3, 4, 5, 6, 7, 8, 9, 12] cdns,num-lanes: description: diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml b/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml index 1b3de6678c08..3e101c3c5ea9 100644 --- a/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml +++ b/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml @@ -12,6 +12,7 @@ maintainers: properties: compatible: enum: + - rockchip,rk3562-naneng-combphy - rockchip,rk3568-naneng-combphy - rockchip,rk3576-naneng-combphy - rockchip,rk3588-naneng-combphy @@ -41,6 +42,9 @@ properties: - const: phy - const: apb + phy-supply: + description: Single PHY regulator + rockchip,enable-ssc: type: boolean description: diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt b/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt deleted file mode 100644 index 960da7fcaa9e..000000000000 --- a/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt +++ /dev/null @@ -1,84 +0,0 @@ -* ROCKCHIP type-c PHY ---------------------- - -Required properties: - - compatible : must be "rockchip,rk3399-typec-phy" - - reg: Address and length of the usb phy control register set - - rockchip,grf : phandle to the syscon managing the "general - register files" - - clocks : phandle + clock specifier for the phy clocks - - clock-names : string, clock name, must be "tcpdcore", "tcpdphy-ref"; - - assigned-clocks: main clock, should be <&cru SCLK_UPHY0_TCPDCORE> or - <&cru SCLK_UPHY1_TCPDCORE>; - - assigned-clock-rates : the phy core clk frequency, shall be: 50000000 - - resets : a list of phandle + reset specifier pairs - - reset-names : string reset name, must be: - "uphy", "uphy-pipe", "uphy-tcphy" - -Optional properties: - - extcon : extcon specifier for the Power Delivery - -Required nodes : a sub-node is required for each port the phy provides. - The sub-node name is used to identify dp or usb3 port, - and shall be the following entries: - * "dp-port" : the name of DP port. - * "usb3-port" : the name of USB3 port. - -Required properties (port (child) node): -- #phy-cells : must be 0, See ./phy-bindings.txt for details. - -Deprecated properties, do not use in new device tree sources, these -properties are determined by the compatible value: - - rockchip,typec-conn-dir - - rockchip,usb3tousb2-en - - rockchip,external-psm - - rockchip,pipe-status - -Example: - tcphy0: phy@ff7c0000 { - compatible = "rockchip,rk3399-typec-phy"; - reg = <0x0 0xff7c0000 0x0 0x40000>; - rockchip,grf = <&grf>; - extcon = <&fusb0>; - clocks = <&cru SCLK_UPHY0_TCPDCORE>, - <&cru SCLK_UPHY0_TCPDPHY_REF>; - clock-names = "tcpdcore", "tcpdphy-ref"; - assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>; - assigned-clock-rates = <50000000>; - resets = <&cru SRST_UPHY0>, - <&cru SRST_UPHY0_PIPE_L00>, - <&cru SRST_P_UPHY0_TCPHY>; - reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; - - tcphy0_dp: dp-port { - #phy-cells = <0>; - }; - - tcphy0_usb3: usb3-port { - #phy-cells = <0>; - }; - }; - - tcphy1: phy@ff800000 { - compatible = "rockchip,rk3399-typec-phy"; - reg = <0x0 0xff800000 0x0 0x40000>; - rockchip,grf = <&grf>; - extcon = <&fusb1>; - clocks = <&cru SCLK_UPHY1_TCPDCORE>, - <&cru SCLK_UPHY1_TCPDPHY_REF>; - clock-names = "tcpdcore", "tcpdphy-ref"; - assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>; - assigned-clock-rates = <50000000>; - resets = <&cru SRST_UPHY1>, - <&cru SRST_UPHY1_PIPE_L00>, - <&cru SRST_P_UPHY1_TCPHY>; - reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; - - tcphy1_dp: dp-port { - #phy-cells = <0>; - }; - - tcphy1_usb3: usb3-port { - #phy-cells = <0>; - }; - }; diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml b/Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml index b42f1272903d..8b7059d5b182 100644 --- a/Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml +++ b/Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml @@ -47,6 +47,9 @@ properties: - const: pcs_apb - const: pma_apb + phy-supply: + description: Single PHY regulator + rockchip,dp-lane-mux: $ref: /schemas/types.yaml#/definitions/uint32-array minItems: 2 diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml new file mode 100644 index 000000000000..6e9df81441e9 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml @@ -0,0 +1,109 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/qcom,ipq5332-uniphy-pcie-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm UNIPHY PCIe 28LP PHY + +maintainers: + - Nitheesh Sekar <quic_nsekar@quicinc.com> + - Varadarajan Narayanan <quic_varada@quicinc.com> + +description: + PCIe and USB combo PHY found in Qualcomm IPQ5018 & IPQ5332 SoCs + +properties: + compatible: + enum: + - qcom,ipq5018-uniphy-pcie-phy + - qcom,ipq5332-uniphy-pcie-phy + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 2 + + resets: + minItems: 2 + maxItems: 3 + + "#phy-cells": + const: 0 + + "#clock-cells": + const: 0 + + num-lanes: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2] + +required: + - compatible + - reg + - clocks + - resets + - "#phy-cells" + - "#clock-cells" + - num-lanes + +additionalProperties: false + +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq5018-uniphy-pcie-phy + then: + properties: + clocks: + items: + - description: pcie pipe clock + resets: + items: + - description: phy reset + - description: cfg reset + + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq5332-uniphy-pcie-phy + then: + properties: + clocks: + items: + - description: pcie pipe clock + - description: pcie ahb clock + resets: + items: + - description: phy reset + - description: ahb reset + - description: cfg reset + +examples: + - | + #include <dt-bindings/clock/qcom,ipq5332-gcc.h> + + pcie0_phy: phy@4b0000 { + compatible = "qcom,ipq5332-uniphy-pcie-phy"; + reg = <0x004b0000 0x800>; + + clocks = <&gcc GCC_PCIE3X1_0_PIPE_CLK>, + <&gcc GCC_PCIE3X1_PHY_AHB_CLK>; + + resets = <&gcc GCC_PCIE3X1_0_PHY_BCR>, + <&gcc GCC_PCIE3X1_PHY_AHB_CLK_ARES>, + <&gcc GCC_PCIE3X1_0_PHY_PHY_BCR>; + + #clock-cells = <0>; + + #phy-cells = <0>; + + num-lanes = <1>; + }; diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml index 89391649e0b5..2c6c9296e4c0 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml @@ -17,6 +17,7 @@ properties: compatible: enum: - qcom,qcs615-qmp-gen3x1-pcie-phy + - qcom,qcs8300-qmp-gen4x2-pcie-phy - qcom,sa8775p-qmp-gen4x2-pcie-phy - qcom,sa8775p-qmp-gen4x4-pcie-phy - qcom,sar2130p-qmp-gen3x2-pcie-phy @@ -45,6 +46,7 @@ properties: - qcom,x1e80100-qmp-gen4x2-pcie-phy - qcom,x1e80100-qmp-gen4x4-pcie-phy - qcom,x1e80100-qmp-gen4x8-pcie-phy + - qcom,x1p42100-qmp-gen4x4-pcie-phy reg: minItems: 1 @@ -124,6 +126,7 @@ allOf: enum: - qcom,sc8280xp-qmp-gen3x4-pcie-phy - qcom,x1e80100-qmp-gen4x4-pcie-phy + - qcom,x1p42100-qmp-gen4x4-pcie-phy then: properties: reg: @@ -180,6 +183,7 @@ allOf: - qcom,x1e80100-qmp-gen4x2-pcie-phy - qcom,x1e80100-qmp-gen4x4-pcie-phy - qcom,x1e80100-qmp-gen4x8-pcie-phy + - qcom,x1p42100-qmp-gen4x4-pcie-phy then: properties: clocks: @@ -192,6 +196,7 @@ allOf: compatible: contains: enum: + - qcom,qcs8300-qmp-gen4x2-pcie-phy - qcom,sa8775p-qmp-gen4x2-pcie-phy - qcom,sa8775p-qmp-gen4x4-pcie-phy then: @@ -217,12 +222,6 @@ allOf: minItems: 2 reset-names: minItems: 2 - else: - properties: - resets: - maxItems: 1 - reset-names: - maxItems: 1 - if: properties: diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml index 72bed2933b03..a58370a6a5d3 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml @@ -44,6 +44,7 @@ properties: - qcom,sm8475-qmp-ufs-phy - qcom,sm8550-qmp-ufs-phy - qcom,sm8650-qmp-ufs-phy + - qcom,sm8750-qmp-ufs-phy reg: maxItems: 1 @@ -111,6 +112,7 @@ allOf: - qcom,sm8475-qmp-ufs-phy - qcom,sm8550-qmp-ufs-phy - qcom,sm8650-qmp-ufs-phy + - qcom,sm8750-qmp-ufs-phy then: properties: clocks: diff --git a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml index af275cea3456..2822dce8d9f4 100644 --- a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml +++ b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml @@ -16,6 +16,7 @@ properties: - enum: - renesas,usb2-phy-r8a77470 # RZ/G1C - renesas,usb2-phy-r9a08g045 # RZ/G3S + - renesas,usb2-phy-r9a09g057 # RZ/V2H(P) - items: - enum: @@ -105,8 +106,13 @@ allOf: properties: compatible: contains: - const: renesas,rzg2l-usb2-phy + enum: + - renesas,usb2-phy-r9a09g057 + - renesas,rzg2l-usb2-phy then: + properties: + clocks: + minItems: 2 required: - resets diff --git a/Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml b/Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml index 6a7ef556414c..58e735b5dd05 100644 --- a/Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml +++ b/Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml @@ -13,12 +13,14 @@ properties: compatible: enum: - rockchip,px30-usb2phy + - rockchip,rk3036-usb2phy - rockchip,rk3128-usb2phy - rockchip,rk3228-usb2phy - rockchip,rk3308-usb2phy - rockchip,rk3328-usb2phy - rockchip,rk3366-usb2phy - rockchip,rk3399-usb2phy + - rockchip,rk3562-usb2phy - rockchip,rk3568-usb2phy - rockchip,rk3576-usb2phy - rockchip,rk3588-usb2phy @@ -184,12 +186,14 @@ allOf: contains: enum: - rockchip,px30-usb2phy + - rockchip,rk3036-usb2phy - rockchip,rk3128-usb2phy - rockchip,rk3228-usb2phy - rockchip,rk3308-usb2phy - rockchip,rk3328-usb2phy - rockchip,rk3366-usb2phy - rockchip,rk3399-usb2phy + - rockchip,rk3562-usb2phy - rockchip,rk3568-usb2phy - rockchip,rk3588-usb2phy - rockchip,rv1108-usb2phy diff --git a/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml index ba67dca5a446..d7de8b527c5c 100644 --- a/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml +++ b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml @@ -46,6 +46,9 @@ properties: reset-names: const: phy + phy-supply: + description: Single PHY regulator + rockchip,phy-grf: $ref: /schemas/types.yaml#/definitions/phandle description: phandle to the syscon managing the phy "general register files" diff --git a/Documentation/devicetree/bindings/phy/rockchip,rk3399-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/rockchip,rk3399-pcie-phy.yaml new file mode 100644 index 000000000000..f46f065e5dbe --- /dev/null +++ b/Documentation/devicetree/bindings/phy/rockchip,rk3399-pcie-phy.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/rockchip,rk3399-pcie-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip RK3399 PCIE PHY + +maintainers: + - Heiko Stuebner <heiko@sntech.de> + +properties: + compatible: + const: rockchip,rk3399-pcie-phy + + '#phy-cells': + oneOf: + - const: 0 + deprecated: true + - const: 1 + description: One lane per phy mode + + clocks: + maxItems: 1 + + clock-names: + const: refclk + + resets: + maxItems: 1 + + reset-names: + const: phy + +required: + - compatible + - '#phy-cells' + - clocks + - clock-names + - resets + - reset-names + +additionalProperties: false + +... diff --git a/Documentation/devicetree/bindings/phy/rockchip,rk3399-typec-phy.yaml b/Documentation/devicetree/bindings/phy/rockchip,rk3399-typec-phy.yaml new file mode 100644 index 000000000000..91c011f68cd0 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/rockchip,rk3399-typec-phy.yaml @@ -0,0 +1,116 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/rockchip,rk3399-typec-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip Type-C PHY + +maintainers: + - Heiko Stuebner <heiko@sntech.de> + +properties: + compatible: + const: rockchip,rk3399-typec-phy + + reg: + maxItems: 1 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: tcpdcore + - const: tcpdphy-ref + + extcon: true + + power-domains: + maxItems: 1 + + resets: + maxItems: 3 + + reset-names: + items: + - const: uphy + - const: uphy-pipe + - const: uphy-tcphy + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the syscon managing the "general register files" (GRF). + + dp-port: + type: object + additionalProperties: false + + properties: + '#phy-cells': + const: 0 + + port: + $ref: /schemas/graph.yaml#/properties/port + description: Connection to USB Type-C connector + + required: + - '#phy-cells' + + usb3-port: + type: object + additionalProperties: false + + properties: + '#phy-cells': + const: 0 + + orientation-switch: true + + port: + $ref: /schemas/graph.yaml#/properties/port + description: Connection to USB Type-C connector SS port + + required: + - '#phy-cells' + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - reset-names + - dp-port + - usb3-port + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/rk3399-cru.h> + + phy@ff7c0000 { + compatible = "rockchip,rk3399-typec-phy"; + reg = <0xff7c0000 0x40000>; + rockchip,grf = <&grf>; + extcon = <&fusb0>; + clocks = <&cru SCLK_UPHY0_TCPDCORE>, + <&cru SCLK_UPHY0_TCPDPHY_REF>; + clock-names = "tcpdcore", "tcpdphy-ref"; + resets = <&cru SRST_UPHY0>, + <&cru SRST_UPHY0_PIPE_L00>, + <&cru SRST_P_UPHY0_TCPHY>; + reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; + + dp-port { + #phy-cells = <0>; + }; + + usb3-port { + #phy-cells = <0>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/phy/rockchip,rk3588-hdptx-phy.yaml b/Documentation/devicetree/bindings/phy/rockchip,rk3588-hdptx-phy.yaml index 84fe59dbcf48..7a307f45cdec 100644 --- a/Documentation/devicetree/bindings/phy/rockchip,rk3588-hdptx-phy.yaml +++ b/Documentation/devicetree/bindings/phy/rockchip,rk3588-hdptx-phy.yaml @@ -11,8 +11,13 @@ maintainers: properties: compatible: - enum: - - rockchip,rk3588-hdptx-phy + oneOf: + - enum: + - rockchip,rk3588-hdptx-phy + - items: + - enum: + - rockchip,rk3576-hdptx-phy + - const: rockchip,rk3588-hdptx-phy reg: maxItems: 1 @@ -34,24 +39,12 @@ properties: const: 0 resets: - items: - - description: PHY reset line - - description: APB reset line - - description: INIT reset line - - description: CMN reset line - - description: LANE reset line - - description: ROPLL reset line - - description: LCPLL reset line + minItems: 4 + maxItems: 7 reset-names: - items: - - const: phy - - const: apb - - const: init - - const: cmn - - const: lane - - const: ropll - - const: lcpll + minItems: 4 + maxItems: 7 rockchip,grf: $ref: /schemas/types.yaml#/definitions/phandle @@ -67,6 +60,39 @@ required: - reset-names - rockchip,grf +allOf: + - if: + properties: + compatible: + contains: + enum: + - rockchip,rk3576-hdptx-phy + then: + properties: + resets: + minItems: 4 + maxItems: 4 + reset-names: + items: + - const: apb + - const: init + - const: cmn + - const: lane + else: + properties: + resets: + minItems: 7 + maxItems: 7 + reset-names: + items: + - const: phy + - const: apb + - const: init + - const: cmn + - const: lane + - const: ropll + - const: lcpll + additionalProperties: false examples: diff --git a/Documentation/devicetree/bindings/phy/rockchip,rk3588-mipi-dcphy.yaml b/Documentation/devicetree/bindings/phy/rockchip,rk3588-mipi-dcphy.yaml new file mode 100644 index 000000000000..c8ff5ba22a86 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/rockchip,rk3588-mipi-dcphy.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/rockchip,rk3588-mipi-dcphy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip MIPI D-/C-PHY with Samsung IP block + +maintainers: + - Guochun Huang <hero.huang@rock-chips.com> + - Heiko Stuebner <heiko@sntech.de> + +properties: + compatible: + enum: + - rockchip,rk3576-mipi-dcphy + - rockchip,rk3588-mipi-dcphy + + reg: + maxItems: 1 + + "#phy-cells": + const: 1 + description: | + Argument is mode to operate in. Supported modes are: + - PHY_TYPE_DPHY + - PHY_TYPE_CPHY + See include/dt-bindings/phy/phy.h for constants. + + clocks: + maxItems: 2 + + clock-names: + items: + - const: pclk + - const: ref + + resets: + maxItems: 4 + + reset-names: + items: + - const: m_phy + - const: apb + - const: grf + - const: s_phy + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the syscon managing the 'mipi dcphy general register files'. + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - reset-names + - "#phy-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/rockchip,rk3588-cru.h> + #include <dt-bindings/reset/rockchip,rk3588-cru.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + phy@feda0000 { + compatible = "rockchip,rk3588-mipi-dcphy"; + reg = <0x0 0xfeda0000 0x0 0x10000>; + clocks = <&cru PCLK_MIPI_DCPHY0>, + <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>; + clock-names = "pclk", "ref"; + resets = <&cru SRST_M_MIPI_DCPHY0>, + <&cru SRST_P_MIPI_DCPHY0>, + <&cru SRST_P_MIPI_DCPHY0_GRF>, + <&cru SRST_S_MIPI_DCPHY0>; + reset-names = "m_phy", "apb", "grf", "s_phy"; + rockchip,grf = <&mipidcphy0_grf>; + #phy-cells = <1>; + }; + }; diff --git a/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt deleted file mode 100644 index b496042f1f44..000000000000 --- a/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt +++ /dev/null @@ -1,36 +0,0 @@ -Rockchip PCIE PHY ------------------------ - -Required properties: - - compatible: rockchip,rk3399-pcie-phy - - clocks: Must contain an entry in clock-names. - See ../clocks/clock-bindings.txt for details. - - clock-names: Must be "refclk" - - resets: Must contain an entry in reset-names. - See ../reset/reset.txt for details. - - reset-names: Must be "phy" - -Required properties for legacy PHY mode (deprecated): - - #phy-cells: must be 0 - -Required properties for per-lane PHY mode (preferred): - - #phy-cells: must be 1 - -Example: - -grf: syscon@ff770000 { - compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; - #address-cells = <1>; - #size-cells = <1>; - - ... - - pcie_phy: pcie-phy { - compatible = "rockchip,rk3399-pcie-phy"; - #phy-cells = <0>; - clocks = <&cru SCLK_PCIEPHY_REF>; - clock-names = "refclk"; - resets = <&cru SRST_PCIEPHY>; - reset-names = "phy"; - }; -}; diff --git a/Documentation/devicetree/bindings/phy/samsung,exynos2200-eusb2-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,exynos2200-eusb2-phy.yaml new file mode 100644 index 000000000000..5e7e1bc2e39a --- /dev/null +++ b/Documentation/devicetree/bindings/phy/samsung,exynos2200-eusb2-phy.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/samsung,exynos2200-eusb2-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos2200 eUSB2 phy controller + +maintainers: + - Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> + +description: + Samsung Exynos2200 eUSB2 phy, based on Synopsys eUSB2 IP block, supports + LS/FS/HS usb connectivity. + +properties: + compatible: + enum: + - samsung,exynos2200-eusb2-phy + + reg: + maxItems: 1 + + "#phy-cells": + const: 0 + + clocks: + items: + - description: Reference clock + - description: Bus (APB) clock + - description: Control clock + + clock-names: + items: + - const: ref + - const: bus + - const: ctrl + + resets: + maxItems: 1 + + phys: + maxItems: 1 + description: + Phandle to eUSB2 to USB 2.0 repeater + + vdd-supply: + description: + Phandle to 0.88V regulator supply to PHY digital circuit. + + vdda12-supply: + description: + Phandle to 1.2V regulator supply to PHY refclk pll block. + +required: + - compatible + - reg + - "#phy-cells" + - clocks + - clock-names + - vdd-supply + - vdda12-supply + +additionalProperties: false + +examples: + - | + usb_hsphy: phy@10ab0000 { + compatible = "samsung,exynos2200-eusb2-phy"; + reg = <0x10ab0000 0x10000>; + #phy-cells = <0>; + + clocks = <&cmu_hsi0 7>, + <&cmu_hsi0 5>, + <&cmu_hsi0 8>; + clock-names = "ref", "bus", "ctrl"; + + vdd-supply = <&vreg_0p88>; + vdda12-supply = <&vreg_1p2>; + }; diff --git a/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml index f402e31bf58d..d70ffeb6e824 100644 --- a/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml +++ b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml @@ -18,6 +18,7 @@ properties: - google,gs101-ufs-phy - samsung,exynos7-ufs-phy - samsung,exynosautov9-ufs-phy + - samsung,exynosautov920-ufs-phy - tesla,fsd-ufs-phy reg: diff --git a/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml index 16321cdd4919..cc60d2f6f70e 100644 --- a/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml +++ b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml @@ -26,31 +26,41 @@ properties: compatible: enum: - google,gs101-usb31drd-phy + - samsung,exynos2200-usb32drd-phy - samsung,exynos5250-usbdrd-phy - samsung,exynos5420-usbdrd-phy - samsung,exynos5433-usbdrd-phy - samsung,exynos7-usbdrd-phy + - samsung,exynos7870-usbdrd-phy - samsung,exynos850-usbdrd-phy clocks: - minItems: 2 + minItems: 1 maxItems: 5 clock-names: - minItems: 2 + minItems: 1 maxItems: 5 description: | - At least two clocks:: + Typically two clocks: - Main PHY clock (same as USB DRD controller i.e. DWC3 IP clock), used for register access. - PHY reference clock (usually crystal clock), used for PHY operations, associated by phy name. It is used to determine bit values for clock settings register. For Exynos5420 this is given as 'sclk_usbphy30' - in the CMU. + in the CMU. It's not needed for Exynos2200. "#phy-cells": const: 1 + phys: + maxItems: 1 + description: + USBDRD-underlying high-speed PHY + + phy-names: + const: hs + port: $ref: /schemas/graph.yaml#/properties/port description: @@ -83,14 +93,19 @@ properties: pll-supply: description: Power supply for the USB PLL. + dvdd-usb20-supply: description: DVDD power supply for the USB 2.0 phy. + vddh-usb20-supply: description: VDDh power supply for the USB 2.0 phy. + vdd33-usb20-supply: description: 3.3V power supply for the USB 2.0 phy. + vdda-usbdp-supply: description: VDDa power supply for the USB DP phy. + vddh-usbdp-supply: description: VDDh power supply for the USB DP phy. @@ -109,6 +124,8 @@ allOf: contains: const: google,gs101-usb31drd-phy then: + $ref: /schemas/usb/usb-switch.yaml# + properties: clocks: items: @@ -117,6 +134,7 @@ allOf: - description: Gate of control interface AXI clock - description: Gate of control interface APB clock - description: Gate of SCL APB clock + clock-names: items: - const: phy @@ -124,12 +142,17 @@ allOf: - const: ctrl_aclk - const: ctrl_pclk - const: scl_pclk + reg: minItems: 3 + reg-names: minItems: 3 + required: - reg-names + - orientation-switch + - port - pll-supply - dvdd-usb20-supply - vddh-usb20-supply @@ -142,6 +165,27 @@ allOf: compatible: contains: enum: + - samsung,exynos2200-usb32drd-phy + then: + properties: + clocks: + maxItems: 1 + clock-names: + items: + - const: phy + reg: + maxItems: 1 + reg-names: + maxItems: 1 + required: + - phys + - phy-names + + - if: + properties: + compatible: + contains: + enum: - samsung,exynos5433-usbdrd-phy - samsung,exynos7-usbdrd-phy then: @@ -149,6 +193,7 @@ allOf: clocks: minItems: 5 maxItems: 5 + clock-names: items: - const: phy @@ -156,8 +201,10 @@ allOf: - const: phy_utmi - const: phy_pipe - const: itp + reg: maxItems: 1 + reg-names: maxItems: 1 @@ -168,22 +215,26 @@ allOf: enum: - samsung,exynos5250-usbdrd-phy - samsung,exynos5420-usbdrd-phy + - samsung,exynos7870-usbdrd-phy - samsung,exynos850-usbdrd-phy then: properties: clocks: minItems: 2 maxItems: 2 + clock-names: items: - const: phy - const: ref + reg: maxItems: 1 + reg-names: maxItems: 1 -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml index b2601d698dcd..21fd4f1ba78b 100644 --- a/Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml @@ -24,6 +24,9 @@ properties: '#gpio-cells': const: 2 + gpio-ranges: + maxItems: 1 + interrupt-controller: true '#interrupt-cells': diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sun55i-a523-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/allwinner,sun55i-a523-pinctrl.yaml new file mode 100644 index 000000000000..154e03da8ce9 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sun55i-a523-pinctrl.yaml @@ -0,0 +1,175 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/allwinner,sun55i-a523-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A523 Pin Controller + +maintainers: + - Andre Przywara <andre.przywara@arm.com> + +properties: + "#gpio-cells": + const: 3 + description: + GPIO consumers must use three arguments, first the number of the + bank, then the pin number inside that bank, and finally the GPIO + flags. + + "#interrupt-cells": + const: 3 + description: + Interrupts consumers must use three arguments, first the number + of the bank, then the pin number inside that bank, and finally + the interrupts flags. + + compatible: + enum: + - allwinner,sun55i-a523-pinctrl + - allwinner,sun55i-a523-r-pinctrl + + reg: + maxItems: 1 + + interrupts: + minItems: 2 + maxItems: 10 + description: + One interrupt per external interrupt bank supported on the + controller, sorted by bank number ascending order. + + clocks: + items: + - description: Bus Clock + - description: High Frequency Oscillator + - description: Low Frequency Oscillator + + clock-names: + items: + - const: apb + - const: hosc + - const: losc + + gpio-controller: true + interrupt-controller: true + gpio-line-names: true + + input-debounce: + description: + Debouncing periods in microseconds, one period per interrupt + bank found in the controller + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 2 + maxItems: 10 + +patternProperties: + # It's pretty scary, but the basic idea is that: + # - One node name can start with either s- or r- for PRCM nodes, + # - Then, the name itself can be any repetition of <string>- (to + # accommodate with nodes like uart4-rts-cts-pins), where each + # string can be either starting with 'p' but in a string longer + # than 3, or something that doesn't start with 'p', + # - Then, the bank name is optional and will be between pa and pm. + # Some pins groups that have several options will have the pin + # numbers then, + # - Finally, the name will end with either -pin or pins. + + "^([rs]-)?(([a-z0-9]{3,}|[a-oq-z][a-z0-9]*?)?-)+?(p[a-m][0-9]*?-)??pins?$": + type: object + + properties: + pins: true + function: true + bias-disable: true + bias-pull-up: true + bias-pull-down: true + + drive-strength: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [10, 20, 30, 40] + + allwinner,pinmux: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + Pinmux selector value, for each pin. Almost every time this value + is the same for all pins, so any array shorter than the number of + pins will repeat the last value, to allow just specifying a single + cell, for all cells. + + required: + - pins + - allwinner,pinmux + - function + + additionalProperties: false + + "^vcc-p[a-m]-supply$": + description: + Power supplies for pin banks. + +required: + - "#gpio-cells" + - compatible + - reg + - clocks + - clock-names + - gpio-controller + - "#interrupt-cells" + - interrupts + - interrupt-controller + +allOf: + - $ref: pinctrl.yaml# + - if: + properties: + compatible: + enum: + - allwinner,sun55i-a523-pinctrl + + then: + properties: + interrupts: + minItems: 10 + maxItems: 10 + + - if: + properties: + compatible: + enum: + - allwinner,sun55i-a523-r-pinctrl + + then: + properties: + interrupts: + minItems: 2 + maxItems: 2 + +additionalProperties: false + +examples: + - | + r_pio: pinctrl@7022000 { + compatible = "allwinner,sun55i-a523-r-pinctrl"; + reg = <0x7022000 0x800>; + interrupts = <0 159 4>, <0 161 4>; + clocks = <&r_ccu 1>, <&osc24M>, <&osc32k>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + #gpio-cells = <3>; + interrupt-controller; + #interrupt-cells = <3>; + + r_i2c_pins: r-i2c-pins { + pins = "PL0", "PL1"; + allwinner,pinmux = <2>; + function = "r_i2c0"; + bias-pull-up; + }; + + r_spi_pins: r-spi-pins { + pins = "PL11" ,"PL12", "PL13"; + allwinner,pinmux = <6>; + function = "r_spi"; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml b/Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml new file mode 100644 index 000000000000..a6ef4797e5c5 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml @@ -0,0 +1,132 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/amlogic,pinctrl-a4.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic pinmux controller + +maintainers: + - Xianwei Zhao <xianwei.zhao@amlogic.com> + +allOf: + - $ref: pinctrl.yaml# + +properties: + compatible: + oneOf: + - const: amlogic,pinctrl-a4 + - items: + - enum: + - amlogic,pinctrl-a5 + - const: amlogic,pinctrl-a4 + + "#address-cells": + const: 2 + + "#size-cells": + const: 2 + + ranges: true + +patternProperties: + "^gpio@[0-9a-f]+$": + type: object + + additionalProperties: false + properties: + reg: + minItems: 1 + items: + - description: pin config register + - description: pin mux setting register (some special pin fixed function) + - description: pin drive strength register (optional) + + reg-names: + minItems: 1 + items: + - const: gpio + - const: mux + - const: ds + + gpio-controller: true + + "#gpio-cells": + const: 2 + + gpio-ranges: + maxItems: 1 + + required: + - reg + - reg-names + - gpio-controller + - "#gpio-cells" + - gpio-ranges + + "^func-[0-9a-z-]+$": + type: object + additionalProperties: false + patternProperties: + "^group-[0-9a-z-]+$": + type: object + unevaluatedProperties: false + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml + - $ref: /schemas/pinctrl/pinmux-node.yaml + + required: + - pinmux + +required: + - compatible + - "#address-cells" + - "#size-cells" + - ranges + +additionalProperties: false + +examples: + - | + #include <dt-bindings/pinctrl/amlogic,pinctrl.h> + apb { + #address-cells = <2>; + #size-cells = <2>; + periphs_pinctrl: pinctrl { + compatible = "amlogic,pinctrl-a4"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio@4240 { + reg = <0 0x4240 0 0x40>, <0 0x4000 0 0x8>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 8 10>; + }; + + func-uart-b { + group-default { + pinmux = <AML_PINMUX(AMLOGIC_GPIO_B, 1, 4)>; + bias-pull-up; + drive-strength-microamp = <4000>; + }; + + group-pins1 { + pinmux = <AML_PINMUX(AMLOGIC_GPIO_B, 5, 2)>; + bias-pull-up; + drive-strength-microamp = <4000>; + }; + }; + + func-uart-c { + group-default { + pinmux = <AML_PINMUX(AMLOGIC_GPIO_B, 3, 1)>, + <AML_PINMUX(AMLOGIC_GPIO_B, 2, 1)>; + bias-pull-up; + drive-strength-microamp = <4000>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pio4-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pio4-pinctrl.txt index 774c3c269c40..81a05a09f19f 100644 --- a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pio4-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pio4-pinctrl.txt @@ -6,6 +6,7 @@ configure it. Required properties: - compatible: "atmel,sama5d2-pinctrl" + "microchip,sama7d65-pinctrl", "microchip,sama7g5-pinctrl" "microchip,sama7g5-pinctrl" - reg: base address and length of the PIO controller. - interrupts: interrupt outputs from the controller, one for each bank. diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,bcm21664-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/brcm,bcm21664-pinctrl.yaml new file mode 100644 index 000000000000..1283a588416d --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm21664-pinctrl.yaml @@ -0,0 +1,152 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/brcm,bcm21664-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom BCM21664 pin controller + +maintainers: + - Florian Fainelli <florian.fainelli@broadcom.com> + - Ray Jui <rjui@broadcom.com> + - Scott Branden <sbranden@broadcom.com> + +allOf: + - $ref: pinctrl.yaml# + +properties: + compatible: + const: brcm,bcm21664-pinctrl + + reg: + maxItems: 1 + +patternProperties: + '-pins$': + type: object + additionalProperties: false + + patternProperties: + '-grp[0-9]$': + type: object + + properties: + pins: + description: + Specifies the name(s) of one or more pins to be configured by + this node. + items: + enum: [ adcsyn, batrm, bsc1clk, bsc1dat, camcs0, camcs1, clk32k, + clk_cx8, dclk1, dclk4, dclkreq1, dclkreq4, dmic0clk, + dmic0dq, dsi0te, gpio00, gpio01, gpio02, gpio03, gpio04, + gpio05, gpio06, gpio07, gpio08, gpio09, gpio10, gpio11, + gpio12, gpio13, gpio14, gpio15, gpio16, gpio17, gpio18, + gpio19, gpio20, gpio21, gpio22, gpio23, gpio24, gpio25, + gpio26, gpio27, gpio28, gpio32, gpio33, gpio34, gpio93, + gpio94, gps_calreq, gps_hostreq, gps_pablank, gps_tmark, + icusbdm, icusbdp, lcdcs0, lcdres, lcdscl, lcdsda, lcdte, + mdmgpio00, mdmgpio01, mdmgpio02, mdmgpio03, mdmgpio04, + mdmgpio05, mdmgpio06, mdmgpio07, mdmgpio08, mmc0ck, + mmc0cmd, mmc0dat0, mmc0dat1, mmc0dat2, mmc0dat3, mmc0dat4, + mmc0dat5, mmc0dat6, mmc0dat7, mmc0rst, mmc1ck, mmc1cmd, + mmc1dat0, mmc1dat1, mmc1dat2, mmc1dat3, mmc1dat4, + mmc1dat5, mmc1dat6, mmc1dat7, mmc1rst, pc1, pc2, pmbscclk, + pmbscdat, pmuint, resetn, rfst2g_mtsloten3g, + rtxdata2g_txdata3g1, rtxen2g_txdata3g2, rxdata3g0, + rxdata3g1, rxdata3g2, sdck, sdcmd, sddat0, sddat1, sddat2, + sddat3, simclk, simdat, simdet, simrst, spi0clk, spi0fss, + spi0rxd, spi0txd, sri_c, sri_d, sri_e, sspck, sspdi, + sspdo, sspsyn, stat1, stat2, swclktck, swdiotms, sysclken, + tdi, tdo, testmode, traceclk, tracedt00, tracedt01, + tracedt02, tracedt03, tracedt04, tracedt05, tracedt06, + tracedt07, tracedt08, tracedt09, tracedt10, tracedt11, + tracedt12, tracedt13, tracedt14, tracedt15, trstb, + txdata3g0, ubctsn, ubrtsn, ubrx, ubtx ] + + function: + description: + Specifies the pin mux selection. + enum: [ alt1, alt2, alt3, alt4, alt5, alt6 ] + + bias-disable: true + + bias-pull-up: + type: boolean + + bias-pull-down: + type: boolean + + slew-rate: + description: | + Meaning depends on configured pin mux: + bsc*clk/pmbscclk or bsc*dat/pmbscdat or gpio16/gpio17: + 0: Standard (100 kbps) & Fast (400 kbps) mode + 1: Highspeed (3.4 Mbps) mode + Otherwise: + 0: fast slew rate + 1: normal slew rate + + drive-strength: + enum: [ 2, 4, 6, 8, 10, 12, 14, 16 ] + + input-enable: true + input-disable: true + + input-schmitt-enable: true + input-schmitt-disable: true + + required: + - pins + + additionalProperties: false + + allOf: + - $ref: pincfg-node.yaml# + # Limitations for I2C pins + - if: + properties: + pins: + contains: + enum: [ bsc1clk, bsc1dat, gpio16, gpio17, pmbscclk, + pmbscdat ] + then: + properties: + drive-strength: false + bias-pull-down: false + input-schmitt-enable: false + input-schmitt-disable: false + + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + pinctrl@35004800 { + compatible = "brcm,bcm21664-pinctrl"; + reg = <0x35004800 0x7f0>; + + dev-a-active-pins { + /* group node defining 1 standard pin */ + std-grp0 { + pins = "gpio00"; + function = "alt1"; + input-schmitt-enable; + bias-disable; + slew-rate = <1>; + drive-strength = <4>; + }; + + /* group node defining 2 I2C pins */ + i2c-grp0 { + pins = "bsc1clk", "bsc1dat"; + function = "alt2"; + bias-pull-up; + input-enable; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-iomuxc1.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-iomuxc1.yaml new file mode 100644 index 000000000000..957918b73a93 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-iomuxc1.yaml @@ -0,0 +1,99 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/fsl,imx7ulp-iomuxc1.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX7ULP IOMUX Controller + +description: | + i.MX 7ULP has three IOMUXC instances: IOMUXC0 for M4 ports, IOMUXC1 for A7 + ports and IOMUXC DDR for DDR interface. + + Note: This binding doc is only for the IOMUXC1 support in A7 Domain and it + only supports generic pin config. + + Please refer to fsl,imx-pinctrl.txt in this directory for common binding + part and usage. + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +properties: + compatible: + const: fsl,imx7ulp-iomuxc1 + + reg: + maxItems: 1 + +patternProperties: + 'grp$': + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + + properties: + fsl,pins: + description: + Each entry consists of 5 integers which represents the mux + and config setting for one pin. The first 4 integers + <mux_conf_reg input_reg mux_mode input_val> are specified + using a PIN_FUNC_ID macro, which can be found in + imx7ulp-pinfunc.h in the device tree source folder. + The last integer CONFIG is the pad setting value like + pull-up on this pin. + + Please refer to i.MX7ULP Reference Manual for detailed + CONFIG settings. + $ref: /schemas/types.yaml#/definitions/uint32-matrix + items: + items: + - description: | + "mux_conf_reg" indicates the offset of mux register. + - description: | + "input_reg" indicates the offset of select input register. + - description: | + "mux_mode" indicates the mux value to be applied. + - description: | + "input_val" indicates the select input value to be applied. + - description: | + CONFIG bits definition: + PAD_CTL_OBE (1 << 17) + PAD_CTL_IBE (1 << 16) + PAD_CTL_LK (1 << 16) + PAD_CTL_DSE_HI (1 << 6) + PAD_CTL_DSE_STD (0 << 6) + PAD_CTL_ODE (1 << 5) + PAD_CTL_PUSH_PULL (0 << 5) + PAD_CTL_SRE_SLOW (1 << 2) + PAD_CTL_SRE_STD (0 << 2) + PAD_CTL_PE (1 << 0) + + required: + - fsl,pins + + additionalProperties: false + +required: + - compatible + - reg + +allOf: + - $ref: pinctrl.yaml# + +unevaluatedProperties: false + +examples: + - | + pinctrl@40ac0000 { + compatible = "fsl,imx7ulp-iomuxc1"; + reg = <0x40ac0000 0x1000>; + + lpuart4grp { + fsl,pins = < + 0x000c 0x0248 0x4 0x1 0x1 + 0x0008 0x024c 0x4 0x1 0x1 + >; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt deleted file mode 100644 index bfa3703a7446..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt +++ /dev/null @@ -1,53 +0,0 @@ -* Freescale i.MX7ULP IOMUX Controller - -i.MX 7ULP has three IOMUXC instances: IOMUXC0 for M4 ports, IOMUXC1 for A7 -ports and IOMUXC DDR for DDR interface. - -Note: -This binding doc is only for the IOMUXC1 support in A7 Domain and it only -supports generic pin config. - -Please refer to fsl,imx-pinctrl.txt in this directory for common binding -part and usage. - -Required properties: -- compatible: "fsl,imx7ulp-iomuxc1". -- fsl,pins: Each entry consists of 5 integers which represents the mux - and config setting for one pin. The first 4 integers - <mux_conf_reg input_reg mux_mode input_val> are specified - using a PIN_FUNC_ID macro, which can be found in - imx7ulp-pinfunc.h in the device tree source folder. - The last integer CONFIG is the pad setting value like - pull-up on this pin. - - Please refer to i.MX7ULP Reference Manual for detailed - CONFIG settings. - -CONFIG bits definition: -PAD_CTL_OBE (1 << 17) -PAD_CTL_IBE (1 << 16) -PAD_CTL_LK (1 << 16) -PAD_CTL_DSE_HI (1 << 6) -PAD_CTL_DSE_STD (0 << 6) -PAD_CTL_ODE (1 << 5) -PAD_CTL_PUSH_PULL (0 << 5) -PAD_CTL_SRE_SLOW (1 << 2) -PAD_CTL_SRE_STD (0 << 2) -PAD_CTL_PE (1 << 0) - -Examples: -#include "imx7ulp-pinfunc.h" - -/* Pin Controller Node */ -iomuxc1: pinctrl@40ac0000 { - compatible = "fsl,imx7ulp-iomuxc1"; - reg = <0x40ac0000 0x1000>; - - /* Pin Configuration Node */ - pinctrl_lpuart4: lpuart4grp { - fsl,pins = < - IMX7ULP_PAD_PTC3__LPUART4_RX 0x1 - IMX7ULP_PAD_PTC2__LPUART4_TX 0x1 - >; - }; -}; diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,vf610-iomuxc.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,vf610-iomuxc.yaml new file mode 100644 index 000000000000..3e13587df310 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/fsl,vf610-iomuxc.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/fsl,vf610-iomuxc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale Vybrid VF610 IOMUX Controller + +description: + Please refer to fsl,imx-pinctrl.txt in this directory for common binding part + and usage. + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +properties: + compatible: + const: fsl,vf610-iomuxc + + reg: + maxItems: 1 + +patternProperties: + 'grp$': + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + + properties: + fsl,pins: + description: + two integers array, represents a group of pins mux and config setting. + The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a pin + working on a specific function, CONFIG is the pad setting value such + as pull-up, speed, ode for this pin. Please refer to Vybrid VF610 + datasheet for the valid pad config settings. + $ref: /schemas/types.yaml#/definitions/uint32-matrix + items: + items: + - description: + PIN_FUN_ID refer to vf610-pinfunc.h in device tree source folder + for all available PIN_FUNC_ID for Vybrid VF610. + - description: | + CONFIG bits definition is + PAD_CTL_SPEED_LOW (1 << 12) + PAD_CTL_SPEED_MED (2 << 12) + PAD_CTL_SPEED_HIGH (3 << 12) + PAD_CTL_SRE_FAST (1 << 11) + PAD_CTL_SRE_SLOW (0 << 11) + PAD_CTL_ODE (1 << 10) + PAD_CTL_HYS (1 << 9) + PAD_CTL_DSE_DISABLE (0 << 6) + PAD_CTL_DSE_150ohm (1 << 6) + PAD_CTL_DSE_75ohm (2 << 6) + PAD_CTL_DSE_50ohm (3 << 6) + PAD_CTL_DSE_37ohm (4 << 6) + PAD_CTL_DSE_30ohm (5 << 6) + PAD_CTL_DSE_25ohm (6 << 6) + PAD_CTL_DSE_20ohm (7 << 6) + PAD_CTL_PUS_100K_DOWN (0 << 4) + PAD_CTL_PUS_47K_UP (1 << 4) + PAD_CTL_PUS_100K_UP (2 << 4) + PAD_CTL_PUS_22K_UP (3 << 4) + PAD_CTL_PKE (1 << 3) + PAD_CTL_PUE (1 << 2) + PAD_CTL_OBE_ENABLE (1 << 1) + PAD_CTL_IBE_ENABLE (1 << 0) + PAD_CTL_OBE_IBE_ENABLE (3 << 0) + + required: + - fsl,pins + + additionalProperties: false + +required: + - compatible + - reg + +allOf: + - $ref: pinctrl.yaml# + +unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,vf610-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,vf610-pinctrl.txt deleted file mode 100644 index ddcdeb697c29..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/fsl,vf610-pinctrl.txt +++ /dev/null @@ -1,41 +0,0 @@ -Freescale Vybrid VF610 IOMUX Controller - -Please refer to fsl,imx-pinctrl.txt in this directory for common binding part -and usage. - -Required properties: -- compatible: "fsl,vf610-iomuxc" -- fsl,pins: two integers array, represents a group of pins mux and config - setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is - a pin working on a specific function, CONFIG is the pad setting value - such as pull-up, speed, ode for this pin. Please refer to Vybrid VF610 - datasheet for the valid pad config settings. - -CONFIG bits definition: -PAD_CTL_SPEED_LOW (1 << 12) -PAD_CTL_SPEED_MED (2 << 12) -PAD_CTL_SPEED_HIGH (3 << 12) -PAD_CTL_SRE_FAST (1 << 11) -PAD_CTL_SRE_SLOW (0 << 11) -PAD_CTL_ODE (1 << 10) -PAD_CTL_HYS (1 << 9) -PAD_CTL_DSE_DISABLE (0 << 6) -PAD_CTL_DSE_150ohm (1 << 6) -PAD_CTL_DSE_75ohm (2 << 6) -PAD_CTL_DSE_50ohm (3 << 6) -PAD_CTL_DSE_37ohm (4 << 6) -PAD_CTL_DSE_30ohm (5 << 6) -PAD_CTL_DSE_25ohm (6 << 6) -PAD_CTL_DSE_20ohm (7 << 6) -PAD_CTL_PUS_100K_DOWN (0 << 4) -PAD_CTL_PUS_47K_UP (1 << 4) -PAD_CTL_PUS_100K_UP (2 << 4) -PAD_CTL_PUS_22K_UP (3 << 4) -PAD_CTL_PKE (1 << 3) -PAD_CTL_PUE (1 << 2) -PAD_CTL_OBE_ENABLE (1 << 1) -PAD_CTL_IBE_ENABLE (1 << 0) -PAD_CTL_OBE_IBE_ENABLE (3 << 0) - -Please refer to vf610-pinfunc.h in device tree source folder -for all available PIN_FUNC_ID for Vybrid VF610. diff --git a/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.yaml index 890961826c6f..84e960255a36 100644 --- a/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.yaml @@ -42,6 +42,7 @@ properties: - ingenic,jz4780-pinctrl - ingenic,x1000-pinctrl - ingenic,x1500-pinctrl + - ingenic,x1600-pinctrl - ingenic,x1830-pinctrl - ingenic,x2000-pinctrl - ingenic,x2100-pinctrl @@ -81,6 +82,7 @@ patternProperties: - ingenic,jz4780-gpio - ingenic,x1000-gpio - ingenic,x1500-gpio + - ingenic,x1600-gpio - ingenic,x1830-gpio - ingenic,x2000-gpio - ingenic,x2100-gpio diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml index bccff08a5ba3..b9680b896f12 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml @@ -136,75 +136,44 @@ examples: #address-cells = <2>; #size-cells = <2>; - syscfg_pctl_a: syscfg-pctl-a@10005000 { - compatible = "mediatek,mt8135-pctl-a-syscfg", "syscon"; - reg = <0 0x10005000 0 0x1000>; - }; - - syscfg_pctl_b: syscfg-pctl-b@1020c020 { - compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon"; - reg = <0 0x1020C020 0 0x1000>; - }; - pinctrl@1c20800 { - compatible = "mediatek,mt8135-pinctrl"; - reg = <0 0x1000B000 0 0x1000>; - mediatek,pctl-regmap = <&syscfg_pctl_a>, <&syscfg_pctl_b>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; - - i2c0_pins_a: i2c0-pins { - pins1 { - pinmux = <MT8135_PIN_100_SDA0__FUNC_SDA0>, - <MT8135_PIN_101_SCL0__FUNC_SCL0>; - bias-disable; - }; - }; - - i2c1_pins_a: i2c1-pins { - pins { - pinmux = <MT8135_PIN_195_SDA1__FUNC_SDA1>, - <MT8135_PIN_196_SCL1__FUNC_SCL1>; - bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + compatible = "mediatek,mt8135-pinctrl"; + reg = <0 0x1000B000 0 0x1000>; + mediatek,pctl-regmap = <&syscfg_pctl_a>, <&syscfg_pctl_b>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; + + i2c0_pins_a: i2c0-pins { + pins1 { + pinmux = <MT8135_PIN_100_SDA0__FUNC_SDA0>, + <MT8135_PIN_101_SCL0__FUNC_SCL0>; + bias-disable; + }; }; - }; - i2c2_pins_a: i2c2-pins { - pins1 { - pinmux = <MT8135_PIN_193_SDA2__FUNC_SDA2>; - bias-pull-down; + i2c1_pins_a: i2c1-pins { + pins { + pinmux = <MT8135_PIN_195_SDA1__FUNC_SDA1>, + <MT8135_PIN_196_SCL1__FUNC_SCL1>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; }; - pins2 { - pinmux = <MT8135_PIN_49_WATCHDOG__FUNC_GPIO49>; - bias-pull-up; - }; - }; - - i2c3_pins_a: i2c3-pins { - pins1 { - pinmux = <MT8135_PIN_40_DAC_CLK__FUNC_GPIO40>, - <MT8135_PIN_41_DAC_WS__FUNC_GPIO41>; - bias-pull-up = <MTK_PUPD_SET_R1R0_01>; - }; - - pins2 { - pinmux = <MT8135_PIN_35_SCL3__FUNC_SCL3>, - <MT8135_PIN_36_SDA3__FUNC_SDA3>; - output-low; - bias-pull-up = <MTK_PUPD_SET_R1R0_01>; - }; + i2c2_pins_a: i2c2-pins { + pins1 { + pinmux = <MT8135_PIN_193_SDA2__FUNC_SDA2>; + bias-pull-down; + }; - pins3 { - pinmux = <MT8135_PIN_57_JTCK__FUNC_GPIO57>, - <MT8135_PIN_60_JTDI__FUNC_JTDI>; - drive-strength = <32>; + pins2 { + pinmux = <MT8135_PIN_49_WATCHDOG__FUNC_GPIO49>; + bias-pull-up; + }; }; - }; }; }; diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml index 3bbc00df5548..f4bab7a132d3 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml @@ -245,9 +245,4 @@ examples: }; }; }; - - mmc0 { - pinctrl-0 = <&mmc0_pins_default>; - pinctrl-names = "default"; - }; }; diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6893-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6893-pinctrl.yaml new file mode 100644 index 000000000000..fa189fe00624 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6893-pinctrl.yaml @@ -0,0 +1,193 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6893-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT6893 Pin Controller + +maintainers: + - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> + +description: + The MediaTek's MT6893 Pin controller is used to control SoC pins. + +properties: + compatible: + const: mediatek,mt6893-pinctrl + + reg: + items: + - description: pin controller base + - description: rm group IO + - description: bm group IO + - description: lm group IO + - description: lb group IO + - description: rt group IO + - description: lt group IO + - description: tm group IO + - description: External Interrupt (EINT) controller base + + reg-names: + items: + - const: base + - const: rm + - const: bm + - const: lm + - const: lb + - const: rt + - const: lt + - const: tm + - const: eint + + gpio-controller: true + + '#gpio-cells': + description: + Number of cells in GPIO specifier. Since the generic GPIO binding is used, + the amount of cells must be specified as 2. See the below mentioned gpio + binding representation for description of particular cells. + const: 2 + + gpio-ranges: + maxItems: 1 + + gpio-line-names: true + + interrupts: + description: The interrupt outputs to sysirq + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + +# PIN CONFIGURATION NODES +patternProperties: + '-pins$': + type: object + additionalProperties: false + + patternProperties: + '^pins': + type: object + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml + - $ref: /schemas/pinctrl/pinmux-node.yaml + description: + A pinctrl node should contain at least one subnodes representing the + pinctrl groups available on the machine. Each subnode will list the + pins it needs, and how they should be configured, with regard to muxer + configuration, pullups, drive strength, input enable/disable and input + schmitt. + + properties: + pinmux: + description: + Integer array, represents gpio pin number and mux setting. + Supported pin number and mux are defined as macros in + arch/arm64/boot/dts/mediatek/mt8196-pinfunc.h for this SoC. + + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + + drive-strength-microamp: + enum: [125, 250, 500, 1000] + + bias-pull-down: + oneOf: + - type: boolean + - enum: [75000, 5000] + description: Pull down RSEL type resistance values (in ohms) + description: + For normal pull down type there is no need to specify a resistance + value, hence this can be specified as a boolean property. + For RSEL pull down type a resistance value (in ohms) can be added. + + bias-pull-up: + oneOf: + - type: boolean + - enum: [10000, 5000, 4000, 3000] + description: Pull up RSEL type resistance values (in ohms) + description: + For normal pull up type there is no need to specify a resistance + value, hence this can be specified as a boolean property. + For RSEL pull up type a resistance value (in ohms) can be added. + + bias-disable: true + + output-high: true + + output-low: true + + input-enable: true + + input-disable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + required: + - pinmux + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/pinctrl/mt65xx.h> + #define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) + #define PINMUX_GPIO99__FUNC_SCL0 (MTK_PIN_NO(99) | 1) + #define PINMUX_GPIO100__FUNC_SDA0 (MTK_PIN_NO(100) | 1) + + pio: pinctrl@10005000 { + compatible = "mediatek,mt6893-pinctrl"; + reg = <0x10005000 0x1000>, + <0x11c20000 0x0200>, + <0x11d10000 0x0200>, + <0x11e20000 0x0200>, + <0x11e70000 0x0200>, + <0x11ea0000 0x0200>, + <0x11f20000 0x0200>, + <0x11f30000 0x0200>, + <0x1100b000 0x1000>; + reg-names = "base", "rm", "bm", "lm", "lb", "rt", + "lt", "tm", "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 220>; + interrupt-controller; + interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>; + #interrupt-cells = <2>; + + gpio-pins { + pins { + pinmux = <PINMUX_GPIO0__FUNC_GPIO0>; + bias-pull-up = <4000>; + drive-strength = <6>; + }; + }; + + i2c0-pins { + pins-bus { + pinmux = <PINMUX_GPIO99__FUNC_SCL0>, + <PINMUX_GPIO100__FUNC_SDA0>; + bias-pull-down = <75000>; + drive-strength-microamp = <1000>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml index d74cae9d4d65..9acca85184fa 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml @@ -366,34 +366,34 @@ examples: #size-cells = <2>; pio: pinctrl@10211000 { - compatible = "mediatek,mt7622-pinctrl"; - reg = <0 0x10211000 0 0x1000>; - gpio-controller; - #gpio-cells = <2>; - - pinctrl_eth_default: eth-pins { - mux-mdio { - groups = "mdc_mdio"; - function = "eth"; - drive-strength = <12>; + compatible = "mediatek,mt7622-pinctrl"; + reg = <0 0x10211000 0 0x1000>; + gpio-controller; + #gpio-cells = <2>; + + pinctrl_eth_default: eth-pins { + mux-mdio { + groups = "mdc_mdio"; + function = "eth"; + drive-strength = <12>; + }; + + mux-gmac2 { + groups = "rgmii_via_gmac2"; + function = "eth"; + drive-strength = <12>; + }; + + mux-esw { + groups = "esw"; + function = "eth"; + drive-strength = <8>; + }; + + conf-mdio { + pins = "MDC"; + bias-pull-up; + }; }; - - mux-gmac2 { - groups = "rgmii_via_gmac2"; - function = "eth"; - drive-strength = <12>; - }; - - mux-esw { - groups = "esw"; - function = "eth"; - drive-strength = <8>; - }; - - conf-mdio { - pins = "MDC"; - bias-pull-up; - }; - }; }; }; diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml index 8507bd15f243..464879274cae 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml @@ -195,43 +195,43 @@ examples: #size-cells = <2>; pio: pinctrl@10005000 { - compatible = "mediatek,mt8183-pinctrl"; - reg = <0 0x10005000 0 0x1000>, - <0 0x11f20000 0 0x1000>, - <0 0x11e80000 0 0x1000>, - <0 0x11e70000 0 0x1000>, - <0 0x11e90000 0 0x1000>, - <0 0x11d30000 0 0x1000>, - <0 0x11d20000 0 0x1000>, - <0 0x11c50000 0 0x1000>, - <0 0x11f30000 0 0x1000>, - <0 0x1000b000 0 0x1000>; - reg-names = "iocfg0", "iocfg1", "iocfg2", - "iocfg3", "iocfg4", "iocfg5", - "iocfg6", "iocfg7", "iocfg8", - "eint"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pio 0 0 192>; - interrupt-controller; - interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; - #interrupt-cells = <2>; - - i2c0_pins_a: i2c0-pins { - pins1 { - pinmux = <PINMUX_GPIO48__FUNC_SCL5>, - <PINMUX_GPIO49__FUNC_SDA5>; - mediatek,pull-up-adv = <3>; - drive-strength-microamp = <1000>; + compatible = "mediatek,mt8183-pinctrl"; + reg = <0 0x10005000 0 0x1000>, + <0 0x11f20000 0 0x1000>, + <0 0x11e80000 0 0x1000>, + <0 0x11e70000 0 0x1000>, + <0 0x11e90000 0 0x1000>, + <0 0x11d30000 0 0x1000>, + <0 0x11d20000 0 0x1000>, + <0 0x11c50000 0 0x1000>, + <0 0x11f30000 0 0x1000>, + <0 0x1000b000 0 0x1000>; + reg-names = "iocfg0", "iocfg1", "iocfg2", + "iocfg3", "iocfg4", "iocfg5", + "iocfg6", "iocfg7", "iocfg8", + "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 192>; + interrupt-controller; + interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <2>; + + i2c0_pins_a: i2c0-pins { + pins1 { + pinmux = <PINMUX_GPIO48__FUNC_SCL5>, + <PINMUX_GPIO49__FUNC_SDA5>; + mediatek,pull-up-adv = <3>; + drive-strength-microamp = <1000>; + }; }; - }; - i2c1_pins_a: i2c1-pins { - pins { - pinmux = <PINMUX_GPIO50__FUNC_SCL3>, - <PINMUX_GPIO51__FUNC_SDA3>; - mediatek,pull-down-adv = <2>; + i2c1_pins_a: i2c1-pins { + pins { + pinmux = <PINMUX_GPIO50__FUNC_SCL3>, + <PINMUX_GPIO51__FUNC_SDA3>; + mediatek,pull-down-adv = <2>; + }; }; - }; }; }; diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8192-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8192-pinctrl.yaml index 1686427eb854..949dcd6fd847 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8192-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8192-pinctrl.yaml @@ -142,43 +142,43 @@ additionalProperties: false examples: - | - #include <dt-bindings/pinctrl/mt8192-pinfunc.h> - #include <dt-bindings/interrupt-controller/arm-gic.h> - pio: pinctrl@10005000 { - compatible = "mediatek,mt8192-pinctrl"; - reg = <0x10005000 0x1000>, - <0x11c20000 0x1000>, - <0x11d10000 0x1000>, - <0x11d30000 0x1000>, - <0x11d40000 0x1000>, - <0x11e20000 0x1000>, - <0x11e70000 0x1000>, - <0x11ea0000 0x1000>, - <0x11f20000 0x1000>, - <0x11f30000 0x1000>, - <0x1000b000 0x1000>; - reg-names = "iocfg0", "iocfg_rm", "iocfg_bm", - "iocfg_bl", "iocfg_br", "iocfg_lm", - "iocfg_lb", "iocfg_rt", "iocfg_lt", - "iocfg_tl", "eint"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pio 0 0 220>; - interrupt-controller; - interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>; - #interrupt-cells = <2>; - - spi1-default-pins { - pins-cs-mosi-clk { - pinmux = <PINMUX_GPIO157__FUNC_SPI1_A_CSB>, - <PINMUX_GPIO159__FUNC_SPI1_A_MO>, - <PINMUX_GPIO156__FUNC_SPI1_A_CLK>; - bias-disable; - }; - - pins-miso { - pinmux = <PINMUX_GPIO158__FUNC_SPI1_A_MI>; - bias-pull-down; - }; - }; + #include <dt-bindings/pinctrl/mt8192-pinfunc.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + pio: pinctrl@10005000 { + compatible = "mediatek,mt8192-pinctrl"; + reg = <0x10005000 0x1000>, + <0x11c20000 0x1000>, + <0x11d10000 0x1000>, + <0x11d30000 0x1000>, + <0x11d40000 0x1000>, + <0x11e20000 0x1000>, + <0x11e70000 0x1000>, + <0x11ea0000 0x1000>, + <0x11f20000 0x1000>, + <0x11f30000 0x1000>, + <0x1000b000 0x1000>; + reg-names = "iocfg0", "iocfg_rm", "iocfg_bm", + "iocfg_bl", "iocfg_br", "iocfg_lm", + "iocfg_lb", "iocfg_rt", "iocfg_lt", + "iocfg_tl", "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 220>; + interrupt-controller; + interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>; + #interrupt-cells = <2>; + + spi1-default-pins { + pins-cs-mosi-clk { + pinmux = <PINMUX_GPIO157__FUNC_SPI1_A_CSB>, + <PINMUX_GPIO159__FUNC_SPI1_A_MO>, + <PINMUX_GPIO156__FUNC_SPI1_A_CLK>; + bias-disable; }; + + pins-miso { + pinmux = <PINMUX_GPIO158__FUNC_SPI1_A_MI>; + bias-pull-down; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8196-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8196-pinctrl.yaml new file mode 100644 index 000000000000..9082bd625e2f --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8196-pinctrl.yaml @@ -0,0 +1,236 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt8196-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT8196 Pin Controller + +maintainers: + - Lei Xue <lei.xue@mediatek.com> + - Cathy Xu <ot_cathy.xu@mediatek.com> + +description: + The MediaTek's MT8196 Pin controller is used to control SoC pins. + +properties: + compatible: + const: mediatek,mt8196-pinctrl + + reg: + items: + - description: gpio base + - description: rt group IO + - description: rm1 group IO + - description: rm2 group IO + - description: rb group IO + - description: bm1 group IO + - description: bm2 group IO + - description: bm3 group IO + - description: lt group IO + - description: lm1 group IO + - description: lm2 group IO + - description: lb1 group IO + - description: lb2 group IO + - description: tm1 group IO + - description: tm2 group IO + - description: tm3 group IO + - description: eint0 group IO + - description: eint1 group IO + - description: eint2 group IO + - description: eint3 group IO + - description: eint4 group IO + + reg-names: + items: + - const: base + - const: rt + - const: rm1 + - const: rm2 + - const: rb + - const: bm1 + - const: bm2 + - const: bm3 + - const: lt + - const: lm1 + - const: lm2 + - const: lb1 + - const: lb2 + - const: tm1 + - const: tm2 + - const: tm3 + - const: eint0 + - const: eint1 + - const: eint2 + - const: eint3 + - const: eint4 + + interrupts: + description: The interrupt outputs to sysirq. + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + gpio-controller: true + + '#gpio-cells': + description: + Number of cells in GPIO specifier, should be two. The first cell is the + pin number, the second cell is used to specify optional parameters which + are defined in <dt-bindings/gpio/gpio.h>. + const: 2 + + gpio-ranges: + maxItems: 1 + + gpio-line-names: true + +# PIN CONFIGURATION NODES +patternProperties: + '-pins$': + type: object + additionalProperties: false + + patternProperties: + '^pins': + type: object + $ref: /schemas/pinctrl/pincfg-node.yaml + additionalProperties: false + description: + A pinctrl node should contain at least one subnode representing the + pinctrl groups available on the machine. Each subnode will list the + pins it needs, and how they should be configured, with regard to muxer + configuration, pullups, drive strength, input enable/disable and input + schmitt. + + properties: + pinmux: + description: + Integer array, represents gpio pin number and mux setting. + Supported pin number and mux varies for different SoCs, and are + defined as macros in arch/arm64/boot/dts/mediatek/mt8196-pinfunc.h + directly, for this SoC. + + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + + bias-pull-down: + oneOf: + - type: boolean + - enum: [100, 101, 102, 103] + description: mt8196 pull down PUPD/R0/R1 type define value. + - enum: [75000, 5000] + description: mt8196 pull down RSEL type si unit value(ohm). + description: | + For pull down type is normal, it doesn't need add R1R0 define + and resistance value. + For pull down type is PUPD/R0/R1 type, it can add R1R0 define to + set different resistance. It can support "MTK_PUPD_SET_R1R0_00" & + "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" & + "MTK_PUPD_SET_R1R0_11" define in mt8196. + For pull down type is PD/RSEL, it can add resistance value(ohm) + to set different resistance by identifying property + "mediatek,rsel-resistance-in-si-unit". It can support resistance + value(ohm) "75000" & "5000" in mt8196. + + bias-pull-up: + oneOf: + - type: boolean + - enum: [100, 101, 102, 103] + description: mt8196 pull up PUPD/R0/R1 type define value. + - enum: [1000, 1500, 2000, 3000, 4000, 5000, 75000] + description: mt8196 pull up RSEL type si unit value(ohm). + description: | + For pull up type is normal, it don't need add R1R0 define + and resistance value. + For pull up type is PUPD/R0/R1 type, it can add R1R0 define to + set different resistance. It can support "MTK_PUPD_SET_R1R0_00" & + "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" & + "MTK_PUPD_SET_R1R0_11" define in mt8196. + For pull up type is PU/RSEL, it can add resistance value(ohm) + to set different resistance by identifying property + "mediatek,rsel-resistance-in-si-unit". It can support resistance + value(ohm) "1000" & "1500" & "2000" & "3000" & "4000" & "5000" & + "75000" in mt8196. + + bias-disable: true + + output-high: true + + output-low: true + + input-enable: true + + input-disable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + required: + - pinmux + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + #include <dt-bindings/pinctrl/mt65xx.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #define PINMUX_GPIO99__FUNC_SCL0 (MTK_PIN_NO(99) | 1) + #define PINMUX_GPIO100__FUNC_SDA0 (MTK_PIN_NO(100) | 1) + + pio: pinctrl@1002d000 { + compatible = "mediatek,mt8196-pinctrl"; + reg = <0x1002d000 0x1000>, + <0x12000000 0x1000>, + <0x12020000 0x1000>, + <0x12040000 0x1000>, + <0x12060000 0x1000>, + <0x12820000 0x1000>, + <0x12840000 0x1000>, + <0x12860000 0x1000>, + <0x13000000 0x1000>, + <0x13020000 0x1000>, + <0x13040000 0x1000>, + <0x130f0000 0x1000>, + <0x13110000 0x1000>, + <0x13800000 0x1000>, + <0x13820000 0x1000>, + <0x13860000 0x1000>, + <0x12080000 0x1000>, + <0x12880000 0x1000>, + <0x13080000 0x1000>, + <0x13880000 0x1000>, + <0x1c54a000 0x1000>; + reg-names = "base", "rt", "rm1", "rm2", "rb" , "bm1", + "bm2", "bm3", "lt", "lm1", "lm2", "lb1", + "lb2", "tm1", "tm2", "tm3", "eint0", "eint1", + "eint2", "eint3", "eint4"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 271>; + interrupt-controller; + interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH 0>; + #interrupt-cells = <2>; + + i2c0-pins { + pins { + pinmux = <PINMUX_GPIO99__FUNC_SCL0>, + <PINMUX_GPIO100__FUNC_SDA0>; + bias-disable; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,qcs615-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,qcs615-tlmm.yaml index 1ce4b5df584a..2791e578c1de 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,qcs615-tlmm.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,qcs615-tlmm.yaml @@ -110,7 +110,7 @@ examples: <0x03c00000 0x300000>; reg-names = "east", "west", "south"; interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; - gpio-ranges = <&tlmm 0 0 123>; + gpio-ranges = <&tlmm 0 0 124>; gpio-controller; #gpio-cells = <2>; interrupt-controller; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,qcs8300-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,qcs8300-tlmm.yaml index bb0d7132886a..489b41dcc179 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,qcs8300-tlmm.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,qcs8300-tlmm.yaml @@ -106,7 +106,7 @@ examples: interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; - gpio-ranges = <&tlmm 0 0 133>; + gpio-ranges = <&tlmm 0 0 134>; interrupt-controller; #interrupt-cells = <2>; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sa8775p-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sa8775p-tlmm.yaml index 749dbc563ac5..7a156b9bfaf3 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sa8775p-tlmm.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sa8775p-tlmm.yaml @@ -79,7 +79,7 @@ $defs: cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, ddr_pxi4, ddr_pxi5, edp0_hot, edp0_lcd, edp1_hot, edp1_lcd, edp2_hot, edp2_lcd, edp3_hot, - edp3_lcd, emac0_mcg0, emac0_mcg1, emac0_mcg2, emac0_mcg3, + edp3_lcd, egpio, emac0_mcg0, emac0_mcg1, emac0_mcg2, emac0_mcg3, emac0_mdc, emac0_mdio, emac0_ptp_aux, emac0_ptp_pps, emac1_mcg0, emac1_mcg1, emac1_mcg2, emac1_mcg3, emac1_mdc, emac1_mdio, emac1_ptp_aux, emac1_ptp_pps, gcc_gp1, gcc_gp2, gcc_gp3, diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml index 768bb3c2b456..5156d54b240b 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml @@ -27,6 +27,7 @@ properties: - renesas,r9a07g044-pinctrl # RZ/G2{L,LC} - renesas,r9a08g045-pinctrl # RZ/G3S - renesas,r9a09g047-pinctrl # RZ/G3E + - renesas,r9a09g056-pinctrl # RZ/V2N - renesas,r9a09g057-pinctrl # RZ/V2H(P) - items: @@ -145,6 +146,7 @@ allOf: contains: enum: - renesas,r9a09g047-pinctrl + - renesas,r9a09g056-pinctrl - renesas,r9a09g057-pinctrl then: properties: diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzn1-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzn1-pinctrl.yaml index 816688580e33..aa882b5bfe97 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzn1-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzn1-pinctrl.yaml @@ -13,9 +13,7 @@ maintainers: properties: compatible: items: - - enum: - - renesas,r9a06g032-pinctrl # RZ/N1D - - renesas,r9a06g033-pinctrl # RZ/N1S + - const: renesas,r9a06g032-pinctrl # RZ/N1D - const: renesas,rzn1-pinctrl # Generic RZ/N1 reg: diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml index 80a2b1934849..960758dc417f 100644 --- a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml @@ -44,6 +44,7 @@ properties: - rockchip,rk3328-pinctrl - rockchip,rk3368-pinctrl - rockchip,rk3399-pinctrl + - rockchip,rk3528-pinctrl - rockchip,rk3562-pinctrl - rockchip,rk3568-pinctrl - rockchip,rk3576-pinctrl diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml index 68ed714eb0a1..0da6d69f5991 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml @@ -40,6 +40,7 @@ properties: - items: - enum: - samsung,exynos5433-wakeup-eint + - samsung,exynos7870-wakeup-eint - samsung,exynos7885-wakeup-eint - samsung,exynos850-wakeup-eint - samsung,exynos8895-wakeup-eint @@ -47,6 +48,7 @@ properties: - items: - enum: - google,gs101-wakeup-eint + - samsung,exynos2200-wakeup-eint - samsung,exynos9810-wakeup-eint - samsung,exynos990-wakeup-eint - samsung,exynosautov9-wakeup-eint @@ -104,6 +106,7 @@ allOf: - contains: enum: - samsung,exynos5433-wakeup-eint + - samsung,exynos7870-wakeup-eint - samsung,exynos7885-wakeup-eint - samsung,exynos8895-wakeup-eint then: diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml index 5296a9e4faae..de8460856141 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml @@ -42,6 +42,7 @@ properties: - samsung,s3c2450-pinctrl - samsung,s3c64xx-pinctrl - samsung,s5pv210-pinctrl + - samsung,exynos2200-pinctrl - samsung,exynos3250-pinctrl - samsung,exynos4210-pinctrl - samsung,exynos4x12-pinctrl @@ -51,6 +52,7 @@ properties: - samsung,exynos5420-pinctrl - samsung,exynos5433-pinctrl - samsung,exynos7-pinctrl + - samsung,exynos7870-pinctrl - samsung,exynos7885-pinctrl - samsung,exynos850-pinctrl - samsung,exynos8895-pinctrl diff --git a/Documentation/devicetree/bindings/pinctrl/sophgo,sg2042-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/sophgo,sg2042-pinctrl.yaml new file mode 100644 index 000000000000..924dfe1404a5 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/sophgo,sg2042-pinctrl.yaml @@ -0,0 +1,129 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/sophgo,sg2042-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo SG2042 Pin Controller + +maintainers: + - Inochi Amaoto <inochiama@outlook.com> + +properties: + compatible: + enum: + - sophgo,sg2042-pinctrl + - sophgo,sg2044-pinctrl + + reg: + maxItems: 1 + +patternProperties: + '-cfg$': + type: object + description: + A pinctrl node should contain at least one subnode representing the + pinctrl groups available on the machine. + + additionalProperties: false + + patternProperties: + '-pins$': + type: object + description: | + Each subnode will list the pins it needs, and how they should + be configured, with regard to muxer configuration, bias input + enable/disable, input schmitt trigger enable, drive strength + output enable/disable state. For configuration detail, + refer to https://github.com/sophgo/sophgo-doc/. + + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + + properties: + pinmux: + description: | + The list of GPIOs and their mux settings that properties in the + node apply to. This should be set using the PINMUX macro. + + bias-disable: true + + bias-pull-up: + type: boolean + + bias-pull-down: + type: boolean + + drive-strength-microamp: + description: typical current when output low level. + + input-schmitt-enable: true + + input-schmitt-disable: true + + required: + - pinmux + + additionalProperties: false + +required: + - compatible + - reg + +allOf: + - if: + properties: + compatible: + contains: + const: sophgo,sg2042-pinctrl + then: + patternProperties: + '-cfg$': + patternProperties: + '-pins$': + properties: + drive-strength-microamp: + enum: [ 5400, 8100, 10700, 13400, + 16100, 18800, 21400, 24100, + 26800, 29400, 32100, 34800, + 37400, 40100, 42800, 45400 ] + + - if: + properties: + compatible: + contains: + const: sophgo,sg2044-pinctrl + then: + patternProperties: + '-cfg$': + patternProperties: + '-pins$': + properties: + drive-strength-microamp: + enum: [ 3200, 6400, 9600, 12700, + 15900, 19100, 22200, 25300, + 29500, 32700, 35900, 39000, + 42000, 45200, 48300, 51400] + +additionalProperties: false + +examples: + - | + #include <dt-bindings/pinctrl/pinctrl-sg2042.h> + + pinctrl@30011000 { + compatible = "sophgo,sg2042-pinctrl"; + reg = <30011000 0x1000>; + + uart0_cfg: uart0-cfg { + uart0-pins { + pinmux = <PINMUX(PIN_UART0_TX, 0)>, + <PINMUX(PIN_UART0_RX, 0)>; + bias-pull-up; + drive-strength-microamp = <13400>; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml index b01ecd83b71b..d80e88aa07b4 100644 --- a/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml @@ -17,6 +17,19 @@ properties: items: - description: pinctrl io memory base + clocks: + items: + - description: Functional Clock + - description: Bus Clock + + clock-names: + items: + - const: func + - const: bus + + resets: + maxItems: 1 + patternProperties: '-cfg$': type: object @@ -94,6 +107,8 @@ patternProperties: required: - compatible - reg + - clocks + - clock-names additionalProperties: false @@ -108,6 +123,9 @@ examples: pinctrl@d401e000 { compatible = "spacemit,k1-pinctrl"; reg = <0x0 0xd401e000 0x0 0x400>; + clocks = <&syscon_apbc 42>, + <&syscon_apbc 94>; + clock-names = "func", "bus"; uart0_2_cfg: uart0-2-cfg { uart0-2-pins { diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-aon-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-aon-pinctrl.yaml index b470901f5f56..4dbef86bd958 100644 --- a/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-aon-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-aon-pinctrl.yaml @@ -15,7 +15,7 @@ description: | Some peripherals such as PWM have their I/O go through the 4 "GPIOs". maintainers: - - Jianlong Huang <jianlong.huang@starfivetech.com> + - Hal Feng <hal.feng@starfivetech.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-sys-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-sys-pinctrl.yaml index 222b9e240f8a..e2a25a20f6a6 100644 --- a/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-sys-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-sys-pinctrl.yaml @@ -18,7 +18,7 @@ description: | any GPIO can be set up to be controlled by any of the peripherals. maintainers: - - Jianlong Huang <jianlong.huang@starfivetech.com> + - Hal Feng <hal.feng@starfivetech.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/platform/huawei,gaokun-ec.yaml b/Documentation/devicetree/bindings/platform/huawei,gaokun-ec.yaml new file mode 100644 index 000000000000..4a03b0ee3149 --- /dev/null +++ b/Documentation/devicetree/bindings/platform/huawei,gaokun-ec.yaml @@ -0,0 +1,124 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/platform/huawei,gaokun-ec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Huawei Matebook E Go Embedded Controller + +maintainers: + - Pengyu Luo <mitltlatltl@gmail.com> + +description: + Different from other Qualcomm Snapdragon sc8180x and sc8280xp-based + machines, the Huawei Matebook E Go tablets use embedded controllers + while others use a system called PMIC GLink which handles battery, + UCSI, USB Type-C DP Alt Mode. In addition, Huawei's implementation + also handles additional features, such as charging thresholds, FN + lock, smart charging, tablet lid status, thermal sensors, and more. + +properties: + compatible: + enum: + - huawei,gaokun3-ec + + reg: + const: 0x38 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + interrupts: + maxItems: 1 + +patternProperties: + '^connector@[01]$': + $ref: /schemas/connector/usb-connector.yaml# + + properties: + reg: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + i2c { + #address-cells = <1>; + #size-cells = <0>; + + embedded-controller@38 { + compatible = "huawei,gaokun3-ec"; + reg = <0x38>; + + interrupts-extended = <&tlmm 107 IRQ_TYPE_LEVEL_LOW>; + + #address-cells = <1>; + #size-cells = <0>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + ucsi0_ss_in: endpoint { + remote-endpoint = <&usb_0_qmpphy_out>; + }; + }; + + port@1 { + reg = <1>; + + ucsi0_sbu: endpoint { + remote-endpoint = <&usb0_sbu_mux>; + }; + }; + }; + }; + + connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + ucsi1_ss_in: endpoint { + remote-endpoint = <&usb_1_qmpphy_out>; + }; + }; + + port@1 { + reg = <1>; + + ucsi1_sbu: endpoint { + remote-endpoint = <&usb1_sbu_mux>; + }; + }; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pmem/pmem-region.txt b/Documentation/devicetree/bindings/pmem/pmem-region.txt deleted file mode 100644 index cd79975e85ec..000000000000 --- a/Documentation/devicetree/bindings/pmem/pmem-region.txt +++ /dev/null @@ -1,65 +0,0 @@ -Device-tree bindings for persistent memory regions ------------------------------------------------------ - -Persistent memory refers to a class of memory devices that are: - - a) Usable as main system memory (i.e. cacheable), and - b) Retain their contents across power failure. - -Given b) it is best to think of persistent memory as a kind of memory mapped -storage device. To ensure data integrity the operating system needs to manage -persistent regions separately to the normal memory pool. To aid with that this -binding provides a standardised interface for discovering where persistent -memory regions exist inside the physical address space. - -Bindings for the region nodes: ------------------------------ - -Required properties: - - compatible = "pmem-region" - - - reg = <base, size>; - The reg property should specify an address range that is - translatable to a system physical address range. This address - range should be mappable as normal system memory would be - (i.e cacheable). - - If the reg property contains multiple address ranges - each address range will be treated as though it was specified - in a separate device node. Having multiple address ranges in a - node implies no special relationship between the two ranges. - -Optional properties: - - Any relevant NUMA associativity properties for the target platform. - - - volatile; This property indicates that this region is actually - backed by non-persistent memory. This lets the OS know that it - may skip the cache flushes required to ensure data is made - persistent after a write. - - If this property is absent then the OS must assume that the region - is backed by non-volatile memory. - -Examples: --------------------- - - /* - * This node specifies one 4KB region spanning from - * 0x5000 to 0x5fff that is backed by non-volatile memory. - */ - pmem@5000 { - compatible = "pmem-region"; - reg = <0x00005000 0x00001000>; - }; - - /* - * This node specifies two 4KB regions that are backed by - * volatile (normal) memory. - */ - pmem@6000 { - compatible = "pmem-region"; - reg = < 0x00006000 0x00001000 - 0x00008000 0x00001000 >; - volatile; - }; - diff --git a/Documentation/devicetree/bindings/pmem/pmem-region.yaml b/Documentation/devicetree/bindings/pmem/pmem-region.yaml new file mode 100644 index 000000000000..bd0f0c793f03 --- /dev/null +++ b/Documentation/devicetree/bindings/pmem/pmem-region.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pmem-region.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +maintainers: + - Oliver O'Halloran <oohall@gmail.com> + +title: Persistent Memory Regions + +description: | + Persistent memory refers to a class of memory devices that are: + + a) Usable as main system memory (i.e. cacheable), and + b) Retain their contents across power failure. + + Given b) it is best to think of persistent memory as a kind of memory mapped + storage device. To ensure data integrity the operating system needs to manage + persistent regions separately to the normal memory pool. To aid with that this + binding provides a standardised interface for discovering where persistent + memory regions exist inside the physical address space. + +properties: + compatible: + const: pmem-region + + reg: + maxItems: 1 + + volatile: + description: + Indicates the region is volatile (non-persistent) and the OS can skip + cache flushes for writes + type: boolean + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pmem@5000 { + compatible = "pmem-region"; + reg = <0x00005000 0x00001000>; + }; diff --git a/Documentation/devicetree/bindings/power/allwinner,sun20i-d1-ppu.yaml b/Documentation/devicetree/bindings/power/allwinner,sun20i-d1-ppu.yaml index 46e2647a5d72..f578be6a3bc8 100644 --- a/Documentation/devicetree/bindings/power/allwinner,sun20i-d1-ppu.yaml +++ b/Documentation/devicetree/bindings/power/allwinner,sun20i-d1-ppu.yaml @@ -17,6 +17,7 @@ properties: compatible: enum: - allwinner,sun20i-d1-ppu + - allwinner,sun8i-v853-ppu reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/power/allwinner,sun50i-h6-prcm-ppu.yaml b/Documentation/devicetree/bindings/power/allwinner,sun50i-h6-prcm-ppu.yaml new file mode 100644 index 000000000000..73a9b4d6220e --- /dev/null +++ b/Documentation/devicetree/bindings/power/allwinner,sun50i-h6-prcm-ppu.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/allwinner,sun50i-h6-prcm-ppu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner SoCs PRCM power domain controller + +maintainers: + - Andre Przywara <andre.przywara@arm.com> + +description: + The Allwinner Power Reset Clock Management (PRCM) unit contains bits to + control a few power domains. + +properties: + compatible: + enum: + - allwinner,sun50i-h6-prcm-ppu + - allwinner,sun50i-h616-prcm-ppu + - allwinner,sun55i-a523-prcm-ppu + + reg: + maxItems: 1 + + '#power-domain-cells': + const: 1 + +required: + - compatible + - reg + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + prcm_ppu: power-controller@7010210 { + compatible = "allwinner,sun50i-h616-prcm-ppu"; + reg = <0x7010210 0x10>; + #power-domain-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml b/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml index 59a6af735a21..6e9a670eaf56 100644 --- a/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml +++ b/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml @@ -31,6 +31,11 @@ properties: compatible: items: - enum: + - apple,s5l8960x-pmgr-pwrstate + - apple,t7000-pmgr-pwrstate + - apple,s8000-pmgr-pwrstate + - apple,t8010-pmgr-pwrstate + - apple,t8015-pmgr-pwrstate - apple,t8103-pmgr-pwrstate - apple,t8112-pmgr-pwrstate - apple,t6000-pmgr-pwrstate diff --git a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml index 591a080ca3ff..9c7cc632abee 100644 --- a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml +++ b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml @@ -25,6 +25,7 @@ properties: enum: - mediatek,mt6735-power-controller - mediatek,mt6795-power-controller + - mediatek,mt6893-power-controller - mediatek,mt8167-power-controller - mediatek,mt8173-power-controller - mediatek,mt8183-power-controller @@ -88,6 +89,7 @@ $defs: description: | Power domain index. Valid values are defined in: "include/dt-bindings/power/mt6795-power.h" - for MT8167 type power domain. + "include/dt-bindings/power/mediatek,mt6893-power.h" - for MT6893 type power domain. "include/dt-bindings/power/mt8167-power.h" - for MT8167 type power domain. "include/dt-bindings/power/mt8173-power.h" - for MT8173 type power domain. "include/dt-bindings/power/mt8183-power.h" - for MT8183 type power domain. diff --git a/Documentation/devicetree/bindings/power/qcom,kpss-acc-v2.yaml b/Documentation/devicetree/bindings/power/qcom,kpss-acc-v2.yaml index 202a5d51ee88..3fa77fe14c87 100644 --- a/Documentation/devicetree/bindings/power/qcom,kpss-acc-v2.yaml +++ b/Documentation/devicetree/bindings/power/qcom,kpss-acc-v2.yaml @@ -18,7 +18,9 @@ description: properties: compatible: - const: qcom,kpss-acc-v2 + enum: + - qcom,kpss-acc-v2 + - qcom,msm8916-acc reg: items: diff --git a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml index 655687369a23..1bf65f2a583a 100644 --- a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml +++ b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml @@ -50,6 +50,7 @@ properties: - qcom,sdx55-rpmhpd - qcom,sdx65-rpmhpd - qcom,sdx75-rpmhpd + - qcom,sm4450-rpmhpd - qcom,sm6115-rpmpd - qcom,sm6125-rpmpd - qcom,sm6350-rpmhpd diff --git a/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml b/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml index 0735ceb7c103..9c34249b2d6d 100644 --- a/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml +++ b/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml @@ -17,6 +17,11 @@ properties: compatible: oneOf: - items: + - enum: + - microchip,sama7d65-shdwc + - const: microchip,sama7g5-shdwc + - const: syscon + - items: - const: microchip,sama7g5-shdwc - const: syscon - enum: diff --git a/Documentation/devicetree/bindings/power/reset/syscon-reboot.yaml b/Documentation/devicetree/bindings/power/reset/syscon-reboot.yaml index 19d3093e6cd2..ccd555870094 100644 --- a/Documentation/devicetree/bindings/power/reset/syscon-reboot.yaml +++ b/Documentation/devicetree/bindings/power/reset/syscon-reboot.yaml @@ -21,7 +21,9 @@ description: |+ properties: compatible: - const: syscon-reboot + enum: + - syscon-reboot + - google,gs101-reboot mask: $ref: /schemas/types.yaml#/definitions/uint32 @@ -49,12 +51,6 @@ properties: priority: default: 192 -oneOf: - - required: - - offset - - required: - - reg - required: - compatible @@ -63,12 +59,29 @@ additionalProperties: false allOf: - $ref: restart-handler.yaml# - if: - not: - required: - - mask + properties: + compatible: + contains: + const: google,gs101-reboot then: - required: - - value + properties: + mask: false + offset: false + reg: false + value: false + + else: + if: + not: + required: + - mask + then: + required: + - value + + oneOf: + - required: [offset] + - required: [reg] examples: - | @@ -78,3 +91,8 @@ examples: offset = <0x0>; mask = <0x1>; }; + + - | + reboot { + compatible = "google,gs101-reboot"; + }; diff --git a/Documentation/devicetree/bindings/power/reset/toradex,smarc-ec.yaml b/Documentation/devicetree/bindings/power/reset/toradex,smarc-ec.yaml new file mode 100644 index 000000000000..ffcd5f2c2bf6 --- /dev/null +++ b/Documentation/devicetree/bindings/power/reset/toradex,smarc-ec.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/reset/toradex,smarc-ec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Toradex Embedded Controller + +maintainers: + - Emanuele Ghidoli <emanuele.ghidoli@toradex.com> + - Francesco Dolcini <francesco.dolcini@toradex.com> + +description: | + The Toradex Embedded Controller (EC) is used on Toradex SMARC modules, + primarily to manage power and reset functionalities. + + The EC provides the following functions: + - Reads the SMARC POWER_BTN# and RESET_IN# signals and controls the PMIC accordingly. + - Controls the SoC boot mode signals based on the SMARC BOOT_SEL# and FORCE_RECOV# inputs. + - Manages the CARRIER_STDBY# signal in response to relevant SoC signals. + + The EC runs a small firmware, factory programmed into its internal flash, and communicates over I2C. + It allows software to control power-off and reset functionalities of the module. + +properties: + compatible: + items: + - enum: + - toradex,smarc-imx95-ec + - toradex,smarc-imx8mp-ec + - const: toradex,smarc-ec + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + reset-controller@28 { + compatible = "toradex,smarc-imx95-ec", "toradex,smarc-ec"; + reg = <0x28>; + }; + }; diff --git a/Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.yaml b/Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.yaml index 799831636194..079ad977b907 100644 --- a/Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.yaml +++ b/Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.yaml @@ -46,7 +46,6 @@ properties: required: - compatible - - interrupts additionalProperties: false diff --git a/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml b/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml index 650dc0aae6f5..f494b7710c09 100644 --- a/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml +++ b/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml @@ -40,6 +40,7 @@ properties: - rockchip,rk3366-power-controller - rockchip,rk3368-power-controller - rockchip,rk3399-power-controller + - rockchip,rk3562-power-controller - rockchip,rk3568-power-controller - rockchip,rk3576-power-controller - rockchip,rk3588-power-controller @@ -132,6 +133,9 @@ $defs: A number of phandles to clocks that need to be enabled while power domain switches state. + domain-supply: + description: domain regulator supply. + pm_qos: $ref: /schemas/types.yaml#/definitions/phandle-array items: diff --git a/Documentation/devicetree/bindings/power/supply/bq24190.yaml b/Documentation/devicetree/bindings/power/supply/bq24190.yaml index 07adf88997b4..307c99c07721 100644 --- a/Documentation/devicetree/bindings/power/supply/bq24190.yaml +++ b/Documentation/devicetree/bindings/power/supply/bq24190.yaml @@ -19,6 +19,7 @@ properties: - ti,bq24190 - ti,bq24192 - ti,bq24192i + - ti,bq24193 - ti,bq24196 - ti,bq24296 - ti,bq24297 diff --git a/Documentation/devicetree/bindings/power/supply/bq25980.yaml b/Documentation/devicetree/bindings/power/supply/bq25980.yaml index b70ce8d7f86c..256adbef55eb 100644 --- a/Documentation/devicetree/bindings/power/supply/bq25980.yaml +++ b/Documentation/devicetree/bindings/power/supply/bq25980.yaml @@ -87,28 +87,28 @@ unevaluatedProperties: false examples: - | bat: battery { - compatible = "simple-battery"; - constant-charge-current-max-microamp = <4000000>; - constant-charge-voltage-max-microvolt = <8400000>; - precharge-current-microamp = <160000>; - charge-term-current-microamp = <160000>; + compatible = "simple-battery"; + constant-charge-current-max-microamp = <4000000>; + constant-charge-voltage-max-microvolt = <8400000>; + precharge-current-microamp = <160000>; + charge-term-current-microamp = <160000>; }; #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> i2c { - #address-cells = <1>; - #size-cells = <0>; - - bq25980: charger@65 { - compatible = "ti,bq25980"; - reg = <0x65>; - interrupt-parent = <&gpio1>; - interrupts = <16 IRQ_TYPE_EDGE_FALLING>; - ti,watchdog-timeout-ms = <0>; - ti,sc-ocp-limit-microamp = <2000000>; - ti,sc-ovp-limit-microvolt = <17800000>; - monitored-battery = <&bat>; - }; + #address-cells = <1>; + #size-cells = <0>; + + bq25980: charger@65 { + compatible = "ti,bq25980"; + reg = <0x65>; + interrupt-parent = <&gpio1>; + interrupts = <16 IRQ_TYPE_EDGE_FALLING>; + ti,watchdog-timeout-ms = <0>; + ti,sc-ocp-limit-microamp = <2000000>; + ti,sc-ovp-limit-microvolt = <17800000>; + monitored-battery = <&bat>; + }; }; ... diff --git a/Documentation/devicetree/bindings/power/supply/ingenic,battery.yaml b/Documentation/devicetree/bindings/power/supply/ingenic,battery.yaml index 741022b4449d..cb04fb25d8ac 100644 --- a/Documentation/devicetree/bindings/power/supply/ingenic,battery.yaml +++ b/Documentation/devicetree/bindings/power/supply/ingenic,battery.yaml @@ -48,14 +48,14 @@ examples: #include <dt-bindings/iio/adc/ingenic,adc.h> simple_battery: battery { - compatible = "simple-battery"; - voltage-min-design-microvolt = <3600000>; - voltage-max-design-microvolt = <4200000>; + compatible = "simple-battery"; + voltage-min-design-microvolt = <3600000>; + voltage-max-design-microvolt = <4200000>; }; ingenic-battery { - compatible = "ingenic,jz4740-battery"; - io-channels = <&adc INGENIC_ADC_BATTERY>; - io-channel-names = "battery"; - monitored-battery = <&simple_battery>; + compatible = "ingenic,jz4740-battery"; + io-channels = <&adc INGENIC_ADC_BATTERY>; + io-channel-names = "battery"; + monitored-battery = <&simple_battery>; }; diff --git a/Documentation/devicetree/bindings/power/supply/ltc4162-l.yaml b/Documentation/devicetree/bindings/power/supply/ltc4162-l.yaml index 06595a953659..bc7ed7b22085 100644 --- a/Documentation/devicetree/bindings/power/supply/ltc4162-l.yaml +++ b/Documentation/devicetree/bindings/power/supply/ltc4162-l.yaml @@ -61,13 +61,13 @@ additionalProperties: false examples: - | i2c { - #address-cells = <1>; - #size-cells = <0>; - charger: battery-charger@68 { - compatible = "lltc,ltc4162-l"; - reg = <0x68>; - lltc,rsnsb-micro-ohms = <10000>; - lltc,rsnsi-micro-ohms = <16000>; - lltc,cell-count = <2>; - }; + #address-cells = <1>; + #size-cells = <0>; + charger: battery-charger@68 { + compatible = "lltc,ltc4162-l"; + reg = <0x68>; + lltc,rsnsb-micro-ohms = <10000>; + lltc,rsnsi-micro-ohms = <16000>; + lltc,cell-count = <2>; + }; }; diff --git a/Documentation/devicetree/bindings/power/supply/maxim,max77705.yaml b/Documentation/devicetree/bindings/power/supply/maxim,max77705.yaml new file mode 100644 index 000000000000..e3b84068993b --- /dev/null +++ b/Documentation/devicetree/bindings/power/supply/maxim,max77705.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/supply/maxim,max77705.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Maxim MAX777705 charger + +maintainers: + - Dzmitry Sankouski <dsankouski@gmail.com> + +description: | + This is a device tree bindings for charger found in Maxim MAX77705 chip. + +allOf: + - $ref: power-supply.yaml# + +properties: + compatible: + const: maxim,max77705-charger + + interrupts: + maxItems: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - monitored-battery + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + charger@69 { + compatible = "maxim,max77705-charger"; + reg = <0x69>; + monitored-battery = <&battery>; + interrupt-parent = <&pm8998_gpios>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + }; + }; diff --git a/Documentation/devicetree/bindings/power/supply/maxim,max8971.yaml b/Documentation/devicetree/bindings/power/supply/maxim,max8971.yaml new file mode 100644 index 000000000000..2244cc3d45a6 --- /dev/null +++ b/Documentation/devicetree/bindings/power/supply/maxim,max8971.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/supply/maxim,max8971.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Maxim MAX8971 IC charger + +maintainers: + - Svyatoslav Ryhel <clamor95@gmail.com> + +description: + The MAX8971 is a compact, high-frequency, high-efficiency switch-mode charger + for a one-cell lithium-ion (Li+) battery. + +allOf: + - $ref: power-supply.yaml# + +properties: + compatible: + const: maxim,max8971 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + monitored-battery: true + + port: + description: + An optional port node to link the extcon device to detect type of plug. + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + - reg + - interrupts + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interrupt-controller/irq.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + charger@35 { + compatible = "maxim,max8971"; + reg = <0x35>; + + interrupt-parent = <&gpio>; + interrupts = <74 IRQ_TYPE_LEVEL_LOW>; + + monitored-battery = <&battery>; + + port { + charger_input: endpoint { + remote-endpoint = <&extcon_output>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/power/supply/pegatron,chagall-ec.yaml b/Documentation/devicetree/bindings/power/supply/pegatron,chagall-ec.yaml new file mode 100644 index 000000000000..defb0861e268 --- /dev/null +++ b/Documentation/devicetree/bindings/power/supply/pegatron,chagall-ec.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/supply/pegatron,chagall-ec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Pegatron Chagall EC + +maintainers: + - Svyatoslav Ryhel <clamor95@gmail.com> + +description: + Pegatron Chagall EC is based on an 8-bit programmable microcontroller from + Infineon/Cypress Semiconductor, it communicates over I2C and is used in the + Pegatron Chagall tablet for fuel gauge and battery control functions. + +$ref: /schemas/power/supply/power-supply.yaml + +properties: + compatible: + const: pegatron,chagall-ec + + reg: + maxItems: 1 + + monitored-battery: true + power-supplies: true + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + embedded-controller@10 { + compatible = "pegatron,chagall-ec"; + reg = <0x10>; + + monitored-battery = <&battery>; + power-supplies = <&mains>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/power/supply/qcom,pmi8998-charger.yaml b/Documentation/devicetree/bindings/power/supply/qcom,pmi8998-charger.yaml index a0f9d49ff8fb..90c7dc7632c5 100644 --- a/Documentation/devicetree/bindings/power/supply/qcom,pmi8998-charger.yaml +++ b/Documentation/devicetree/bindings/power/supply/qcom,pmi8998-charger.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm PMI8998/PM660 Switch-Mode Battery Charger "2" maintainers: - - Caleb Connolly <caleb.connolly@linaro.org> + - Casey Connolly <casey.connolly@linaro.org> properties: compatible: diff --git a/Documentation/devicetree/bindings/power/supply/x-powers,axp20x-battery-power-supply.yaml b/Documentation/devicetree/bindings/power/supply/x-powers,axp20x-battery-power-supply.yaml index 5ccd375eb294..3504c76a01d8 100644 --- a/Documentation/devicetree/bindings/power/supply/x-powers,axp20x-battery-power-supply.yaml +++ b/Documentation/devicetree/bindings/power/supply/x-powers,axp20x-battery-power-supply.yaml @@ -14,9 +14,6 @@ maintainers: - Chen-Yu Tsai <wens@csie.org> - Sebastian Reichel <sre@kernel.org> -allOf: - - $ref: power-supply.yaml# - properties: compatible: oneOf: @@ -35,7 +32,24 @@ properties: this gauge. $ref: /schemas/types.yaml#/definitions/phandle + x-powers,no-thermistor: + type: boolean + description: Indicates that no thermistor is connected to the TS pin + required: - compatible +allOf: + - $ref: power-supply.yaml# + - if: + not: + properties: + compatible: + contains: + enum: + - x-powers,axp717-battery-power-supply + then: + properties: + x-powers,no-thermistor: false + additionalProperties: false diff --git a/Documentation/devicetree/bindings/power/wakeup-source.txt b/Documentation/devicetree/bindings/power/wakeup-source.txt index 27f1797be963..66bb016305f9 100644 --- a/Documentation/devicetree/bindings/power/wakeup-source.txt +++ b/Documentation/devicetree/bindings/power/wakeup-source.txt @@ -23,7 +23,7 @@ List of legacy properties and respective binding document 1. "gpio-key,wakeup" Documentation/devicetree/bindings/input/gpio-keys{,-polled}.txt 2. "has-tpo" Documentation/devicetree/bindings/rtc/rtc-opal.txt -3. "linux,wakeup" Documentation/devicetree/bindings/input/gpio-matrix-keypad.txt +3. "linux,wakeup" Documentation/devicetree/bindings/input/gpio-matrix-keypad.yaml Documentation/devicetree/bindings/mfd/tc3589x.txt Documentation/devicetree/bindings/input/touchscreen/ti,ads7843.yaml 4. "linux,keypad-wakeup" Documentation/devicetree/bindings/input/qcom,pm8921-keypad.yaml diff --git a/Documentation/devicetree/bindings/powerpc/fsl/dma.txt b/Documentation/devicetree/bindings/powerpc/fsl/dma.txt deleted file mode 100644 index c11ad5c6db21..000000000000 --- a/Documentation/devicetree/bindings/powerpc/fsl/dma.txt +++ /dev/null @@ -1,204 +0,0 @@ -* Freescale DMA Controllers - -** Freescale Elo DMA Controller - This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx - series chips such as mpc8315, mpc8349, mpc8379 etc. - -Required properties: - -- compatible : must include "fsl,elo-dma" -- reg : DMA General Status Register, i.e. DGSR which contains - status for all the 4 DMA channels -- ranges : describes the mapping between the address space of the - DMA channels and the address space of the DMA controller -- cell-index : controller index. 0 for controller @ 0x8100 -- interrupts : interrupt specifier for DMA IRQ - -- DMA channel nodes: - - compatible : must include "fsl,elo-dma-channel" - However, see note below. - - reg : DMA channel specific registers - - cell-index : DMA channel index starts at 0. - -Optional properties: - - interrupts : interrupt specifier for DMA channel IRQ - (on 83xx this is expected to be identical to - the interrupts property of the parent node) - -Example: - dma@82a8 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,mpc8349-dma", "fsl,elo-dma"; - reg = <0x82a8 4>; - ranges = <0 0x8100 0x1a4>; - interrupt-parent = <&ipic>; - interrupts = <71 8>; - cell-index = <0>; - dma-channel@0 { - compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; - cell-index = <0>; - reg = <0 0x80>; - interrupt-parent = <&ipic>; - interrupts = <71 8>; - }; - dma-channel@80 { - compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; - cell-index = <1>; - reg = <0x80 0x80>; - interrupt-parent = <&ipic>; - interrupts = <71 8>; - }; - dma-channel@100 { - compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; - cell-index = <2>; - reg = <0x100 0x80>; - interrupt-parent = <&ipic>; - interrupts = <71 8>; - }; - dma-channel@180 { - compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; - cell-index = <3>; - reg = <0x180 0x80>; - interrupt-parent = <&ipic>; - interrupts = <71 8>; - }; - }; - -** Freescale EloPlus DMA Controller - This is a 4-channel DMA controller with extended addresses and chaining, - mainly used in Freescale mpc85xx/86xx, Pxxx and BSC series chips, such as - mpc8540, mpc8641 p4080, bsc9131 etc. - -Required properties: - -- compatible : must include "fsl,eloplus-dma" -- reg : DMA General Status Register, i.e. DGSR which contains - status for all the 4 DMA channels -- cell-index : controller index. 0 for controller @ 0x21000, - 1 for controller @ 0xc000 -- ranges : describes the mapping between the address space of the - DMA channels and the address space of the DMA controller - -- DMA channel nodes: - - compatible : must include "fsl,eloplus-dma-channel" - However, see note below. - - cell-index : DMA channel index starts at 0. - - reg : DMA channel specific registers - - interrupts : interrupt specifier for DMA channel IRQ - -Example: - dma@21300 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma"; - reg = <0x21300 4>; - ranges = <0 0x21100 0x200>; - cell-index = <0>; - dma-channel@0 { - compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel"; - reg = <0 0x80>; - cell-index = <0>; - interrupt-parent = <&mpic>; - interrupts = <20 2>; - }; - dma-channel@80 { - compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel"; - reg = <0x80 0x80>; - cell-index = <1>; - interrupt-parent = <&mpic>; - interrupts = <21 2>; - }; - dma-channel@100 { - compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel"; - reg = <0x100 0x80>; - cell-index = <2>; - interrupt-parent = <&mpic>; - interrupts = <22 2>; - }; - dma-channel@180 { - compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel"; - reg = <0x180 0x80>; - cell-index = <3>; - interrupt-parent = <&mpic>; - interrupts = <23 2>; - }; - }; - -** Freescale Elo3 DMA Controller - DMA controller which has same function as EloPlus except that Elo3 has 8 - channels while EloPlus has only 4, it is used in Freescale Txxx and Bxxx - series chips, such as t1040, t4240, b4860. - -Required properties: - -- compatible : must include "fsl,elo3-dma" -- reg : contains two entries for DMA General Status Registers, - i.e. DGSR0 which includes status for channel 1~4, and - DGSR1 for channel 5~8 -- ranges : describes the mapping between the address space of the - DMA channels and the address space of the DMA controller - -- DMA channel nodes: - - compatible : must include "fsl,eloplus-dma-channel" - - reg : DMA channel specific registers - - interrupts : interrupt specifier for DMA channel IRQ - -Example: -dma@100300 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,elo3-dma"; - reg = <0x100300 0x4>, - <0x100600 0x4>; - ranges = <0x0 0x100100 0x500>; - dma-channel@0 { - compatible = "fsl,eloplus-dma-channel"; - reg = <0x0 0x80>; - interrupts = <28 2 0 0>; - }; - dma-channel@80 { - compatible = "fsl,eloplus-dma-channel"; - reg = <0x80 0x80>; - interrupts = <29 2 0 0>; - }; - dma-channel@100 { - compatible = "fsl,eloplus-dma-channel"; - reg = <0x100 0x80>; - interrupts = <30 2 0 0>; - }; - dma-channel@180 { - compatible = "fsl,eloplus-dma-channel"; - reg = <0x180 0x80>; - interrupts = <31 2 0 0>; - }; - dma-channel@300 { - compatible = "fsl,eloplus-dma-channel"; - reg = <0x300 0x80>; - interrupts = <76 2 0 0>; - }; - dma-channel@380 { - compatible = "fsl,eloplus-dma-channel"; - reg = <0x380 0x80>; - interrupts = <77 2 0 0>; - }; - dma-channel@400 { - compatible = "fsl,eloplus-dma-channel"; - reg = <0x400 0x80>; - interrupts = <78 2 0 0>; - }; - dma-channel@480 { - compatible = "fsl,eloplus-dma-channel"; - reg = <0x480 0x80>; - interrupts = <79 2 0 0>; - }; -}; - -Note on DMA channel compatible properties: The compatible property must say -"fsl,elo-dma-channel" or "fsl,eloplus-dma-channel" to be used by the Elo DMA -driver (fsldma). Any DMA channel used by fsldma cannot be used by another -DMA driver, such as the SSI sound drivers for the MPC8610. Therefore, any DMA -channel that should be used for another driver should not use -"fsl,elo-dma-channel" or "fsl,eloplus-dma-channel". For the SSI drivers, for -example, the compatible property should be "fsl,ssi-dma-channel". See ssi.txt -for more information. diff --git a/Documentation/devicetree/bindings/powerpc/fsl/mcu-mpc8349emitx.txt b/Documentation/devicetree/bindings/powerpc/fsl/mcu-mpc8349emitx.txt deleted file mode 100644 index 37f91fa57654..000000000000 --- a/Documentation/devicetree/bindings/powerpc/fsl/mcu-mpc8349emitx.txt +++ /dev/null @@ -1,17 +0,0 @@ -Freescale MPC8349E-mITX-compatible Power Management Micro Controller Unit (MCU) - -Required properties: -- compatible : "fsl,<mcu-chip>-<board>", "fsl,mcu-mpc8349emitx". -- reg : should specify I2C address (0x0a). -- #gpio-cells : should be 2. -- gpio-controller : should be present. - -Example: - -mcu@a { - #gpio-cells = <2>; - compatible = "fsl,mc9s08qg8-mpc8349emitx", - "fsl,mcu-mpc8349emitx"; - reg = <0x0a>; - gpio-controller; -}; diff --git a/Documentation/devicetree/bindings/powerpc/fsl/pmc.txt b/Documentation/devicetree/bindings/powerpc/fsl/pmc.txt deleted file mode 100644 index 07256b7ffcaa..000000000000 --- a/Documentation/devicetree/bindings/powerpc/fsl/pmc.txt +++ /dev/null @@ -1,63 +0,0 @@ -* Power Management Controller - -Properties: -- compatible: "fsl,<chip>-pmc". - - "fsl,mpc8349-pmc" should be listed for any chip whose PMC is - compatible. "fsl,mpc8313-pmc" should also be listed for any chip - whose PMC is compatible, and implies deep-sleep capability. - - "fsl,mpc8548-pmc" should be listed for any chip whose PMC is - compatible. "fsl,mpc8536-pmc" should also be listed for any chip - whose PMC is compatible, and implies deep-sleep capability. - - "fsl,mpc8641d-pmc" should be listed for any chip whose PMC is - compatible; all statements below that apply to "fsl,mpc8548-pmc" also - apply to "fsl,mpc8641d-pmc". - - Compatibility does not include bit assignments in SCCR/PMCDR/DEVDISR; these - bit assignments are indicated via the sleep specifier in each device's - sleep property. - -- reg: For devices compatible with "fsl,mpc8349-pmc", the first resource - is the PMC block, and the second resource is the Clock Configuration - block. - - For devices compatible with "fsl,mpc8548-pmc", the first resource - is a 32-byte block beginning with DEVDISR. - -- interrupts: For "fsl,mpc8349-pmc"-compatible devices, the first - resource is the PMC block interrupt. - -- fsl,mpc8313-wakeup-timer: For "fsl,mpc8313-pmc"-compatible devices, - this is a phandle to an "fsl,gtm" node on which timer 4 can be used as - a wakeup source from deep sleep. - -Sleep specifiers: - - fsl,mpc8349-pmc: Sleep specifiers consist of one cell. For each bit - that is set in the cell, the corresponding bit in SCCR will be saved - and cleared on suspend, and restored on resume. This sleep controller - supports disabling and resuming devices at any time. - - fsl,mpc8536-pmc: Sleep specifiers consist of three cells, the third of - which will be ORed into PMCDR upon suspend, and cleared from PMCDR - upon resume. The first two cells are as described for fsl,mpc8578-pmc. - This sleep controller only supports disabling devices during system - sleep, or permanently. - - fsl,mpc8548-pmc: Sleep specifiers consist of one or two cells, the - first of which will be ORed into DEVDISR (and the second into - DEVDISR2, if present -- this cell should be zero or absent if the - hardware does not have DEVDISR2) upon a request for permanent device - disabling. This sleep controller does not support configuring devices - to disable during system sleep (unless supported by another compatible - match), or dynamically. - -Example: - - power@b00 { - compatible = "fsl,mpc8313-pmc", "fsl,mpc8349-pmc"; - reg = <0xb00 0x100 0xa00 0x100>; - interrupts = <80 8>; - }; diff --git a/Documentation/devicetree/bindings/powerpc/fsl/pmc.yaml b/Documentation/devicetree/bindings/powerpc/fsl/pmc.yaml new file mode 100644 index 000000000000..276ece7f01db --- /dev/null +++ b/Documentation/devicetree/bindings/powerpc/fsl/pmc.yaml @@ -0,0 +1,152 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/powerpc/fsl/pmc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Power Management Controller + +maintainers: + - J. Neuschäfer <j.ne@posteo.net> + +description: | + The Power Management Controller in several MPC8xxx SoCs helps save power by + controlling chip-wide low-power states as well as peripheral clock gating. + + Sleep of peripheral devices is configured by the `sleep` property, for + example `sleep = <&pmc 0x00000030>`. Any cells after the &pmc phandle are + called a sleep specifier. + + For "fsl,mpc8349-pmc", sleep specifiers consist of one cell. For each bit that + is set in the cell, the corresponding bit in SCCR will be saved and cleared + on suspend, and restored on resume. This sleep controller supports disabling + and resuming devices at any time. + + For "fsl,mpc8536-pmc", sleep specifiers consist of three cells, the third of + which will be ORed into PMCDR upon suspend, and cleared from PMCDR upon + resume. The first two cells are as described for fsl,mpc8548-pmc. This + sleep controller only supports disabling devices during system sleep, or + permanently. + + For "fsl,mpc8548-pmc" or "fsl,mpc8641d-pmc", Sleep specifiers consist of one + or two cells, the first of which will be ORed into DEVDISR (and the second + into DEVDISR2, if present -- this cell should be zero or absent if the + hardware does not have DEVDISR2) upon a request for permanent device + disabling. This sleep controller does not support configuring devices to + disable during system sleep (unless supported by another compatible match), + or dynamically. + +properties: + compatible: + oneOf: + - items: + - const: fsl,mpc8315-pmc + - const: fsl,mpc8313-pmc + - const: fsl,mpc8349-pmc + + - items: + - enum: + - fsl,mpc8313-pmc + - fsl,mpc8323-pmc + - fsl,mpc8360-pmc + - fsl,mpc8377-pmc + - fsl,mpc8378-pmc + - fsl,mpc8379-pmc + - const: fsl,mpc8349-pmc + + - items: + - const: fsl,p1022-pmc + - const: fsl,mpc8536-pmc + - const: fsl,mpc8548-pmc + + - items: + - enum: + - fsl,mpc8536-pmc + - fsl,mpc8568-pmc + - fsl,mpc8569-pmc + - const: fsl,mpc8548-pmc + + - enum: + - fsl,mpc8548-pmc + - fsl,mpc8641d-pmc + + description: | + "fsl,mpc8349-pmc" should be listed for any chip whose PMC is + compatible. "fsl,mpc8313-pmc" should also be listed for any chip + whose PMC is compatible, and implies deep-sleep capability. + + "fsl,mpc8548-pmc" should be listed for any chip whose PMC is + compatible. "fsl,mpc8536-pmc" should also be listed for any chip + whose PMC is compatible, and implies deep-sleep capability. + + "fsl,mpc8641d-pmc" should be listed for any chip whose PMC is + compatible; all statements below that apply to "fsl,mpc8548-pmc" also + apply to "fsl,mpc8641d-pmc". + + Compatibility does not include bit assignments in SCCR/PMCDR/DEVDISR; these + bit assignments are indicated via the sleep specifier in each device's + sleep property. + + reg: + minItems: 1 + maxItems: 2 + + interrupts: + maxItems: 1 + + fsl,mpc8313-wakeup-timer: + $ref: /schemas/types.yaml#/definitions/phandle + description: + For "fsl,mpc8313-pmc"-compatible devices, this is a phandle to an + "fsl,gtm" node on which timer 4 can be used as a wakeup source from deep + sleep. + +allOf: + - if: + properties: + compatible: + contains: + const: fsl,mpc8349-pmc + then: + properties: + reg: + items: + - description: PMC block + - description: Clock Configuration block + + - if: + properties: + compatible: + contains: + enum: + - fsl,mpc8548-pmc + - fsl,mpc8641d-pmc + then: + properties: + reg: + items: + - description: 32-byte block beginning with DEVDISR + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + pmc: power@b00 { + compatible = "fsl,mpc8377-pmc", "fsl,mpc8349-pmc"; + reg = <0xb00 0x100>, <0xa00 0x100>; + interrupts = <80 IRQ_TYPE_LEVEL_LOW>; + }; + + - | + power@e0070 { + compatible = "fsl,mpc8548-pmc"; + reg = <0xe0070 0x20>; + }; + +... diff --git a/Documentation/devicetree/bindings/pps/pps-gpio.yaml b/Documentation/devicetree/bindings/pps/pps-gpio.yaml index fd4adfa8d2d4..383a838744eb 100644 --- a/Documentation/devicetree/bindings/pps/pps-gpio.yaml +++ b/Documentation/devicetree/bindings/pps/pps-gpio.yaml @@ -36,14 +36,14 @@ additionalProperties: false examples: - | - #include <dt-bindings/gpio/gpio.h> - - pps { - compatible = "pps-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pps>; - gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; - assert-falling-edge; - echo-gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>; - echo-active-ms = <100>; - }; + #include <dt-bindings/gpio/gpio.h> + + pps { + compatible = "pps-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pps>; + gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; + assert-falling-edge; + echo-gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>; + echo-active-ms = <100>; + }; diff --git a/Documentation/devicetree/bindings/pwm/adi,axi-pwmgen.yaml b/Documentation/devicetree/bindings/pwm/adi,axi-pwmgen.yaml index 45e112d0efb4..5575c58357d6 100644 --- a/Documentation/devicetree/bindings/pwm/adi,axi-pwmgen.yaml +++ b/Documentation/devicetree/bindings/pwm/adi,axi-pwmgen.yaml @@ -30,11 +30,19 @@ properties: const: 3 clocks: - maxItems: 1 + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + items: + - const: axi + - const: ext required: - reg - clocks + - clock-names unevaluatedProperties: false @@ -43,6 +51,7 @@ examples: pwm@44b00000 { compatible = "adi,axi-pwmgen-2.00.a"; reg = <0x44b00000 0x1000>; - clocks = <&spi_clk>; + clocks = <&fpga_clk>, <&spi_clk>; + clock-names = "axi", "ext"; #pwm-cells = <3>; }; diff --git a/Documentation/devicetree/bindings/pwm/imx-tpm-pwm.yaml b/Documentation/devicetree/bindings/pwm/imx-tpm-pwm.yaml index ac0a35bf8648..d5a9340ff920 100644 --- a/Documentation/devicetree/bindings/pwm/imx-tpm-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/imx-tpm-pwm.yaml @@ -23,8 +23,15 @@ properties: const: 3 compatible: - enum: - - fsl,imx7ulp-pwm + oneOf: + - enum: + - fsl,imx7ulp-pwm + - items: + - enum: + - fsl,imx93-pwm + - fsl,imx94-pwm + - fsl,imx95-pwm + - const: fsl,imx7ulp-pwm reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/pwm/loongson,ls7a-pwm.yaml b/Documentation/devicetree/bindings/pwm/loongson,ls7a-pwm.yaml new file mode 100644 index 000000000000..5d64fb40a0d6 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/loongson,ls7a-pwm.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/loongson,ls7a-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Loongson PWM Controller + +maintainers: + - Binbin Zhou <zhoubinbin@loongson.cn> + +description: + The Loongson PWM has one pulse width output signal and one pulse input + signal to be measured. + It can be found on Loongson-2K series cpus and Loongson LS7A bridge chips. + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + oneOf: + - const: loongson,ls7a-pwm + - items: + - enum: + - loongson,ls2k0500-pwm + - loongson,ls2k1000-pwm + - loongson,ls2k2000-pwm + - const: loongson,ls7a-pwm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + '#pwm-cells': + description: + The first cell must have a value of 0, which specifies the PWM output signal; + The second cell is the period in nanoseconds; + The third cell flag supported by this binding is PWM_POLARITY_INVERTED. + const: 3 + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/clock/loongson,ls2k-clk.h> + + pwm@1fe22000 { + compatible = "loongson,ls2k1000-pwm", "loongson,ls7a-pwm"; + reg = <0x1fe22000 0x10>; + interrupt-parent = <&liointc0>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk LOONGSON2_APB_CLK>; + #pwm-cells = <3>; + }; diff --git a/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml b/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml index 195e4371196b..68ef30414325 100644 --- a/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml +++ b/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml @@ -27,6 +27,7 @@ properties: - const: mediatek,mt8173-disp-pwm - items: - enum: + - mediatek,mt6893-disp-pwm - mediatek,mt8186-disp-pwm - mediatek,mt8188-disp-pwm - mediatek,mt8192-disp-pwm diff --git a/Documentation/devicetree/bindings/pwm/nxp,mc33xs2410.yaml b/Documentation/devicetree/bindings/pwm/nxp,mc33xs2410.yaml new file mode 100644 index 000000000000..1729fe5c3dfb --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/nxp,mc33xs2410.yaml @@ -0,0 +1,118 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/nxp,mc33xs2410.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: High-side switch MC33XS2410 + +maintainers: + - Dimitri Fedrau <dima.fedrau@gmail.com> + +allOf: + - $ref: pwm.yaml# + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + const: nxp,mc33xs2410 + + reg: + maxItems: 1 + + spi-max-frequency: + maximum: 10000000 + + spi-cpha: true + + spi-cs-setup-delay-ns: + minimum: 100 + default: 100 + + spi-cs-hold-delay-ns: + minimum: 10 + default: 10 + + spi-cs-inactive-delay-ns: + minimum: 300 + default: 300 + + reset-gpios: + description: + GPIO connected to the active low reset pin. + maxItems: 1 + + "#pwm-cells": + const: 3 + + pwm-names: + items: + - const: di0 + - const: di1 + - const: di2 + - const: di3 + + pwms: + description: + Direct inputs(di0-3) are used to directly turn-on or turn-off the + outputs. + maxItems: 4 + + interrupts: + maxItems: 1 + + clocks: + description: + The external clock can be used if the internal clock doesn't meet + timing requirements over temperature and voltage operating range. + maxItems: 1 + + vdd-supply: + description: + Logic supply voltage + + vspi-supply: + description: + Supply voltage for SPI + + vpwr-supply: + description: + Power switch supply + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interrupt-controller/irq.h> + spi { + #address-cells = <1>; + #size-cells = <0>; + + pwm@0 { + compatible = "nxp,mc33xs2410"; + reg = <0x0>; + spi-max-frequency = <4000000>; + spi-cpha; + spi-cs-setup-delay-ns = <100>; + spi-cs-hold-delay-ns = <10>; + spi-cs-inactive-delay-ns = <300>; + reset-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; + #pwm-cells = <3>; + pwm-names = "di0", "di1", "di2", "di3"; + pwms = <&pwm0 0 1000000>, + <&pwm1 0 1000000>, + <&pwm2 0 1000000>, + <&pwm3 0 1000000>; + interrupt-parent = <&gpio0>; + interrupts = <31 IRQ_TYPE_LEVEL_LOW>; + clocks = <&clk_ext_fixed>; + vdd-supply = <®_3v3>; + vspi-supply = <®_3v3>; + vpwr-supply = <®_24v0>; + }; + }; diff --git a/Documentation/devicetree/bindings/pwm/pwm-nexus-node.yaml b/Documentation/devicetree/bindings/pwm/pwm-nexus-node.yaml new file mode 100644 index 000000000000..3b40e271fe8d --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/pwm-nexus-node.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/pwm-nexus-node.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: PWM Nexus node properties + +description: > + Platforms can have a standardized connector/expansion slot that exposes PWMs + signals to expansion boards. + + A nexus node allows to remap a phandle list in a consumer node through a + connector node in a generic way. With this remapping, the consumer node needs + to know only about the nexus node. Resources behind the nexus node are + decoupled by the nexus node itself. + +maintainers: + - Herve Codina <herve.codina@bootlin.com> + +select: true + +properties: + '#pwm-cells': true + + pwm-map: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + + pwm-map-mask: + $ref: /schemas/types.yaml#/definitions/uint32-array + + pwm-map-pass-thru: + $ref: /schemas/types.yaml#/definitions/uint32-array + +dependentRequired: + pwm-map: ['#pwm-cells'] + pwm-map-mask: [ pwm-map ] + pwm-map-pass-thru: [ pwm-map ] + +additionalProperties: true + +examples: + - | + pwm1: pwm@100 { + reg = <0x100 0x10>; + #pwm-cells = <3>; + }; + + pwm2: pwm@200 { + reg = <0x200 0x10>; + #pwm-cells = <3>; + }; + + connector: connector { + #pwm-cells = <3>; + pwm-map = <0 0 0 &pwm1 1 0 0>, + <1 0 0 &pwm2 4 0 0>, + <2 0 0 &pwm1 3 0 0>; + pwm-map-mask = <0xffffffff 0x0 0x0>; + pwm-map-pass-thru = <0x0 0xffffffff 0xffffffff>; + }; + + device { + pwms = <&connector 1 57000 0>; + }; diff --git a/Documentation/devicetree/bindings/pwm/pwm-rockchip.yaml b/Documentation/devicetree/bindings/pwm/pwm-rockchip.yaml index 65bfb492b3a4..c8cdfb723336 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-rockchip.yaml +++ b/Documentation/devicetree/bindings/pwm/pwm-rockchip.yaml @@ -30,6 +30,8 @@ properties: - enum: - rockchip,px30-pwm - rockchip,rk3308-pwm + - rockchip,rk3528-pwm + - rockchip,rk3562-pwm - rockchip,rk3568-pwm - rockchip,rk3588-pwm - rockchip,rv1126-pwm diff --git a/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml b/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml new file mode 100644 index 000000000000..13b807765a30 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml @@ -0,0 +1,378 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/renesas,rzg2l-gpt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/G2L General PWM Timer (GPT) + +maintainers: + - Biju Das <biju.das.jz@bp.renesas.com> + +description: | + RZ/G2L General PWM Timer (GPT) composed of 8 channels with 32-bit timer + (GPT32E). It supports the following functions + * 32 bits x 8 channels. + * Up-counting or down-counting (saw waves) or up/down-counting + (triangle waves) for each counter. + * Clock sources independently selectable for each channel. + * Two I/O pins per channel. + * Two output compare/input capture registers per channel. + * For the two output compare/input capture registers of each channel, + four registers are provided as buffer registers and are capable of + operating as comparison registers when buffering is not in use. + * In output compare operation, buffer switching can be at crests or + troughs, enabling the generation of laterally asymmetric PWM waveforms. + * Registers for setting up frame cycles in each channel (with capability + for generating interrupts at overflow or underflow) + * Generation of dead times in PWM operation. + * Synchronous starting, stopping and clearing counters for arbitrary + channels. + * Starting, stopping, clearing and up/down counters in response to input + level comparison. + * Starting, clearing, stopping and up/down counters in response to a + maximum of four external triggers. + * Output pin disable function by dead time error and detected + short-circuits between output pins. + * A/D converter start triggers can be generated (GPT32E0 to GPT32E3) + * Enables the noise filter for input capture and external trigger + operation. + + The below pwm channels are supported. + pwm0 - GPT32E0.GTIOC0A channel + pwm1 - GPT32E0.GTIOC0B channel + pwm2 - GPT32E1.GTIOC1A channel + pwm3 - GPT32E1.GTIOC1B channel + pwm4 - GPT32E2.GTIOC2A channel + pwm5 - GPT32E2.GTIOC2B channel + pwm6 - GPT32E3.GTIOC3A channel + pwm7 - GPT32E3.GTIOC3B channel + pwm8 - GPT32E4.GTIOC4A channel + pwm9 - GPT32E4.GTIOC4B channel + pwm10 - GPT32E5.GTIOC5A channel + pwm11 - GPT32E5.GTIOC5B channel + pwm12 - GPT32E6.GTIOC6A channel + pwm13 - GPT32E6.GTIOC6B channel + pwm14 - GPT32E7.GTIOC7A channel + pwm15 - GPT32E7.GTIOC7B channel + +properties: + compatible: + items: + - enum: + - renesas,r9a07g044-gpt # RZ/G2{L,LC} + - renesas,r9a07g054-gpt # RZ/V2L + - const: renesas,rzg2l-gpt + + reg: + maxItems: 1 + + '#pwm-cells': + const: 3 + + interrupts: + items: + - description: GPT32E0.GTCCRA input capture/compare match + - description: GPT32E0.GTCCRB input capture/compare + - description: GPT32E0.GTCCRC compare match + - description: GPT32E0.GTCCRD compare match + - description: GPT32E0.GTCCRE compare match + - description: GPT32E0.GTCCRF compare match + - description: GPT32E0.GTADTRA compare match + - description: GPT32E0.GTADTRB compare match + - description: GPT32E0.GTCNT overflow/GTPR compare match + - description: GPT32E0.GTCNT underflow + - description: GPT32E1.GTCCRA input capture/compare match + - description: GPT32E1.GTCCRB input capture/compare + - description: GPT32E1.GTCCRC compare match + - description: GPT32E1.GTCCRD compare match + - description: GPT32E1.GTCCRE compare match + - description: GPT32E1.GTCCRF compare match + - description: GPT32E1.GTADTRA compare match + - description: GPT32E1.GTADTRB compare match + - description: GPT32E1.GTCNT overflow/GTPR compare match + - description: GPT32E1.GTCNT underflow + - description: GPT32E2.GTCCRA input capture/compare match + - description: GPT32E2.GTCCRB input capture/compare + - description: GPT32E2.GTCCRC compare match + - description: GPT32E2.GTCCRD compare match + - description: GPT32E2.GTCCRE compare match + - description: GPT32E2.GTCCRF compare match + - description: GPT32E2.GTADTRA compare match + - description: GPT32E2.GTADTRB compare match + - description: GPT32E2.GTCNT overflow/GTPR compare match + - description: GPT32E2.GTCNT underflow + - description: GPT32E3.GTCCRA input capture/compare match + - description: GPT32E3.GTCCRB input capture/compare + - description: GPT32E3.GTCCRC compare match + - description: GPT32E3.GTCCRD compare match + - description: GPT32E3.GTCCRE compare match + - description: GPT32E3.GTCCRF compare match + - description: GPT32E3.GTADTRA compare match + - description: GPT32E3.GTADTRB compare match + - description: GPT32E3.GTCNT overflow/GTPR compare match + - description: GPT32E3.GTCNT underflow + - description: GPT32E4.GTCCRA input capture/compare match + - description: GPT32E4.GTCCRB input capture/compare + - description: GPT32E4.GTCCRC compare match + - description: GPT32E4.GTCCRD compare match + - description: GPT32E4.GTCCRE compare match + - description: GPT32E4.GTCCRF compare match + - description: GPT32E4.GTADTRA compare match + - description: GPT32E4.GTADTRB compare match + - description: GPT32E4.GTCNT overflow/GTPR compare match + - description: GPT32E4.GTCNT underflow + - description: GPT32E5.GTCCRA input capture/compare match + - description: GPT32E5.GTCCRB input capture/compare + - description: GPT32E5.GTCCRC compare match + - description: GPT32E5.GTCCRD compare match + - description: GPT32E5.GTCCRE compare match + - description: GPT32E5.GTCCRF compare match + - description: GPT32E5.GTADTRA compare match + - description: GPT32E5.GTADTRB compare match + - description: GPT32E5.GTCNT overflow/GTPR compare match + - description: GPT32E5.GTCNT underflow + - description: GPT32E6.GTCCRA input capture/compare match + - description: GPT32E6.GTCCRB input capture/compare + - description: GPT32E6.GTCCRC compare match + - description: GPT32E6.GTCCRD compare match + - description: GPT32E6.GTCCRE compare match + - description: GPT32E6.GTCCRF compare match + - description: GPT32E6.GTADTRA compare match + - description: GPT32E6.GTADTRB compare match + - description: GPT32E6.GTCNT overflow/GTPR compare match + - description: GPT32E6.GTCNT underflow + - description: GPT32E7.GTCCRA input capture/compare match + - description: GPT32E7.GTCCRB input capture/compare + - description: GPT32E7.GTCCRC compare match + - description: GPT32E7.GTCCRD compare match + - description: GPT32E7.GTCCRE compare match + - description: GPT32E7.GTCCRF compare match + - description: GPT32E7.GTADTRA compare match + - description: GPT32E7.GTADTRB compare match + - description: GPT32E7.GTCNT overflow/GTPR compare match + - description: GPT32E7.GTCNT underflow + + interrupt-names: + items: + - const: ccmpa0 + - const: ccmpb0 + - const: cmpc0 + - const: cmpd0 + - const: cmpe0 + - const: cmpf0 + - const: adtrga0 + - const: adtrgb0 + - const: ovf0 + - const: unf0 + - const: ccmpa1 + - const: ccmpb1 + - const: cmpc1 + - const: cmpd1 + - const: cmpe1 + - const: cmpf1 + - const: adtrga1 + - const: adtrgb1 + - const: ovf1 + - const: unf1 + - const: ccmpa2 + - const: ccmpb2 + - const: cmpc2 + - const: cmpd2 + - const: cmpe2 + - const: cmpf2 + - const: adtrga2 + - const: adtrgb2 + - const: ovf2 + - const: unf2 + - const: ccmpa3 + - const: ccmpb3 + - const: cmpc3 + - const: cmpd3 + - const: cmpe3 + - const: cmpf3 + - const: adtrga3 + - const: adtrgb3 + - const: ovf3 + - const: unf3 + - const: ccmpa4 + - const: ccmpb4 + - const: cmpc4 + - const: cmpd4 + - const: cmpe4 + - const: cmpf4 + - const: adtrga4 + - const: adtrgb4 + - const: ovf4 + - const: unf4 + - const: ccmpa5 + - const: ccmpb5 + - const: cmpc5 + - const: cmpd5 + - const: cmpe5 + - const: cmpf5 + - const: adtrga5 + - const: adtrgb5 + - const: ovf5 + - const: unf5 + - const: ccmpa6 + - const: ccmpb6 + - const: cmpc6 + - const: cmpd6 + - const: cmpe6 + - const: cmpf6 + - const: adtrga6 + - const: adtrgb6 + - const: ovf6 + - const: unf6 + - const: ccmpa7 + - const: ccmpb7 + - const: cmpc7 + - const: cmpd7 + - const: cmpe7 + - const: cmpf7 + - const: adtrga7 + - const: adtrgb7 + - const: ovf7 + - const: unf7 + + clocks: + maxItems: 1 + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - power-domains + - resets + +allOf: + - $ref: pwm.yaml# + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/r9a07g044-cpg.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + gpt: pwm@10048000 { + compatible = "renesas,r9a07g044-gpt", "renesas,rzg2l-gpt"; + reg = <0x10048000 0x800>; + interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 219 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 220 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 221 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 222 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 223 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 224 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 225 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 226 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 227 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 231 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 232 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 233 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 234 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 235 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 237 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 238 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 239 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 240 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 244 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 245 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 246 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 247 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 248 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 249 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 251 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 252 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 253 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 257 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 258 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 259 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 260 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 261 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 262 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 265 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 270 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 272 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 273 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 274 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 275 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 276 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 278 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 283 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 284 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 285 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 286 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 287 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 288 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 290 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 292 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 300 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 301 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 302 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 303 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 304 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 305 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 310 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 311 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 312 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 313 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 316 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 317 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ccmpa0", "ccmpb0", "cmpc0", "cmpd0", + "cmpe0", "cmpf0", "adtrga0", "adtrgb0", + "ovf0", "unf0", + "ccmpa1", "ccmpb1", "cmpc1", "cmpd1", + "cmpe1", "cmpf1", "adtrga1", "adtrgb1", + "ovf1", "unf1", + "ccmpa2", "ccmpb2", "cmpc2", "cmpd2", + "cmpe2", "cmpf2", "adtrga2", "adtrgb2", + "ovf2", "unf2", + "ccmpa3", "ccmpb3", "cmpc3", "cmpd3", + "cmpe3", "cmpf3", "adtrga3", "adtrgb3", + "ovf3", "unf3", + "ccmpa4", "ccmpb4", "cmpc4", "cmpd4", + "cmpe4", "cmpf4", "adtrga4", "adtrgb4", + "ovf4", "unf4", + "ccmpa5", "ccmpb5", "cmpc5", "cmpd5", + "cmpe5", "cmpf5", "adtrga5", "adtrgb5", + "ovf5", "unf5", + "ccmpa6", "ccmpb6", "cmpc6", "cmpd6", + "cmpe6", "cmpf6", "adtrga6", "adtrgb6", + "ovf6", "unf6", + "ccmpa7", "ccmpb7", "cmpc7", "cmpd7", + "cmpe7", "cmpf7", "adtrga7", "adtrgb7", + "ovf7", "unf7"; + clocks = <&cpg CPG_MOD R9A07G044_GPT_PCLK>; + power-domains = <&cpg>; + resets = <&cpg R9A07G044_GPT_RST_C>; + #pwm-cells = <3>; + }; diff --git a/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.yaml b/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.yaml index a4dfa09344dd..f85ee5d20ccb 100644 --- a/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.yaml @@ -9,15 +9,6 @@ title: Renesas R-Car Timer Pulse Unit PWM Controller maintainers: - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> -select: - properties: - compatible: - contains: - const: renesas,tpu - required: - - compatible - - '#pwm-cells' - properties: compatible: items: diff --git a/Documentation/devicetree/bindings/pwm/sophgo,sg2042-pwm.yaml b/Documentation/devicetree/bindings/pwm/sophgo,sg2042-pwm.yaml new file mode 100644 index 000000000000..bbb6326d47d7 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/sophgo,sg2042-pwm.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/sophgo,sg2042-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo SG2042 PWM controller + +maintainers: + - Chen Wang <unicorn_wang@outlook.com> + +description: + This controller contains 4 channels which can generate PWM waveforms. + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + const: sophgo,sg2042-pwm + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: apb + + resets: + maxItems: 1 + + "#pwm-cells": + const: 3 + +required: + - compatible + - reg + - clocks + - clock-names + - resets + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/reset/sophgo,sg2042-reset.h> + + pwm@7f006000 { + compatible = "sophgo,sg2042-pwm"; + reg = <0x7f006000 0x1000>; + #pwm-cells = <3>; + clocks = <&clock 67>; + clock-names = "apb"; + resets = <&rstgen RST_PWM>; + }; diff --git a/Documentation/devicetree/bindings/pwm/via,vt8500-pwm.yaml b/Documentation/devicetree/bindings/pwm/via,vt8500-pwm.yaml new file mode 100644 index 000000000000..d9146ad715ba --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/via,vt8500-pwm.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/via,vt8500-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: VIA/Wondermedia VT8500/WM8xxx series SoC PWM controller + +maintainers: + - Alexey Charkov <alchark@gmail.com> + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + items: + - const: via,vt8500-pwm + + reg: + maxItems: 1 + + '#pwm-cells': + const: 3 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - clocks + +additionalProperties: false + +examples: + - | + pwm1: pwm@d8220000 { + compatible = "via,vt8500-pwm"; + reg = <0xd8220000 0x1000>; + #pwm-cells = <3>; + clocks = <&clkpwm>; + }; diff --git a/Documentation/devicetree/bindings/pwm/vt8500-pwm.txt b/Documentation/devicetree/bindings/pwm/vt8500-pwm.txt deleted file mode 100644 index 4fba93ce1985..000000000000 --- a/Documentation/devicetree/bindings/pwm/vt8500-pwm.txt +++ /dev/null @@ -1,18 +0,0 @@ -VIA/Wondermedia VT8500/WM8xxx series SoC PWM controller - -Required properties: -- compatible: should be "via,vt8500-pwm" -- reg: physical base address and length of the controller's registers -- #pwm-cells: should be 3. See pwm.yaml in this directory for a description of - the cells format. The only third cell flag supported by this binding is - PWM_POLARITY_INVERTED. -- clocks: phandle to the PWM source clock - -Example: - -pwm1: pwm@d8220000 { - #pwm-cells = <3>; - compatible = "via,vt8500-pwm"; - reg = <0xd8220000 0x1000>; - clocks = <&clkpwm>; -}; diff --git a/Documentation/devicetree/bindings/regulator/adi,adp5055-regulator.yaml b/Documentation/devicetree/bindings/regulator/adi,adp5055-regulator.yaml new file mode 100644 index 000000000000..9c4ead4c9fd1 --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/adi,adp5055-regulator.yaml @@ -0,0 +1,157 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/adi,adp5055-regulator.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices ADP5055 Triple Buck Regulator + +maintainers: + - Alexis Czezar Torreno <alexisczezar.torreno@analog.com> + +description: | + The ADP5055 combines three high performance buck regulator. The device enables + direct connection to high input voltages up to 18 V with no preregulators. + https://www.analog.com/media/en/technical-documentation/data-sheets/adp5055.pdf + +properties: + compatible: + enum: + - adi,adp5055 + + reg: + enum: + - 0x70 + - 0x71 + + adi,tset-us: + description: + Setting time used by the device. This is changed via soldering specific + resistor values on the CFG2 pin. + enum: [2600, 20800] + default: 2600 + + adi,ocp-blanking: + description: + If present, overcurrent protection (OCP) blanking for all regulator is on. + type: boolean + + adi,delay-power-good: + description: + Configures delay timer of the power good (PWRGD) pin. Delay is based on + Tset which can be 2.6 ms or 20.8 ms. + type: boolean + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + +patternProperties: + '^buck[0-2]$': + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + + properties: + enable-gpios: + maxItems: 1 + description: + GPIO specifier to enable the GPIO control for each regulator. The + driver supports two modes of enable, hardware only (GPIOs) or software + only (Registers). Pure hardware enabling requires each regulator to + contain this property. If at least one regulator does not have this, + the driver automatically switches to software only mode. + + adi,dvs-limit-upper-microvolt: + description: + Configure the allowable upper side limit of the voltage output of each + regulator in microvolt. Relative to the default Vref trimming value. + Vref = 600 mV. Voltages are in 12 mV steps, value is autoadjusted. + Vout_high = Vref_trim + dvs-limit-upper. + minimum: 12000 + maximum: 192000 + default: 192000 + + adi,dvs-limit-lower-microvolt: + description: + Configure the allowable lower side limit of the voltage output of each + regulator in microvolt. Relative to the default Vref trimming value. + Vref = 600 mV. Voltages are in 12 mV steps, value is autoadjusted. + Vout_low = Vref_trim + dvs-limit-lower. + minimum: -190500 + maximum: -10500 + default: -190500 + + adi,fast-transient: + description: + Configures the fast transient sensitivity for each regulator. + "none" - No fast transient. + "3G_1.5%" - 1.5% window with 3*350uA/V + "5G_1.5%" - 1.5% window with 5*350uA/V + "5G_2.5%" - 2.5% window with 5*350uA/V + enum: [none, 3G_1.5%, 5G_1.5%, 5G_2.5%] + default: 5G_2.5% + + adi,mask-power-good: + description: + If present, masks individual regulators PWRGD signal to the external + PWRGD hardware pin. + type: boolean + + required: + - regulator-name + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + regulator@70 { + compatible = "adi,adp5055"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + adi,tset-us = <2600>; + adi,ocp-blanking; + adi,delay-power-good; + + buck0 { + regulator-name = "buck0"; + enable-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; + adi,dvs-limit-upper-microvolt = <192000>; + adi,dvs-limit-lower-microvolt = <(-190500)>; + adi,fast-transient = "5G_2.5%"; + adi,mask-power-good; + }; + + buck1 { + regulator-name = "buck1"; + enable-gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; + adi,dvs-limit-upper-microvolt = <192000>; + adi,dvs-limit-lower-microvolt = <(-190500)>; + adi,fast-transient = "5G_2.5%"; + adi,mask-power-good; + }; + + buck2 { + regulator-name = "buck2"; + enable-gpios = <&gpio 19 GPIO_ACTIVE_HIGH>; + adi,dvs-limit-upper-microvolt = <192000>; + adi,dvs-limit-lower-microvolt = <(-190500)>; + adi,fast-transient = "5G_2.5%"; + adi,mask-power-good; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/regulator/brcm,bcm59054.yaml b/Documentation/devicetree/bindings/regulator/brcm,bcm59054.yaml new file mode 100644 index 000000000000..5b46d7fca05e --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/brcm,bcm59054.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/brcm,bcm59054.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom BCM59054 Power Management Unit regulators + +description: | + This is a part of device tree bindings for the BCM59054 power + management unit. + + See Documentation/devicetree/bindings/mfd/brcm,bcm59056.yaml for + additional information and example. + +maintainers: + - Artur Weber <aweber.kernel@gmail.com> + +patternProperties: + "^(cam|sim|mmc)ldo[1-2]$": + type: object + $ref: /schemas/regulator/regulator.yaml# + unevaluatedProperties: false + + "^(rf|sd|sdx|aud|mic|usb|vib|tcx)ldo$": + type: object + $ref: /schemas/regulator/regulator.yaml# + unevaluatedProperties: false + + "^(c|mm|v)sr$": + type: object + $ref: /schemas/regulator/regulator.yaml# + unevaluatedProperties: false + + "^(io|sd)sr[1-2]$": + type: object + $ref: /schemas/regulator/regulator.yaml# + unevaluatedProperties: false + + "^gpldo[1-3]$": + type: object + $ref: /schemas/regulator/regulator.yaml# + unevaluatedProperties: false + + "^lvldo[1-2]$": + type: object + $ref: /schemas/regulator/regulator.yaml# + unevaluatedProperties: false + +properties: + vbus: + type: object + $ref: /schemas/regulator/regulator.yaml# + unevaluatedProperties: false + +additionalProperties: false diff --git a/Documentation/devicetree/bindings/regulator/brcm,bcm59056.yaml b/Documentation/devicetree/bindings/regulator/brcm,bcm59056.yaml new file mode 100644 index 000000000000..7a5e36394d21 --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/brcm,bcm59056.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/brcm,bcm59056.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom BCM59056 Power Management Unit regulators + +description: | + This is a part of device tree bindings for the BCM59056 power + management unit. + + See Documentation/devicetree/bindings/mfd/brcm,bcm59056.yaml for + additional information and example. + +maintainers: + - Artur Weber <aweber.kernel@gmail.com> + +patternProperties: + "^(cam|sim|mmc)ldo[1-2]$": + type: object + $ref: /schemas/regulator/regulator.yaml# + unevaluatedProperties: false + + "^(rf|sd|sdx|aud|mic|usb|vib)ldo$": + type: object + $ref: /schemas/regulator/regulator.yaml# + unevaluatedProperties: false + + "^(c|m|v)sr$": + type: object + $ref: /schemas/regulator/regulator.yaml# + unevaluatedProperties: false + + "^(io|sd)sr[1-2]$": + type: object + $ref: /schemas/regulator/regulator.yaml# + unevaluatedProperties: false + + "^gpldo[1-6]$": + type: object + $ref: /schemas/regulator/regulator.yaml# + unevaluatedProperties: false + +properties: + vbus: + type: object + $ref: /schemas/regulator/regulator.yaml# + unevaluatedProperties: false + +additionalProperties: false diff --git a/Documentation/devicetree/bindings/regulator/mediatek,mt6357-regulator.yaml b/Documentation/devicetree/bindings/regulator/mediatek,mt6357-regulator.yaml index 6327bb2f6ee0..698266c09e25 100644 --- a/Documentation/devicetree/bindings/regulator/mediatek,mt6357-regulator.yaml +++ b/Documentation/devicetree/bindings/regulator/mediatek,mt6357-regulator.yaml @@ -33,7 +33,7 @@ patternProperties: "^ldo-v(camio18|aud28|aux18|io18|io28|rf12|rf18|cn18|cn28|fe28)$": type: object - $ref: fixed-regulator.yaml# + $ref: regulator.yaml# unevaluatedProperties: false description: Properties for single fixed LDO regulator. @@ -112,7 +112,6 @@ examples: regulator-enable-ramp-delay = <220>; }; mt6357_vfe28_reg: ldo-vfe28 { - compatible = "regulator-fixed"; regulator-name = "vfe28"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; @@ -125,14 +124,12 @@ examples: regulator-enable-ramp-delay = <110>; }; mt6357_vrf18_reg: ldo-vrf18 { - compatible = "regulator-fixed"; regulator-name = "vrf18"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-enable-ramp-delay = <110>; }; mt6357_vrf12_reg: ldo-vrf12 { - compatible = "regulator-fixed"; regulator-name = "vrf12"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; @@ -157,14 +154,12 @@ examples: regulator-enable-ramp-delay = <264>; }; mt6357_vcn28_reg: ldo-vcn28 { - compatible = "regulator-fixed"; regulator-name = "vcn28"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; regulator-enable-ramp-delay = <264>; }; mt6357_vcn18_reg: ldo-vcn18 { - compatible = "regulator-fixed"; regulator-name = "vcn18"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; @@ -183,7 +178,6 @@ examples: regulator-enable-ramp-delay = <264>; }; mt6357_vcamio_reg: ldo-vcamio18 { - compatible = "regulator-fixed"; regulator-name = "vcamio"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; @@ -212,28 +206,24 @@ examples: regulator-always-on; }; mt6357_vaux18_reg: ldo-vaux18 { - compatible = "regulator-fixed"; regulator-name = "vaux18"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-enable-ramp-delay = <264>; }; mt6357_vaud28_reg: ldo-vaud28 { - compatible = "regulator-fixed"; regulator-name = "vaud28"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; regulator-enable-ramp-delay = <264>; }; mt6357_vio28_reg: ldo-vio28 { - compatible = "regulator-fixed"; regulator-name = "vio28"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; regulator-enable-ramp-delay = <264>; }; mt6357_vio18_reg: ldo-vio18 { - compatible = "regulator-fixed"; regulator-name = "vio18"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; diff --git a/Documentation/devicetree/bindings/regulator/nxp,pca9450-regulator.yaml b/Documentation/devicetree/bindings/regulator/nxp,pca9450-regulator.yaml index 68709a7dc43f..4ffe5c3faea0 100644 --- a/Documentation/devicetree/bindings/regulator/nxp,pca9450-regulator.yaml +++ b/Documentation/devicetree/bindings/regulator/nxp,pca9450-regulator.yaml @@ -17,6 +17,9 @@ description: | Datasheet is available at https://www.nxp.com/docs/en/data-sheet/PCA9450DS.pdf + Support PF9453, Datasheet is available at + https://www.nxp.com/docs/en/data-sheet/PF9453_SDS.pdf + # The valid names for PCA9450 regulator nodes are: # BUCK1, BUCK2, BUCK3, BUCK4, BUCK5, BUCK6, # LDO1, LDO2, LDO3, LDO4, LDO5 @@ -30,6 +33,7 @@ properties: - nxp,pca9450c - nxp,pca9451a - nxp,pca9452 + - nxp,pf9453 reg: maxItems: 1 @@ -42,8 +46,30 @@ properties: description: | list of regulators provided by this controller + properties: + LDO5: + type: object + $ref: regulator.yaml# + description: + Properties for single LDO5 regulator. + + properties: + nxp,sd-vsel-fixed-low: + type: boolean + description: + Let the driver know that SD_VSEL is hardwired to low level and + there is no GPIO to get the actual value from. + + sd-vsel-gpios: + description: + GPIO that can be used to read the current status of the SD_VSEL + signal in order for the driver to know if LDO5CTRL_L or LDO5CTRL_H + is used by the hardware. + + unevaluatedProperties: false + patternProperties: - "^LDO[1-5]$": + "^LDO([1-4]|-SNVS)$": type: object $ref: regulator.yaml# description: @@ -78,11 +104,6 @@ properties: additionalProperties: false - sd-vsel-gpios: - description: GPIO that is used to switch LDO5 between being configured by - LDO5CTRL_L or LDO5CTRL_H register. Use this if the SD_VSEL signal is - connected to a host GPIO. - nxp,i2c-lt-enable: type: boolean description: @@ -101,6 +122,24 @@ required: additionalProperties: false +allOf: + - if: + properties: + compatible: + contains: + const: nxp,pf9453 + then: + properties: + regulators: + patternProperties: + "^LDO[3-4]$": false + "^BUCK[5-6]$": false + else: + properties: + regulators: + properties: + LDO-SNVS: false + examples: - | #include <dt-bindings/interrupt-controller/irq.h> diff --git a/Documentation/devicetree/bindings/regulator/richtek,rtq2208.yaml b/Documentation/devicetree/bindings/regulator/richtek,rtq2208.yaml index 87accc6f13b8..022c1f197364 100644 --- a/Documentation/devicetree/bindings/regulator/richtek,rtq2208.yaml +++ b/Documentation/devicetree/bindings/regulator/richtek,rtq2208.yaml @@ -39,7 +39,7 @@ properties: interrupts: maxItems: 1 - + richtek,mtp-sel-high: type: boolean description: @@ -77,6 +77,7 @@ properties: properties: richtek,fixed-microvolt: + deprecated: true description: | This property can be used to set a fixed operating voltage that lies outside the range of the regulator's adjustable mode. diff --git a/Documentation/devicetree/bindings/regulator/rohm,bd96802-regulator.yaml b/Documentation/devicetree/bindings/regulator/rohm,bd96802-regulator.yaml new file mode 100644 index 000000000000..671eaf1096d3 --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/rohm,bd96802-regulator.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/rohm,bd96802-regulator.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ROHM BD96802 Power Management Integrated Circuit regulators + +maintainers: + - Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> + +description: + This module is part of the ROHM BD96802 MFD device. For more details + see Documentation/devicetree/bindings/mfd/rohm,bd96802-pmic.yaml. + + The regulator controller is represented as a sub-node of the PMIC node + on the device tree. + + Regulator nodes should be named to buck1 and buck2. + +patternProperties: + "^buck[1-2]$": + type: object + description: + Properties for single BUCK regulator. + $ref: regulator.yaml# + + properties: + rohm,initial-voltage-microvolt: + description: + Initial voltage for regulator. Voltage can be tuned +/-150 mV from + this value. NOTE, This can be modified via I2C only when PMIC is in + STBY state. + minimum: 500000 + maximum: 3300000 + + rohm,keep-on-stby: + description: + Keep the regulator powered when PMIC transitions to STBY state. + type: boolean + + unevaluatedProperties: false + +additionalProperties: false diff --git a/Documentation/devicetree/bindings/regulator/samsung,s2mpu05.yaml b/Documentation/devicetree/bindings/regulator/samsung,s2mpu05.yaml new file mode 100644 index 000000000000..378518a5a7f5 --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/samsung,s2mpu05.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/samsung,s2mpu05.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung S2MPU05 Power Management IC regulators + +maintainers: + - Kaustabh Chakraborty <kauschluss@disroot.org> + +description: | + This is a part of device tree bindings for S2M and S5M family of Power + Management IC (PMIC). + + The S2MPU05 provides buck and LDO regulators. + + See also Documentation/devicetree/bindings/mfd/samsung,s2mps11.yaml for + additional information and example. + +patternProperties: + # 21 LDOs + "^ldo([1-9]|10|2[5-9]|3[0-5])$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + description: + Properties for single LDO regulator. + + LDOs 11-24 are used for CP, and they're left unimplemented due to lack + of documentation on these regulators. + + required: + - regulator-name + + # 5 bucks + "^buck[1-5]$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + description: + Properties for single buck regulator. + + required: + - regulator-name + +additionalProperties: false diff --git a/Documentation/devicetree/bindings/regulator/ti,tps65219.yaml b/Documentation/devicetree/bindings/regulator/ti,tps65219.yaml index 78e64521d401..7c64e588a8b5 100644 --- a/Documentation/devicetree/bindings/regulator/ti,tps65219.yaml +++ b/Documentation/devicetree/bindings/regulator/ti,tps65219.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/regulator/ti,tps65219.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: TI tps65219 Power Management Integrated Circuit regulators +title: TI TPS65214/TPS65215/TPS65219 Power Management Integrated Circuit maintainers: - Jerome Neanne <jerome.neanne@baylibre.com> @@ -12,9 +12,20 @@ maintainers: description: | Regulator nodes should be named to buck<number> and ldo<number>. + TI TPS65219 is a Power Management IC with 3 Buck regulators, 4 Low + Drop-out Regulators (LDOs), 1 GPIO, 2 GPOs, and power-button. + + TI TPS65215 is a derivative of TPS65219 with 3 Buck regulators, 2 Low + Drop-out Regulators (LDOs), 1 GPIO, 1 GPO, and power-button. + + TI TPS65214 is a derivative of TPS65219 with 3 Buck regulators, 2 Low + Drop-out Regulators (LDOs), 1 GPIO, 1 GPO, and power-button. + properties: compatible: enum: + - ti,tps65214 + - ti,tps65215 - ti,tps65219 reg: @@ -90,6 +101,20 @@ required: additionalProperties: false +allOf: + - if: + properties: + compatible: + contains: + enum: + - ti,tps65214 + - ti,tps65215 + then: + properties: + regulators: + patternProperties: + "^ldo[3-4]$": false + examples: - | #include <dt-bindings/interrupt-controller/arm-gic.h> diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,msm8916-mss-pil.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,msm8916-mss-pil.yaml index 588b010b2a9e..c179b560572b 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,msm8916-mss-pil.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,msm8916-mss-pil.yaml @@ -17,8 +17,10 @@ properties: compatible: oneOf: - enum: + - qcom,msm8226-mss-pil - qcom,msm8909-mss-pil - qcom,msm8916-mss-pil + - qcom,msm8926-mss-pil - qcom,msm8953-mss-pil - qcom,msm8974-mss-pil @@ -70,16 +72,18 @@ properties: items: - description: CX proxy power domain (control handed over after startup) - description: MX proxy power domain (control handed over after startup) + (not valid for qcom,msm8226-mss-pil, qcom,msm8926-mss-pil + and qcom,msm8974-mss-pil) - description: MSS proxy power domain (control handed over after startup) (only valid for qcom,msm8953-mss-pil) - minItems: 2 + minItems: 1 power-domain-names: items: - const: cx - - const: mx + - const: mx # not valid for qcom,msm8226-mss-pil, qcom-msm8926-mss-pil and qcom,msm8974-mss-pil - const: mss # only valid for qcom,msm8953-mss-pil - minItems: 2 + minItems: 1 pll-supply: description: PLL proxy supply (control handed over after startup) @@ -106,6 +110,15 @@ properties: items: - const: stop + qcom,ext-bhs-reg: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: External power block headswitch (BHS) register + (only valid for qcom,msm8226-mss-pil) + items: + - items: + - description: phandle to external BHS syscon region + - description: offset to the external BHS register + qcom,halt-regs: $ref: /schemas/types.yaml#/definitions/phandle-array description: @@ -207,17 +220,58 @@ allOf: required: - power-domains - power-domain-names - else: + + - if: + properties: + compatible: + contains: + enum: + - qcom,msm8909-mss-pil + - qcom,msm8916-mss-pil + then: properties: power-domains: + minItems: 2 maxItems: 2 power-domain-names: + minItems: 2 maxItems: 2 - if: properties: compatible: - const: qcom,msm8974-mss-pil + contains: + enum: + - qcom,msm8226-mss-pil + - qcom,msm8926-mss-pil + - qcom,msm8974-mss-pil + then: + properties: + power-domains: + maxItems: 1 + power-domain-names: + maxItems: 1 + required: + - mx-supply + + - if: + properties: + compatible: + const: qcom,msm8226-mss-pil + then: + required: + - qcom,ext-bhs-reg + else: + properties: + qcom,ext-bhs-reg: false + + - if: + properties: + compatible: + contains: + enum: + - qcom,msm8926-mss-pil + - qcom,msm8974-mss-pil then: required: - mss-supply diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sc8180x-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sc8180x-pas.yaml deleted file mode 100644 index 45ee9fbe0966..000000000000 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sc8180x-pas.yaml +++ /dev/null @@ -1,96 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/remoteproc/qcom,sc8180x-pas.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Qualcomm SC8180X Peripheral Authentication Service - -maintainers: - - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> - -description: - Qualcomm SC8180X SoC Peripheral Authentication Service loads and boots - firmware on the Qualcomm DSP Hexagon cores. - -properties: - compatible: - enum: - - qcom,sc8180x-adsp-pas - - qcom,sc8180x-cdsp-pas - - qcom,sc8180x-mpss-pas - - reg: - maxItems: 1 - - clocks: - items: - - description: XO clock - - clock-names: - items: - - const: xo - - qcom,qmp: - $ref: /schemas/types.yaml#/definitions/phandle - description: Reference to the AOSS side-channel message RAM. - - smd-edge: false - - memory-region: - maxItems: 1 - description: Reference to the reserved-memory for the Hexagon core - - firmware-name: - maxItems: 1 - description: Firmware name for the Hexagon core - -required: - - compatible - - reg - - memory-region - -allOf: - - $ref: /schemas/remoteproc/qcom,pas-common.yaml# - - if: - properties: - compatible: - enum: - - qcom,sc8180x-adsp-pas - - qcom,sc8180x-cdsp-pas - then: - properties: - interrupts: - maxItems: 5 - interrupt-names: - maxItems: 5 - else: - properties: - interrupts: - minItems: 6 - interrupt-names: - minItems: 6 - - - if: - properties: - compatible: - enum: - - qcom,sc8180x-adsp-pas - - qcom,sc8180x-cdsp-pas - then: - properties: - power-domains: - items: - - description: LCX power domain - - description: LMX power domain - power-domain-names: - items: - - const: lcx - - const: lmx - else: - properties: - # TODO: incomplete - power-domains: false - power-domain-names: false - -unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sm6115-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sm6115-pas.yaml index 059cb87b4d6c..eeb6a8aafeb9 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sm6115-pas.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sm6115-pas.yaml @@ -127,7 +127,7 @@ examples: clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; clock-names = "xo"; - firmware-name = "qcom/sm6115/adsp.mdt"; + firmware-name = "qcom/sm6115/adsp.mbn"; interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>, <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sm8150-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sm8150-pas.yaml index d67386c50fa4..5dcc2a32c080 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sm8150-pas.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sm8150-pas.yaml @@ -16,6 +16,9 @@ description: properties: compatible: enum: + - qcom,sc8180x-adsp-pas + - qcom,sc8180x-cdsp-pas + - qcom,sc8180x-slpi-pas - qcom,sm8150-adsp-pas - qcom,sm8150-cdsp-pas - qcom,sm8150-mpss-pas @@ -60,6 +63,9 @@ allOf: properties: compatible: enum: + - qcom,sc8180x-adsp-pas + - qcom,sc8180x-cdsp-pas + - qcom,sc8180x-slpi-pas - qcom,sm8150-adsp-pas - qcom,sm8150-cdsp-pas - qcom,sm8150-slpi-pas @@ -83,6 +89,8 @@ allOf: properties: compatible: enum: + - qcom,sc8180x-adsp-pas + - qcom,sc8180x-cdsp-pas - qcom,sm8150-adsp-pas - qcom,sm8150-cdsp-pas - qcom,sm8250-cdsp-pas @@ -99,6 +107,7 @@ allOf: properties: compatible: enum: + - qcom,sc8180x-mpss-pas - qcom,sm8150-mpss-pas then: properties: @@ -115,6 +124,7 @@ allOf: properties: compatible: enum: + - qcom,sc8180x-slpi-pas - qcom,sm8150-slpi-pas - qcom,sm8250-adsp-pas - qcom,sm8250-slpi-pas diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sm8350-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sm8350-pas.yaml index fd3423e6051b..6d09823153fc 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sm8350-pas.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sm8350-pas.yaml @@ -15,16 +15,20 @@ description: properties: compatible: - enum: - - qcom,sar2130p-adsp-pas - - qcom,sm8350-adsp-pas - - qcom,sm8350-cdsp-pas - - qcom,sm8350-slpi-pas - - qcom,sm8350-mpss-pas - - qcom,sm8450-adsp-pas - - qcom,sm8450-cdsp-pas - - qcom,sm8450-mpss-pas - - qcom,sm8450-slpi-pas + oneOf: + - enum: + - qcom,sar2130p-adsp-pas + - qcom,sm8350-adsp-pas + - qcom,sm8350-cdsp-pas + - qcom,sm8350-slpi-pas + - qcom,sm8350-mpss-pas + - qcom,sm8450-adsp-pas + - qcom,sm8450-cdsp-pas + - qcom,sm8450-mpss-pas + - qcom,sm8450-slpi-pas + - items: + - const: qcom,sc8280xp-slpi-pas + - const: qcom,sm8350-slpi-pas reg: maxItems: 1 @@ -61,14 +65,15 @@ allOf: - if: properties: compatible: - enum: - - qcom,sar2130p-adsp-pas - - qcom,sm8350-adsp-pas - - qcom,sm8350-cdsp-pas - - qcom,sm8350-slpi-pas - - qcom,sm8450-adsp-pas - - qcom,sm8450-cdsp-pas - - qcom,sm8450-slpi-pas + contains: + enum: + - qcom,sar2130p-adsp-pas + - qcom,sm8350-adsp-pas + - qcom,sm8350-cdsp-pas + - qcom,sm8350-slpi-pas + - qcom,sm8450-adsp-pas + - qcom,sm8450-cdsp-pas + - qcom,sm8450-slpi-pas then: properties: interrupts: @@ -102,12 +107,13 @@ allOf: - if: properties: compatible: - enum: - - qcom,sar2130p-adsp-pas - - qcom,sm8350-adsp-pas - - qcom,sm8350-slpi-pas - - qcom,sm8450-adsp-pas - - qcom,sm8450-slpi-pas + contains: + enum: + - qcom,sar2130p-adsp-pas + - qcom,sm8350-adsp-pas + - qcom,sm8350-slpi-pas + - qcom,sm8450-adsp-pas + - qcom,sm8450-slpi-pas then: properties: power-domains: diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml index a24cbb61bda7..2dd479cf4821 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml @@ -24,11 +24,15 @@ properties: - qcom,sm8650-adsp-pas - qcom,sm8650-cdsp-pas - qcom,sm8650-mpss-pas + - qcom,sm8750-mpss-pas - qcom,x1e80100-adsp-pas - qcom,x1e80100-cdsp-pas - items: - const: qcom,sm8750-adsp-pas - const: qcom,sm8550-adsp-pas + - items: + - const: qcom,sm8750-cdsp-pas + - const: qcom,sm8650-cdsp-pas reg: maxItems: 1 @@ -114,6 +118,23 @@ allOf: memory-region: minItems: 3 maxItems: 3 + + - if: + properties: + compatible: + contains: + enum: + - qcom,sm8750-cdsp-pas + then: + properties: + interrupts: + maxItems: 6 + interrupt-names: + maxItems: 6 + memory-region: + minItems: 3 + maxItems: 3 + - if: properties: compatible: @@ -147,6 +168,21 @@ allOf: - if: properties: compatible: + enum: + - qcom,sm8750-mpss-pas + then: + properties: + interrupts: + minItems: 6 + interrupt-names: + minItems: 6 + memory-region: + minItems: 4 + maxItems: 4 + + - if: + properties: + compatible: contains: enum: - qcom,sm8550-adsp-pas @@ -171,6 +207,7 @@ allOf: - qcom,sdx75-mpss-pas - qcom,sm8550-mpss-pas - qcom,sm8650-mpss-pas + - qcom,sm8750-mpss-pas then: properties: power-domains: @@ -184,10 +221,11 @@ allOf: - if: properties: compatible: - enum: - - qcom,sm8550-cdsp-pas - - qcom,sm8650-cdsp-pas - - qcom,x1e80100-cdsp-pas + contains: + enum: + - qcom,sm8550-cdsp-pas + - qcom,sm8650-cdsp-pas + - qcom,x1e80100-cdsp-pas then: properties: power-domains: diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,wcnss-pil.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,wcnss-pil.yaml index 8e033b22d28c..117fb4d0c4ad 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,wcnss-pil.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,wcnss-pil.yaml @@ -69,9 +69,11 @@ properties: CX regulator to be held on behalf of the booting of the WCNSS core. power-domains: + minItems: 1 maxItems: 2 power-domain-names: + minItems: 1 items: - const: cx - const: mx @@ -187,22 +189,43 @@ allOf: - qcom,pronto-v1-pil - qcom,pronto-v2-pil then: - properties: - vddmx-supply: - deprecated: true - description: Deprecated for qcom,pronto-v1/2-pil - - vddcx-supply: - deprecated: true - description: Deprecated for qcom,pronto-v1/2-pil - + # CX and MX must be present either as power domains or regulators oneOf: + # Both CX and MX represented as power domains - required: - power-domains - power-domain-names + properties: + power-domains: + minItems: 2 + power-domain-names: + minItems: 2 + vddmx-supply: false + vddcx-supply: false + # CX represented as power domain, MX as regulator + - required: + - power-domains + - power-domain-names + - vddmx-supply + properties: + power-domains: + maxItems: 1 + power-domain-names: + maxItems: 1 + vddcx-supply: false + # Both CX and MX represented as regulators - required: - vddmx-supply - vddcx-supply + properties: + power-domains: false + power-domain-names: false + vddmx-supply: + deprecated: true + description: Deprecated for qcom,pronto-v1/2-pil + vddcx-supply: + deprecated: true + description: Deprecated for qcom,pronto-v1/2-pil - if: properties: @@ -212,6 +235,10 @@ allOf: - qcom,pronto-v3-pil then: properties: + power-domains: + minItems: 2 + power-domain-names: + minItems: 2 vddmx-supply: false vddcx-supply: false diff --git a/Documentation/devicetree/bindings/remoteproc/st,stm32-rproc.yaml b/Documentation/devicetree/bindings/remoteproc/st,stm32-rproc.yaml index 370af61d8f28..843679c557e7 100644 --- a/Documentation/devicetree/bindings/remoteproc/st,stm32-rproc.yaml +++ b/Documentation/devicetree/bindings/remoteproc/st,stm32-rproc.yaml @@ -139,6 +139,10 @@ properties: If defined, when remoteproc is probed, it loads the default firmware and starts the remote processor. + firmware-name: + maxItems: 1 + description: Default name of the remote processor firmware. + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/reset/amlogic,meson-reset.yaml b/Documentation/devicetree/bindings/reset/amlogic,meson-reset.yaml index 695ef38a7bb3..150e95c0d9be 100644 --- a/Documentation/devicetree/bindings/reset/amlogic,meson-reset.yaml +++ b/Documentation/devicetree/bindings/reset/amlogic,meson-reset.yaml @@ -12,14 +12,20 @@ maintainers: properties: compatible: - enum: - - amlogic,meson8b-reset # Reset Controller on Meson8b and compatible SoCs - - amlogic,meson-gxbb-reset # Reset Controller on GXBB and compatible SoCs - - amlogic,meson-axg-reset # Reset Controller on AXG and compatible SoCs - - amlogic,meson-a1-reset # Reset Controller on A1 and compatible SoCs - - amlogic,meson-s4-reset # Reset Controller on S4 and compatible SoCs - - amlogic,c3-reset # Reset Controller on C3 and compatible SoCs - - amlogic,t7-reset + oneOf: + - enum: + - amlogic,meson8b-reset # Reset Controller on Meson8b and compatible SoCs + - amlogic,meson-gxbb-reset # Reset Controller on GXBB and compatible SoCs + - amlogic,meson-axg-reset # Reset Controller on AXG and compatible SoCs + - amlogic,meson-a1-reset # Reset Controller on A1 and compatible SoCs + - amlogic,meson-s4-reset # Reset Controller on S4 and compatible SoCs + - amlogic,c3-reset # Reset Controller on C3 and compatible SoCs + - amlogic,t7-reset + - items: + - enum: + - amlogic,a4-reset + - amlogic,a5-reset + - const: amlogic,meson-s4-reset reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml b/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml index 98465d26949e..84c4801df8d9 100644 --- a/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml +++ b/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml @@ -24,8 +24,15 @@ properties: - microchip,sam9x60-rstc - microchip,sama7g5-rstc - items: + - const: microchip,sama7d65-rstc + - const: microchip,sama7g5-rstc + - items: - const: atmel,sama5d3-rstc - const: atmel,at91sam9g45-rstc + - items: + - enum: + - microchip,sam9x7-rstc + - const: microchip,sam9x60-rstc reg: minItems: 1 diff --git a/Documentation/devicetree/bindings/reset/renesas,rzv2h-usb2phy-reset.yaml b/Documentation/devicetree/bindings/reset/renesas,rzv2h-usb2phy-reset.yaml new file mode 100644 index 000000000000..c79f61c2373b --- /dev/null +++ b/Documentation/devicetree/bindings/reset/renesas,rzv2h-usb2phy-reset.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/renesas,rzv2h-usb2phy-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/V2H(P) USB2PHY Port reset Control + +maintainers: + - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> + +description: + The RZ/V2H(P) USB2PHY Control mainly controls Port reset and power down of the + USB2.0 PHY. + +properties: + compatible: + const: renesas,r9a09g057-usb2phy-reset # RZ/V2H(P) + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + power-domains: + maxItems: 1 + + '#reset-cells': + const: 0 + +required: + - compatible + - reg + - clocks + - resets + - power-domains + - '#reset-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/renesas,r9a09g057-cpg.h> + + reset-controller@15830000 { + compatible = "renesas,r9a09g057-usb2phy-reset"; + reg = <0x15830000 0x10000>; + clocks = <&cpg CPG_MOD 0xb6>; + resets = <&cpg 0xaf>; + power-domains = <&cpg>; + #reset-cells = <0>; + }; diff --git a/Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml b/Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml index 76e1931f0908..1d1b84575960 100644 --- a/Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml +++ b/Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml @@ -11,7 +11,12 @@ maintainers: properties: compatible: - const: sophgo,sg2042-reset + oneOf: + - items: + - enum: + - sophgo,sg2044-reset + - const: sophgo,sg2042-reset + - const: sophgo,sg2042-reset reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/reset/thead,th1520-reset.yaml b/Documentation/devicetree/bindings/reset/thead,th1520-reset.yaml new file mode 100644 index 000000000000..f2e91d0add7a --- /dev/null +++ b/Documentation/devicetree/bindings/reset/thead,th1520-reset.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/thead,th1520-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: T-HEAD TH1520 SoC Reset Controller + +description: + The T-HEAD TH1520 reset controller is a hardware block that asserts/deasserts + resets for SoC subsystems. + +maintainers: + - Michal Wilczynski <m.wilczynski@samsung.com> + +properties: + compatible: + enum: + - thead,th1520-reset + + reg: + maxItems: 1 + + "#reset-cells": + const: 1 + +required: + - compatible + - reg + - "#reset-cells" + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + rst: reset-controller@ffef528000 { + compatible = "thead,th1520-reset"; + reg = <0xff 0xef528000 0x0 0x1000>; + #reset-cells = <1>; + }; + }; diff --git a/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml b/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml index 1f1b42dde94d..1db85fc9966f 100644 --- a/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml +++ b/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml @@ -7,7 +7,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Zynq UltraScale+ MPSoC and Versal reset maintainers: - - Mubin Sayyed <mubin.sayyed@amd.com> - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> description: | diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index a63b994e0763..ede6a58ccf53 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -224,6 +224,12 @@ properties: as ratified at commit 4a69197e5617 ("Update to ratified state") of riscv-svvptc. + - const: zaamo + description: | + The standard Zaamo extension for atomic memory operations as + ratified at commit e87412e621f1 ("integrate Zaamo and Zalrsc text + (#1304)") of the unprivileged ISA specification. + - const: zabha description: | The Zabha extension for Byte and Halfword Atomic Memory Operations @@ -236,6 +242,12 @@ properties: is supported as ratified at commit 5059e0ca641c ("update to ratified") of the riscv-zacas. + - const: zalrsc + description: | + The standard Zalrsc extension for load-reserved/store-conditional as + ratified at commit e87412e621f1 ("integrate Zaamo and Zalrsc text + (#1304)") of the unprivileged ISA specification. + - const: zawrs description: | The Zawrs extension for entering a low-power state or for trapping @@ -329,6 +341,12 @@ properties: instructions, as ratified in commit 056b6ff ("Zfa is ratified") of riscv-isa-manual. + - const: zfbfmin + description: + The standard Zfbfmin extension which provides minimal support for + 16-bit half-precision brain floating-point instructions, as ratified + in commit 4dc23d62 ("Added Chapter title to BF16") of riscv-isa-manual. + - const: zfh description: The standard Zfh extension for 16-bit half-precision binary @@ -525,6 +543,18 @@ properties: in commit 6f702a2 ("Vector extensions are now ratified") of riscv-v-spec. + - const: zvfbfmin + description: + The standard Zvfbfmin extension for minimal support for vectored + 16-bit half-precision brain floating-point instructions, as ratified + in commit 4dc23d62 ("Added Chapter title to BF16") of riscv-isa-manual. + + - const: zvfbfwma + description: + The standard Zvfbfwma extension for vectored half-precision brain + floating-point widening multiply-accumulate instructions, as ratified + in commit 4dc23d62 ("Added Chapter title to BF16") of riscv-isa-manual. + - const: zvfh description: The standard Zvfh extension for vectored half-precision @@ -632,6 +662,31 @@ properties: Registers in the AX45MP datasheet. https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf + # SiFive + - const: xsfvqmaccdod + description: + SiFive Int8 Matrix Multiplication Extensions Specification. + See more details in + https://www.sifive.com/document-file/sifive-int8-matrix-multiplication-extensions-specification + + - const: xsfvqmaccqoq + description: + SiFive Int8 Matrix Multiplication Extensions Specification. + See more details in + https://www.sifive.com/document-file/sifive-int8-matrix-multiplication-extensions-specification + + - const: xsfvfnrclipxfqf + description: + SiFive FP32-to-int8 Ranged Clip Instructions Extensions Specification. + See more details in + https://www.sifive.com/document-file/fp32-to-int8-ranged-clip-instructions + + - const: xsfvfwmaccqqq + description: + SiFive Matrix Multiply Accumulate Instruction Extensions Specification. + See more details in + https://www.sifive.com/document-file/matrix-multiply-accumulate-instruction + # T-HEAD - const: xtheadvector description: @@ -639,6 +694,12 @@ properties: https://github.com/T-head-Semi/thead-extension-spec/blob/95358cb2cca9489361c61d335e03d3134b14133f/xtheadvector.adoc. allOf: + - if: + contains: + const: d + then: + contains: + const: f # Zcb depends on Zca - if: contains: @@ -673,6 +734,119 @@ properties: then: contains: const: zca + # Zfbfmin depends on F + - if: + contains: + const: zfbfmin + then: + contains: + const: f + # Zvfbfmin depends on V or Zve32f + - if: + contains: + const: zvfbfmin + then: + oneOf: + - contains: + const: v + - contains: + const: zve32f + # Zvfbfwma depends on Zfbfmin and Zvfbfmin + - if: + contains: + const: zvfbfwma + then: + allOf: + - contains: + const: zfbfmin + - contains: + const: zvfbfmin + # Zacas depends on Zaamo + - if: + contains: + const: zacas + then: + contains: + const: zaamo + + - if: + contains: + const: zve32x + then: + contains: + const: zicsr + + - if: + contains: + const: zve32f + then: + allOf: + - contains: + const: f + - contains: + const: zve32x + + - if: + contains: + const: zve64x + then: + contains: + const: zve32x + + - if: + contains: + const: zve64f + then: + allOf: + - contains: + const: f + - contains: + const: zve32f + - contains: + const: zve64x + + - if: + contains: + const: zve64d + then: + allOf: + - contains: + const: d + - contains: + const: zve64f + + - if: + contains: + anyOf: + - const: zvbc + - const: zvkn + - const: zvknc + - const: zvkng + - const: zvknhb + - const: zvksc + then: + contains: + anyOf: + - const: v + - const: zve64x + + - if: + contains: + anyOf: + - const: zvbb + - const: zvkb + - const: zvkg + - const: zvkned + - const: zvknha + - const: zvksed + - const: zvksh + - const: zvks + - const: zvkt + then: + contains: + anyOf: + - const: v + - const: zve32x allOf: # Zcf extension does not exist on rv64 diff --git a/Documentation/devicetree/bindings/riscv/sophgo.yaml b/Documentation/devicetree/bindings/riscv/sophgo.yaml index a14cb10ff3f0..b4c4d7a7d7ad 100644 --- a/Documentation/devicetree/bindings/riscv/sophgo.yaml +++ b/Documentation/devicetree/bindings/riscv/sophgo.yaml @@ -35,6 +35,10 @@ properties: - enum: - milkv,pioneer - const: sophgo,sg2042 + - items: + - enum: + - sophgo,srd3-10 + - const: sophgo,sg2044 additionalProperties: true diff --git a/Documentation/devicetree/bindings/riscv/spacemit.yaml b/Documentation/devicetree/bindings/riscv/spacemit.yaml index 52e55077af1a..077b94f10dca 100644 --- a/Documentation/devicetree/bindings/riscv/spacemit.yaml +++ b/Documentation/devicetree/bindings/riscv/spacemit.yaml @@ -21,6 +21,7 @@ properties: - items: - enum: - bananapi,bpi-f3 + - milkv,jupiter - const: spacemit,k1 additionalProperties: true diff --git a/Documentation/devicetree/bindings/rng/rockchip,rk3588-rng.yaml b/Documentation/devicetree/bindings/rng/rockchip,rk3588-rng.yaml new file mode 100644 index 000000000000..fcc5be80142d --- /dev/null +++ b/Documentation/devicetree/bindings/rng/rockchip,rk3588-rng.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rng/rockchip,rk3588-rng.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip RK3576/RK3588 TRNG + +description: True Random Number Generator on Rockchip RK3576/RK3588 SoCs + +maintainers: + - Nicolas Frattaroli <nicolas.frattaroli@collabora.com> + +properties: + compatible: + enum: + - rockchip,rk3576-rng + - rockchip,rk3588-rng + + reg: + maxItems: 1 + + clocks: + items: + - description: TRNG AHB clock + + interrupts: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - interrupts + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/rockchip,rk3588-cru.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/reset/rockchip,rk3588-cru.h> + bus { + #address-cells = <2>; + #size-cells = <2>; + + rng@fe378000 { + compatible = "rockchip,rk3588-rng"; + reg = <0x0 0xfe378000 0x0 0x200>; + interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&scmi_clk SCMI_HCLK_SECURE_NS>; + resets = <&scmi_reset SCMI_SRST_H_TRNG_NS>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/rtc/adi,max31335.yaml b/Documentation/devicetree/bindings/rtc/adi,max31335.yaml index 0125cf6727cc..bce7558d0d87 100644 --- a/Documentation/devicetree/bindings/rtc/adi,max31335.yaml +++ b/Documentation/devicetree/bindings/rtc/adi,max31335.yaml @@ -18,7 +18,9 @@ allOf: properties: compatible: - const: adi,max31335 + enum: + - adi,max31331 + - adi,max31335 reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.yaml b/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.yaml index c8bb2eef442d..7c5b13caa40b 100644 --- a/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.yaml +++ b/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.yaml @@ -23,7 +23,9 @@ properties: - microchip,sam9x60-rtc - microchip,sama7g5-rtc - items: - - const: microchip,sam9x7-rtc + - enum: + - microchip,sam9x7-rtc + - microchip,sama7d65-rtc - const: microchip,sam9x60-rtc reg: diff --git a/Documentation/devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml b/Documentation/devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml index a7f6c1d1a08a..9c9b981fe38b 100644 --- a/Documentation/devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml +++ b/Documentation/devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml @@ -22,6 +22,7 @@ properties: - enum: - microchip,sam9x60-rtt - microchip,sam9x7-rtt + - microchip,sama7d65-rtt - const: atmel,at91sam9260-rtt - items: - const: microchip,sama7g5-rtt diff --git a/Documentation/devicetree/bindings/rtc/nxp,pcf2127.yaml b/Documentation/devicetree/bindings/rtc/nxp,pcf2127.yaml index 2d9fe5a75b06..11fcf0ca1ae0 100644 --- a/Documentation/devicetree/bindings/rtc/nxp,pcf2127.yaml +++ b/Documentation/devicetree/bindings/rtc/nxp,pcf2127.yaml @@ -8,6 +8,7 @@ title: NXP PCF2127 Real Time Clock allOf: - $ref: rtc.yaml# + - $ref: /schemas/spi/spi-peripheral-props.yaml# maintainers: - Alexandre Belloni <alexandre.belloni@bootlin.com> @@ -34,7 +35,7 @@ required: - compatible - reg -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/rtc/nxp,s32g-rtc.yaml b/Documentation/devicetree/bindings/rtc/nxp,s32g-rtc.yaml new file mode 100644 index 000000000000..40fd2fa298fe --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/nxp,s32g-rtc.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/nxp,s32g-rtc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP S32G2/S32G3 Real Time Clock (RTC) + +maintainers: + - Bogdan Hamciuc <bogdan.hamciuc@nxp.com> + - Ciprian Marian Costea <ciprianmarian.costea@nxp.com> + +description: + RTC hardware module present on S32G2/S32G3 SoCs is used as a wakeup source. + It is not kept alive during system reset and it is not battery-powered. + +allOf: + - $ref: rtc.yaml# + +properties: + compatible: + oneOf: + - enum: + - nxp,s32g2-rtc + - items: + - const: nxp,s32g3-rtc + - const: nxp,s32g2-rtc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: ipg clock drives the access to the RTC iomapped registers + - description: Clock source for the RTC module. Can be selected between + 4 different clock sources using an integrated hardware mux. + On S32G2/S32G3 SoCs, 'source0' is the SIRC clock (~32KHz) and it is + available during standby and runtime. 'source1' is reserved and cannot + be used. 'source2' is the FIRC clock and it is only available during + runtime providing a better resolution (~48MHz). 'source3' is an external + RTC clock source which can be additionally added in hardware. + + clock-names: + items: + - const: ipg + - enum: [ source0, source1, source2, source3 ] + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + + rtc@40060000 { + compatible = "nxp,s32g3-rtc", + "nxp,s32g2-rtc"; + reg = <0x40060000 0x1000>; + interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 54>, <&clks 55>; + clock-names = "ipg", "source0"; + }; diff --git a/Documentation/devicetree/bindings/rtc/qcom-pm8xxx-rtc.yaml b/Documentation/devicetree/bindings/rtc/qcom-pm8xxx-rtc.yaml index d274bb7a534b..7497dc3ac5b2 100644 --- a/Documentation/devicetree/bindings/rtc/qcom-pm8xxx-rtc.yaml +++ b/Documentation/devicetree/bindings/rtc/qcom-pm8xxx-rtc.yaml @@ -50,6 +50,17 @@ properties: items: - const: offset + qcom,no-alarm: + type: boolean + description: + RTC alarm is not owned by the OS + + qcom,uefi-rtc-info: + type: boolean + description: + RTC offset is stored as a four-byte GPS time offset in a 12-byte UEFI + variable 882f8c2b-9646-435f-8de5-f208ff80c1bd-RTCInfo + wakeup-source: true required: diff --git a/Documentation/devicetree/bindings/rtc/renesas,rzn1-rtc.yaml b/Documentation/devicetree/bindings/rtc/renesas,rzn1-rtc.yaml index f6e0c613af67..f6fdcc7090b6 100644 --- a/Documentation/devicetree/bindings/rtc/renesas,rzn1-rtc.yaml +++ b/Documentation/devicetree/bindings/rtc/renesas,rzn1-rtc.yaml @@ -33,10 +33,14 @@ properties: - const: pps clocks: - maxItems: 1 + minItems: 1 + maxItems: 2 clock-names: - const: hclk + minItems: 1 + items: + - const: hclk + - const: xtal power-domains: maxItems: 1 diff --git a/Documentation/devicetree/bindings/serial/8250.yaml b/Documentation/devicetree/bindings/serial/8250.yaml index 0bde2379e864..c6bc27709bf7 100644 --- a/Documentation/devicetree/bindings/serial/8250.yaml +++ b/Documentation/devicetree/bindings/serial/8250.yaml @@ -45,7 +45,7 @@ allOf: - ns16550 - ns16550a then: - anyOf: + oneOf: - required: [ clock-frequency ] - required: [ clocks ] @@ -77,7 +77,6 @@ properties: - altr,16550-FIFO64 - altr,16550-FIFO128 - fsl,16550-FIFO64 - - fsl,ns16550 - andestech,uart16550 - nxp,lpc1850-uart - opencores,uart16550-rtlsvn105 @@ -86,6 +85,7 @@ properties: - items: - enum: - ns16750 + - fsl,ns16550 - cavium,octeon-3860-uart - xlnx,xps-uart16550-2.00.b - ralink,rt2880-uart @@ -135,7 +135,16 @@ properties: clock-frequency: true clocks: - maxItems: 1 + minItems: 1 + items: + - description: The core function clock + - description: An optional bus clock + + clock-names: + minItems: 1 + items: + - const: core + - const: bus resets: maxItems: 1 @@ -224,6 +233,25 @@ required: - reg - interrupts +if: + properties: + compatible: + contains: + const: spacemit,k1-uart +then: + required: [clock-names] + properties: + clocks: + minItems: 2 + clock-names: + minItems: 2 +else: + properties: + clocks: + maxItems: 1 + clock-names: + maxItems: 1 + unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/serial/8250_omap.yaml b/Documentation/devicetree/bindings/serial/8250_omap.yaml index 4b78de6b46a2..1859f71297ff 100644 --- a/Documentation/devicetree/bindings/serial/8250_omap.yaml +++ b/Documentation/devicetree/bindings/serial/8250_omap.yaml @@ -64,14 +64,7 @@ properties: clock-names: const: fclk - rts-gpios: true - cts-gpios: true - dtr-gpios: true - dsr-gpios: true - rng-gpios: true - dcd-gpios: true rs485-rts-active-high: true - rts-gpio: true power-domains: true clock-frequency: true current-speed: true diff --git a/Documentation/devicetree/bindings/serial/altera_jtaguart.txt b/Documentation/devicetree/bindings/serial/altera_jtaguart.txt deleted file mode 100644 index 55a901051e8f..000000000000 --- a/Documentation/devicetree/bindings/serial/altera_jtaguart.txt +++ /dev/null @@ -1,5 +0,0 @@ -Altera JTAG UART - -Required properties: -- compatible : should be "ALTR,juart-1.0" <DEPRECATED> -- compatible : should be "altr,juart-1.0" diff --git a/Documentation/devicetree/bindings/serial/altera_uart.txt b/Documentation/devicetree/bindings/serial/altera_uart.txt deleted file mode 100644 index 81bf7ffb1a81..000000000000 --- a/Documentation/devicetree/bindings/serial/altera_uart.txt +++ /dev/null @@ -1,8 +0,0 @@ -Altera UART - -Required properties: -- compatible : should be "ALTR,uart-1.0" <DEPRECATED> -- compatible : should be "altr,uart-1.0" - -Optional properties: -- clock-frequency : frequency of the clock input to the UART diff --git a/Documentation/devicetree/bindings/serial/altr,juart-1.0.yaml b/Documentation/devicetree/bindings/serial/altr,juart-1.0.yaml new file mode 100644 index 000000000000..02e20fa591da --- /dev/null +++ b/Documentation/devicetree/bindings/serial/altr,juart-1.0.yaml @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/altr,juart-1.0.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Altera JTAG UART + +maintainers: + - Dinh Nguyen <dinguyen@kernel.org> + +properties: + compatible: + const: altr,juart-1.0 + +required: + - compatible + +additionalProperties: false diff --git a/Documentation/devicetree/bindings/serial/altr,uart-1.0.yaml b/Documentation/devicetree/bindings/serial/altr,uart-1.0.yaml new file mode 100644 index 000000000000..72d4972e1e22 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/altr,uart-1.0.yaml @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/altr,uart-1.0.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Altera UART + +maintainers: + - Dinh Nguyen <dinguyen@kernel.org> + +allOf: + - $ref: /schemas/serial/serial.yaml# + +properties: + compatible: + const: altr,uart-1.0 + + clock-frequency: + description: Frequency of the clock input to the UART. + +required: + - compatible + +unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/serial/amlogic,meson-uart.yaml b/Documentation/devicetree/bindings/serial/amlogic,meson-uart.yaml index 0565fb7649c5..d8ad1bb6172d 100644 --- a/Documentation/devicetree/bindings/serial/amlogic,meson-uart.yaml +++ b/Documentation/devicetree/bindings/serial/amlogic,meson-uart.yaml @@ -56,6 +56,9 @@ properties: items: - enum: - amlogic,a4-uart + - amlogic,s6-uart + - amlogic,s7-uart + - amlogic,s7d-uart - amlogic,t7-uart - const: amlogic,meson-s4-uart diff --git a/Documentation/devicetree/bindings/serial/arc-uart.txt b/Documentation/devicetree/bindings/serial/arc-uart.txt deleted file mode 100644 index 256cc150ca7e..000000000000 --- a/Documentation/devicetree/bindings/serial/arc-uart.txt +++ /dev/null @@ -1,25 +0,0 @@ -* Synopsys ARC UART : Non standard UART used in some of the ARC FPGA boards - -Required properties: -- compatible : "snps,arc-uart" -- reg : offset and length of the register set for the device. -- interrupts : device interrupt -- clock-frequency : the input clock frequency for the UART -- current-speed : baud rate for UART - -e.g. - -arcuart0: serial@c0fc1000 { - compatible = "snps,arc-uart"; - reg = <0xc0fc1000 0x100>; - interrupts = <5>; - clock-frequency = <80000000>; - current-speed = <115200>; -}; - -Note: Each port should have an alias correctly numbered in "aliases" node. - -e.g. -aliases { - serial0 = &arcuart0; -}; diff --git a/Documentation/devicetree/bindings/serial/arm,mps2-uart.txt b/Documentation/devicetree/bindings/serial/arm,mps2-uart.txt deleted file mode 100644 index 128cc6aed001..000000000000 --- a/Documentation/devicetree/bindings/serial/arm,mps2-uart.txt +++ /dev/null @@ -1,19 +0,0 @@ -ARM MPS2 UART - -Required properties: -- compatible : Should be "arm,mps2-uart" -- reg : Address and length of the register set -- interrupts : Reference to the UART RX, TX and overrun interrupts - -Required clocking property: -- clocks : The input clock of the UART - - -Examples: - -uart0: serial@40004000 { - compatible = "arm,mps2-uart"; - reg = <0x40004000 0x1000>; - interrupts = <0 1 12>; - clocks = <&sysclk>; -}; diff --git a/Documentation/devicetree/bindings/serial/arm,mps2-uart.yaml b/Documentation/devicetree/bindings/serial/arm,mps2-uart.yaml new file mode 100644 index 000000000000..4a8df078e6f3 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/arm,mps2-uart.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/arm,mps2-uart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Arm MPS2 UART + +maintainers: + - Vladimir Murzin <vladimir.murzin@arm.com> + +allOf: + - $ref: /schemas/serial/serial.yaml# + +properties: + compatible: + const: arm,mps2-uart + + reg: + maxItems: 1 + + interrupts: + items: + - description: RX interrupt + - description: TX interrupt + - description: Overrun interrupt + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +unevaluatedProperties: false + +examples: + - | + serial@40004000 { + compatible = "arm,mps2-uart"; + reg = <0x40004000 0x1000>; + interrupts = <0>, <1>, <12>; + clocks = <&sysclk>; + }; diff --git a/Documentation/devicetree/bindings/serial/arm,sbsa-uart.yaml b/Documentation/devicetree/bindings/serial/arm,sbsa-uart.yaml new file mode 100644 index 000000000000..68e3fd64b1d8 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/arm,sbsa-uart.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +--- +$id: http://devicetree.org/schemas/serial/arm,sbsa-uart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM SBSA UART + +maintainers: + - Andre Przywara <andre.przywara@arm.com> + +description: + This UART uses a subset of the PL011 registers and consequently lives in the + PL011 driver. It's baudrate and other communication parameters cannot be + adjusted at runtime, so it lacks a clock specifier here. + +allOf: + - $ref: /schemas/serial/serial.yaml# + +properties: + compatible: + const: arm,sbsa-uart + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + current-speed: + description: fixed baud rate set by the firmware + +required: + - compatible + - reg + - interrupts + - current-speed + +unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/serial/arm_sbsa_uart.txt b/Documentation/devicetree/bindings/serial/arm_sbsa_uart.txt deleted file mode 100644 index 4163e7eb7763..000000000000 --- a/Documentation/devicetree/bindings/serial/arm_sbsa_uart.txt +++ /dev/null @@ -1,10 +0,0 @@ -* ARM SBSA defined generic UART -This UART uses a subset of the PL011 registers and consequently lives -in the PL011 driver. It's baudrate and other communication parameters -cannot be adjusted at runtime, so it lacks a clock specifier here. - -Required properties: -- compatible: must be "arm,sbsa-uart" -- reg: exactly one register range -- interrupts: exactly one interrupt specifier -- current-speed: the (fixed) baud rate set by the firmware diff --git a/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml b/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml index f466c38518c4..087a8926f8b4 100644 --- a/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml +++ b/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml @@ -26,6 +26,7 @@ properties: - enum: - microchip,sam9x60-usart - microchip,sam9x7-usart + - microchip,sama7d65-usart - const: atmel,at91sam9260-usart - items: - const: microchip,sam9x60-dbgu diff --git a/Documentation/devicetree/bindings/serial/cirrus,clps711x-uart.txt b/Documentation/devicetree/bindings/serial/cirrus,clps711x-uart.txt deleted file mode 100644 index 07013fa60a48..000000000000 --- a/Documentation/devicetree/bindings/serial/cirrus,clps711x-uart.txt +++ /dev/null @@ -1,31 +0,0 @@ -* Cirrus Logic CLPS711X Universal Asynchronous Receiver/Transmitter (UART) - -Required properties: -- compatible: Should be "cirrus,ep7209-uart". -- reg: Address and length of the register set for the device. -- interrupts: Should contain UART TX and RX interrupt. -- clocks: Should contain UART core clock number. -- syscon: Phandle to SYSCON node, which contain UART control bits. - -Optional properties: -- {rts,cts,dtr,dsr,rng,dcd}-gpios: specify a GPIO for RTS/CTS/DTR/DSR/RI/DCD - line respectively. - -Note: Each UART port should have an alias correctly numbered -in "aliases" node. - -Example: - aliases { - serial0 = &uart1; - }; - - uart1: uart@80000480 { - compatible = "cirrus,ep7312-uart","cirrus,ep7209-uart"; - reg = <0x80000480 0x80>; - interrupts = <12 13>; - clocks = <&clks 11>; - syscon = <&syscon1>; - cts-gpios = <&sysgpio 0 GPIO_ACTIVE_LOW>; - dsr-gpios = <&sysgpio 1 GPIO_ACTIVE_LOW>; - dcd-gpios = <&sysgpio 2 GPIO_ACTIVE_LOW>; - }; diff --git a/Documentation/devicetree/bindings/serial/cirrus,ep7209-uart.yaml b/Documentation/devicetree/bindings/serial/cirrus,ep7209-uart.yaml new file mode 100644 index 000000000000..c9976e86872b --- /dev/null +++ b/Documentation/devicetree/bindings/serial/cirrus,ep7209-uart.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/cirrus,ep7209-uart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cirrus Logic CLPS711X Universal Asynchronous Receiver/Transmitter (UART) + +maintainers: + - Alexander Shiyan <shc_work@mail.ru> + +allOf: + - $ref: /schemas/serial/serial.yaml# + +properties: + compatible: + const: cirrus,ep7209-uart + + reg: + maxItems: 1 + + interrupts: + items: + - description: UART TX interrupt + - description: UART RX interrupt + + clocks: + maxItems: 1 + + syscon: + description: Phandle to SYSCON node, which contains UART control bits. + $ref: /schemas/types.yaml#/definitions/phandle + +required: + - compatible + - reg + - interrupts + - clocks + - syscon + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + serial@80000480 { + compatible = "cirrus,ep7209-uart"; + reg = <0x80000480 0x80>; + interrupts = <12>, <13>; + clocks = <&clks 11>; + syscon = <&syscon1>; + cts-gpios = <&sysgpio 0 GPIO_ACTIVE_LOW>; + dsr-gpios = <&sysgpio 1 GPIO_ACTIVE_LOW>; + dcd-gpios = <&sysgpio 2 GPIO_ACTIVE_LOW>; + }; diff --git a/Documentation/devicetree/bindings/serial/cnxt,cx92755-usart.yaml b/Documentation/devicetree/bindings/serial/cnxt,cx92755-usart.yaml new file mode 100644 index 000000000000..720229455330 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/cnxt,cx92755-usart.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/cnxt,cx92755-usart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Conexant Digicolor USART + +maintainers: + - Baruch Siach <baruch@tkos.co.il> + +description: > + Note: this binding is only applicable for using the USART peripheral as UART. + USART also support synchronous serial protocols like SPI and I2S. + Use the binding that matches the wiring of your system. + +allOf: + - $ref: /schemas/serial/serial.yaml# + +properties: + compatible: + const: cnxt,cx92755-usart + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - interrupts + +unevaluatedProperties: false + +examples: + - | + serial@f0000740 { + compatible = "cnxt,cx92755-usart"; + reg = <0xf0000740 0x20>; + clocks = <&main_clk>; + interrupts = <44>; + }; diff --git a/Documentation/devicetree/bindings/serial/digicolor-usart.txt b/Documentation/devicetree/bindings/serial/digicolor-usart.txt deleted file mode 100644 index 2d3ede66889d..000000000000 --- a/Documentation/devicetree/bindings/serial/digicolor-usart.txt +++ /dev/null @@ -1,27 +0,0 @@ -Binding for Conexant Digicolor USART - -Note: this binding is only applicable for using the USART peripheral as -UART. USART also support synchronous serial protocols like SPI and I2S. Use -the binding that matches the wiring of your system. - -Required properties: -- compatible : should be "cnxt,cx92755-usart". -- reg: Should contain USART controller registers location and length. -- interrupts: Should contain a single USART controller interrupt. -- clocks: Must contain phandles to the USART clock - See ../clocks/clock-bindings.txt for details. - -Note: Each UART port should have an alias correctly numbered -in "aliases" node. - -Example: - aliases { - serial0 = &uart0; - }; - - uart0: uart@f0000740 { - compatible = "cnxt,cx92755-usart"; - reg = <0xf0000740 0x20>; - clocks = <&main_clk>; - interrupts = <44>; - }; diff --git a/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml b/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml index 3f9ace89dee9..c42261b5a80a 100644 --- a/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml +++ b/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml @@ -30,6 +30,7 @@ properties: - items: - enum: - fsl,imx93-lpuart + - fsl,imx94-lpuart - fsl,imx95-lpuart - const: fsl,imx8ulp-lpuart - const: fsl,imx7ulp-lpuart diff --git a/Documentation/devicetree/bindings/serial/lantiq,asc.yaml b/Documentation/devicetree/bindings/serial/lantiq,asc.yaml new file mode 100644 index 000000000000..96e8c79cb047 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/lantiq,asc.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/lantiq,asc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Lantiq SoC ASC serial controller + +maintainers: + - John Crispin <john@phrozen.org> + - Songjun Wu <songjun.wu@linux.intel.com> + +allOf: + - $ref: /schemas/serial/serial.yaml# + +properties: + compatible: + const: lantiq,asc + + reg: + maxItems: 1 + + interrupts: + items: + - description: TX interrupt + - description: RX interrupt + - description: Error interrupt + + clocks: + items: + - description: Frequency clock + - description: Gate clock + + clock-names: + items: + - const: freq + - const: asc + +required: + - compatible + - reg + - interrupts + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/mips-gic.h> + + serial@16600000 { + compatible = "lantiq,asc"; + reg = <0x16600000 0x100000>; + interrupts = <GIC_SHARED 103 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SHARED 105 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SHARED 106 IRQ_TYPE_LEVEL_HIGH>; + }; diff --git a/Documentation/devicetree/bindings/serial/lantiq_asc.txt b/Documentation/devicetree/bindings/serial/lantiq_asc.txt deleted file mode 100644 index 40e81a5818f6..000000000000 --- a/Documentation/devicetree/bindings/serial/lantiq_asc.txt +++ /dev/null @@ -1,31 +0,0 @@ -Lantiq SoC ASC serial controller - -Required properties: -- compatible : Should be "lantiq,asc" -- reg : Address and length of the register set for the device -- interrupts: the 3 (tx rx err) interrupt numbers. The interrupt specifier - depends on the interrupt-parent interrupt controller. - -Optional properties: -- clocks: Should contain frequency clock and gate clock -- clock-names: Should be "freq" and "asc" - -Example: - -asc0: serial@16600000 { - compatible = "lantiq,asc"; - reg = <0x16600000 0x100000>; - interrupt-parent = <&gic>; - interrupts = <GIC_SHARED 103 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SHARED 105 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SHARED 106 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cgu CLK_SSX4>, <&cgu GCLK_UART>; - clock-names = "freq", "asc"; -}; - -asc1: serial@e100c00 { - compatible = "lantiq,asc"; - reg = <0xE100C00 0x400>; - interrupt-parent = <&icu0>; - interrupts = <112 113 114>; -}; diff --git a/Documentation/devicetree/bindings/serial/marvell,armada-3700-uart.yaml b/Documentation/devicetree/bindings/serial/marvell,armada-3700-uart.yaml new file mode 100644 index 000000000000..6c7fa3d19369 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/marvell,armada-3700-uart.yaml @@ -0,0 +1,102 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/marvell,armada-3700-uart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Armada-3700 UART + +maintainers: + - Pali Rohár <pali@kernel.org> + +description: + Marvell UART is a non standard UART used in some of Marvell EBU SoCs (e.g. + Armada-3700). + +properties: + compatible: + enum: + - marvell,armada-3700-uart + - marvell,armada-3700-uart-ext + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + description: + UART reference clock used to derive the baud rate. If absent, only fixed + baud rate from the bootloader is supported. + + interrupts: + minItems: 2 + items: + - description: UART sum interrupt + - description: UART TX interrupt + - description: UART RX interrupt + + interrupt-names: + minItems: 2 + maxItems: 3 + +required: + - compatible + - reg + - interrupts + - interrupt-names + +unevaluatedProperties: false + +allOf: + - $ref: /schemas/serial/serial.yaml# + - if: + properties: + compatible: + const: marvell,armada-3700-uart-ext + then: + properties: + interrupts: + maxItems: 2 + + interrupt-names: + items: + - const: uart-tx + - const: uart-rx + else: + properties: + interrupts: + minItems: 3 + + interrupt-names: + items: + - const: uart-sum + - const: uart-tx + - const: uart-rx + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + serial@12000 { + compatible = "marvell,armada-3700-uart"; + reg = <0x12000 0x18>; + clocks = <&uartclk 0>; + interrupts = + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uart-sum", "uart-tx", "uart-rx"; + }; + + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + serial@12200 { + compatible = "marvell,armada-3700-uart-ext"; + reg = <0x12200 0x30>; + clocks = <&uartclk 1>; + interrupts = + <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "uart-tx", "uart-rx"; + }; diff --git a/Documentation/devicetree/bindings/serial/mediatek,uart.yaml b/Documentation/devicetree/bindings/serial/mediatek,uart.yaml index 1b02f0b197ff..c55d9a0efa19 100644 --- a/Documentation/devicetree/bindings/serial/mediatek,uart.yaml +++ b/Documentation/devicetree/bindings/serial/mediatek,uart.yaml @@ -33,6 +33,7 @@ properties: - mediatek,mt6779-uart - mediatek,mt6795-uart - mediatek,mt6797-uart + - mediatek,mt6893-uart - mediatek,mt7622-uart - mediatek,mt7623-uart - mediatek,mt7629-uart diff --git a/Documentation/devicetree/bindings/serial/microchip,pic32-uart.txt b/Documentation/devicetree/bindings/serial/microchip,pic32-uart.txt deleted file mode 100644 index c8dd440e9747..000000000000 --- a/Documentation/devicetree/bindings/serial/microchip,pic32-uart.txt +++ /dev/null @@ -1,29 +0,0 @@ -* Microchip Universal Asynchronous Receiver Transmitter (UART) - -Required properties: -- compatible: Should be "microchip,pic32mzda-uart" -- reg: Should contain registers location and length -- interrupts: Should contain interrupt -- clocks: Phandle to the clock. - See: Documentation/devicetree/bindings/clock/clock-bindings.txt -- pinctrl-names: A pinctrl state names "default" must be defined. -- pinctrl-0: Phandle referencing pin configuration of the UART peripheral. - See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt - -Optional properties: -- cts-gpios: CTS pin for UART - -Example: - uart1: serial@1f822000 { - compatible = "microchip,pic32mzda-uart"; - reg = <0x1f822000 0x50>; - interrupts = <112 IRQ_TYPE_LEVEL_HIGH>, - <113 IRQ_TYPE_LEVEL_HIGH>, - <114 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rootclk PB2CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1 - &pinctrl_uart1_cts - &pinctrl_uart1_rts>; - cts-gpios = <&gpio1 15 0>; - }; diff --git a/Documentation/devicetree/bindings/serial/microchip,pic32mzda-uart.yaml b/Documentation/devicetree/bindings/serial/microchip,pic32mzda-uart.yaml new file mode 100644 index 000000000000..b176fd5b580e --- /dev/null +++ b/Documentation/devicetree/bindings/serial/microchip,pic32mzda-uart.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/microchip,pic32mzda-uart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PIC32 UART + +maintainers: + - Andrei Pistirica <andrei.pistirica@microchip.com> + - Purna Chandra Mandal <purna.mandal@microchip.com> + +allOf: + - $ref: /schemas/serial/serial.yaml# + +properties: + compatible: + const: microchip,pic32mzda-uart + + reg: + maxItems: 1 + + interrupts: + items: + - description: Fault + - description: RX + - description: TX + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/clock/microchip,pic32-clock.h> + + serial@1f822000 { + compatible = "microchip,pic32mzda-uart"; + reg = <0x1f822000 0x50>; + interrupts = <112 IRQ_TYPE_LEVEL_HIGH>, + <113 IRQ_TYPE_LEVEL_HIGH>, + <114 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rootclk PB2CLK>; + cts-gpios = <&gpio1 15 0>; + }; diff --git a/Documentation/devicetree/bindings/serial/milbeaut-uart.txt b/Documentation/devicetree/bindings/serial/milbeaut-uart.txt deleted file mode 100644 index 3d2fb1a7ba94..000000000000 --- a/Documentation/devicetree/bindings/serial/milbeaut-uart.txt +++ /dev/null @@ -1,21 +0,0 @@ -Socionext Milbeaut UART controller - -Required properties: -- compatible: should be "socionext,milbeaut-usio-uart". -- reg: offset and length of the register set for the device. -- interrupts: two interrupts specifier. -- interrupt-names: should be "rx", "tx". -- clocks: phandle to the input clock. - -Optional properties: -- auto-flow-control: flow control enable. - -Example: - usio1: usio_uart@1e700010 { - compatible = "socionext,milbeaut-usio-uart"; - reg = <0x1e700010 0x10>; - interrupts = <0 141 0x4>, <0 149 0x4>; - interrupt-names = "rx", "tx"; - clocks = <&clk 2>; - auto-flow-control; - }; diff --git a/Documentation/devicetree/bindings/serial/mvebu-uart.txt b/Documentation/devicetree/bindings/serial/mvebu-uart.txt deleted file mode 100644 index a062bbca532c..000000000000 --- a/Documentation/devicetree/bindings/serial/mvebu-uart.txt +++ /dev/null @@ -1,56 +0,0 @@ -* Marvell UART : Non standard UART used in some of Marvell EBU SoCs - e.g., Armada-3700. - -Required properties: -- compatible: - - "marvell,armada-3700-uart" for the standard variant of the UART - (32 bytes FIFO, no DMA, level interrupts, 8-bit access to the - FIFO), called also UART1. - - "marvell,armada-3700-uart-ext" for the extended variant of the - UART (128 bytes FIFO, DMA, front interrupts, 8-bit or 32-bit - accesses to the FIFO), called also UART2. -- reg: offset and length of the register set for the device. -- clocks: UART reference clock used to derive the baudrate. If no clock - is provided (possible only with the "marvell,armada-3700-uart" - compatible string for backward compatibility), it will only work - if the baudrate was initialized by the bootloader and no baudrate - change will then be possible. When provided it should be UART1-clk - for standard variant of UART and UART2-clk for extended variant - of UART. TBG clock (with UART TBG divisors d1=d2=1) or xtal clock - should not be used and are supported only for backward compatibility. -- interrupts: - - Must contain three elements for the standard variant of the IP - (marvell,armada-3700-uart): "uart-sum", "uart-tx" and "uart-rx", - respectively the UART sum interrupt, the UART TX interrupt and - UART RX interrupt. A corresponding interrupt-names property must - be defined. - - Must contain two elements for the extended variant of the IP - (marvell,armada-3700-uart-ext): "uart-tx" and "uart-rx", - respectively the UART TX interrupt and the UART RX interrupt. A - corresponding interrupt-names property must be defined. - - For backward compatibility reasons, a single element interrupts - property is also supported for the standard variant of the IP, - containing only the UART sum interrupt. This form is deprecated - and should no longer be used. - -Example: - uart0: serial@12000 { - compatible = "marvell,armada-3700-uart"; - reg = <0x12000 0x18>; - clocks = <&uartclk 0>; - interrupts = - <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "uart-sum", "uart-tx", "uart-rx"; - }; - - uart1: serial@12200 { - compatible = "marvell,armada-3700-uart-ext"; - reg = <0x12200 0x30>; - clocks = <&uartclk 1>; - interrupts = - <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "uart-tx", "uart-rx"; - }; diff --git a/Documentation/devicetree/bindings/serial/nvidia,tegra264-utc.yaml b/Documentation/devicetree/bindings/serial/nvidia,tegra264-utc.yaml new file mode 100644 index 000000000000..572cc574da64 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/nvidia,tegra264-utc.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/nvidia,tegra264-utc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra UTC (UART Trace Controller) client + +maintainers: + - Kartik Rajput <kkartik@nvidia.com> + - Thierry Reding <thierry.reding@gmail.com> + - Jonathan Hunter <jonathanh@nvidia.com> + +description: + Represents a client interface of the Tegra UTC (UART Trace Controller). The + Tegra UTC allows multiple clients within the Tegra SoC to share a physical + UART interface. It supports up to 16 clients. Each client operates as an + independent UART endpoint with a dedicated interrupt and 128-character TX/RX + FIFOs. + + The Tegra UTC clients use 8-N-1 configuration and operates on a baudrate + configured by the bootloader at the controller level. + +allOf: + - $ref: serial.yaml# + +properties: + compatible: + const: nvidia,tegra264-utc + + reg: + items: + - description: TX region. + - description: RX region. + + reg-names: + items: + - const: tx + - const: rx + + interrupts: + maxItems: 1 + + tx-threshold: + minimum: 1 + maximum: 128 + + rx-threshold: + minimum: 1 + maximum: 128 + +required: + - compatible + - reg + - reg-names + - interrupts + - tx-threshold + - rx-threshold + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + tegra_utc: serial@c4e0000 { + compatible = "nvidia,tegra264-utc"; + reg = <0xc4e0000 0x8000>, <0xc4e8000 0x8000>; + reg-names = "tx", "rx"; + interrupts = <GIC_SPI 514 IRQ_TYPE_LEVEL_HIGH>; + tx-threshold = <4>; + rx-threshold = <4>; + }; diff --git a/Documentation/devicetree/bindings/serial/nxp,lpc3220-hsuart.yaml b/Documentation/devicetree/bindings/serial/nxp,lpc3220-hsuart.yaml new file mode 100644 index 000000000000..ffa2ea59f256 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/nxp,lpc3220-hsuart.yaml @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/nxp,lpc3220-hsuart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP LPC32xx SoC High Speed UART + +maintainers: + - Vladimir Zapolskiy <vz@mleia.com> + - Piotr Wojtaszczyk <piotr.wojtaszczyk@timesys.com> + +allOf: + - $ref: /schemas/serial/serial.yaml# + +properties: + compatible: + const: nxp,lpc3220-hsuart + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +unevaluatedProperties: false + +examples: + - | + serial@40014000 { + compatible = "nxp,lpc3220-hsuart"; + reg = <0x40014000 0x1000>; + interrupts = <26 0>; + }; diff --git a/Documentation/devicetree/bindings/serial/nxp-lpc32xx-hsuart.txt b/Documentation/devicetree/bindings/serial/nxp-lpc32xx-hsuart.txt deleted file mode 100644 index 0d439dfc1aa5..000000000000 --- a/Documentation/devicetree/bindings/serial/nxp-lpc32xx-hsuart.txt +++ /dev/null @@ -1,14 +0,0 @@ -* NXP LPC32xx SoC High Speed UART - -Required properties: -- compatible: Should be "nxp,lpc3220-hsuart" -- reg: Should contain registers location and length -- interrupts: Should contain interrupt - -Example: - - uart1: serial@40014000 { - compatible = "nxp,lpc3220-hsuart"; - reg = <0x40014000 0x1000>; - interrupts = <26 0>; - }; diff --git a/Documentation/devicetree/bindings/serial/pl011.yaml b/Documentation/devicetree/bindings/serial/pl011.yaml index 9571041030b7..3fcf2d042372 100644 --- a/Documentation/devicetree/bindings/serial/pl011.yaml +++ b/Documentation/devicetree/bindings/serial/pl011.yaml @@ -92,6 +92,9 @@ properties: 3000ms. default: 3000 + power-domains: + maxItems: 1 + resets: maxItems: 1 diff --git a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml new file mode 100644 index 000000000000..ea879db5f485 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml @@ -0,0 +1,78 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/renesas,rsci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RSCI Serial Communication Interface + +maintainers: + - Geert Uytterhoeven <geert+renesas@glider.be> + - Thierry Bultel <thierry.bultel.yh@bp.renesas.com> + +allOf: + - $ref: serial.yaml# + +properties: + compatible: + const: renesas,r9a09g077-rsci # RZ/T2H + + reg: + maxItems: 1 + + interrupts: + items: + - description: Error interrupt + - description: Receive buffer full interrupt + - description: Transmit buffer empty interrupt + - description: Transmit end interrupt + + interrupt-names: + items: + - const: eri + - const: rxi + - const: txi + - const: tei + + clocks: + maxItems: 1 + + clock-names: + const: fck # UART functional clock + + power-domains: + maxItems: 1 + + uart-has-rtscts: false + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - power-domains + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/renesas-cpg-mssr.h> + + aliases { + serial0 = &sci0; + }; + + sci0: serial@80005000 { + compatible = "renesas,r9a09g077-rsci"; + reg = <0x80005000 0x400>; + interrupts = <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 591 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 592 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD 108>; + clock-names = "fck"; + power-domains = <&cpg>; + }; diff --git a/Documentation/devicetree/bindings/serial/samsung_uart.yaml b/Documentation/devicetree/bindings/serial/samsung_uart.yaml index 070eba9f19d3..83d9986d8e98 100644 --- a/Documentation/devicetree/bindings/serial/samsung_uart.yaml +++ b/Documentation/devicetree/bindings/serial/samsung_uart.yaml @@ -42,6 +42,10 @@ properties: - samsung,exynosautov9-uart - samsung,exynosautov920-uart - const: samsung,exynos850-uart + - items: + - enum: + - samsung,exynos7870-uart + - const: samsung,exynos8895-uart reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/serial/snps,arc-uart.yaml b/Documentation/devicetree/bindings/serial/snps,arc-uart.yaml new file mode 100644 index 000000000000..dd3096fbfb6a --- /dev/null +++ b/Documentation/devicetree/bindings/serial/snps,arc-uart.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/snps,arc-uart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Synopsys ARC UART + +maintainers: + - Vineet Gupta <vgupta@kernel.org> + +description: + Synopsys ARC UART is a non-standard UART used in some of the ARC FPGA boards. + +allOf: + - $ref: /schemas/serial/serial.yaml# + +properties: + compatible: + const: snps,arc-uart + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clock-frequency: + description: the input clock frequency for the UART + + current-speed: + description: baud rate for UART + +required: + - compatible + - reg + - interrupts + - clock-frequency + - current-speed + +unevaluatedProperties: false + +examples: + - | + serial@c0fc1000 { + compatible = "snps,arc-uart"; + reg = <0xc0fc1000 0x100>; + interrupts = <5>; + clock-frequency = <80000000>; + current-speed = <115200>; + }; diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml index 1c163cb5dff1..8f1b7f704c5b 100644 --- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml +++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml @@ -16,6 +16,18 @@ allOf: - if: properties: compatible: + items: + - {} + - const: renesas,rzn1-uart + - const: snps,dw-apb-uart + then: + properties: + dmas: false + dma-names: false + + - if: + properties: + compatible: contains: const: starfive,jh7110-uart then: @@ -31,9 +43,11 @@ properties: compatible: oneOf: - items: - - enum: - - renesas,r9a06g032-uart - - renesas,r9a06g033-uart + - const: renesas,r9a06g032-uart + - const: renesas,rzn1-uart + - const: snps,dw-apb-uart + - items: + - const: renesas,r9a06g032-uart - const: renesas,rzn1-uart - items: - enum: @@ -51,6 +65,7 @@ properties: - rockchip,rk3368-uart - rockchip,rk3399-uart - rockchip,rk3528-uart + - rockchip,rk3562-uart - rockchip,rk3568-uart - rockchip,rk3576-uart - rockchip,rk3588-uart diff --git a/Documentation/devicetree/bindings/serial/socionext,milbeaut-usio-uart.yaml b/Documentation/devicetree/bindings/serial/socionext,milbeaut-usio-uart.yaml new file mode 100644 index 000000000000..34a997ca2e11 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/socionext,milbeaut-usio-uart.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/socionext,milbeaut-usio-uart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Socionext Milbeaut UART controller + +maintainers: + - Sugaya Taichi <sugaya.taichi@socionext.com> + +allOf: + - $ref: /schemas/serial/serial.yaml# + +properties: + compatible: + const: socionext,milbeaut-usio-uart + + reg: + maxItems: 1 + + interrupts: + items: + - description: RX interrupt specifier + - description: TX interrupt specifier + + interrupt-names: + items: + - const: rx + - const: tx + + clocks: + maxItems: 1 + + auto-flow-control: + description: Enable automatic flow control. + type: boolean + +required: + - compatible + - reg + - interrupts + - interrupt-names + +unevaluatedProperties: false + +examples: + - | + serial@1e700010 { + compatible = "socionext,milbeaut-usio-uart"; + reg = <0x1e700010 0x10>; + interrupts = <0 141 0x4>, <0 149 0x4>; + interrupt-names = "rx", "tx"; + clocks = <&clk 2>; + auto-flow-control; + }; diff --git a/Documentation/devicetree/bindings/serial/sprd-uart.yaml b/Documentation/devicetree/bindings/serial/sprd-uart.yaml index a2a5056eba04..5bf2656afcfd 100644 --- a/Documentation/devicetree/bindings/serial/sprd-uart.yaml +++ b/Documentation/devicetree/bindings/serial/sprd-uart.yaml @@ -17,13 +17,18 @@ properties: oneOf: - items: - enum: - - sprd,sc9632-uart + - sprd,ums9632-uart + - const: sprd,sc9632-uart + - items: + - enum: - sprd,sc9860-uart - sprd,sc9863a-uart - sprd,ums512-uart - sprd,ums9620-uart - const: sprd,sc9836-uart - - const: sprd,sc9836-uart + - enum: + - sprd,sc9632-uart + - sprd,sc9836-uart reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/soc/amlogic/amlogic,meson-gx-clk-measure.yaml b/Documentation/devicetree/bindings/soc/amlogic/amlogic,meson-gx-clk-measure.yaml index 77c281153010..39d4637c2d08 100644 --- a/Documentation/devicetree/bindings/soc/amlogic/amlogic,meson-gx-clk-measure.yaml +++ b/Documentation/devicetree/bindings/soc/amlogic/amlogic,meson-gx-clk-measure.yaml @@ -22,6 +22,8 @@ properties: - amlogic,meson-axg-clk-measure - amlogic,meson-g12a-clk-measure - amlogic,meson-sm1-clk-measure + - amlogic,c3-clk-measure + - amlogic,s4-clk-measure reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/soc/fsl/fsl,ls1028a-reset.yaml b/Documentation/devicetree/bindings/soc/fsl/fsl,ls1028a-reset.yaml index 234089b5954d..b43df10c5ef4 100644 --- a/Documentation/devicetree/bindings/soc/fsl/fsl,ls1028a-reset.yaml +++ b/Documentation/devicetree/bindings/soc/fsl/fsl,ls1028a-reset.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas//soc/fsl/fsl,ls1028a-reset.yaml# +$id: http://devicetree.org/schemas/soc/fsl/fsl,ls1028a-reset.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Freescale Layerscape Reset Registers Module diff --git a/Documentation/devicetree/bindings/soc/fsl/fsl,qman-fqd.yaml b/Documentation/devicetree/bindings/soc/fsl/fsl,qman-fqd.yaml index de0b4ae740ff..a975bce59975 100644 --- a/Documentation/devicetree/bindings/soc/fsl/fsl,qman-fqd.yaml +++ b/Documentation/devicetree/bindings/soc/fsl/fsl,qman-fqd.yaml @@ -50,7 +50,7 @@ required: - compatible allOf: - - $ref: reserved-memory.yaml + - $ref: /schemas/reserved-memory/reserved-memory.yaml unevaluatedProperties: false @@ -61,7 +61,7 @@ examples: #size-cells = <2>; qman-fqd { - compatible = "shared-dma-pool"; + compatible = "fsl,qman-fqd"; size = <0 0x400000>; alignment = <0 0x400000>; no-map; diff --git a/Documentation/devicetree/bindings/soc/google/google,gs101-pmu-intr-gen.yaml b/Documentation/devicetree/bindings/soc/google/google,gs101-pmu-intr-gen.yaml new file mode 100644 index 000000000000..2be022ca6a7d --- /dev/null +++ b/Documentation/devicetree/bindings/soc/google/google,gs101-pmu-intr-gen.yaml @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/google/google,gs101-pmu-intr-gen.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Google Power Management Unit (PMU) Interrupt Generation + +description: | + PMU interrupt generator for handshaking between PMU through interrupts. + +maintainers: + - Peter Griffin <peter.griffin@linaro.org> + +properties: + compatible: + items: + - const: google,gs101-pmu-intr-gen + - const: syscon + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pmu_intr_gen: syscon@17470000 { + compatible = "google,gs101-pmu-intr-gen", "syscon"; + reg = <0x17470000 0x10000>; + }; diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,aips-bus.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,aips-bus.yaml index 80d99861fec5..70a4af650110 100644 --- a/Documentation/devicetree/bindings/soc/imx/fsl,aips-bus.yaml +++ b/Documentation/devicetree/bindings/soc/imx/fsl,aips-bus.yaml @@ -22,6 +22,9 @@ select: required: - compatible +allOf: + - $ref: /schemas/simple-bus.yaml# + properties: compatible: items: @@ -35,7 +38,7 @@ required: - compatible - reg -additionalProperties: true +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mt8183-dvfsrc.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mt8183-dvfsrc.yaml index 1ad5b61b249f..4c96d4917967 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mt8183-dvfsrc.yaml +++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mt8183-dvfsrc.yaml @@ -23,6 +23,7 @@ properties: compatible: oneOf: - enum: + - mediatek,mt6893-dvfsrc - mediatek,mt8183-dvfsrc - mediatek,mt8195-dvfsrc - items: diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml index 7b031ef09669..54cd585f19e3 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml @@ -54,6 +54,10 @@ properties: dma-coherent: true + firmware-name: + maxItems: 1 + description: Specify the name of the QUP firmware to load. + required: - compatible - reg @@ -135,6 +139,7 @@ examples: #address-cells = <2>; #size-cells = <2>; ranges; + firmware-name = "qcom/sa8775p/qupv3fw.elf"; i2c0: i2c@a94000 { compatible = "qcom,geni-i2c"; diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml index 2d3fe0b54243..4c9e78f29523 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml @@ -38,6 +38,7 @@ properties: - items: - enum: - qcom,sm8650-pmic-glink + - qcom,sm8750-pmic-glink - qcom,x1e80100-pmic-glink - const: qcom,sm8550-pmic-glink - const: qcom,pmic-glink diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,rpm.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,rpm.yaml index b00be9e01206..3e8d99cb4dc3 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,rpm.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,rpm.yaml @@ -36,6 +36,13 @@ properties: - const: err - const: wakeup + clocks: + maxItems: 1 + + clock-names: + items: + - const: ram + qcom,ipc: $ref: /schemas/types.yaml#/definitions/phandle-array items: @@ -46,6 +53,14 @@ properties: description: Three entries specifying the outgoing ipc bit used for signaling the RPM. + clock-controller: + type: object + additionalProperties: true + properties: + compatible: + contains: + const: qcom,rpmcc + patternProperties: "^regulators(-[01])?$": type: object diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml index af632d0e0355..036562eb5140 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml @@ -44,7 +44,13 @@ description: | properties: compatible: - const: qcom,rpmh-rsc + oneOf: + - items: + - enum: + - qcom,sc7180-rpmh-apps-rsc + - qcom,sdm845-rpmh-apps-rsc + - const: qcom,rpmh-rsc + - const: qcom,rpmh-rsc interrupts: minItems: 1 @@ -124,7 +130,21 @@ required: - qcom,tcs-offset - reg - reg-names - - power-domains + +allOf: + # Some platforms may lack a OSI-mode PSCI implementation, which implies the + # system power domain can't provide feedback about entering power collapse + - if: + not: + properties: + compatible: + contains: + enum: + - qcom,sc7180-rpmh-apps-rsc + - qcom,sdm845-rpmh-apps-rsc + then: + required: + - power-domains additionalProperties: false diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml index ca4bce817273..c2f1f5946cfa 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml @@ -73,9 +73,10 @@ examples: #size-cells = <0>; cpu@0 { - compatible = "qcom,kryo"; + compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "qcom,kpss-acc-v2"; + qcom,acc = <&acc0>; qcom,saw = <&saw0>; reg = <0x0>; operating-points-v2 = <&cpu_opp_table>; diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,wcnss.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,wcnss.yaml index fd6db0ca98eb..4fcae6bedfff 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,wcnss.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,wcnss.yaml @@ -54,7 +54,7 @@ properties: - compatible wifi: - additionalProperties: false + unevaluatedProperties: false type: object properties: compatible: @@ -88,6 +88,9 @@ properties: - qcom,smem-states - qcom,smem-state-names + allOf: + - $ref: /schemas/net/wireless/wireless-controller.yaml# + required: - compatible - qcom,mmio diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml index ebbf0c9109ce..c41dcaea568a 100644 --- a/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml +++ b/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml @@ -22,7 +22,11 @@ description: | properties: compatible: - const: renesas,r9a09g057-sys + items: + - enum: + - renesas,r9a09g047-sys # RZ/G3E + - renesas,r9a09g056-sys # RZ/V2N + - renesas,r9a09g057-sys # RZ/V2H reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml index 225c0f07ae94..5e6e6e6208dc 100644 --- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml +++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml @@ -375,6 +375,13 @@ properties: - renesas,r8a779g3 # ES3.x - const: renesas,r8a779g0 + - description: R-Car V4H (R8A779G3) + items: + - enum: + - retronix,sparrow-hawk # Sparrow Hawk board + - const: renesas,r8a779g3 # ES3.x + - const: renesas,r8a779g0 + - description: R-Car V4M (R8A779H0) items: - enum: @@ -493,6 +500,13 @@ properties: - renesas,r9a07g044l2 # Dual Cortex-A55 RZ/G2L - const: renesas,r9a07g044 + - items: + - enum: + # MYIR Remi Pi SBC (MYB-YG2LX-REMI) + - myir,remi-pi + - const: renesas,r9a07g044l2 + - const: renesas,r9a07g044 + - description: RZ/V2L (R9A07G054) items: - enum: @@ -544,6 +558,21 @@ properties: - renesas,r9a09g047e58 # Quad Cortex-A55 + Cortex-M33 + Ethos-U55 (21mm BGA) - const: renesas,r9a09g047 + - description: RZ/V2N (R9A09G056) + items: + - enum: + - renesas,rzv2n-evk # RZ/V2N EVK (RTK0EF0186C03000BJ) + - enum: + - renesas,r9a09g056n41 # RZ/V2N + - renesas,r9a09g056n42 # RZ/V2N with Mali-G31 support + - renesas,r9a09g056n43 # RZ/V2N with Mali-C55 support + - renesas,r9a09g056n44 # RZ/V2N with Mali-G31 + Mali-C55 support + - renesas,r9a09g056n45 # RZ/V2N with cryptographic extension support + - renesas,r9a09g056n46 # RZ/V2N with Mali-G31 + cryptographic extension support + - renesas,r9a09g056n47 # RZ/V2N with Mali-C55 + cryptographic extension support + - renesas,r9a09g056n48 # RZ/V2N with Mali-G31 + Mali-C55 + cryptographic extension support + - const: renesas,r9a09g056 + - description: RZ/V2H(P) (R9A09G057) items: - enum: @@ -552,8 +581,27 @@ properties: - renesas,r9a09g057h41 # RZ/V2H - renesas,r9a09g057h42 # RZ/V2H with Mali-G31 support - renesas,r9a09g057h44 # RZ/V2HP with Mali-G31 + Mali-C55 support + - renesas,r9a09g057h45 # RZ/V2H with cryptographic extension support + - renesas,r9a09g057h46 # RZ/V2H with Mali-G31 + cryptographic extension support + - renesas,r9a09g057h48 # RZ/V2HP with Mali-G31 + Mali-C55 + cryptographic extension support + - const: renesas,r9a09g057 + + - description: Yuridenki-Shokai RZ/V2H Kakip + items: + - const: yuridenki,kakip + - const: renesas,r9a09g057h48 - const: renesas,r9a09g057 + - description: RZ/T2H (R9A09G077) + items: + - enum: + - renesas,rzt2h-evk # RZ/T2H Evaluation Board + - enum: + - renesas,r9a09g077m04 # RZ/T2H with Single Cortex-A55 + Dual Cortex-R52 - no security + - renesas,r9a09g077m24 # RZ/T2H with Dual Cortex-A55 + Dual Cortex-R52 - no security + - renesas,r9a09g077m44 # RZ/T2H with Quad Cortex-A55 + Dual Cortex-R52 - no security + - const: renesas,r9a09g077 + additionalProperties: true ... diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml index 61f38b68a4a3..ccdcc889ba8e 100644 --- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml +++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml @@ -15,6 +15,15 @@ properties: - items: - enum: - rockchip,rk3288-sgrf + - rockchip,rk3528-ioc-grf + - rockchip,rk3528-vo-grf + - rockchip,rk3528-vpu-grf + - rockchip,rk3562-ioc-grf + - rockchip,rk3562-peri-grf + - rockchip,rk3562-pipephy-grf + - rockchip,rk3562-pmu-grf + - rockchip,rk3562-sys-grf + - rockchip,rk3562-usbphy-grf - rockchip,rk3566-pipe-grf - rockchip,rk3568-pcie3-phy-grf - rockchip,rk3568-pipe-grf @@ -79,6 +88,7 @@ properties: - rockchip,rk3368-pmugrf - rockchip,rk3399-grf - rockchip,rk3399-pmugrf + - rockchip,rk3562-pmu-grf - rockchip,rk3568-grf - rockchip,rk3568-pmugrf - rockchip,rk3576-ioc-grf @@ -198,8 +208,8 @@ allOf: pcie-phy: type: object - description: - Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt + $ref: /schemas/phy/rockchip,rk3399-pcie-phy.yaml# + unevaluatedProperties: false patternProperties: "^phy@[0-9a-f]+$": @@ -323,6 +333,15 @@ examples: #phy-cells = <0>; }; + pcie-phy { + compatible = "rockchip,rk3399-pcie-phy"; + #phy-cells = <1>; + clocks = <&cru SCLK_PCIEPHY_REF>; + clock-names = "refclk"; + resets = <&cru SRST_PCIEPHY>; + reset-names = "phy"; + }; + phy@f780 { compatible = "rockchip,rk3399-emmc-phy"; reg = <0xf780 0x20>; diff --git a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml index 8e6d051d8c97..3109df43d502 100644 --- a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml +++ b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml @@ -52,6 +52,8 @@ properties: - const: syscon - items: - enum: + - samsung,exynos2200-pmu + - samsung,exynos7870-pmu - samsung,exynos7885-pmu - samsung,exynos8895-pmu - samsung,exynos9810-pmu @@ -127,6 +129,11 @@ properties: description: Node for reboot method + google,pmu-intr-gen-syscon: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to PMU interrupt generation interface. + required: - compatible - reg @@ -187,6 +194,16 @@ allOf: properties: dp-phy: false + - if: + properties: + compatible: + contains: + enum: + - google,gs101-pmu + then: + required: + - google,pmu-intr-gen-syscon + examples: - | #include <dt-bindings/clock/exynos5250.h> diff --git a/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml b/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml index 5b046932fbc3..cb22637091e8 100644 --- a/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml +++ b/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml @@ -11,11 +11,21 @@ maintainers: - Krzysztof Kozlowski <krzk@kernel.org> description: | - USI IP-core provides selectable serial protocol (UART, SPI or High-Speed I2C). - USI shares almost all internal circuits within each protocol, so only one - protocol can be chosen at a time. USI is modeled as a node with zero or more - child nodes, each representing a serial sub-node device. The mode setting - selects which particular function will be used. + The USI IP-core provides configurable support for serial protocols, enabling + different serial communication modes depending on the version. + + In USIv1, configurations are available to enable either one or two protocols + simultaneously in select combinations - High-Speed I2C0, High-Speed + I2C1, SPI, UART, High-Speed I2C0 and I2C1 or both High-Speed + I2C1 and UART. + + In USIv2, only one protocol can be active at a time, either UART, SPI, or + High-Speed I2C. + + The USI core shares internal circuits across protocols, meaning only the + selected configuration is active at any given time. USI is modeled as a node + with zero or more child nodes, each representing a serial sub-node device. The + mode setting selects which particular function will be used. properties: $nodename: @@ -31,6 +41,7 @@ properties: - const: samsung,exynos850-usi - enum: - samsung,exynos850-usi + - samsung,exynos8895-usi reg: maxItems: 1 @@ -64,7 +75,7 @@ properties: samsung,mode: $ref: /schemas/types.yaml#/definitions/uint32 - enum: [0, 1, 2, 3] + enum: [0, 1, 2, 3, 4, 5, 6] description: Selects USI function (which serial protocol to use). Refer to <include/dt-bindings/soc/samsung,exynos-usi.h> for valid USI mode values. @@ -101,37 +112,59 @@ required: - samsung,sysreg - samsung,mode -if: - properties: - compatible: - contains: - enum: - - samsung,exynos850-usi +allOf: + - if: + properties: + compatible: + contains: + enum: + - samsung,exynos850-usi + + then: + properties: + reg: + maxItems: 1 + + clocks: + items: + - description: Bus (APB) clock + - description: Operating clock for UART/SPI/I2C protocol -then: - properties: - reg: - maxItems: 1 + clock-names: + maxItems: 2 - clocks: - items: - - description: Bus (APB) clock - - description: Operating clock for UART/SPI/I2C protocol + samsung,mode: + enum: [0, 1, 2, 3] - clock-names: - maxItems: 2 + required: + - reg + - clocks + - clock-names - required: - - reg - - clocks - - clock-names + - if: + properties: + compatible: + contains: + enum: + - samsung,exynos8895-usi -else: - properties: - reg: false - clocks: false - clock-names: false - samsung,clkreq-on: false + then: + properties: + reg: false + + clocks: + items: + - description: Bus (APB) clock + - description: Operating clock for UART/SPI protocol + + clock-names: + maxItems: 2 + + samsung,clkreq-on: false + + required: + - clocks + - clock-names additionalProperties: false @@ -144,7 +177,7 @@ examples: compatible = "samsung,exynos850-usi"; reg = <0x138200c0 0x20>; samsung,sysreg = <&sysreg_peri 0x1010>; - samsung,mode = <USI_V2_UART>; + samsung,mode = <USI_MODE_UART>; samsung,clkreq-on; /* needed for UART mode */ #address-cells = <1>; #size-cells = <1>; @@ -158,7 +191,6 @@ examples: interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cmu_peri 32>, <&cmu_peri 31>; clock-names = "uart", "clk_uart_baud0"; - status = "disabled"; }; hsi2c_0: i2c@13820000 { diff --git a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml index a75aef240629..d27ed6c9d61e 100644 --- a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml +++ b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml @@ -18,6 +18,11 @@ properties: - google,gs101-hsi2-sysreg - google,gs101-peric0-sysreg - google,gs101-peric1-sysreg + - samsung,exynos2200-cmgp-sysreg + - samsung,exynos2200-peric0-sysreg + - samsung,exynos2200-peric1-sysreg + - samsung,exynos2200-peric2-sysreg + - samsung,exynos2200-ufs-sysreg - samsung,exynos3-sysreg - samsung,exynos4-sysreg - samsung,exynos5-sysreg diff --git a/Documentation/devicetree/bindings/soc/sophgo/sophgo,cv1800b-rtc.yaml b/Documentation/devicetree/bindings/soc/sophgo/sophgo,cv1800b-rtc.yaml new file mode 100644 index 000000000000..5cf186c396c9 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/sophgo/sophgo,cv1800b-rtc.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sophgo/sophgo,cv1800b-rtc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Real Time Clock of the Sophgo CV1800 SoC + +description: + The RTC (Real Time Clock) is an independently powered module in the chip. It + contains a 32KHz oscillator and a Power-On-Reset (POR) sub-module, which can + be used for time display and scheduled alarm produce. In addition, the + hardware state machine provides triggering and timing control for chip + power-on, power-off and reset. + + Furthermore, the 8051 subsystem is located within RTCSYS and is independently + powered. System software can use the 8051 to manage wake conditions and wake + the system while the system is asleep, and communicate with external devices + through peripheral controllers. + + Technical Reference Manual available at + https://github.com/sophgo/sophgo-doc/tree/main/SG200X/TRM + +maintainers: + - sophgo@lists.linux.dev + +allOf: + - $ref: /schemas/rtc/rtc.yaml# + +properties: + compatible: + items: + - const: sophgo,cv1800b-rtc + - const: syscon + + reg: + maxItems: 1 + + interrupts: + items: + - description: RTC Alarm + - description: RTC Longpress + - description: VBAT DET + + interrupt-names: + items: + - const: alarm + - const: longpress + - const: vbat + + clocks: + items: + - description: RTC clock source + - description: DW8051 MCU clock source + + clock-names: + items: + - const: rtc + - const: mcu + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/sophgo,cv1800.h> + #include <dt-bindings/interrupt-controller/irq.h> + + rtc@5025000 { + compatible = "sophgo,cv1800b-rtc", "syscon"; + reg = <0x5025000 0x2000>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH>, + <18 IRQ_TYPE_LEVEL_HIGH>, + <19 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "alarm", "longpress", "vbat"; + clocks = <&clk CLK_RTC_25M>, + <&clk CLK_SRC_RTC_SYS_0>; + clock-names = "rtc", "mcu"; + }; diff --git a/Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2044-top-syscon.yaml b/Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2044-top-syscon.yaml new file mode 100644 index 000000000000..a82cc3cae576 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2044-top-syscon.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/sophgo/sophgo,sg2044-top-syscon.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo SG2044 SoC TOP system controller + +maintainers: + - Inochi Amaoto <inochiama@gmail.com> + +description: + The Sophgo SG2044 TOP system controller is a hardware block grouping + multiple small functions, such as clocks and some other internal + function. + +properties: + compatible: + items: + - const: sophgo,sg2044-top-syscon + - const: syscon + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + '#clock-cells': + const: 1 + description: + See <dt-bindings/clock/sophgo,sg2044-pll.h> for valid clock. + +required: + - compatible + - reg + - clocks + - '#clock-cells' + +additionalProperties: false + +examples: + - | + syscon@50000000 { + compatible = "sophgo,sg2044-top-syscon", "syscon"; + reg = <0x50000000 0x1000>; + #clock-cells = <1>; + clocks = <&osc>; + }; diff --git a/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml new file mode 100644 index 000000000000..30aaf49da03d --- /dev/null +++ b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/spacemit/spacemit,k1-syscon.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SpacemiT K1 SoC System Controller + +maintainers: + - Haylen Chu <heylenay@4d2.org> + +description: + System controllers found on SpacemiT K1 SoC, which are capable of + clock, reset and power-management functions. + +properties: + compatible: + enum: + - spacemit,k1-syscon-apbc + - spacemit,k1-syscon-apmu + - spacemit,k1-syscon-mpmu + + reg: + maxItems: 1 + + clocks: + maxItems: 4 + + clock-names: + items: + - const: osc + - const: vctcxo_1m + - const: vctcxo_3m + - const: vctcxo_24m + + "#clock-cells": + const: 1 + description: + See <dt-bindings/clock/spacemit,k1-syscon.h> for valid indices. + + "#power-domain-cells": + const: 1 + + "#reset-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - "#clock-cells" + - "#reset-cells" + +allOf: + - if: + properties: + compatible: + contains: + const: spacemit,k1-syscon-apbc + then: + properties: + "#power-domain-cells": false + else: + required: + - "#power-domain-cells" + +additionalProperties: false + +examples: + - | + system-controller@d4050000 { + compatible = "spacemit,k1-syscon-mpmu"; + reg = <0xd4050000 0x209c>; + clocks = <&osc>, <&vctcxo_1m>, <&vctcxo_3m>, <&vctcxo_24m>; + clock-names = "osc", "vctcxo_1m", "vctcxo_3m", "vctcxo_24m"; + #clock-cells = <1>; + #power-domain-cells = <1>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-controller.yaml b/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-controller.yaml index 378e9cc5fac2..f3bd0be3b279 100644 --- a/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-controller.yaml +++ b/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-controller.yaml @@ -26,6 +26,7 @@ properties: compatible: items: - enum: + - ti,am654-system-controller - ti,j7200-system-controller - ti,j721e-system-controller - ti,j721s2-system-controller @@ -68,6 +69,23 @@ patternProperties: description: The node corresponding to SoC chip identification. + "^pcie-ctrl@[0-9a-f]+$": + type: object + description: + The node corresponding to PCIe control register. + + "^clock@[0-9a-f]+$": + type: object + $ref: /schemas/soc/ti/ti,am654-serdes-ctrl.yaml# + description: + This is the Serdes Control region. + + "^dss-oldi-io-ctrl@[0-9a-f]+$": + type: object + $ref: /schemas/mfd/syscon.yaml# + description: + This is the DSS OLDI CTRL region. + required: - compatible - reg @@ -110,5 +128,10 @@ examples: compatible = "ti,am654-chipid"; reg = <0x14 0x4>; }; + + pcie0_ctrl: pcie-ctrl@4070 { + compatible = "ti,j784s4-pcie-ctrl", "syscon"; + reg = <0x4070 0x4>; + }; }; ... diff --git a/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml b/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml index 131aba5ed9f4..fb5c39c79d28 100644 --- a/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml +++ b/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml @@ -9,8 +9,8 @@ title: Xilinx Zynq Platforms maintainers: - Michal Simek <michal.simek@amd.com> -description: | - Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC +description: + AMD/Xilinx boards with ARM 32/64bits cores properties: $nodename: @@ -187,6 +187,13 @@ properties: - const: qemu,mbv - const: amd,mbv + - description: Xilinx Versal NET VN-X revA platform + items: + enum: + - xlnx,versal-net-vnx-revA + - xlnx,versal-net-vnx + - xlnx,versal-net + additionalProperties: true ... diff --git a/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-codec.yaml b/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-codec.yaml index ccae64ce3071..b4eca702febc 100644 --- a/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-codec.yaml +++ b/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-codec.yaml @@ -102,6 +102,10 @@ properties: maxItems: 1 description: GPIO to enable the external amplifier + hp-det-gpios: + maxItems: 1 + description: GPIO for headphone/line-out detection + required: - "#sound-dai-cells" - compatible @@ -251,8 +255,10 @@ allOf: allwinner,audio-routing: items: enum: + - Headphone - LINEOUT - Line Out + - Speaker dmas: items: diff --git a/Documentation/devicetree/bindings/sound/atmel,at91-ssc.yaml b/Documentation/devicetree/bindings/sound/atmel,at91-ssc.yaml new file mode 100644 index 000000000000..a05e61431824 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/atmel,at91-ssc.yaml @@ -0,0 +1,104 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/atmel,at91-ssc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Atmel Serial Synchronous Serial (SSC) + +maintainers: + - Andrei Simion <andrei.simion@microchip.com> + +description: + The Atmel Synchronous Serial Controller (SSC) provides a versatile + synchronous communication link for audio and telecom applications, + supporting protocols like I2S, Short Frame Sync, and Long Frame Sync. + +properties: + compatible: + enum: + - atmel,at91rm9200-ssc + - atmel,at91sam9g45-ssc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: pclk + + dmas: + items: + - description: TX DMA Channel + - description: RX DMA Channel + + dma-names: + items: + - const: tx + - const: rx + + atmel,clk-from-rk-pin: + description: + Specify the clock source for the SSC (Synchronous Serial Controller) + when operating in slave mode. By default, the clock is sourced from + the TK pin. + type: boolean + + "#sound-dai-cells": + const: 0 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +allOf: + - $ref: dai-common.yaml# + - if: + properties: + compatible: + contains: + enum: + - atmel,at91sam9g45-ssc + then: + required: + - dmas + - dma-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/at91.h> + #include <dt-bindings/dma/at91.h> + #include <dt-bindings/interrupt-controller/irq.h> + + ssc@100000 { + compatible = "atmel,at91sam9g45-ssc"; + reg = <0x100000 0x4000>; + interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>; + dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(38))>, + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(39))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 28>; + clock-names = "pclk"; + #sound-dai-cells = <0>; + }; + + ssc@c00000 { + compatible = "atmel,at91rm9200-ssc"; + reg = <0xc00000 0x4000>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; + clock-names = "pclk"; + }; diff --git a/Documentation/devicetree/bindings/sound/atmel,at91sam9g20ek-wm8731.yaml b/Documentation/devicetree/bindings/sound/atmel,at91sam9g20ek-wm8731.yaml new file mode 100644 index 000000000000..627da2d890b2 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/atmel,at91sam9g20ek-wm8731.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/atmel,at91sam9g20ek-wm8731.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Atmel at91sam9g20ek wm8731 audio complex + +maintainers: + - Balakrishnan Sambath <balakrishnan.s@microchip.com> + +description: + The audio complex configuration for Atmel at91sam9g20ek with WM8731 audio codec. + +properties: + compatible: + const: atmel,at91sam9g20ek-wm8731-audio + + atmel,model: + $ref: /schemas/types.yaml#/definitions/string + description: The user-visible name of this sound complex. + + atmel,audio-routing: + $ref: /schemas/types.yaml#/definitions/non-unique-string-array + description: A list of the connections between audio components. + minItems: 2 + maxItems: 4 + items: + enum: + # Board Connectors + - Ext Spk + - Int Mic + + # CODEC Pins + - LOUT + - ROUT + - LHPOUT + - RHPOUT + - LLINEIN + - RLINEIN + - MICIN + + atmel,ssc-controller: + $ref: /schemas/types.yaml#/definitions/phandle + description: The phandle of the SSC controller. + + atmel,audio-codec: + $ref: /schemas/types.yaml#/definitions/phandle + description: The phandle of WM8731 audio codec. + +required: + - compatible + - atmel,model + - atmel,audio-routing + - atmel,ssc-controller + - atmel,audio-codec + +additionalProperties: false + +examples: + - | + sound { + compatible = "atmel,at91sam9g20ek-wm8731-audio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pck0_as_mck>; + atmel,model = "wm8731 @ AT91SAMG20EK"; + atmel,audio-routing = + "Ext Spk", "LHPOUT", + "Int Mic", "MICIN"; + atmel,ssc-controller = <&ssc0>; + atmel,audio-codec = <&wm8731>; + }; diff --git a/Documentation/devicetree/bindings/sound/atmel-at91sam9g20ek-wm8731-audio.txt b/Documentation/devicetree/bindings/sound/atmel-at91sam9g20ek-wm8731-audio.txt deleted file mode 100644 index 9c5a9947b64d..000000000000 --- a/Documentation/devicetree/bindings/sound/atmel-at91sam9g20ek-wm8731-audio.txt +++ /dev/null @@ -1,26 +0,0 @@ -* Atmel at91sam9g20ek wm8731 audio complex - -Required properties: - - compatible: "atmel,at91sam9g20ek-wm8731-audio" - - atmel,model: The user-visible name of this sound complex. - - atmel,audio-routing: A list of the connections between audio components. - - atmel,ssc-controller: The phandle of the SSC controller - - atmel,audio-codec: The phandle of the WM8731 audio codec -Optional properties: - - pinctrl-names, pinctrl-0: Please refer to pinctrl-bindings.txt - -Example: -sound { - compatible = "atmel,at91sam9g20ek-wm8731-audio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pck0_as_mck>; - - atmel,model = "wm8731 @ AT91SAMG20EK"; - - atmel,audio-routing = - "Ext Spk", "LHPOUT", - "Int MIC", "MICIN"; - - atmel,ssc-controller = <&ssc0>; - atmel,audio-codec = <&wm8731>; -}; diff --git a/Documentation/devicetree/bindings/sound/audio-graph-card2.yaml b/Documentation/devicetree/bindings/sound/audio-graph-card2.yaml index f943f90d8b15..40eb1d7d6cf1 100644 --- a/Documentation/devicetree/bindings/sound/audio-graph-card2.yaml +++ b/Documentation/devicetree/bindings/sound/audio-graph-card2.yaml @@ -18,11 +18,7 @@ properties: label: maxItems: 1 routing: - description: | - A list of the connections between audio components. - Each entry is a pair of strings, the first being the - connection's sink, the second being the connection's source. - $ref: /schemas/types.yaml#/definitions/non-unique-string-array + $ref: audio-graph.yaml#/properties/routing aux-devs: description: | List of phandles pointing to auxiliary devices, such @@ -37,6 +33,12 @@ properties: codec2codec: type: object description: Codec to Codec node + hp-det-gpios: + $ref: audio-graph.yaml#/properties/hp-det-gpios + mic-det-gpios: + $ref: audio-graph.yaml#/properties/mic-det-gpios + widgets: + $ref: audio-graph.yaml#/properties/widgets required: - compatible diff --git a/Documentation/devicetree/bindings/sound/awinic,aw88395.yaml b/Documentation/devicetree/bindings/sound/awinic,aw88395.yaml index 6676406bf2de..bb92d6ca3144 100644 --- a/Documentation/devicetree/bindings/sound/awinic,aw88395.yaml +++ b/Documentation/devicetree/bindings/sound/awinic,aw88395.yaml @@ -19,6 +19,7 @@ properties: enum: - awinic,aw88081 - awinic,aw88083 + - awinic,aw88166 - awinic,aw88261 - awinic,aw88395 - awinic,aw88399 diff --git a/Documentation/devicetree/bindings/sound/cirrus,cs48l32.yaml b/Documentation/devicetree/bindings/sound/cirrus,cs48l32.yaml new file mode 100644 index 000000000000..bf087b57aaf6 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/cirrus,cs48l32.yaml @@ -0,0 +1,195 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/cirrus,cs48l32.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cirrus Logic CS48L32 audio DSP. + +maintainers: + - patches@opensource.cirrus.com + +description: | + The CS48L32 is a high-performance low-power audio DSP for smartphones and + other portable audio devices. The CS48L32 combines a programmable Halo Core + DSP with a variety of power-efficient fixed-function audio processors. + + See also the binding headers: + + include/dt-bindings/sound/cs48l32.yaml + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + - $ref: dai-common.yaml# + +properties: + compatible: + enum: + - cirrus,cs48l32 + + reg: + description: SPI chip-select number. + maxItems: 1 + + spi-max-frequency: + maximum: 25000000 + + vdd-a-supply: + description: Regulator supplying VDD_A + + vdd-d-supply: + description: Regulator supplying VDD_D + + vdd-io-supply: + description: Regulator supplying VDD_IO + + vdd-cp-supply: + description: Regulator supplying VDD_CP + + reset-gpios: + description: + One entry specifying the GPIO controlling /RESET. Although optional, + it is strongly recommended to use a hardware reset. + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: The clock supplied on MCLK1 + + clock-names: + const: mclk1 + + '#sound-dai-cells': + const: 1 + + cirrus,in-type: + description: | + A list of input type settings for each ADC input. + Inputs are one of these types: + CS48L32_IN_TYPE_DIFF : analog differential (default) + CS48L32_IN_TYPE_SE : analog single-ended + + The type of the left (L) and right (R) channel on each input is + independently configured, as are the two groups of pins muxable to + the input (referred to in the datasheet as "1" and "2"). + + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - description: + IN1L_1 analog input type. One of the CS48L32_IN_TYPE_xxx. + minimum: 0 + maximum: 1 + default: 0 + - description: + IN1R_1 analog input type. One of the CS48L32_IN_TYPE_xxx. + minimum: 0 + maximum: 1 + default: 0 + - description: + IN1L_2 analog input type. One of the CS48L32_IN_TYPE_xxx. + minimum: 0 + maximum: 1 + default: 0 + - description: + IN1R_2 analog input type. One of the CS48L32_IN_TYPE_xxx. + minimum: 0 + maximum: 1 + default: 0 + + cirrus,pdm-sup: + description: | + Indicate which MICBIAS output supplies bias to the microphone. + There is one cell per input (IN1, IN2, ...). + + One of the CS48L32_MICBIAS_xxx values. + CS48L32_PDM_SUP_VOUT_MIC : mic biased from VOUT_MIC + CS48L32_PDM_SUP_MICBIAS1 : mic biased from MICBIAS1 + + Also see the INn_PDM_SUP field in the datasheet. + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - description: IN1 PDM supply source + minimum: 0 + maximum: 1 + default: 0 + - description: IN2 PDM supply source + minimum: 0 + maximum: 1 + default: 0 + +required: + - compatible + - reg + - vdd-a-supply + - vdd-d-supply + - vdd-io-supply + - vdd-cp-supply + +additionalProperties: false + +examples: + - | + #include <dt-bindings/sound/cs48l32.h> + + spi@e0006000 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0xe0006000 0x1000>; + + codec@1 { + compatible = "cirrus,cs48l32"; + + reg = <0x1>; + spi-max-frequency = <2500000>; + + vdd-a-supply = <®ulator_1v8>; + vdd-d-supply = <®ulator_1v2>; + vdd-io-supply = <®ulator_1v8>; + vdd-cp-supply = <®ulator_1v8>; + + reset-gpios = <&gpio 0 0>; + + clocks = <&clks 0>; + clock-names = "mclk1"; + + interrupt-parent = <&gpio0>; + interrupts = <56 8>; + + #sound-dai-cells = <1>; + + cirrus,in-type = < + CS48L32_IN_TYPE_DIFF CS48L32_IN_TYPE_DIFF + CS48L32_IN_TYPE_SE CS48L32_IN_TYPE_SE + >; + + cirrus,pdm-sup = < + CS48L32_PDM_SUP_MICBIAS1 CS48L32_PDM_SUP_MICBIAS1 + >; + }; + }; + +# +# Minimal config +# + - | + #include <dt-bindings/sound/cs48l32.h> + + spi@e0006000 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0xe0006000 0x1000>; + + codec@1 { + compatible = "cirrus,cs48l32"; + + reg = <0x1>; + + vdd-a-supply = <®ulator_1v8>; + vdd-d-supply = <®ulator_1v2>; + vdd-io-supply = <®ulator_1v8>; + vdd-cp-supply = <®ulator_1v8>; + }; + }; diff --git a/Documentation/devicetree/bindings/sound/dmic-codec.yaml b/Documentation/devicetree/bindings/sound/dmic-codec.yaml index 59ef0cf6b6e5..cc3c84dd4c26 100644 --- a/Documentation/devicetree/bindings/sound/dmic-codec.yaml +++ b/Documentation/devicetree/bindings/sound/dmic-codec.yaml @@ -19,6 +19,9 @@ properties: '#sound-dai-cells': const: 0 + vref-supply: + description: Phandle to the digital microphone reference supply + dmicen-gpios: description: GPIO specifier for DMIC to control start and stop maxItems: 1 diff --git a/Documentation/devicetree/bindings/sound/everest,es8328.yaml b/Documentation/devicetree/bindings/sound/everest,es8328.yaml index ed18e40dcaac..ddddd7b143ab 100644 --- a/Documentation/devicetree/bindings/sound/everest,es8328.yaml +++ b/Documentation/devicetree/bindings/sound/everest,es8328.yaml @@ -24,9 +24,13 @@ maintainers: properties: compatible: - enum: - - everest,es8328 - - everest,es8388 + oneOf: + - enum: + - everest,es8328 + - items: + - enum: + - everest,es8388 + - const: everest,es8328 reg: maxItems: 1 @@ -56,6 +60,7 @@ properties: required: - compatible + - reg - clocks - DVDD-supply - AVDD-supply diff --git a/Documentation/devicetree/bindings/sound/everest,es8375.yaml b/Documentation/devicetree/bindings/sound/everest,es8375.yaml new file mode 100644 index 000000000000..4a3d671c66b1 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/everest,es8375.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/everest,es8375.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Everest ES8375 audio CODEC + +maintainers: + - Michael Zhang <zhangyi@everest-semi.com> + +allOf: + - $ref: dai-common.yaml# + +properties: + compatible: + const: everest,es8375 + + reg: + maxItems: 1 + + clocks: + items: + - description: clock for master clock (MCLK) + + clock-names: + items: + - const: mclk + + vdda-supply: + description: + Analogue power supply. + + vddd-supply: + description: + Interface power supply. + + everest,mclk-src: + $ref: /schemas/types.yaml#/definitions/uint8 + description: | + Represents the MCLK/SCLK pair pins used as the internal clock. + 0 represents selecting MCLK. + 1 represents selecting SCLK. + enum: [0, 1] + default: 0 + + "#sound-dai-cells": + const: 0 + +required: + - compatible + - reg + - "#sound-dai-cells" + - vdda-supply + - vddd-supply + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + es8375: codec@18 { + compatible = "everest,es8375"; + reg = <0x18>; + vdda-supply = <&vdd3v3>; + vddd-supply = <&vdd3v3>; + #sound-dai-cells = <0>; + }; + }; diff --git a/Documentation/devicetree/bindings/sound/everest,es8389.yaml b/Documentation/devicetree/bindings/sound/everest,es8389.yaml new file mode 100644 index 000000000000..a673df485ab3 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/everest,es8389.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/everest,es8389.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Everest ES8389 audio CODEC + +maintainers: + - Michael Zhang <zhangyi@everest-semi.com> + +allOf: + - $ref: dai-common.yaml# + +properties: + compatible: + const: everest,es8389 + + reg: + maxItems: 1 + + clocks: + items: + - description: clock for master clock (MCLK) + + clock-names: + items: + - const: mclk + + "#sound-dai-cells": + const: 0 + +required: + - compatible + - reg + - "#sound-dai-cells" + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + es8389: codec@10 { + compatible = "everest,es8389"; + reg = <0x10>; + #sound-dai-cells = <0>; + }; + }; diff --git a/Documentation/devicetree/bindings/sound/fsl,audmix.yaml b/Documentation/devicetree/bindings/sound/fsl,audmix.yaml index 9413b901cf77..3ad197b3c82c 100644 --- a/Documentation/devicetree/bindings/sound/fsl,audmix.yaml +++ b/Documentation/devicetree/bindings/sound/fsl,audmix.yaml @@ -61,13 +61,26 @@ properties: - description: serial audio input 2 maxItems: 1 + ports: + $ref: /schemas/graph.yaml#/properties/ports + patternProperties: + '^port@[0-1]': + $ref: audio-graph-port.yaml# + unevaluatedProperties: false + description: Input port from SAI TX + + properties: + port@2: + $ref: audio-graph-port.yaml# + unevaluatedProperties: false + description: Output port to SAI RX + required: - compatible - reg - clocks - clock-names - power-domains - - dais unevaluatedProperties: false @@ -80,4 +93,50 @@ examples: clock-names = "ipg"; power-domains = <&pd_audmix>; dais = <&sai4>, <&sai5>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + playback-only; + + amix_endpoint0: endpoint { + dai-tdm-slot-num = <8>; + dai-tdm-slot-width = <32>; + dai-tdm-slot-width-map = <32 8 32>; + dai-format = "dsp_a"; + remote-endpoint = <&be00_ep>; + }; + }; + + port@1 { + reg = <1>; + playback-only; + + amix_endpoint1: endpoint { + dai-tdm-slot-num = <8>; + dai-tdm-slot-width = <32>; + dai-tdm-slot-width-map = <32 8 32>; + dai-format = "dsp_a"; + remote-endpoint = <&be01_ep>; + }; + }; + + port@2 { + reg = <2>; + capture-only; + + amix_endpoint2: endpoint { + dai-tdm-slot-num = <8>; + dai-tdm-slot-width = <32>; + dai-tdm-slot-width-map = <32 8 32>; + dai-format = "dsp_a"; + bitclock-master; + frame-master; + remote-endpoint = <&be02_ep>; + }; + }; + }; }; diff --git a/Documentation/devicetree/bindings/sound/fsl,easrc.yaml b/Documentation/devicetree/bindings/sound/fsl,easrc.yaml index c454110f4281..8f1108e7e14e 100644 --- a/Documentation/devicetree/bindings/sound/fsl,easrc.yaml +++ b/Documentation/devicetree/bindings/sound/fsl,easrc.yaml @@ -80,7 +80,10 @@ required: - fsl,asrc-rate - fsl,asrc-format -additionalProperties: false +allOf: + - $ref: dai-common.yaml# + +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/sound/fsl,imx-asrc.yaml b/Documentation/devicetree/bindings/sound/fsl,imx-asrc.yaml index 76aa1f248488..85799f83e65f 100644 --- a/Documentation/devicetree/bindings/sound/fsl,imx-asrc.yaml +++ b/Documentation/devicetree/bindings/sound/fsl,imx-asrc.yaml @@ -77,6 +77,10 @@ properties: power-domains: maxItems: 1 + port: + $ref: audio-graph-port.yaml# + unevaluatedProperties: false + fsl,asrc-rate: $ref: /schemas/types.yaml#/definitions/uint32 description: The mutual sample rate used by DPCM Back Ends @@ -120,6 +124,7 @@ required: - fsl,asrc-width allOf: + - $ref: dai-common.yaml# - if: properties: compatible: @@ -145,7 +150,7 @@ allOf: required: - power-domains -additionalProperties: false +unevaluatedProperties: false examples: - | @@ -173,4 +178,12 @@ examples: "txa", "txb", "txc"; fsl,asrc-rate = <48000>; fsl,asrc-width = <16>; + + port { + playback-only; + + asrc_endpoint: endpoint { + remote-endpoint = <&fe00_ep>; + }; + }; }; diff --git a/Documentation/devicetree/bindings/sound/fsl,imx95-cm7-sof.yaml b/Documentation/devicetree/bindings/sound/fsl,imx95-cm7-sof.yaml new file mode 100644 index 000000000000..f00ae3219e15 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/fsl,imx95-cm7-sof.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/fsl,imx95-cm7-sof.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP imx95 CM7 core + +maintainers: + - Daniel Baluta <daniel.baluta@nxp.com> + +description: NXP imx95 CM7 core used for audio processing + +properties: + compatible: + const: fsl,imx95-cm7-sof + + reg: + maxItems: 1 + + reg-names: + const: sram + + memory-region: + maxItems: 1 + + memory-region-names: + const: dma + + port: + description: SAI3 port + $ref: audio-graph-port.yaml# + unevaluatedProperties: false + +required: + - compatible + - reg + - reg-names + - memory-region + - memory-region-names + - port + +allOf: + - $ref: fsl,sof-cpu.yaml# + +unevaluatedProperties: false + +examples: + - | + cm7-cpu@80000000 { + compatible = "fsl,imx95-cm7-sof"; + reg = <0x80000000 0x6100000>; + reg-names = "sram"; + mboxes = <&mu7 2 0>, <&mu7 2 1>, <&mu7 3 0>, <&mu7 3 1>; + mbox-names = "txdb0", "txdb1", "rxdb0", "rxdb1"; + memory-region = <&adma_res>; + memory-region-names = "dma"; + port { + /* SAI3-WM8962 link */ + endpoint { + remote-endpoint = <&wm8962_ep>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/sound/fsl,mqs.yaml b/Documentation/devicetree/bindings/sound/fsl,mqs.yaml index 8c22e8348b14..1415247c92c8 100644 --- a/Documentation/devicetree/bindings/sound/fsl,mqs.yaml +++ b/Documentation/devicetree/bindings/sound/fsl,mqs.yaml @@ -28,6 +28,9 @@ properties: - fsl,imx95-aonmix-mqs - fsl,imx95-netcmix-mqs + "#sound-dai-cells": + const: 0 + clocks: minItems: 1 maxItems: 2 @@ -49,12 +52,17 @@ properties: resets: maxItems: 1 + port: + $ref: audio-graph-port.yaml# + unevaluatedProperties: false + required: - compatible - clocks - clock-names allOf: + - $ref: dai-common.yaml# - if: properties: compatible: @@ -86,7 +94,7 @@ allOf: required: - gpr -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/sound/fsl,sai.yaml b/Documentation/devicetree/bindings/sound/fsl,sai.yaml index a5d9c246cc47..0d733e5b08a4 100644 --- a/Documentation/devicetree/bindings/sound/fsl,sai.yaml +++ b/Documentation/devicetree/bindings/sound/fsl,sai.yaml @@ -41,6 +41,10 @@ properties: - fsl,imx93-sai - fsl,imx95-sai - fsl,vf610-sai + - items: + - enum: + - fsl,imx94-sai + - const: fsl,imx95-sai reg: maxItems: 1 @@ -93,6 +97,24 @@ properties: items: - description: receive and transmit interrupt + ports: + $ref: /schemas/graph.yaml#/properties/ports + properties: + port@0: + $ref: audio-graph-port.yaml# + unevaluatedProperties: false + description: port for TX and RX + + port@1: + $ref: audio-graph-port.yaml# + unevaluatedProperties: false + description: port for TX only + + port@2: + $ref: audio-graph-port.yaml# + unevaluatedProperties: false + description: port for RX only + big-endian: description: | required if all the SAI registers are big-endian rather than little-endian. @@ -204,4 +226,37 @@ examples: dma-names = "rx", "tx"; fsl,dataline = <1 0xff 0xff 2 0xff 0x11>; #sound-dai-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + playback-only; + + sai1_endpoint0: endpoint { + dai-tdm-slot-num = <8>; + dai-tdm-slot-width = <32>; + dai-tdm-slot-width-map = <32 8 32>; + dai-format = "dsp_a"; + bitclock-master; + frame-master; + remote-endpoint = <&mcodec01_ep>; + }; + }; + + port@2 { + reg = <2>; + capture-only; + + sai1_endpoint1: endpoint { + dai-tdm-slot-num = <8>; + dai-tdm-slot-width = <32>; + dai-tdm-slot-width-map = <32 8 32>; + dai-format = "dsp_a"; + remote-endpoint = <&fe02_ep>; + }; + }; + }; }; diff --git a/Documentation/devicetree/bindings/sound/fsl,sof-cpu.yaml b/Documentation/devicetree/bindings/sound/fsl,sof-cpu.yaml new file mode 100644 index 000000000000..31863932dbc3 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/fsl,sof-cpu.yaml @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/fsl,sof-cpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP audio processor common properties + +maintainers: + - Daniel Baluta <daniel.baluta@nxp.com> + +properties: + mboxes: + maxItems: 4 + + mbox-names: + items: + - const: txdb0 + - const: txdb1 + - const: rxdb0 + - const: rxdb1 + +required: + - mboxes + - mbox-names + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/sound/ics43432.txt b/Documentation/devicetree/bindings/sound/ics43432.txt deleted file mode 100644 index e6f05f2f6c4e..000000000000 --- a/Documentation/devicetree/bindings/sound/ics43432.txt +++ /dev/null @@ -1,19 +0,0 @@ -Invensense ICS-43432-compatible MEMS microphone with I2S output. - -There are no software configuration options for this device, indeed, the only -host connection is the I2S interface. Apart from requirements on clock -frequency (460 kHz to 3.379 MHz according to the data sheet) there must be -64 clock cycles in each stereo output frame; 24 of the 32 available bits -contain audio data. A hardware pin determines if the device outputs data -on the left or right channel of the I2S frame. - -Required properties: - - compatible: should be one of the following. - "invensense,ics43432": For the Invensense ICS43432 - "cui,cmm-4030d-261": For the CUI CMM-4030D-261-I2S-TR - -Example: - - ics43432: ics43432 { - compatible = "invensense,ics43432"; - }; diff --git a/Documentation/devicetree/bindings/sound/imx-audio-card.yaml b/Documentation/devicetree/bindings/sound/imx-audio-card.yaml index f7ad5ea2491e..3c75c8c78987 100644 --- a/Documentation/devicetree/bindings/sound/imx-audio-card.yaml +++ b/Documentation/devicetree/bindings/sound/imx-audio-card.yaml @@ -46,6 +46,14 @@ patternProperties: description: see tdm-slot.txt. $ref: /schemas/types.yaml#/definitions/uint32 + playback-only: + description: link is used only for playback + $ref: /schemas/types.yaml#/definitions/flag + + capture-only: + description: link is used only for capture + $ref: /schemas/types.yaml#/definitions/flag + cpu: description: Holds subnode which indicates cpu dai. type: object @@ -71,6 +79,12 @@ patternProperties: - link-name - cpu + allOf: + - not: + required: + - playback-only + - capture-only + additionalProperties: false required: diff --git a/Documentation/devicetree/bindings/sound/invensense,ics43432.yaml b/Documentation/devicetree/bindings/sound/invensense,ics43432.yaml new file mode 100644 index 000000000000..7bd984817aa9 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/invensense,ics43432.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/invensense,ics43432.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Invensense ICS-43432-compatible MEMS Microphone with I2S Output + +maintainers: + - Oleksij Rempel <o.rempel@pengutronix.de> + +description: + The ICS-43432 and compatible MEMS microphones output audio over an I2S + interface and require no software configuration. The only host connection + is the I2S bus. The microphone requires an I2S clock frequency between + 460 kHz and 3.379 MHz and 64 clock cycles per stereo frame. Each frame + contains 32-bit slots per channel, with 24 bits carrying audio data. + A hardware pin determines whether the microphone outputs audio on the + left or right channel of the I2S frame. + +allOf: + - $ref: dai-common.yaml# + +properties: + compatible: + enum: + - invensense,ics43432 + - cui,cmm-4030d-261 + + port: + $ref: audio-graph-port.yaml# + unevaluatedProperties: false + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + ics43432: ics43432 { + compatible = "invensense,ics43432"; + + port { + endpoint { + remote-endpoint = <&i2s1_endpoint>; + dai-format = "i2s"; + }; + }; + + }; diff --git a/Documentation/devicetree/bindings/sound/loongson,ls1b-ac97.yaml b/Documentation/devicetree/bindings/sound/loongson,ls1b-ac97.yaml new file mode 100644 index 000000000000..1c6a2771f942 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/loongson,ls1b-ac97.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/loongson,ls1b-ac97.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Loongson-1 AC97 Controller + +maintainers: + - Keguang Zhang <keguang.zhang@gmail.com> + +description: + The Loongson-1 AC97 controller supports 2-channel stereo output and input. + It is paired with the DMA engine to handle playback and capture functions. + +allOf: + - $ref: dai-common.yaml# + +properties: + compatible: + oneOf: + - const: loongson,ls1b-ac97 + - items: + - enum: + - loongson,ls1a-ac97 + - loongson,ls1c-ac97 + - const: loongson,ls1b-ac97 + + reg: + maxItems: 3 + + reg-names: + items: + - const: ac97 + - const: audio-tx + - const: audio-rx + + dmas: + maxItems: 2 + + dma-names: + items: + - const: tx + - const: rx + + '#sound-dai-cells': + const: 0 + +required: + - compatible + - reg + - reg-names + - dmas + - dma-names + - '#sound-dai-cells' + +unevaluatedProperties: false + +examples: + - | + audio-controller@1fe74000 { + compatible = "loongson,ls1b-ac97"; + reg = <0x1fe74000 0x60>, <0x1fe72420 0x4>, <0x1fe74c4c 0x4>; + reg-names = "ac97", "audio-tx", "audio-rx"; + dmas = <&dma 1>, <&dma 2>; + dma-names = "tx", "rx"; + #sound-dai-cells = <0>; + }; diff --git a/Documentation/devicetree/bindings/sound/maxim,max98925.yaml b/Documentation/devicetree/bindings/sound/maxim,max98925.yaml index 32fd86204a7a..121e8d2d44da 100644 --- a/Documentation/devicetree/bindings/sound/maxim,max98925.yaml +++ b/Documentation/devicetree/bindings/sound/maxim,max98925.yaml @@ -77,11 +77,11 @@ additionalProperties: false examples: - | + #include <dt-bindings/gpio/gpio.h> i2c { #address-cells = <1>; #size-cells = <0>; - #include <dt-bindings/gpio/gpio.h> audio-codec@3a { compatible = "maxim,max98927"; reg = <0x3a>; diff --git a/Documentation/devicetree/bindings/sound/mediatek,mt8188-mt6359.yaml b/Documentation/devicetree/bindings/sound/mediatek,mt8188-mt6359.yaml index 362e729b51b4..7ba2ea2dfa0b 100644 --- a/Documentation/devicetree/bindings/sound/mediatek,mt8188-mt6359.yaml +++ b/Documentation/devicetree/bindings/sound/mediatek,mt8188-mt6359.yaml @@ -40,6 +40,14 @@ properties: hardware that provides additional audio functionalities if present. The AFE will link to ADSP when the phandle is provided. + mediatek,accdet: + $ref: /schemas/types.yaml#/definitions/phandle + description: + The phandle to the MT6359 accessory detection block, which detects audio + jack insertion and removal. This property should only be present if the + accdet block is actually wired to the audio jack pins and to be used for + jack detection. + patternProperties: "^dai-link-[0-9]+$": type: object @@ -62,6 +70,7 @@ patternProperties: - PCM1_BE - DL_SRC_BE - UL_SRC_BE + - DMIC_BE codec: description: Holds subnode which indicates codec dai. @@ -87,10 +96,9 @@ patternProperties: mediatek,clk-provider: $ref: /schemas/types.yaml#/definitions/string description: Indicates dai-link clock master. - items: - enum: - - cpu - - codec + enum: + - cpu + - codec additionalProperties: false diff --git a/Documentation/devicetree/bindings/sound/mt8186-mt6366-da7219-max98357.yaml b/Documentation/devicetree/bindings/sound/mt8186-mt6366-da7219-max98357.yaml index cbc641ecbe94..037f21443ad1 100644 --- a/Documentation/devicetree/bindings/sound/mt8186-mt6366-da7219-max98357.yaml +++ b/Documentation/devicetree/bindings/sound/mt8186-mt6366-da7219-max98357.yaml @@ -124,10 +124,9 @@ patternProperties: mediatek,clk-provider: $ref: /schemas/types.yaml#/definitions/string description: Indicates dai-link clock master. - items: - enum: - - cpu - - codec + enum: + - cpu + - codec required: - link-name diff --git a/Documentation/devicetree/bindings/sound/mt8195-mt6359.yaml b/Documentation/devicetree/bindings/sound/mt8195-mt6359.yaml index 2af1d8ffbd8b..356e1feee962 100644 --- a/Documentation/devicetree/bindings/sound/mt8195-mt6359.yaml +++ b/Documentation/devicetree/bindings/sound/mt8195-mt6359.yaml @@ -21,6 +21,7 @@ properties: - mediatek,mt8195_mt6359_rt1019_rt5682 - mediatek,mt8195_mt6359_rt1011_rt5682 - mediatek,mt8195_mt6359_max98390_rt5682 + - mediatek,mt8195_mt6359 model: $ref: /schemas/types.yaml#/definitions/string @@ -44,6 +45,8 @@ properties: - Right Spk # Sources + - Headphone L + - Headphone R - Headset Mic - HPOL - HPOR @@ -88,6 +91,7 @@ patternProperties: link-name: description: Indicates dai-link name and PCM stream name enum: + - DL_SRC_BE - DPTX_BE - ETDM1_IN_BE - ETDM2_IN_BE diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-graph-card.yaml b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-graph-card.yaml index b4bee466d67a..da89523ccf5f 100644 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-graph-card.yaml +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-graph-card.yaml @@ -23,6 +23,7 @@ properties: enum: - nvidia,tegra210-audio-graph-card - nvidia,tegra186-audio-graph-card + - nvidia,tegra264-audio-graph-card clocks: minItems: 2 diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra186-asrc.yaml b/Documentation/devicetree/bindings/sound/nvidia,tegra186-asrc.yaml index e15f387c4c29..66b56e71599b 100644 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra186-asrc.yaml +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra186-asrc.yaml @@ -31,7 +31,9 @@ properties: compatible: oneOf: - - const: nvidia,tegra186-asrc + - enum: + - nvidia,tegra186-asrc + - nvidia,tegra264-asrc - items: - enum: - nvidia,tegra234-asrc diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra186-dspk.yaml b/Documentation/devicetree/bindings/sound/nvidia,tegra186-dspk.yaml index e1362c77472b..46ba167081ef 100644 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra186-dspk.yaml +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra186-dspk.yaml @@ -29,6 +29,7 @@ properties: - const: nvidia,tegra186-dspk - items: - enum: + - nvidia,tegra264-dspk - nvidia,tegra234-dspk - nvidia,tegra194-dspk - const: nvidia,tegra186-dspk diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra210-admaif.yaml b/Documentation/devicetree/bindings/sound/nvidia,tegra210-admaif.yaml index 15ab40aeab1e..b32f33214ba6 100644 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra210-admaif.yaml +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra210-admaif.yaml @@ -26,6 +26,7 @@ properties: - enum: - nvidia,tegra210-admaif - nvidia,tegra186-admaif + - nvidia,tegra264-admaif - items: - enum: - nvidia,tegra234-admaif @@ -39,6 +40,19 @@ properties: dma-names: true + interconnects: + items: + - description: APE read memory client + - description: APE write memory client + + interconnect-names: + items: + - const: dma-mem # read + - const: write + + iommus: + maxItems: 1 + ports: $ref: /schemas/graph.yaml#/properties/ports description: | @@ -74,6 +88,9 @@ then: Should be "tx1", "tx2" ... "tx10" for DMA Tx channel minItems: 1 maxItems: 20 + interconnects: false + interconnect-names: false + iommus: false else: properties: diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra210-adx.yaml b/Documentation/devicetree/bindings/sound/nvidia,tegra210-adx.yaml index e4c871797fa6..19a80929f93e 100644 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra210-adx.yaml +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra210-adx.yaml @@ -27,7 +27,9 @@ properties: compatible: oneOf: - - const: nvidia,tegra210-adx + - enum: + - nvidia,tegra210-adx + - nvidia,tegra264-adx - items: - enum: - nvidia,tegra234-adx diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra210-ahub.yaml b/Documentation/devicetree/bindings/sound/nvidia,tegra210-ahub.yaml index c4abac81f207..1c9f24d26819 100644 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra210-ahub.yaml +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra210-ahub.yaml @@ -27,6 +27,7 @@ properties: - nvidia,tegra210-ahub - nvidia,tegra186-ahub - nvidia,tegra234-ahub + - nvidia,tegra264-ahub - items: - const: nvidia,tegra194-ahub - const: nvidia,tegra186-ahub diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra210-amx.yaml b/Documentation/devicetree/bindings/sound/nvidia,tegra210-amx.yaml index 021b72546ba4..89712102cfdf 100644 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra210-amx.yaml +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra210-amx.yaml @@ -26,11 +26,13 @@ properties: compatible: oneOf: - - const: nvidia,tegra210-amx + - enum: + - nvidia,tegra210-amx + - nvidia,tegra194-amx + - nvidia,tegra264-amx - items: - const: nvidia,tegra186-amx - const: nvidia,tegra210-amx - - const: nvidia,tegra194-amx - items: - const: nvidia,tegra234-amx - const: nvidia,tegra194-amx diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra210-dmic.yaml b/Documentation/devicetree/bindings/sound/nvidia,tegra210-dmic.yaml index bff551c35da7..bb8088878d4b 100644 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra210-dmic.yaml +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra210-dmic.yaml @@ -28,6 +28,7 @@ properties: - const: nvidia,tegra210-dmic - items: - enum: + - nvidia,tegra264-dmic - nvidia,tegra234-dmic - nvidia,tegra194-dmic - nvidia,tegra186-dmic diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra210-i2s.yaml b/Documentation/devicetree/bindings/sound/nvidia,tegra210-i2s.yaml index a82f11fb6c9a..903e815af8fd 100644 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra210-i2s.yaml +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra210-i2s.yaml @@ -25,7 +25,9 @@ properties: compatible: oneOf: - - const: nvidia,tegra210-i2s + - enum: + - nvidia,tegra210-i2s + - nvidia,tegra264-i2s - items: - enum: - nvidia,tegra234-i2s diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra210-mbdrc.yaml b/Documentation/devicetree/bindings/sound/nvidia,tegra210-mbdrc.yaml index 5b9198602fc6..4c121b9cde1e 100644 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra210-mbdrc.yaml +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra210-mbdrc.yaml @@ -23,6 +23,7 @@ properties: - const: nvidia,tegra210-mbdrc - items: - enum: + - nvidia,tegra264-mbdrc - nvidia,tegra234-mbdrc - nvidia,tegra194-mbdrc - nvidia,tegra186-mbdrc diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra210-mixer.yaml b/Documentation/devicetree/bindings/sound/nvidia,tegra210-mixer.yaml index 049898f02e85..56b4c4fc123c 100644 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra210-mixer.yaml +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra210-mixer.yaml @@ -28,6 +28,7 @@ properties: - const: nvidia,tegra210-amixer - items: - enum: + - nvidia,tegra264-amixer - nvidia,tegra234-amixer - nvidia,tegra194-amixer - nvidia,tegra186-amixer diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra210-mvc.yaml b/Documentation/devicetree/bindings/sound/nvidia,tegra210-mvc.yaml index d0280d8aa3af..bde4ac6319b1 100644 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra210-mvc.yaml +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra210-mvc.yaml @@ -31,6 +31,7 @@ properties: - const: nvidia,tegra210-mvc - items: - enum: + - nvidia,tegra264-mvc - nvidia,tegra234-mvc - nvidia,tegra194-mvc - nvidia,tegra186-mvc diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra210-ope.yaml b/Documentation/devicetree/bindings/sound/nvidia,tegra210-ope.yaml index 9017fb6d575d..756c3096a2d6 100644 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra210-ope.yaml +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra210-ope.yaml @@ -25,6 +25,7 @@ properties: - const: nvidia,tegra210-ope - items: - enum: + - nvidia,tegra264-ope - nvidia,tegra234-ope - nvidia,tegra194-ope - nvidia,tegra186-ope diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra210-peq.yaml b/Documentation/devicetree/bindings/sound/nvidia,tegra210-peq.yaml index 1e373c49d639..2f11a484dc2e 100644 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra210-peq.yaml +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra210-peq.yaml @@ -24,6 +24,7 @@ properties: - const: nvidia,tegra210-peq - items: - enum: + - nvidia,tegra264-peq - nvidia,tegra234-peq - nvidia,tegra194-peq - nvidia,tegra186-peq diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra210-sfc.yaml b/Documentation/devicetree/bindings/sound/nvidia,tegra210-sfc.yaml index 185ca0be4f02..959aa7fffdac 100644 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra210-sfc.yaml +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra210-sfc.yaml @@ -28,6 +28,7 @@ properties: - const: nvidia,tegra210-sfc - items: - enum: + - nvidia,tegra264-sfc - nvidia,tegra234-sfc - nvidia,tegra194-sfc - nvidia,tegra186-sfc diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra30-hda.yaml b/Documentation/devicetree/bindings/sound/nvidia,tegra30-hda.yaml index 12c31b4b99e1..8a8767589ee0 100644 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra30-hda.yaml +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra30-hda.yaml @@ -20,14 +20,17 @@ properties: compatible: oneOf: - - const: nvidia,tegra30-hda + - enum: + - nvidia,tegra30-hda + - nvidia,tegra194-hda + - nvidia,tegra234-hda + - nvidia,tegra264-hda - items: - enum: - - nvidia,tegra234-hda - - nvidia,tegra194-hda - nvidia,tegra186-hda - nvidia,tegra210-hda - nvidia,tegra124-hda + - nvidia,tegra114-hda - const: nvidia,tegra30-hda - items: - const: nvidia,tegra132-hda @@ -42,15 +45,12 @@ properties: maxItems: 1 clocks: - minItems: 2 + minItems: 1 maxItems: 3 clock-names: - minItems: 2 - items: - - const: hda - - const: hda2hdmi - - const: hda2codec_2x + minItems: 1 + maxItems: 3 resets: minItems: 2 @@ -58,10 +58,7 @@ properties: reset-names: minItems: 2 - items: - - const: hda - - const: hda2hdmi - - const: hda2codec_2x + maxItems: 3 power-domains: maxItems: 1 @@ -92,6 +89,92 @@ required: additionalProperties: false +allOf: + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra30-hda + then: + properties: + clocks: + minItems: 3 + clock-names: + items: + - const: hda + - const: hda2hdmi + - const: hda2codec_2x + resets: + minItems: 3 + reset-names: + items: + - const: hda + - const: hda2hdmi + - const: hda2codec_2x + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra194-hda + then: + properties: + clocks: + minItems: 3 + clock-names: + items: + - const: hda + - const: hda2hdmi + - const: hda2codec_2x + resets: + maxItems: 2 + reset-names: + items: + - const: hda + - const: hda2hdmi + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra234-hda + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: hda + - const: hda2codec_2x + resets: + maxItems: 2 + reset-names: + items: + - const: hda + - const: hda2codec_2x + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra264-hda + then: + properties: + clocks: + maxItems: 1 + clock-names: + items: + - const: hda + resets: + maxItems: 2 + reset-names: + items: + - const: hda + - const: hda2codec_2x + power-domains: false + examples: - | #include<dt-bindings/clock/tegra124-car-common.h> diff --git a/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml b/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml index b9e33a7429b0..590eb177f57a 100644 --- a/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml +++ b/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml @@ -28,9 +28,12 @@ properties: - qcom,sm8750-sndcard - const: qcom,sm8450-sndcard - enum: + - fairphone,fp5-sndcard - qcom,apq8096-sndcard - qcom,qcm6490-idp-sndcard - qcom,qcs6490-rb3gen2-sndcard + - qcom,qcs9075-sndcard + - qcom,qcs9100-sndcard - qcom,qrb4210-rb2-sndcard - qcom,qrb5165-rb5-sndcard - qcom,sc7180-qdsp6-sndcard @@ -190,4 +193,19 @@ examples: sound-dai = <&vamacro 0>; }; }; + + usb-dai-link { + link-name = "USB Playback"; + cpu { + sound-dai = <&q6afedai USB_RX>; + }; + + codec { + sound-dai = <&usbdai USB_RX>; + }; + + platform { + sound-dai = <&q6routing>; + }; + }; }; diff --git a/Documentation/devicetree/bindings/sound/qcom,wcd937x-sdw.yaml b/Documentation/devicetree/bindings/sound/qcom,wcd937x-sdw.yaml index d3cf8f59cb23..c8543f969ebb 100644 --- a/Documentation/devicetree/bindings/sound/qcom,wcd937x-sdw.yaml +++ b/Documentation/devicetree/bindings/sound/qcom,wcd937x-sdw.yaml @@ -58,6 +58,40 @@ properties: items: enum: [1, 2, 3, 4, 5] + qcom,tx-channel-mapping: + description: | + Specifies static channel mapping between slave and master tx port + channels. + In the order of slave port channels which is adc1, adc2, adc3, + dmic0, dmic1, mbhc, dmic2, dmic3, dmci4, dmic5, dmic6, dmic7. + $ref: /schemas/types.yaml#/definitions/uint8-array + minItems: 12 + maxItems: 12 + additionalItems: false + items: + enum: + - 1 # WCD9370_SWRM_CH1 + - 2 # WCD9370_SWRM_CH2 + - 3 # WCD9370_SWRM_CH3 + - 4 # WCD9370_SWRM_CH4 + + qcom,rx-channel-mapping: + description: | + Specifies static channels mapping between slave and master rx port + channels. + In the order of slave port channels, which is + hph_l, hph_r, clsh, comp_l, comp_r, lo, dsd_r, dsd_l. + $ref: /schemas/types.yaml#/definitions/uint8-array + minItems: 8 + maxItems: 8 + additionalItems: false + items: + enum: + - 1 # WCD9370_SWRM_CH1 + - 2 # WCD9370_SWRM_CH2 + - 3 # WCD9370_SWRM_CH3 + - 4 # WCD9370_SWRM_CH4 + required: - compatible - reg @@ -74,6 +108,7 @@ examples: compatible = "sdw20217010a00"; reg = <0 4>; qcom,rx-port-mapping = <1 2 3 4 5>; + qcom,rx-channel-mapping = /bits/ 8 <1 2 1 1 2 1 1 2>; }; }; @@ -85,6 +120,7 @@ examples: compatible = "sdw20217010a00"; reg = <0 3>; qcom,tx-port-mapping = <2 2 3 4>; + qcom,tx-channel-mapping = /bits/ 8 <1 2 1 1 2 3 3 4 1 2 3 4>; }; }; diff --git a/Documentation/devicetree/bindings/sound/qcom,wcd938x.yaml b/Documentation/devicetree/bindings/sound/qcom,wcd938x.yaml index 10531350c336..ab1c6285dbf8 100644 --- a/Documentation/devicetree/bindings/sound/qcom,wcd938x.yaml +++ b/Documentation/devicetree/bindings/sound/qcom,wcd938x.yaml @@ -23,9 +23,15 @@ properties: - qcom,wcd9380-codec - qcom,wcd9385-codec + mux-controls: + description: A reference to the audio mux switch for + switching CTIA/OMTP Headset types + maxItems: 1 + us-euro-gpios: description: GPIO spec for swapping gnd and mic segments maxItems: 1 + deprecated: true required: - compatible diff --git a/Documentation/devicetree/bindings/sound/realtek,alc203.yaml b/Documentation/devicetree/bindings/sound/realtek,alc203.yaml new file mode 100644 index 000000000000..6b90788b45eb --- /dev/null +++ b/Documentation/devicetree/bindings/sound/realtek,alc203.yaml @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/realtek,alc203.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Realtek ALC203 AC97 Audio Codec + +maintainers: + - Keguang Zhang <keguang.zhang@gmail.com> + +description: + ALC203 is a full duplex AC97 2.3 compatible stereo audio codec. + +allOf: + - $ref: dai-common.yaml# + +properties: + compatible: + const: realtek,alc203 + + '#sound-dai-cells': + const: 0 + +required: + - compatible + - '#sound-dai-cells' + +unevaluatedProperties: false + +examples: + - | + audio-codec { + compatible = "realtek,alc203"; + #sound-dai-cells = <0>; + }; diff --git a/Documentation/devicetree/bindings/sound/richtek,rt9123.yaml b/Documentation/devicetree/bindings/sound/richtek,rt9123.yaml new file mode 100644 index 000000000000..5acb05cdfefd --- /dev/null +++ b/Documentation/devicetree/bindings/sound/richtek,rt9123.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/richtek,rt9123.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Richtek RT9123 Audio Amplifier + +maintainers: + - ChiYuan Huang <cy_huang@richtek.com> + +description: + RT9123 is a 3.2W mono Class-D audio amplifier that features high efficiency + and performance with ultra-low quiescent current. The digital audio interface + support various formats, including I2S, left-justified, right-justified, and + TDM formats. + +allOf: + - $ref: dai-common.yaml# + +properties: + compatible: + enum: + - richtek,rt9123 + + reg: + maxItems: 1 + + '#sound-dai-cells': + const: 0 + + enable-gpios: + maxItems: 1 + +required: + - compatible + - reg + - '#sound-dai-cells' + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + amplifier@5e { + compatible = "richtek,rt9123"; + reg = <0x5e>; + enable-gpios = <&gpio 26 GPIO_ACTIVE_HIGH>; + #sound-dai-cells = <0>; + }; + }; diff --git a/Documentation/devicetree/bindings/sound/richtek,rt9123p.yaml b/Documentation/devicetree/bindings/sound/richtek,rt9123p.yaml new file mode 100644 index 000000000000..693511dfdda4 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/richtek,rt9123p.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/richtek,rt9123p.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Richtek RT9123P Audio Amplifier + +maintainers: + - ChiYuan Huang <cy_huang@richtek.com> + +description: + RT9123P is a RT9123 variant which does not support I2C control. + +allOf: + - $ref: dai-common.yaml# + +properties: + compatible: + enum: + - richtek,rt9123p + + '#sound-dai-cells': + const: 0 + + enable-gpios: + maxItems: 1 + + enable-delay-ms: + description: + Delay time for 'ENABLE' pin changes intended to make I2S clocks ready to + prevent speaker pop noise. The unit is in millisecond. + +required: + - compatible + - '#sound-dai-cells' + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + amplifier { + compatible = "richtek,rt9123p"; + enable-gpios = <&gpio 26 GPIO_ACTIVE_HIGH>; + #sound-dai-cells = <0>; + }; diff --git a/Documentation/devicetree/bindings/sound/rockchip,rk3576-sai.yaml b/Documentation/devicetree/bindings/sound/rockchip,rk3576-sai.yaml new file mode 100644 index 000000000000..149da9a91451 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/rockchip,rk3576-sai.yaml @@ -0,0 +1,144 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/rockchip,rk3576-sai.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip Serial Audio Interface Controller + +description: + The Rockchip Serial Audio Interface (SAI) controller is a flexible audio + controller that implements the I2S, I2S/TDM and the PDM standards. + +maintainers: + - Nicolas Frattaroli <nicolas.frattaroli@collabora.com> + +allOf: + - $ref: dai-common.yaml# + +properties: + compatible: + const: rockchip,rk3576-sai + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + dmas: + minItems: 1 + maxItems: 2 + + dma-names: + minItems: 1 + items: + - enum: [tx, rx] + - const: rx + + clocks: + items: + - description: master audio clock + - description: AHB clock driving the interface + + clock-names: + items: + - const: mclk + - const: hclk + + resets: + minItems: 1 + items: + - description: reset for the mclk domain + - description: reset for the hclk domain + + reset-names: + minItems: 1 + items: + - const: m + - const: h + + port: + $ref: audio-graph-port.yaml# + unevaluatedProperties: false + + power-domains: + maxItems: 1 + + "#sound-dai-cells": + const: 0 + + rockchip,sai-rx-route: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + Defines the mapping of the controller's SDI ports to actual input lanes, + as well as the number of input lanes. + rockchip,sai-rx-route = <3> would mean sdi3 is receiving from data0, and + that there is only one receiving lane. + This property's absence is to be understood as only one receiving lane + being used if the controller has capture capabilities. + maxItems: 4 + items: + minimum: 0 + maximum: 3 + + rockchip,sai-tx-route: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + Defines the mapping of the controller's SDO ports to actual output lanes, + as well as the number of output lanes. + rockchip,sai-tx-route = <3> would mean sdo3 is sending to data0, and + that there is only one transmitting lane. + This property's absence is to be understood as only one transmitting lane + being used if the controller has playback capabilities. + maxItems: 4 + items: + minimum: 0 + maximum: 3 + +required: + - compatible + - reg + - dmas + - dma-names + - clocks + - clock-names + - "#sound-dai-cells" + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/rockchip,rk3576-cru.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/pinctrl/rockchip.h> + #include <dt-bindings/power/rockchip,rk3576-power.h> + #include <dt-bindings/reset/rockchip,rk3576-cru.h> + + bus { + #address-cells = <2>; + #size-cells = <2>; + sai1: sai@2a610000 { + compatible = "rockchip,rk3576-sai"; + reg = <0x0 0x2a610000 0x0 0x1000>; + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru MCLK_SAI1_8CH>, <&cru HCLK_SAI1_8CH>; + clock-names = "mclk", "hclk"; + dmas = <&dmac0 2>, <&dmac0 3>; + dma-names = "tx", "rx"; + power-domains = <&power RK3576_PD_AUDIO>; + resets = <&cru SRST_M_SAI1_8CH>, <&cru SRST_H_SAI1_8CH>; + reset-names = "m", "h"; + pinctrl-names = "default"; + pinctrl-0 = <&sai1m0_lrck + &sai1m0_sclk + &sai1m0_sdi0 + &sai1m0_sdo0 + &sai1m0_sdo1 + &sai1m0_sdo2 + &sai1m0_sdo3>; + rockchip,sai-tx-route = <3 1 2 0>; + #sound-dai-cells = <0>; + }; + }; diff --git a/Documentation/devicetree/bindings/sound/rockchip-spdif.yaml b/Documentation/devicetree/bindings/sound/rockchip-spdif.yaml index c3c989ef2a2c..32dea7392e8d 100644 --- a/Documentation/devicetree/bindings/sound/rockchip-spdif.yaml +++ b/Documentation/devicetree/bindings/sound/rockchip-spdif.yaml @@ -31,6 +31,10 @@ properties: - rockchip,rk3288-spdif - rockchip,rk3308-spdif - const: rockchip,rk3066-spdif + - items: + - enum: + - rockchip,rk3588-spdif + - const: rockchip,rk3568-spdif reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/sound/ti,tas2770.yaml b/Documentation/devicetree/bindings/sound/ti,tas2770.yaml index 5e7aea43aced..8eab98a0f7a2 100644 --- a/Documentation/devicetree/bindings/sound/ti,tas2770.yaml +++ b/Documentation/devicetree/bindings/sound/ti,tas2770.yaml @@ -23,6 +23,7 @@ properties: compatible: enum: - ti,tas2770 + - ti,tas5770l # Apple variant reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/sound/ti,tas27xx.yaml b/Documentation/devicetree/bindings/sound/ti,tas27xx.yaml index 5447482179c1..fcaae848e78a 100644 --- a/Documentation/devicetree/bindings/sound/ti,tas27xx.yaml +++ b/Documentation/devicetree/bindings/sound/ti,tas27xx.yaml @@ -24,6 +24,7 @@ properties: enum: - ti,tas2764 - ti,tas2780 + - ti,sn012776 # Apple variant of TAS2764 reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/sound/wlf,wm8904.yaml b/Documentation/devicetree/bindings/sound/wlf,wm8904.yaml index 329260cf0fa0..3029a868e5e1 100644 --- a/Documentation/devicetree/bindings/sound/wlf,wm8904.yaml +++ b/Documentation/devicetree/bindings/sound/wlf,wm8904.yaml @@ -38,6 +38,82 @@ properties: DCVDD-supply: true MICVDD-supply: true + wlf,in1l-as-dmicdat1: + type: boolean + description: + Use IN1L/DMICDAT1 as DMICDAT1, enabling the DMIC input path. + Can be used separately or together with wlf,in1r-as-dmicdat2. + + wlf,in1r-as-dmicdat2: + type: boolean + description: + Use IN1R/DMICDAT2 as DMICDAT2, enabling the DMIC input path. + Can be used separately or together with wlf,in1l-as-dmicdat1. + + wlf,gpio-cfg: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 4 + maxItems: 4 + description: + Default register values for R121/122/123/124 (GPIO Control). + If any entry has the value 0xFFFF, the related register won't be set. + default: [0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF] + + wlf,micbias-cfg: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 2 + maxItems: 2 + description: + Default register values for R6/R7 (Mic Bias Control). + default: [0, 0] + + wlf,drc-cfg-names: + $ref: /schemas/types.yaml#/definitions/string-array + description: + List of strings for the available DRC modes. + If absent, DRC is disabled. + + wlf,drc-cfg-regs: + $ref: /schemas/types.yaml#/definitions/uint16-matrix + description: + Sets of default register values for R40/41/42/43 (DRC). + Each set corresponds to a DRC mode, so the number of sets should equal + the length of wlf,drc-cfg-names. + If absent, DRC is disabled. + items: + minItems: 4 + maxItems: 4 + + wlf,retune-mobile-cfg-names: + $ref: /schemas/types.yaml#/definitions/non-unique-string-array + description: + List of strings for the available retune modes. + If absent, retune is disabled. + + wlf,retune-mobile-cfg-hz: + description: + The list must be the same length as wlf,retune-mobile-cfg-names. + If absent, retune is disabled. + + wlf,retune-mobile-cfg-regs: + $ref: /schemas/types.yaml#/definitions/uint16-matrix + description: + Sets of default register values for R134/.../157 (EQ). + Each set corresponds to a retune mode, so the number of sets should equal + the length of wlf,retune-mobile-cfg-names. + If absent, retune is disabled. + items: + minItems: 24 + maxItems: 24 + +dependencies: + wlf,drc-cfg-names: [ 'wlf,drc-cfg-regs' ] + wlf,drc-cfg-regs: [ 'wlf,drc-cfg-names' ] + + wlf,retune-mobile-cfg-names: [ 'wlf,retune-mobile-cfg-hz', 'wlf,retune-mobile-cfg-regs' ] + wlf,retune-mobile-cfg-regs: [ 'wlf,retune-mobile-cfg-names', 'wlf,retune-mobile-cfg-hz' ] + wlf,retune-mobile-cfg-hz: [ 'wlf,retune-mobile-cfg-names', 'wlf,retune-mobile-cfg-regs' ] + required: - compatible - reg @@ -70,5 +146,58 @@ examples: DBVDD-supply = <®_1p8v>; DCVDD-supply = <®_1p8v>; MICVDD-supply = <®_1p8v>; + + wlf,drc-cfg-names = "default", "peaklimiter", "tradition", "soft", + "music"; + /* + * Config registers per name, respectively: + * KNEE_IP = 0, KNEE_OP = 0, HI_COMP = 1, LO_COMP = 1 + * KNEE_IP = -24, KNEE_OP = -6, HI_COMP = 1/4, LO_COMP = 1 + * KNEE_IP = -42, KNEE_OP = -3, HI_COMP = 0, LO_COMP = 1 + * KNEE_IP = -45, KNEE_OP = -9, HI_COMP = 1/8, LO_COMP = 1 + * KNEE_IP = -30, KNEE_OP = -10.5, HI_COMP = 1/4, LO_COMP = 1 + */ + wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>, + /bits/ 16 <0x04af 0x324b 0x0010 0x0408>, + /bits/ 16 <0x04af 0x324b 0x0028 0x0704>, + /bits/ 16 <0x04af 0x324b 0x0018 0x078c>, + /bits/ 16 <0x04af 0x324b 0x0010 0x050e>; + + /* GPIO1 = DMIC_CLK, don't touch others */ + wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>; + + /* Use IN1R as DMICDAT2, leave IN1L as an analog input path */ + wlf,in1r-as-dmicdat2; + + wlf,retune-mobile-cfg-names = "bassboost", "bassboost", "treble"; + wlf,retune-mobile-cfg-hz = <48000>, <44100>, <48000>; + /* + * Config registers per name, respectively: + * EQ_ENA, 100 Hz, 300 Hz, 875 Hz, 2400 Hz, 6900 Hz + * 1, +6 dB, +3 dB, 0 dB, 0 dB, 0 dB + * 1, +6 dB, +3 dB, 0 dB, 0 dB, 0 dB + * 1, -2 dB, -2 dB, 0 dB, 0 dB, +3 dB + * Each one uses the defaults for ReTune Mobile registers 140-157 + */ + wlf,retune-mobile-cfg-regs = /bits/ 16 <0x1 0x12 0xf 0xc 0xc 0xc + 0x0fca 0x0400 0x00d8 0x1eb5 + 0xf145 0x0bd5 0x0075 0x1c58 + 0xf3d3 0x0a54 0x0568 0x168e + 0xf829 0x07ad 0x1103 0x0564 + 0x0559 0x4000>, + + /bits/ 16 <0x1 0x12 0xf 0xc 0xc 0xc + 0x0fca 0x0400 0x00d8 0x1eb5 + 0xf145 0x0bd5 0x0075 0x1c58 + 0xf3d3 0x0a54 0x0568 0x168e + 0xf829 0x07ad 0x1103 0x0564 + 0x0559 0x4000>, + + /bits/ 16 <0x1 0xa 0xa 0xc 0xc 0xf + 0x0fca 0x0400 0x00d8 0x1eb5 + 0xf145 0x0bd5 0x0075 0x1c58 + 0xf3d3 0x0a54 0x0568 0x168e + 0xf829 0x07ad 0x1103 0x0564 + 0x0559 0x4000>; }; }; diff --git a/Documentation/devicetree/bindings/sound/wlf,wm8960.yaml b/Documentation/devicetree/bindings/sound/wlf,wm8960.yaml index 62e62c335d07..3c2b9790ffcf 100644 --- a/Documentation/devicetree/bindings/sound/wlf,wm8960.yaml +++ b/Documentation/devicetree/bindings/sound/wlf,wm8960.yaml @@ -75,6 +75,10 @@ properties: enable DACLRC pin. If shared-lrclk is present, no need to enable DAC for captrue. + port: + $ref: audio-graph-port.yaml# + unevaluatedProperties: false + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/sound/xlnx,audio-formatter.txt b/Documentation/devicetree/bindings/sound/xlnx,audio-formatter.txt deleted file mode 100644 index cbc93c8f4963..000000000000 --- a/Documentation/devicetree/bindings/sound/xlnx,audio-formatter.txt +++ /dev/null @@ -1,29 +0,0 @@ -Device-Tree bindings for Xilinx PL audio formatter - -The IP core supports DMA, data formatting(AES<->PCM conversion) -of audio samples. - -Required properties: - - compatible: "xlnx,audio-formatter-1.0" - - interrupt-names: Names specified to list of interrupts in same - order mentioned under "interrupts". - List of supported interrupt names are: - "irq_mm2s" : interrupt from MM2S block - "irq_s2mm" : interrupt from S2MM block - - interrupts-parent: Phandle for interrupt controller. - - interrupts: List of Interrupt numbers. - - reg: Base address and size of the IP core instance. - - clock-names: List of input clocks. - Required elements: "s_axi_lite_aclk", "aud_mclk" - - clocks: Input clock specifier. Refer to common clock bindings. - -Example: - audio_ss_0_audio_formatter_0: audio_formatter@80010000 { - compatible = "xlnx,audio-formatter-1.0"; - interrupt-names = "irq_mm2s", "irq_s2mm"; - interrupt-parent = <&gic>; - interrupts = <0 104 4>, <0 105 4>; - reg = <0x0 0x80010000 0x0 0x1000>; - clock-names = "s_axi_lite_aclk", "aud_mclk"; - clocks = <&clk 71>, <&clk_wiz_1 0>; - }; diff --git a/Documentation/devicetree/bindings/sound/xlnx,audio-formatter.yaml b/Documentation/devicetree/bindings/sound/xlnx,audio-formatter.yaml new file mode 100644 index 000000000000..82fa448bd2e9 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/xlnx,audio-formatter.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/xlnx,audio-formatter.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx PL audio formatter + +description: + The IP core supports DMA, data formatting(AES<->PCM conversion) + of audio samples. + +maintainers: + - Vincenzo Frascino <vincenzo.frascino@arm.com> + +allOf: + - $ref: dai-common.yaml# + +properties: + compatible: + enum: + - xlnx,audio-formatter-1.0 + + reg: + maxItems: 1 + + interrupt-names: + minItems: 1 + items: + - const: irq_mm2s + - const: irq_s2mm + + interrupts: + minItems: 1 + items: + - description: interrupt from MM2S block + - description: interrupt from S2MM block + + clock-names: + minItems: 1 + items: + - const: s_axi_lite_aclk + - const: aud_mclk + + clocks: + minItems: 1 + items: + - description: clock for the axi data stream + - description: clock for the MEMS microphone data stream + +required: + - compatible + - reg + - interrupt-names + - interrupts + - clock-names + - clocks + +additionalProperties: false + +examples: + - | + audio_formatter@80010000 { + compatible = "xlnx,audio-formatter-1.0"; + reg = <0x80010000 0x1000>; + interrupt-names = "irq_mm2s", "irq_s2mm"; + interrupt-parent = <&gic>; + interrupts = <0 104 4>, <0 105 4>; + clock-names = "s_axi_lite_aclk", "aud_mclk"; + clocks = <&clk 71>, <&clk_wiz_1 0>; + }; +... diff --git a/Documentation/devicetree/bindings/sound/xlnx,i2s.txt b/Documentation/devicetree/bindings/sound/xlnx,i2s.txt deleted file mode 100644 index 5e7c7d5bb60a..000000000000 --- a/Documentation/devicetree/bindings/sound/xlnx,i2s.txt +++ /dev/null @@ -1,28 +0,0 @@ -Device-Tree bindings for Xilinx I2S PL block - -The IP supports I2S based playback/capture audio - -Required property: - - compatible: "xlnx,i2s-transmitter-1.0" for playback and - "xlnx,i2s-receiver-1.0" for capture - -Required property common to both I2S playback and capture: - - reg: Base address and size of the IP core instance. - - xlnx,dwidth: sample data width. Can be any of 16, 24. - - xlnx,num-channels: Number of I2S streams. Can be any of 1, 2, 3, 4. - supported channels = 2 * xlnx,num-channels - -Example: - - i2s_receiver@a0080000 { - compatible = "xlnx,i2s-receiver-1.0"; - reg = <0x0 0xa0080000 0x0 0x10000>; - xlnx,dwidth = <0x18>; - xlnx,num-channels = <1>; - }; - i2s_transmitter@a0090000 { - compatible = "xlnx,i2s-transmitter-1.0"; - reg = <0x0 0xa0090000 0x0 0x10000>; - xlnx,dwidth = <0x18>; - xlnx,num-channels = <1>; - }; diff --git a/Documentation/devicetree/bindings/sound/xlnx,i2s.yaml b/Documentation/devicetree/bindings/sound/xlnx,i2s.yaml new file mode 100644 index 000000000000..3c2b0be07c53 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/xlnx,i2s.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/xlnx,i2s.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx I2S PL block + +description: + The IP supports I2S based playback/capture audio. + +maintainers: + - Vincenzo Frascino <vincenzo.frascino@arm.com> + +allOf: + - $ref: dai-common.yaml# + +properties: + compatible: + enum: + - xlnx,i2s-receiver-1.0 + - xlnx,i2s-transmitter-1.0 + + reg: + maxItems: 1 + + xlnx,dwidth: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: + - 16 + - 24 + description: | + Sample data width. + + xlnx,num-channels: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 4 + description: | + Number of I2S streams. + +required: + - compatible + - reg + - xlnx,dwidth + - xlnx,num-channels + +additionalProperties: false + +examples: + - | + i2s@a0080000 { + compatible = "xlnx,i2s-receiver-1.0"; + reg = <0xa0080000 0x10000>; + xlnx,dwidth = <0x18>; + xlnx,num-channels = <1>; + }; + i2s@a0090000 { + compatible = "xlnx,i2s-transmitter-1.0"; + reg = <0xa0090000 0x10000>; + xlnx,dwidth = <0x18>; + xlnx,num-channels = <1>; + }; + +... diff --git a/Documentation/devicetree/bindings/sound/xlnx,spdif.txt b/Documentation/devicetree/bindings/sound/xlnx,spdif.txt deleted file mode 100644 index 15c2d64d247c..000000000000 --- a/Documentation/devicetree/bindings/sound/xlnx,spdif.txt +++ /dev/null @@ -1,28 +0,0 @@ -Device-Tree bindings for Xilinx SPDIF IP - -The IP supports playback and capture of SPDIF audio - -Required properties: - - compatible: "xlnx,spdif-2.0" - - clock-names: List of input clocks. - Required elements: "s_axi_aclk", "aud_clk_i" - - clocks: Input clock specifier. Refer to common clock bindings. - - reg: Base address and address length of the IP core instance. - - interrupts-parent: Phandle for interrupt controller. - - interrupts: List of Interrupt numbers. - - xlnx,spdif-mode: 0 :- receiver mode - 1 :- transmitter mode - - xlnx,aud_clk_i: input audio clock value. - -Example: - spdif_0: spdif@80010000 { - clock-names = "aud_clk_i", "s_axi_aclk"; - clocks = <&misc_clk_0>, <&clk 71>; - compatible = "xlnx,spdif-2.0"; - interrupt-names = "spdif_interrupt"; - interrupt-parent = <&gic>; - interrupts = <0 91 4>; - reg = <0x0 0x80010000 0x0 0x10000>; - xlnx,spdif-mode = <1>; - xlnx,aud_clk_i = <49152913>; - }; diff --git a/Documentation/devicetree/bindings/sound/xlnx,spdif.yaml b/Documentation/devicetree/bindings/sound/xlnx,spdif.yaml new file mode 100644 index 000000000000..a45d8a0755fe --- /dev/null +++ b/Documentation/devicetree/bindings/sound/xlnx,spdif.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/xlnx,spdif.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx SPDIF IP + +description: + The IP supports playback and capture of SPDIF audio. + +maintainers: + - Vincenzo Frascino <vincenzo.frascino@arm.com> + +allOf: + - $ref: dai-common.yaml# + +properties: + compatible: + enum: + - xlnx,spdif-2.0 + + reg: + maxItems: 1 + + interrupts: + items: + - description: SPDIF audio interrupt + + clock-names: + items: + - const: aud_clk_i + - const: s_axi_aclk + + clocks: + minItems: 1 + items: + - description: input audio clock + - description: clock for the AXI data stream + + xlnx,spdif-mode: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: + - 0 + - 1 + description: | + 0 - receiver + 1 - transmitter + + xlnx,aud_clk_i: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Input audio clock frequency. It affects the sampling rate. + +required: + - compatible + - reg + - interrupts + - clock-names + - clocks + +additionalProperties: false + +examples: + - | + spdif@80010000 { + compatible = "xlnx,spdif-2.0"; + reg = <0x80010000 0x10000>; + clock-names = "aud_clk_i", "s_axi_aclk"; + clocks = <&misc_clk_0>, <&clk 71>; + interrupt-parent = <&gic>; + interrupts = <0 91 4>; + xlnx,spdif-mode = <1>; + xlnx,aud_clk_i = <49152913>; + }; + +... diff --git a/Documentation/devicetree/bindings/soundwire/qcom,soundwire.yaml b/Documentation/devicetree/bindings/soundwire/qcom,soundwire.yaml index 3591c8c49bfe..95d947fda6a7 100644 --- a/Documentation/devicetree/bindings/soundwire/qcom,soundwire.yaml +++ b/Documentation/devicetree/bindings/soundwire/qcom,soundwire.yaml @@ -15,13 +15,18 @@ description: properties: compatible: - enum: - - qcom,soundwire-v1.3.0 - - qcom,soundwire-v1.5.0 - - qcom,soundwire-v1.5.1 - - qcom,soundwire-v1.6.0 - - qcom,soundwire-v1.7.0 - - qcom,soundwire-v2.0.0 + oneOf: + - enum: + - qcom,soundwire-v1.3.0 + - qcom,soundwire-v1.5.0 + - qcom,soundwire-v1.5.1 + - qcom,soundwire-v1.6.0 + - qcom,soundwire-v1.7.0 + - qcom,soundwire-v2.0.0 + - items: + - enum: + - qcom,soundwire-v2.1.0 + - const: qcom,soundwire-v2.0.0 reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/spi/adi,axi-spi-engine.yaml b/Documentation/devicetree/bindings/spi/adi,axi-spi-engine.yaml index d48faa42d025..4b3828eda6cb 100644 --- a/Documentation/devicetree/bindings/spi/adi,axi-spi-engine.yaml +++ b/Documentation/devicetree/bindings/spi/adi,axi-spi-engine.yaml @@ -41,6 +41,26 @@ properties: - const: s_axi_aclk - const: spi_clk + trigger-sources: + description: + An array of trigger source phandles for offload instances. The index in + the array corresponds to the offload instance number. + minItems: 1 + maxItems: 32 + + dmas: + description: + DMA channels connected to the input or output stream interface of an + offload instance. + minItems: 1 + maxItems: 32 + + dma-names: + items: + pattern: "^offload(?:[12]?[0-9]|3[01])-[tr]x$" + minItems: 1 + maxItems: 32 + required: - compatible - reg @@ -59,6 +79,10 @@ examples: clocks = <&clkc 15>, <&clkc 15>; clock-names = "s_axi_aclk", "spi_clk"; + trigger-sources = <&trigger_clock>; + dmas = <&dma 0>; + dma-names = "offload0-rx"; + #address-cells = <1>; #size-cells = <0>; diff --git a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml index b6bc71d19286..53a52fb8b819 100644 --- a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml +++ b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/spi/cdns,qspi-nor.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Cadence Quad SPI controller +title: Cadence Quad/Octal SPI controller maintainers: - Vaishnav Achath <vaishnav.a@ti.com> @@ -76,8 +76,12 @@ properties: - ti,am654-ospi - ti,k2g-qspi - xlnx,versal-ospi-1.0 + # The compatible is qspi-nor for historical reasons but such + # controllers are meant to be used with flashes of all kinds, + # ie. also NAND flashes, not only NOR flashes. - const: cdns,qspi-nor - const: cdns,qspi-nor + deprecated: true reg: items: @@ -142,6 +146,18 @@ properties: items: enum: [ qspi, qspi-ocp, rstc_ref ] +patternProperties: + "^flash@[0-9a-f]+$": + type: object + $ref: cdns,qspi-nor-peripheral-props.yaml + additionalProperties: true + required: + - cdns,read-delay + - cdns,tshsl-ns + - cdns,tsd2d-ns + - cdns,tchsh-ns + - cdns,tslch-ns + required: - compatible - reg @@ -157,7 +173,7 @@ unevaluatedProperties: false examples: - | qspi: spi@ff705000 { - compatible = "cdns,qspi-nor"; + compatible = "intel,socfpga-qspi", "cdns,qspi-nor"; #address-cells = <1>; #size-cells = <0>; reg = <0xff705000 0x1000>, @@ -173,5 +189,10 @@ examples: flash@0 { compatible = "jedec,spi-nor"; reg = <0x0>; + cdns,read-delay = <4>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; }; }; diff --git a/Documentation/devicetree/bindings/spi/fsl,dspi.yaml b/Documentation/devicetree/bindings/spi/fsl,dspi.yaml index 7ca8fceda717..bf9cce53c48d 100644 --- a/Documentation/devicetree/bindings/spi/fsl,dspi.yaml +++ b/Documentation/devicetree/bindings/spi/fsl,dspi.yaml @@ -105,12 +105,12 @@ examples: big-endian; flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <16000000>; - spi-cpol; - spi-cpha; - spi-cs-setup-delay-ns = <100>; - spi-cs-hold-delay-ns = <50>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <16000000>; + spi-cpol; + spi-cpha; + spi-cs-setup-delay-ns = <100>; + spi-cs-hold-delay-ns = <50>; }; }; diff --git a/Documentation/devicetree/bindings/spi/fsl,espi.yaml b/Documentation/devicetree/bindings/spi/fsl,espi.yaml new file mode 100644 index 000000000000..d267bbfaf02f --- /dev/null +++ b/Documentation/devicetree/bindings/spi/fsl,espi.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/fsl,espi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale eSPI (Enhanced Serial Peripheral Interface) controller + +maintainers: + - J. Neuschäfer <j.ne@posteo.net> + +properties: + compatible: + const: fsl,mpc8536-espi + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + fsl,espi-num-chipselects: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 1, 4 ] + description: The number of the chipselect signals. + + fsl,csbef: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 15 + description: Chip select assertion time in bits before frame starts + + fsl,csaft: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 15 + description: Chip select negation time in bits after frame ends + +required: + - compatible + - reg + - interrupts + - fsl,espi-num-chipselects + +allOf: + - $ref: spi-controller.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + spi@110000 { + compatible = "fsl,mpc8536-espi"; + reg = <0x110000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <53 IRQ_TYPE_EDGE_FALLING>; + fsl,espi-num-chipselects = <4>; + fsl,csbef = <1>; + fsl,csaft = <1>; + }; + +... diff --git a/Documentation/devicetree/bindings/spi/fsl,spi.yaml b/Documentation/devicetree/bindings/spi/fsl,spi.yaml new file mode 100644 index 000000000000..d74792fc9bf2 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/fsl,spi.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/fsl,spi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale SPI (Serial Peripheral Interface) controller + +maintainers: + - J. Neuschäfer <j.ne@posteo.net> + +properties: + compatible: + enum: + - fsl,spi + - aeroflexgaisler,spictrl + + reg: + maxItems: 1 + + cell-index: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + QE SPI subblock index. + 0: QE subblock SPI1 + 1: QE subblock SPI2 + + mode: + description: SPI operation mode + enum: + - cpu + - cpu-qe + + interrupts: + maxItems: 1 + + clock-frequency: + description: input clock frequency to non FSL_SOC cores + + cs-gpios: true + + fsl,spisel_boot: + $ref: /schemas/types.yaml#/definitions/flag + description: + For the MPC8306 and MPC8309, specifies that the SPISEL_BOOT signal is used + as chip select for a slave device. Use reg = <number of gpios> in the + corresponding child node, i.e. 0 if the cs-gpios property is not present. + +required: + - compatible + - reg + - mode + - interrupts + +allOf: + - $ref: spi-controller.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + spi@4c0 { + compatible = "fsl,spi"; + reg = <0x4c0 0x40>; + cell-index = <0>; + interrupts = <82 0>; + mode = "cpu"; + cs-gpios = <&gpio 18 IRQ_TYPE_EDGE_RISING // device reg=<0> + &gpio 19 IRQ_TYPE_EDGE_RISING>; // device reg=<1> + }; + +... diff --git a/Documentation/devicetree/bindings/spi/fsl-spi.txt b/Documentation/devicetree/bindings/spi/fsl-spi.txt deleted file mode 100644 index 0654380eb751..000000000000 --- a/Documentation/devicetree/bindings/spi/fsl-spi.txt +++ /dev/null @@ -1,62 +0,0 @@ -* SPI (Serial Peripheral Interface) - -Required properties: -- cell-index : QE SPI subblock index. - 0: QE subblock SPI1 - 1: QE subblock SPI2 -- compatible : should be "fsl,spi" or "aeroflexgaisler,spictrl". -- mode : the SPI operation mode, it can be "cpu" or "cpu-qe". -- reg : Offset and length of the register set for the device -- interrupts : <a b> where a is the interrupt number and b is a - field that represents an encoding of the sense and level - information for the interrupt. This should be encoded based on - the information in section 2) depending on the type of interrupt - controller you have. -- clock-frequency : input clock frequency to non FSL_SOC cores - -Optional properties: -- cs-gpios : specifies the gpio pins to be used for chipselects. - The gpios will be referred to as reg = <index> in the SPI child nodes. - If unspecified, a single SPI device without a chip select can be used. -- fsl,spisel_boot : for the MPC8306 and MPC8309, specifies that the - SPISEL_BOOT signal is used as chip select for a slave device. Use - reg = <number of gpios> in the corresponding child node, i.e. 0 if - the cs-gpios property is not present. - -Example: - spi@4c0 { - cell-index = <0>; - compatible = "fsl,spi"; - reg = <4c0 40>; - interrupts = <82 0>; - interrupt-parent = <700>; - mode = "cpu"; - cs-gpios = <&gpio 18 1 // device reg=<0> - &gpio 19 1>; // device reg=<1> - }; - - -* eSPI (Enhanced Serial Peripheral Interface) - -Required properties: -- compatible : should be "fsl,mpc8536-espi". -- reg : Offset and length of the register set for the device. -- interrupts : should contain eSPI interrupt, the device has one interrupt. -- fsl,espi-num-chipselects : the number of the chipselect signals. - -Optional properties: -- fsl,csbef: chip select assertion time in bits before frame starts -- fsl,csaft: chip select negation time in bits after frame ends - -Example: - spi@110000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,mpc8536-espi"; - reg = <0x110000 0x1000>; - interrupts = <53 0x2>; - interrupt-parent = <&mpic>; - fsl,espi-num-chipselects = <4>; - fsl,csbef = <1>; - fsl,csaft = <1>; - }; diff --git a/Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml b/Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml index e1f5bfa4433c..ed17815263a8 100644 --- a/Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml +++ b/Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml @@ -35,6 +35,8 @@ properties: - enum: - mediatek,mt7981-spi-ipm - mediatek,mt7986-spi-ipm + - mediatek,mt7988-spi-quad + - mediatek,mt7988-spi-single - mediatek,mt8188-spi-ipm - const: mediatek,spi-ipm - items: diff --git a/Documentation/devicetree/bindings/spi/nuvoton,wpcm450-fiu.yaml b/Documentation/devicetree/bindings/spi/nuvoton,wpcm450-fiu.yaml index 4e0d391e1d69..c97bf48b56b4 100644 --- a/Documentation/devicetree/bindings/spi/nuvoton,wpcm450-fiu.yaml +++ b/Documentation/devicetree/bindings/spi/nuvoton,wpcm450-fiu.yaml @@ -59,8 +59,3 @@ examples: reg = <0>; }; }; - - shm: syscon@c8001000 { - compatible = "nuvoton,wpcm450-shm", "syscon"; - reg = <0xc8001000 0x1000>; - }; diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml b/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml index 48e97e240265..8b3640280559 100644 --- a/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml +++ b/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml @@ -10,9 +10,6 @@ maintainers: - Thierry Reding <thierry.reding@gmail.com> - Jonathan Hunter <jonathanh@nvidia.com> -allOf: - - $ref: spi-controller.yaml# - properties: compatible: enum: @@ -47,6 +44,9 @@ properties: - const: rx - const: tx + iommus: + maxItems: 1 + patternProperties: "@[0-9a-f]+$": type: object @@ -69,6 +69,18 @@ required: unevaluatedProperties: false +allOf: + - $ref: spi-controller.yaml# + - if: + properties: + compatible: + not: + contains: + const: nvidia,tegra234-qspi + then: + properties: + iommus: false + examples: - | #include <dt-bindings/clock/tegra210-car.h> diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml b/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml new file mode 100644 index 000000000000..cb1f15224b45 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/qcom,spi-qpic-snand.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm QPIC NAND controller + +maintainers: + - Md sadre Alam <quic_mdalam@quicinc.com> + +description: + The QCOM QPIC-SPI-NAND flash controller is an extended version of + the QCOM QPIC NAND flash controller. It can work both in serial + and parallel mode. It supports typical SPI-NAND page cache + operations in single, dual or quad IO mode with pipelined ECC + encoding/decoding using the QPIC ECC HW engine. + +allOf: + - $ref: /schemas/spi/spi-controller.yaml# + +properties: + compatible: + oneOf: + - items: + - enum: + - qcom,ipq5018-snand + - const: qcom,ipq9574-snand + - const: qcom,ipq9574-snand + + reg: + maxItems: 1 + + clocks: + maxItems: 3 + + clock-names: + items: + - const: core + - const: aon + - const: iom + + dmas: + items: + - description: tx DMA channel + - description: rx DMA channel + - description: cmd DMA channel + + dma-names: + items: + - const: tx + - const: rx + - const: cmd + +required: + - compatible + - reg + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,ipq9574-gcc.h> + spi@79b0000 { + compatible = "qcom,ipq9574-snand"; + reg = <0x1ac00000 0x800>; + + clocks = <&gcc GCC_QPIC_CLK>, + <&gcc GCC_QPIC_AHB_CLK>, + <&gcc GCC_QPIC_IO_MACRO_CLK>; + clock-names = "core", "aon", "iom"; + + #address-cells = <1>; + #size-cells = <0>; + + flash@0 { + compatible = "spi-nand"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + nand-ecc-engine = <&qpic_nand>; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + }; + }; diff --git a/Documentation/devicetree/bindings/spi/renesas,sh-msiof.yaml b/Documentation/devicetree/bindings/spi/renesas,sh-msiof.yaml index 49649fc3f95a..e0c7047ae8ad 100644 --- a/Documentation/devicetree/bindings/spi/renesas,sh-msiof.yaml +++ b/Documentation/devicetree/bindings/spi/renesas,sh-msiof.yaml @@ -4,14 +4,11 @@ $id: http://devicetree.org/schemas/spi/renesas,sh-msiof.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Renesas MSIOF SPI controller +title: Renesas MSIOF SPI / I2S controller maintainers: - Geert Uytterhoeven <geert+renesas@glider.be> -allOf: - - $ref: spi-controller.yaml# - properties: compatible: oneOf: @@ -146,24 +143,38 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32 default: 64 + # for MSIOF-I2S + port: + $ref: ../sound/audio-graph-port.yaml# + unevaluatedProperties: false + required: - compatible - reg - interrupts - clocks - power-domains - - '#address-cells' - - '#size-cells' - -if: - not: - properties: - compatible: - contains: - const: renesas,sh-mobile-msiof -then: - required: - - resets + +allOf: + # additional "required"" + - if: + not: + properties: + compatible: + contains: + const: renesas,sh-mobile-msiof + then: + required: + - resets + + # If it doesn't have "port" node, it is "MSIOF-SPI" + - if: + not: + required: + - port + then: + allOf: + - $ref: spi-controller.yaml# unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/spi/samsung,spi.yaml b/Documentation/devicetree/bindings/spi/samsung,spi.yaml index 3c206a64d60a..fe298d47b1a9 100644 --- a/Documentation/devicetree/bindings/spi/samsung,spi.yaml +++ b/Documentation/devicetree/bindings/spi/samsung,spi.yaml @@ -29,6 +29,7 @@ properties: - items: - enum: - samsung,exynos8895-spi + - samsung,exynosautov920-spi - const: samsung,exynos850-spi - const: samsung,exynos7-spi deprecated: true diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml index bccd00a1ddd0..0543c526b783 100644 --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml @@ -56,19 +56,18 @@ properties: enum: - snps,dw-apb-ssi - snps,dwc-ssi-1.01a - - description: Microsemi Ocelot/Jaguar2 SoC SPI Controller - items: - - enum: - - mscc,ocelot-spi - - mscc,jaguar2-spi - - const: snps,dw-apb-ssi - description: Microchip Sparx5 SoC SPI Controller const: microchip,sparx5-spi - description: Amazon Alpine SPI Controller const: amazon,alpine-dw-apb-ssi - - description: Renesas RZ/N1 SPI Controller + - description: Vendor controllers which use snps,dw-apb-ssi as fallback items: - - const: renesas,rzn1-spi + - enum: + - mscc,ocelot-spi + - mscc,jaguar2-spi + - renesas,rzn1-spi + - sophgo,sg2042-spi + - thead,th1520-spi - const: snps,dw-apb-ssi - description: Intel Keem Bay SPI Controller const: intel,keembay-ssi @@ -84,14 +83,8 @@ properties: const: canaan,k210-spi - description: Renesas RZ/N1 SPI Controller items: - - enum: - - renesas,r9a06g032-spi # RZ/N1D - - renesas,r9a06g033-spi # RZ/N1S + - const: renesas,r9a06g032-spi # RZ/N1D - const: renesas,rzn1-spi # RZ/N1 - - description: T-HEAD TH1520 SoC SPI Controller - items: - - const: thead,th1520-spi - - const: snps,dw-apb-ssi reg: minItems: 1 diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.yaml b/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.yaml index ed1d4aa41b8c..a65a42ccaafe 100644 --- a/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.yaml +++ b/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.yaml @@ -24,6 +24,7 @@ properties: - enum: - fsl,imx8ulp-spi - fsl,imx93-spi + - fsl,imx94-spi - fsl,imx95-spi - const: fsl,imx7ulp-spi reg: diff --git a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml index 0bb443b8decd..8fc17e16efb2 100644 --- a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml +++ b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml @@ -8,12 +8,13 @@ title: Peripheral-specific properties for a SPI bus. description: Many SPI controllers need to add properties to peripheral devices. They could - be common properties like spi-max-frequency, spi-cpha, etc. or they could be - controller specific like delay in clock or data lines, etc. These properties - need to be defined in the peripheral node because they are per-peripheral and - there can be multiple peripherals attached to a controller. All those - properties are listed here. The controller specific properties should go in - their own separate schema that should be referenced from here. + be common properties like spi-max-frequency, spi-cs-high, etc. or they could + be controller specific like delay in clock or data lines, etc. These + properties need to be defined in the peripheral node because they are + per-peripheral and there can be multiple peripherals attached to a + controller. All those properties are listed here. The controller specific + properties should go in their own separate schema that should be referenced + from here. maintainers: - Mark Brown <broonie@kernel.org> diff --git a/Documentation/devicetree/bindings/spi/spi-rockchip.yaml b/Documentation/devicetree/bindings/spi/spi-rockchip.yaml index 46d9d6ee0923..748faf7f7081 100644 --- a/Documentation/devicetree/bindings/spi/spi-rockchip.yaml +++ b/Documentation/devicetree/bindings/spi/spi-rockchip.yaml @@ -34,6 +34,8 @@ properties: - rockchip,rk3328-spi - rockchip,rk3368-spi - rockchip,rk3399-spi + - rockchip,rk3528-spi + - rockchip,rk3562-spi - rockchip,rk3568-spi - rockchip,rk3576-spi - rockchip,rk3588-spi diff --git a/Documentation/devicetree/bindings/spi/spi-sg2044-nor.yaml b/Documentation/devicetree/bindings/spi/spi-sg2044-nor.yaml new file mode 100644 index 000000000000..66e54dedab14 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/spi-sg2044-nor.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/spi-sg2044-nor.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SG2044 SPI NOR controller + +maintainers: + - Longbin Li <looong.bin@gmail.com> + +allOf: + - $ref: spi-controller.yaml# + +properties: + compatible: + oneOf: + - const: sophgo,sg2044-spifmc-nor + - items: + - enum: + - sophgo,sg2042-spifmc-nor + - const: sophgo,sg2044-spifmc-nor + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + interrupts: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - interrupts + - resets + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + spi@1000000 { + compatible = "sophgo,sg2044-spifmc-nor"; + reg = <0x1000000 0x4000000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk 0>; + interrupts = <37 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rst 0>; + }; diff --git a/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml b/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml index 04d4d3b4916d..02cf1314367b 100644 --- a/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml +++ b/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml @@ -65,14 +65,13 @@ allOf: examples: - | - #include <dt-bindings/clock/xlnx-zynqmp-clk.h> soc { #address-cells = <2>; #size-cells = <2>; qspi: spi@ff0f0000 { compatible = "xlnx,zynqmp-qspi-1.0"; - clocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>; + clocks = <&zynqmp_clk 53>, <&zynqmp_clk 82>; clock-names = "ref_clk", "pclk"; interrupts = <0 15 4>; interrupt-parent = <&gic>; diff --git a/Documentation/devicetree/bindings/spi/st,stm32mp25-ospi.yaml b/Documentation/devicetree/bindings/spi/st,stm32mp25-ospi.yaml new file mode 100644 index 000000000000..272bc308726b --- /dev/null +++ b/Documentation/devicetree/bindings/spi/st,stm32mp25-ospi.yaml @@ -0,0 +1,106 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/st,stm32mp25-ospi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32 Octal Serial Peripheral Interface (OSPI) + +maintainers: + - Patrice Chotard <patrice.chotard@foss.st.com> + +allOf: + - $ref: spi-controller.yaml# + +properties: + compatible: + const: st,stm32mp25-ospi + + reg: + maxItems: 1 + + memory-region: + description: + Memory region to be used for memory-map read access. + In memory-mapped mode, read access are performed from the memory + device using the direct mapping. + maxItems: 1 + + clocks: + maxItems: 1 + + interrupts: + maxItems: 1 + + resets: + items: + - description: phandle to OSPI block reset + - description: phandle to delay block reset + + dmas: + maxItems: 2 + + dma-names: + items: + - const: tx + - const: rx + + st,syscfg-dlyb: + description: configure OCTOSPI delay block. + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - description: phandle to syscfg + - description: register offset within syscfg + + access-controllers: + description: phandle to the rifsc device to check access right + and in some cases, an additional phandle to the rcc device for + secure clock control. + items: + - description: phandle to bus controller + - description: phandle to clock controller + minItems: 1 + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - resets + - interrupts + - st,syscfg-dlyb + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/st,stm32mp25-rcc.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/reset/st,stm32mp25-rcc.h> + + spi@40430000 { + compatible = "st,stm32mp25-ospi"; + reg = <0x40430000 0x400>; + memory-region = <&mm_ospi1>; + interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&hpdma 2 0x62 0x00003121 0x0>, + <&hpdma 2 0x42 0x00003112 0x0>; + dma-names = "tx", "rx"; + clocks = <&scmi_clk CK_SCMI_OSPI1>; + resets = <&scmi_reset RST_SCMI_OSPI1>, <&scmi_reset RST_SCMI_OSPI1DLL>; + access-controllers = <&rifsc 74>; + power-domains = <&CLUSTER_PD>; + st,syscfg-dlyb = <&syscfg 0x1000>; + + #address-cells = <1>; + #size-cells = <0>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-rx-bus-width = <4>; + spi-max-frequency = <108000000>; + }; + }; diff --git a/Documentation/devicetree/bindings/spmi/apple,spmi.yaml b/Documentation/devicetree/bindings/spmi/apple,spmi.yaml new file mode 100644 index 000000000000..16bd7eb2b7af --- /dev/null +++ b/Documentation/devicetree/bindings/spmi/apple,spmi.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spmi/apple,spmi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Apple SPMI controller + +maintainers: + - Sasha Finkelstein <fnkl.kernel@gmail.com> + +description: A SPMI controller present on most Apple SoCs + +allOf: + - $ref: spmi.yaml# + +properties: + compatible: + items: + - enum: + - apple,t8103-spmi + - apple,t6000-spmi + - apple,t8112-spmi + - const: apple,spmi + + reg: + maxItems: 1 + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/spmi/spmi.h> + + spmi@920a1300 { + compatible = "apple,t6000-spmi", "apple,spmi"; + reg = <0x920a1300 0x100>; + #address-cells = <2>; + #size-cells = <0>; + + pmic@f { + reg = <0xf SPMI_USID>; + /* PMIC-specific properties */ + }; + }; diff --git a/Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml b/Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml index a7236f7db4ec..e7f7cf72719e 100644 --- a/Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml +++ b/Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml @@ -50,6 +50,7 @@ properties: - enum: - allwinner,sun50i-a100-system-control - allwinner,sun50i-h6-system-control + - allwinner,sun55i-a523-system-control - const: allwinner,sun50i-a64-system-control reg: diff --git a/Documentation/devicetree/bindings/submitting-patches.rst b/Documentation/devicetree/bindings/submitting-patches.rst index a64f21a5f299..f3e23e69a638 100644 --- a/Documentation/devicetree/bindings/submitting-patches.rst +++ b/Documentation/devicetree/bindings/submitting-patches.rst @@ -54,11 +54,22 @@ I. For patch submitters followed as of commit bff5da4335256513497cc8c79f9a9d1665e09864 ("checkpatch: add DT compatible string documentation checks"). ] - 7) If a documented compatible string is not yet matched by the + 7) DTS is treated in general as driver-independent hardware description, thus + any DTS patches, regardless whether using existing or new bindings, should + be placed at the end of patchset to indicate no dependency of drivers on + the DTS. DTS will be anyway applied through separate tree or branch, so + different order would indicate the serie is non-bisectable. + + If a driver subsystem maintainer prefers to apply entire set, instead of + their relevant portion of patchset, please split the DTS patches into + separate patchset with a reference in changelog or cover letter to the + bindings submission on the mailing list. + + 8) If a documented compatible string is not yet matched by the driver, the documentation should also include a compatible string that is matched by the driver. - 8) Bindings are actively used by multiple projects other than the Linux + 9) Bindings are actively used by multiple projects other than the Linux Kernel, extra care and consideration may need to be taken when making changes to existing bindings. @@ -79,6 +90,10 @@ II. For kernel maintainers 3) For a series going though multiple trees, the binding patch should be kept with the driver using the binding. + 4) The DTS files should however never be applied via driver subsystem tree, + but always via platform SoC trees on dedicated branches (see also + Documentation/process/maintainer-soc.rst). + III. Notes ========== diff --git a/Documentation/devicetree/bindings/thermal/airoha,en7581-thermal.yaml b/Documentation/devicetree/bindings/thermal/airoha,en7581-thermal.yaml new file mode 100644 index 000000000000..ca0242ef0378 --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/airoha,en7581-thermal.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/airoha,en7581-thermal.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Airoha EN7581 Thermal Sensor and Monitor + +maintainers: + - Christian Marangi <ansuelsmth@gmail.com> + +properties: + compatible: + const: airoha,en7581-thermal + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + airoha,chip-scu: + description: phandle to the chip SCU syscon + $ref: /schemas/types.yaml#/definitions/phandle + + '#thermal-sensor-cells': + const: 0 + +required: + - compatible + - reg + - interrupts + - airoha,chip-scu + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + thermal-sensor@1efbd800 { + compatible = "airoha,en7581-thermal"; + reg = <0x1efbd000 0xd5c>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + airoha,chip-scu = <&chip_scu>; + + #thermal-sensor-cells = <0>; + }; diff --git a/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml b/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml index dad8de900495..3e61689f6dd4 100644 --- a/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml +++ b/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml @@ -142,38 +142,38 @@ unevaluatedProperties: false examples: - | thermal-sensor@1f04000 { - compatible = "allwinner,sun8i-a83t-ths"; - reg = <0x01f04000 0x100>; - interrupts = <0 31 0>; - nvmem-cells = <&ths_calibration>; - nvmem-cell-names = "calibration"; - #thermal-sensor-cells = <1>; + compatible = "allwinner,sun8i-a83t-ths"; + reg = <0x01f04000 0x100>; + interrupts = <0 31 0>; + nvmem-cells = <&ths_calibration>; + nvmem-cell-names = "calibration"; + #thermal-sensor-cells = <1>; }; - | thermal-sensor@1c25000 { - compatible = "allwinner,sun8i-h3-ths"; - reg = <0x01c25000 0x400>; - clocks = <&ccu 0>, <&ccu 1>; - clock-names = "bus", "mod"; - resets = <&ccu 2>; - interrupts = <0 31 0>; - nvmem-cells = <&ths_calibration>; - nvmem-cell-names = "calibration"; - #thermal-sensor-cells = <0>; + compatible = "allwinner,sun8i-h3-ths"; + reg = <0x01c25000 0x400>; + clocks = <&ccu 0>, <&ccu 1>; + clock-names = "bus", "mod"; + resets = <&ccu 2>; + interrupts = <0 31 0>; + nvmem-cells = <&ths_calibration>; + nvmem-cell-names = "calibration"; + #thermal-sensor-cells = <0>; }; - | thermal-sensor@5070400 { - compatible = "allwinner,sun50i-h6-ths"; - reg = <0x05070400 0x100>; - clocks = <&ccu 0>; - clock-names = "bus"; - resets = <&ccu 2>; - interrupts = <0 15 0>; - nvmem-cells = <&ths_calibration>; - nvmem-cell-names = "calibration"; - #thermal-sensor-cells = <1>; + compatible = "allwinner,sun50i-h6-ths"; + reg = <0x05070400 0x100>; + clocks = <&ccu 0>; + clock-names = "bus"; + resets = <&ccu 2>; + interrupts = <0 15 0>; + nvmem-cells = <&ths_calibration>; + nvmem-cell-names = "calibration"; + #thermal-sensor-cells = <1>; }; ... diff --git a/Documentation/devicetree/bindings/thermal/brcm,avs-tmon.yaml b/Documentation/devicetree/bindings/thermal/brcm,avs-tmon.yaml index 081486b44382..2f62551a49c1 100644 --- a/Documentation/devicetree/bindings/thermal/brcm,avs-tmon.yaml +++ b/Documentation/devicetree/bindings/thermal/brcm,avs-tmon.yaml @@ -18,6 +18,7 @@ properties: compatible: items: - enum: + - brcm,avs-tmon-bcm74110 - brcm,avs-tmon-bcm7216 - brcm,avs-tmon-bcm7445 - const: brcm,avs-tmon diff --git a/Documentation/devicetree/bindings/thermal/imx-thermal.yaml b/Documentation/devicetree/bindings/thermal/imx-thermal.yaml index 337560562337..949b154856c5 100644 --- a/Documentation/devicetree/bindings/thermal/imx-thermal.yaml +++ b/Documentation/devicetree/bindings/thermal/imx-thermal.yaml @@ -80,19 +80,19 @@ examples: #include <dt-bindings/interrupt-controller/arm-gic.h> efuse@21bc000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,imx6sx-ocotp", "syscon"; - reg = <0x021bc000 0x4000>; - clocks = <&clks IMX6SX_CLK_OCOTP>; - - tempmon_calib: calib@38 { - reg = <0x38 4>; - }; - - tempmon_temp_grade: temp-grade@20 { - reg = <0x20 4>; - }; + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,imx6sx-ocotp", "syscon"; + reg = <0x021bc000 0x4000>; + clocks = <&clks IMX6SX_CLK_OCOTP>; + + tempmon_calib: calib@38 { + reg = <0x38 4>; + }; + + tempmon_temp_grade: temp-grade@20 { + reg = <0x20 4>; + }; }; anatop@20c8000 { @@ -103,12 +103,12 @@ examples: <0 127 IRQ_TYPE_LEVEL_HIGH>; tempmon { - compatible = "fsl,imx6sx-tempmon"; - interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; - fsl,tempmon = <&anatop>; - nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; - nvmem-cell-names = "calib", "temp_grade"; - clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>; - #thermal-sensor-cells = <0>; + compatible = "fsl,imx6sx-tempmon"; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + fsl,tempmon = <&anatop>; + nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; + nvmem-cell-names = "calib", "temp_grade"; + clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>; + #thermal-sensor-cells = <0>; }; }; diff --git a/Documentation/devicetree/bindings/thermal/imx8mm-thermal.yaml b/Documentation/devicetree/bindings/thermal/imx8mm-thermal.yaml index bef0e95e7416..df6c7c5d519f 100644 --- a/Documentation/devicetree/bindings/thermal/imx8mm-thermal.yaml +++ b/Documentation/devicetree/bindings/thermal/imx8mm-thermal.yaml @@ -63,10 +63,10 @@ examples: #include <dt-bindings/clock/imx8mm-clock.h> thermal-sensor@30260000 { - compatible = "fsl,imx8mm-tmu"; - reg = <0x30260000 0x10000>; - clocks = <&clk IMX8MM_CLK_TMU_ROOT>; - #thermal-sensor-cells = <0>; + compatible = "fsl,imx8mm-tmu"; + reg = <0x30260000 0x10000>; + clocks = <&clk IMX8MM_CLK_TMU_ROOT>; + #thermal-sensor-cells = <0>; }; ... diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml index b9829bb22cc0..0e653bbe9884 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml @@ -39,6 +39,7 @@ properties: - description: v1 of TSENS items: - enum: + - qcom,ipq5018-tsens - qcom,msm8937-tsens - qcom,msm8956-tsens - qcom,msm8976-tsens @@ -75,6 +76,8 @@ properties: - description: v2 of TSENS with combined interrupt enum: + - qcom,ipq5332-tsens + - qcom,ipq5424-tsens - qcom,ipq8074-tsens - description: v2 of TSENS with combined interrupt @@ -212,6 +215,18 @@ properties: - const: s9_p2_backup - const: s10_p1_backup - const: s10_p2_backup + - minItems: 8 + items: + - const: mode + - const: base0 + - const: base1 + - pattern: '^tsens_sens[0-9]+_off$' + - pattern: '^tsens_sens[0-9]+_off$' + - pattern: '^tsens_sens[0-9]+_off$' + - pattern: '^tsens_sens[0-9]+_off$' + - pattern: '^tsens_sens[0-9]+_off$' + - pattern: '^tsens_sens[0-9]+_off$' + - pattern: '^tsens_sens[0-9]+_off$' "#qcom,sensors": description: @@ -237,6 +252,7 @@ allOf: compatible: contains: enum: + - qcom,ipq5018-tsens - qcom,ipq8064-tsens - qcom,msm8960-tsens - qcom,tsens-v0_1 @@ -271,6 +287,8 @@ allOf: compatible: contains: enum: + - qcom,ipq5332-tsens + - qcom,ipq5424-tsens - qcom,ipq8074-tsens then: properties: @@ -286,6 +304,8 @@ allOf: compatible: contains: enum: + - qcom,ipq5332-tsens + - qcom,ipq5424-tsens - qcom,ipq8074-tsens - qcom,tsens-v0_1 - qcom,tsens-v1 diff --git a/Documentation/devicetree/bindings/thermal/thermal-zones.yaml b/Documentation/devicetree/bindings/thermal/thermal-zones.yaml index 0f435be1dbd8..0de0a9757ccc 100644 --- a/Documentation/devicetree/bindings/thermal/thermal-zones.yaml +++ b/Documentation/devicetree/bindings/thermal/thermal-zones.yaml @@ -82,9 +82,8 @@ patternProperties: $ref: /schemas/types.yaml#/definitions/string description: | The action the OS should perform after the critical temperature is reached. - By default the system will shutdown as a safe action to prevent damage - to the hardware, if the property is not set. - The shutdown action should be always the default and preferred one. + If the property is not set, it is up to the system to select the correct + action. The recommended and preferred default is shutdown. Choose 'reboot' with care, as the hardware may be in thermal stress, thus leading to infinite reboots that may cause damage to the hardware. Make sure the firmware/bootloader will act as the last resort and take diff --git a/Documentation/devicetree/bindings/timer/altr,timer-1.0.txt b/Documentation/devicetree/bindings/timer/altr,timer-1.0.txt deleted file mode 100644 index e698e3488735..000000000000 --- a/Documentation/devicetree/bindings/timer/altr,timer-1.0.txt +++ /dev/null @@ -1,18 +0,0 @@ -Altera Timer - -Required properties: - -- compatible : should be "altr,timer-1.0" -- reg : Specifies base physical address and size of the registers. -- interrupts : Should contain the timer interrupt number -- clock-frequency : The frequency of the clock that drives the counter, in Hz. - -Example: - -timer { - compatible = "altr,timer-1.0"; - reg = <0x00400000 0x00000020>; - interrupt-parent = <&cpu>; - interrupts = <11>; - clock-frequency = <125000000>; -}; diff --git a/Documentation/devicetree/bindings/timer/altr,timer-1.0.yaml b/Documentation/devicetree/bindings/timer/altr,timer-1.0.yaml new file mode 100644 index 000000000000..576260c72d42 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/altr,timer-1.0.yaml @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/altr,timer-1.0.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Altera Timer + +maintainers: + - Dinh Nguyen <dinguyen@kernel.org> + +properties: + compatible: + const: altr,timer-1.0 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clock-frequency: + description: Frequency of the clock that drives the counter, in Hz. + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + timer@400000 { + compatible = "altr,timer-1.0"; + reg = <0x00400000 0x00000020>; + interrupts = <11>; + clock-frequency = <125000000>; + }; diff --git a/Documentation/devicetree/bindings/timer/arm,mps2-timer.txt b/Documentation/devicetree/bindings/timer/arm,mps2-timer.txt deleted file mode 100644 index 48f84d74edde..000000000000 --- a/Documentation/devicetree/bindings/timer/arm,mps2-timer.txt +++ /dev/null @@ -1,28 +0,0 @@ -ARM MPS2 timer - -The MPS2 platform has simple general-purpose 32 bits timers. - -Required properties: -- compatible : Should be "arm,mps2-timer" -- reg : Address and length of the register set -- interrupts : Reference to the timer interrupt - -Required clocking property, have to be one of: -- clocks : The input clock of the timer -- clock-frequency : The rate in HZ in input of the ARM MPS2 timer - -Examples: - -timer1: mps2-timer@40000000 { - compatible = "arm,mps2-timer"; - reg = <0x40000000 0x1000>; - interrupts = <8>; - clocks = <&sysclk>; -}; - -timer2: mps2-timer@40001000 { - compatible = "arm,mps2-timer"; - reg = <0x40001000 0x1000>; - interrupts = <9>; - clock-frequency = <25000000>; -}; diff --git a/Documentation/devicetree/bindings/timer/arm,mps2-timer.yaml b/Documentation/devicetree/bindings/timer/arm,mps2-timer.yaml new file mode 100644 index 000000000000..64c6aedd7e8e --- /dev/null +++ b/Documentation/devicetree/bindings/timer/arm,mps2-timer.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm,mps2-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM MPS2 timer + +maintainers: + - Vladimir Murzin <vladimir.murzin@arm.com> + +description: + The MPS2 platform has simple general-purpose 32 bits timers. + +properties: + compatible: + const: arm,mps2-timer + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-frequency: + description: Rate in Hz of the timer input clock + +oneOf: + - required: [clocks] + - required: [clock-frequency] + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + timer@40000000 { + compatible = "arm,mps2-timer"; + reg = <0x40000000 0x1000>; + interrupts = <8>; + clocks = <&sysclk>; + }; diff --git a/Documentation/devicetree/bindings/timer/arm,twd-timer.yaml b/Documentation/devicetree/bindings/timer/arm,twd-timer.yaml index 5684df6448ef..eb1127352c7b 100644 --- a/Documentation/devicetree/bindings/timer/arm,twd-timer.yaml +++ b/Documentation/devicetree/bindings/timer/arm,twd-timer.yaml @@ -50,7 +50,7 @@ examples: #include <dt-bindings/interrupt-controller/arm-gic.h> timer@2c000600 { - compatible = "arm,arm11mp-twd-timer"; - reg = <0x2c000600 0x20>; - interrupts = <GIC_PPI 13 0xf01>; + compatible = "arm,arm11mp-twd-timer"; + reg = <0x2c000600 0x20>; + interrupts = <GIC_PPI 13 0xf01>; }; diff --git a/Documentation/devicetree/bindings/timer/cirrus,clps711x-timer.txt b/Documentation/devicetree/bindings/timer/cirrus,clps711x-timer.txt deleted file mode 100644 index d4c62e7b1714..000000000000 --- a/Documentation/devicetree/bindings/timer/cirrus,clps711x-timer.txt +++ /dev/null @@ -1,29 +0,0 @@ -* Cirrus Logic CLPS711X Timer Counter - -Required properties: -- compatible: Shall contain "cirrus,ep7209-timer". -- reg : Address and length of the register set. -- interrupts: The interrupt number of the timer. -- clocks : phandle of timer reference clock. - -Note: Each timer should have an alias correctly numbered in "aliases" node. - -Example: - aliases { - timer0 = &timer1; - timer1 = &timer2; - }; - - timer1: timer@80000300 { - compatible = "cirrus,ep7312-timer", "cirrus,ep7209-timer"; - reg = <0x80000300 0x4>; - interrupts = <8>; - clocks = <&clks 5>; - }; - - timer2: timer@80000340 { - compatible = "cirrus,ep7312-timer", "cirrus,ep7209-timer"; - reg = <0x80000340 0x4>; - interrupts = <9>; - clocks = <&clks 6>; - }; diff --git a/Documentation/devicetree/bindings/timer/cirrus,clps711x-timer.yaml b/Documentation/devicetree/bindings/timer/cirrus,clps711x-timer.yaml new file mode 100644 index 000000000000..507b777e16bc --- /dev/null +++ b/Documentation/devicetree/bindings/timer/cirrus,clps711x-timer.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/cirrus,clps711x-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cirrus Logic CLPS711X Timer Counter + +maintainers: + - Alexander Shiyan <shc_work@mail.ru> + +properties: + compatible: + oneOf: + - items: + - enum: + - cirrus,ep7312-timer + - const: cirrus,ep7209-timer + - const: cirrus,ep7209-timer + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - interrupts + +additionalProperties: false + +examples: + - | + timer@80000300 { + compatible = "cirrus,ep7312-timer", "cirrus,ep7209-timer"; + reg = <0x80000300 0x4>; + interrupts = <8>; + clocks = <&clks 5>; + }; diff --git a/Documentation/devicetree/bindings/timer/cnxt,cx92755-timer.yaml b/Documentation/devicetree/bindings/timer/cnxt,cx92755-timer.yaml new file mode 100644 index 000000000000..8f1a5af32a36 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/cnxt,cx92755-timer.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/cnxt,cx92755-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Conexant Digicolor SoCs Timer Controller + +maintainers: + - Baruch Siach <baruch@tkos.co.il> + +properties: + compatible: + const: cnxt,cx92755-timer + + reg: + maxItems: 1 + + interrupts: + description: Contains 8 interrupts, one for each timer + items: + - description: interrupt for timer 0 + - description: interrupt for timer 1 + - description: interrupt for timer 2 + - description: interrupt for timer 3 + - description: interrupt for timer 4 + - description: interrupt for timer 5 + - description: interrupt for timer 6 + - description: interrupt for timer 7 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + timer@f0000fc0 { + compatible = "cnxt,cx92755-timer"; + reg = <0xf0000fc0 0x40>; + interrupts = <19>, <31>, <34>, <35>, <52>, <53>, <54>, <55>; + clocks = <&main_clk>; + }; diff --git a/Documentation/devicetree/bindings/timer/csky,gx6605s-timer.txt b/Documentation/devicetree/bindings/timer/csky,gx6605s-timer.txt deleted file mode 100644 index 6b04344f4bea..000000000000 --- a/Documentation/devicetree/bindings/timer/csky,gx6605s-timer.txt +++ /dev/null @@ -1,42 +0,0 @@ -================= -gx6605s SOC Timer -================= - -The timer is used in gx6605s soc as system timer and the driver -contain clk event and clk source. - -============================== -timer node bindings definition -============================== - - Description: Describes gx6605s SOC timer - - PROPERTIES - - - compatible - Usage: required - Value type: <string> - Definition: must be "csky,gx6605s-timer" - - reg - Usage: required - Value type: <u32 u32> - Definition: <phyaddr size> in soc from cpu view - - clocks - Usage: required - Value type: phandle + clock specifier cells - Definition: must be input clk node - - interrupt - Usage: required - Value type: <u32> - Definition: must be timer irq num defined by soc - -Examples: ---------- - - timer0: timer@20a000 { - compatible = "csky,gx6605s-timer"; - reg = <0x0020a000 0x400>; - clocks = <&dummy_apb_clk>; - interrupts = <10>; - interrupt-parent = <&intc>; - }; diff --git a/Documentation/devicetree/bindings/timer/csky,gx6605s-timer.yaml b/Documentation/devicetree/bindings/timer/csky,gx6605s-timer.yaml new file mode 100644 index 000000000000..888fc8113996 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/csky,gx6605s-timer.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/csky,gx6605s-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: gx6605s SOC Timer + +maintainers: + - Guo Ren <guoren@kernel.org> + +properties: + compatible: + const: csky,gx6605s-timer + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - interrupts + +additionalProperties: false + +examples: + - | + timer@20a000 { + compatible = "csky,gx6605s-timer"; + reg = <0x0020a000 0x400>; + clocks = <&dummy_apb_clk>; + interrupts = <10>; + }; diff --git a/Documentation/devicetree/bindings/timer/csky,mptimer.txt b/Documentation/devicetree/bindings/timer/csky,mptimer.txt deleted file mode 100644 index f5c7e99cf52b..000000000000 --- a/Documentation/devicetree/bindings/timer/csky,mptimer.txt +++ /dev/null @@ -1,42 +0,0 @@ -============================ -C-SKY Multi-processors Timer -============================ - -C-SKY multi-processors timer is designed for C-SKY SMP system and the -regs is accessed by cpu co-processor 4 registers with mtcr/mfcr. - - - PTIM_CTLR "cr<0, 14>" Control reg to start reset timer. - - PTIM_TSR "cr<1, 14>" Interrupt cleanup status reg. - - PTIM_CCVR "cr<3, 14>" Current counter value reg. - - PTIM_LVR "cr<6, 14>" Window value reg to trigger next event. - -============================== -timer node bindings definition -============================== - - Description: Describes SMP timer - - PROPERTIES - - - compatible - Usage: required - Value type: <string> - Definition: must be "csky,mptimer" - - clocks - Usage: required - Value type: <node> - Definition: must be input clk node - - interrupts - Usage: required - Value type: <u32> - Definition: must be timer irq num defined by soc - -Examples: ---------- - - timer: timer { - compatible = "csky,mptimer"; - clocks = <&dummy_apb_clk>; - interrupts = <16>; - interrupt-parent = <&intc>; - }; diff --git a/Documentation/devicetree/bindings/timer/csky,mptimer.yaml b/Documentation/devicetree/bindings/timer/csky,mptimer.yaml new file mode 100644 index 000000000000..12cc5282c8f8 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/csky,mptimer.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/csky,mptimer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: C-SKY Multi-processors Timer + +maintainers: + - Flavio Suligoi <f.suligoi@asem.it> + - Guo Ren <guoren@kernel.org> + +description: | + C-SKY multi-processors timer is designed for C-SKY SMP system and the regs are + accessed by cpu co-processor 4 registers with mtcr/mfcr. + + - PTIM_CTLR "cr<0, 14>" Control reg to start reset timer. + - PTIM_TSR "cr<1, 14>" Interrupt cleanup status reg. + - PTIM_CCVR "cr<3, 14>" Current counter value reg. + - PTIM_LVR "cr<6, 14>" Window value reg to trigger next event. + +properties: + compatible: + items: + - const: csky,mptimer + + clocks: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - clocks + - interrupts + +additionalProperties: false + +examples: + - | + timer { + compatible = "csky,mptimer"; + clocks = <&dummy_apb_clk>; + interrupts = <16>; + }; diff --git a/Documentation/devicetree/bindings/timer/digicolor-timer.txt b/Documentation/devicetree/bindings/timer/digicolor-timer.txt deleted file mode 100644 index d1b659bbc29f..000000000000 --- a/Documentation/devicetree/bindings/timer/digicolor-timer.txt +++ /dev/null @@ -1,18 +0,0 @@ -Conexant Digicolor SoCs Timer Controller - -Required properties: - -- compatible : should be "cnxt,cx92755-timer" -- reg : Specifies base physical address and size of the "Agent Communication" - timer registers -- interrupts : Contains 8 interrupts, one for each timer -- clocks: phandle to the main clock - -Example: - - timer@f0000fc0 { - compatible = "cnxt,cx92755-timer"; - reg = <0xf0000fc0 0x40>; - interrupts = <19>, <31>, <34>, <35>, <52>, <53>, <54>, <55>; - clocks = <&main_clk>; - }; diff --git a/Documentation/devicetree/bindings/timer/econet,en751221-timer.yaml b/Documentation/devicetree/bindings/timer/econet,en751221-timer.yaml new file mode 100644 index 000000000000..c1e7c2b6afde --- /dev/null +++ b/Documentation/devicetree/bindings/timer/econet,en751221-timer.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/econet,en751221-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: EcoNet EN751221 High Precision Timer (HPT) + +maintainers: + - Caleb James DeLisle <cjd@cjdns.fr> + +description: + The EcoNet High Precision Timer (HPT) is a timer peripheral found in various + EcoNet SoCs, including the EN751221 and EN751627 families. It provides per-VPE + count/compare registers and a per-CPU control register, with a single interrupt + line using a percpu-devid interrupt mechanism. + +properties: + compatible: + oneOf: + - const: econet,en751221-timer + - items: + - const: econet,en751627-timer + - const: econet,en751221-timer + + reg: + minItems: 1 + maxItems: 2 + + interrupts: + maxItems: 1 + description: A percpu-devid timer interrupt shared across CPUs. + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +allOf: + - if: + properties: + compatible: + contains: + const: econet,en751627-timer + then: + properties: + reg: + items: + - description: VPE timers 0 and 1 + - description: VPE timers 2 and 3 + else: + properties: + reg: + items: + - description: VPE timers 0 and 1 + +additionalProperties: false + +examples: + - | + timer@1fbf0400 { + compatible = "econet,en751627-timer", "econet,en751221-timer"; + reg = <0x1fbf0400 0x100>, <0x1fbe0000 0x100>; + interrupt-parent = <&intc>; + interrupts = <30>; + clocks = <&hpt_clock>; + }; + - | + timer@1fbf0400 { + compatible = "econet,en751221-timer"; + reg = <0x1fbe0400 0x100>; + interrupt-parent = <&intc>; + interrupts = <30>; + clocks = <&hpt_clock>; + }; +... diff --git a/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.yaml b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.yaml new file mode 100644 index 000000000000..317c5010c4c1 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ezchip,nps400-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: EZChip NPS400 Timers + +maintainers: + - Noam Camus <noamca@mellanox.com> + +properties: + compatible: + enum: + - ezchip,nps400-timer0 + - ezchip,nps400-timer1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - clocks + +additionalProperties: false + +allOf: + - if: + properties: + compatible: + contains: + const: ezchip,nps400-timer0 + then: + required: [ interrupts ] + +examples: + - | + timer { + compatible = "ezchip,nps400-timer0"; + interrupts = <3>; + clocks = <&sysclk>; + }; diff --git a/Documentation/devicetree/bindings/timer/ezchip,nps400-timer0.txt b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer0.txt deleted file mode 100644 index e3cfce8fecc5..000000000000 --- a/Documentation/devicetree/bindings/timer/ezchip,nps400-timer0.txt +++ /dev/null @@ -1,17 +0,0 @@ -NPS Network Processor - -Required properties: - -- compatible : should be "ezchip,nps400-timer0" - -Clocks required for compatible = "ezchip,nps400-timer0": -- interrupts : The interrupt of the first timer -- clocks : Must contain a single entry describing the clock input - -Example: - -timer { - compatible = "ezchip,nps400-timer0"; - interrupts = <3>; - clocks = <&sysclk>; -}; diff --git a/Documentation/devicetree/bindings/timer/ezchip,nps400-timer1.txt b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer1.txt deleted file mode 100644 index c0ab4190b8fb..000000000000 --- a/Documentation/devicetree/bindings/timer/ezchip,nps400-timer1.txt +++ /dev/null @@ -1,15 +0,0 @@ -NPS Network Processor - -Required properties: - -- compatible : should be "ezchip,nps400-timer1" - -Clocks required for compatible = "ezchip,nps400-timer1": -- clocks : Must contain a single entry describing the clock input - -Example: - -timer { - compatible = "ezchip,nps400-timer1"; - clocks = <&sysclk>; -}; diff --git a/Documentation/devicetree/bindings/timer/fsl,gtm.txt b/Documentation/devicetree/bindings/timer/fsl,gtm.txt deleted file mode 100644 index fc1c571f7412..000000000000 --- a/Documentation/devicetree/bindings/timer/fsl,gtm.txt +++ /dev/null @@ -1,30 +0,0 @@ -* Freescale General-purpose Timers Module - -Required properties: - - compatible : should be - "fsl,<chip>-gtm", "fsl,gtm" for SOC GTMs - "fsl,<chip>-qe-gtm", "fsl,qe-gtm", "fsl,gtm" for QE GTMs - "fsl,<chip>-cpm2-gtm", "fsl,cpm2-gtm", "fsl,gtm" for CPM2 GTMs - - reg : should contain gtm registers location and length (0x40). - - interrupts : should contain four interrupts. - - clock-frequency : specifies the frequency driving the timer. - -Example: - -timer@500 { - compatible = "fsl,mpc8360-gtm", "fsl,gtm"; - reg = <0x500 0x40>; - interrupts = <90 8 78 8 84 8 72 8>; - interrupt-parent = <&ipic>; - /* filled by u-boot */ - clock-frequency = <0>; -}; - -timer@440 { - compatible = "fsl,mpc8360-qe-gtm", "fsl,qe-gtm", "fsl,gtm"; - reg = <0x440 0x40>; - interrupts = <12 13 14 15>; - interrupt-parent = <&qeic>; - /* filled by u-boot */ - clock-frequency = <0>; -}; diff --git a/Documentation/devicetree/bindings/timer/fsl,gtm.yaml b/Documentation/devicetree/bindings/timer/fsl,gtm.yaml new file mode 100644 index 000000000000..1f35f1ee0be2 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/fsl,gtm.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/fsl,gtm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale General-purpose Timers Module + +maintainers: + - J. Neuschäfer <j.ne@posteo.net> + +properties: + compatible: + oneOf: + # for SoC GTMs + - items: + - enum: + - fsl,mpc8308-gtm + - fsl,mpc8313-gtm + - fsl,mpc8315-gtm + - fsl,mpc8360-gtm + - const: fsl,gtm + + # for QE GTMs + - items: + - enum: + - fsl,mpc8360-qe-gtm + - fsl,mpc8569-qe-gtm + - const: fsl,qe-gtm + - const: fsl,gtm + + # for CPM2 GTMs (no known examples) + - items: + # - enum: + # - fsl,<chip>-cpm2-gtm + - const: fsl,cpm2-gtm + - const: fsl,gtm + + reg: + maxItems: 1 + + interrupts: + items: + - description: Interrupt for timer 1 (e.g. GTM1 or GTM5) + - description: Interrupt for timer 2 (e.g. GTM2 or GTM6) + - description: Interrupt for timer 3 (e.g. GTM3 or GTM7) + - description: Interrupt for timer 4 (e.g. GTM4 or GTM8) + + clock-frequency: true + +required: + - compatible + - reg + - interrupts + - clock-frequency + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + timer@500 { + compatible = "fsl,mpc8360-gtm", "fsl,gtm"; + reg = <0x500 0x40>; + interrupts = <90 IRQ_TYPE_LEVEL_LOW>, + <78 IRQ_TYPE_LEVEL_LOW>, + <84 IRQ_TYPE_LEVEL_LOW>, + <72 IRQ_TYPE_LEVEL_LOW>; + /* filled by u-boot */ + clock-frequency = <0>; + }; + + - | + timer@440 { + compatible = "fsl,mpc8360-qe-gtm", "fsl,qe-gtm", "fsl,gtm"; + reg = <0x440 0x40>; + interrupts = <12>, <13>, <14>, <15>; + /* filled by u-boot */ + clock-frequency = <0>; + }; + +... diff --git a/Documentation/devicetree/bindings/timer/fsl,vf610-pit.yaml b/Documentation/devicetree/bindings/timer/fsl,vf610-pit.yaml new file mode 100644 index 000000000000..bee2c35bd0e2 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/fsl,vf610-pit.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/fsl,vf610-pit.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale Periodic Interrupt Timer (PIT) + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +description: + The PIT module is an array of timers that can be used to raise interrupts + and trigger DMA channels. + +properties: + compatible: + enum: + - fsl,vf610-pit + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: pit + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/vf610-clock.h> + #include <dt-bindings/interrupt-controller/irq.h> + + timer@40037000 { + compatible = "fsl,vf610-pit"; + reg = <0x40037000 0x1000>; + interrupts = <39 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks VF610_CLK_PIT>; + clock-names = "pit"; + }; diff --git a/Documentation/devicetree/bindings/timer/img,pistachio-gptimer.txt b/Documentation/devicetree/bindings/timer/img,pistachio-gptimer.txt deleted file mode 100644 index 7afce80bf6a0..000000000000 --- a/Documentation/devicetree/bindings/timer/img,pistachio-gptimer.txt +++ /dev/null @@ -1,28 +0,0 @@ -* Pistachio general-purpose timer based clocksource - -Required properties: - - compatible: "img,pistachio-gptimer". - - reg: Address range of the timer registers. - - interrupts: An interrupt for each of the four timers - - clocks: Should contain a clock specifier for each entry in clock-names - - clock-names: Should contain the following entries: - "sys", interface clock - "slow", slow counter clock - "fast", fast counter clock - - img,cr-periph: Must contain a phandle to the peripheral control - syscon node. - -Example: - timer: timer@18102000 { - compatible = "img,pistachio-gptimer"; - reg = <0x18102000 0x100>; - interrupts = <GIC_SHARED 60 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SHARED 61 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SHARED 62 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SHARED 63 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_periph PERIPH_CLK_COUNTER_FAST>, - <&clk_periph PERIPH_CLK_COUNTER_SLOW>, - <&cr_periph SYS_CLK_TIMER>; - clock-names = "fast", "slow", "sys"; - img,cr-periph = <&cr_periph>; - }; diff --git a/Documentation/devicetree/bindings/timer/img,pistachio-gptimer.yaml b/Documentation/devicetree/bindings/timer/img,pistachio-gptimer.yaml new file mode 100644 index 000000000000..a8654bcf68a9 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/img,pistachio-gptimer.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/img,pistachio-gptimer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Pistachio general-purpose timer + +maintainers: + - Ezequiel Garcia <ezequiel.garcia@imgtec.com> + +properties: + compatible: + const: img,pistachio-gptimer + + reg: + maxItems: 1 + + interrupts: + items: + - description: Timer0 interrupt + - description: Timer1 interrupt + - description: Timer2 interrupt + - description: Timer3 interrupt + + clocks: + items: + - description: Fast counter clock + - description: Slow counter clock + - description: Interface clock + + clock-names: + items: + - const: fast + - const: slow + - const: sys + + img,cr-periph: + description: Peripheral control syscon phandle + $ref: /schemas/types.yaml#/definitions/phandle + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - img,cr-periph + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/mips-gic.h> + #include <dt-bindings/clock/pistachio-clk.h> + + timer@18102000 { + compatible = "img,pistachio-gptimer"; + reg = <0x18102000 0x100>; + interrupts = <GIC_SHARED 60 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SHARED 61 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SHARED 62 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SHARED 63 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_periph PERIPH_CLK_COUNTER_FAST>, + <&clk_periph PERIPH_CLK_COUNTER_SLOW>, + <&cr_periph SYS_CLK_TIMER>; + clock-names = "fast", "slow", "sys"; + img,cr-periph = <&cr_periph>; + }; diff --git a/Documentation/devicetree/bindings/timer/jcore,pit.txt b/Documentation/devicetree/bindings/timer/jcore,pit.txt deleted file mode 100644 index af5dd35469d7..000000000000 --- a/Documentation/devicetree/bindings/timer/jcore,pit.txt +++ /dev/null @@ -1,24 +0,0 @@ -J-Core Programmable Interval Timer and Clocksource - -Required properties: - -- compatible: Must be "jcore,pit". - -- reg: Memory region(s) for timer/clocksource registers. For SMP, - there should be one region per cpu, indexed by the sequential, - zero-based hardware cpu number. - -- interrupts: An interrupt to assign for the timer. The actual pit - core is integrated with the aic and allows the timer interrupt - assignment to be programmed by software, but this property is - required in order to reserve an interrupt number that doesn't - conflict with other devices. - - -Example: - -timer@200 { - compatible = "jcore,pit"; - reg = < 0x200 0x30 0x500 0x30 >; - interrupts = < 0x48 >; -}; diff --git a/Documentation/devicetree/bindings/timer/jcore,pit.yaml b/Documentation/devicetree/bindings/timer/jcore,pit.yaml new file mode 100644 index 000000000000..9e6e25b75293 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/jcore,pit.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/jcore,pit.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: J-Core Programmable Interval Timer and Clocksource + +maintainers: + - Rich Felker <dalias@libc.org> + +properties: + compatible: + const: jcore,pit + + reg: + description: + Memory region(s) for timer/clocksource registers. For SMP, there should be + one region per cpu, indexed by the sequential, zero-based hardware cpu + number. + + interrupts: + description: + An interrupt to assign for the timer. The actual pit core is integrated + with the aic and allows the timer interrupt assignment to be programmed by + software, but this property is required in order to reserve an interrupt + number that doesn't conflict with other devices. + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + timer@200 { + compatible = "jcore,pit"; + reg = <0x200 0x30 0x500 0x30>; + interrupts = <0x48>; + }; diff --git a/Documentation/devicetree/bindings/timer/lsi,zevio-timer.txt b/Documentation/devicetree/bindings/timer/lsi,zevio-timer.txt deleted file mode 100644 index b2d07ad90e9a..000000000000 --- a/Documentation/devicetree/bindings/timer/lsi,zevio-timer.txt +++ /dev/null @@ -1,33 +0,0 @@ -TI-NSPIRE timer - -Required properties: - -- compatible : should be "lsi,zevio-timer". -- reg : The physical base address and size of the timer (always first). -- clocks: phandle to the source clock. - -Optional properties: - -- interrupts : The interrupt number of the first timer. -- reg : The interrupt acknowledgement registers - (always after timer base address) - -If any of the optional properties are not given, the timer is added as a -clock-source only. - -Example: - -timer { - compatible = "lsi,zevio-timer"; - reg = <0x900D0000 0x1000>, <0x900A0020 0x8>; - interrupts = <19>; - clocks = <&timer_clk>; -}; - -Example (no clock-events): - -timer { - compatible = "lsi,zevio-timer"; - reg = <0x900D0000 0x1000>; - clocks = <&timer_clk>; -}; diff --git a/Documentation/devicetree/bindings/timer/lsi,zevio-timer.yaml b/Documentation/devicetree/bindings/timer/lsi,zevio-timer.yaml new file mode 100644 index 000000000000..358455d8e7a8 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/lsi,zevio-timer.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/lsi,zevio-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI-NSPIRE timer + +maintainers: + - Daniel Tang <dt.tangr@gmail.com> + +properties: + compatible: + const: lsi,zevio-timer + + reg: + minItems: 1 + items: + - description: Timer registers + - description: Interrupt acknowledgement registers (optional) + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - clocks + +allOf: + - if: + required: [ interrupts ] + then: + properties: + reg: + minItems: 2 + +additionalProperties: false + +examples: + - | + timer@900d0000 { + compatible = "lsi,zevio-timer"; + reg = <0x900D0000 0x1000>, <0x900A0020 0x8>; + interrupts = <19>; + clocks = <&timer_clk>; + }; + - | + timer@900d0000 { + compatible = "lsi,zevio-timer"; + reg = <0x900D0000 0x1000>; + clocks = <&timer_clk>; + }; diff --git a/Documentation/devicetree/bindings/timer/marvell,armada-370-timer.yaml b/Documentation/devicetree/bindings/timer/marvell,armada-370-timer.yaml new file mode 100644 index 000000000000..bc0677fe86eb --- /dev/null +++ b/Documentation/devicetree/bindings/timer/marvell,armada-370-timer.yaml @@ -0,0 +1,88 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/marvell,armada-370-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Armada 370, 375, 380 and XP Timers + +maintainers: + - Andrew Lunn <andrew@lunn.ch> + - Gregory Clement <gregory.clement@bootlin.com> + +properties: + compatible: + oneOf: + - items: + - const: marvell,armada-380-timer + - const: marvell,armada-xp-timer + - items: + - const: marvell,armada-375-timer + - const: marvell,armada-370-timer + - enum: + - marvell,armada-370-timer + - marvell,armada-xp-timer + + reg: + items: + - description: Global timer registers + - description: Local/private timer registers + + interrupts: + items: + - description: Global timer interrupt 0 + - description: Global timer interrupt 1 + - description: Global timer interrupt 2 + - description: Global timer interrupt 3 + - description: First private timer interrupt + - description: Second private timer interrupt + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + items: + - const: nbclk + - const: fixed + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +allOf: + - if: + properties: + compatible: + contains: + enum: + - marvell,armada-375-timer + - marvell,armada-xp-timer + then: + properties: + clocks: + minItems: 2 + clock-names: + minItems: 2 + required: + - clock-names + else: + properties: + clocks: + maxItems: 1 + clock-names: + maxItems: 1 + +examples: + - | + timer@20300 { + compatible = "marvell,armada-xp-timer"; + reg = <0x20300 0x30>, <0x21040 0x30>; + interrupts = <37>, <38>, <39>, <40>, <5>, <6>; + clocks = <&coreclk 2>, <&refclk>; + clock-names = "nbclk", "fixed"; + }; diff --git a/Documentation/devicetree/bindings/timer/marvell,armada-370-xp-timer.txt b/Documentation/devicetree/bindings/timer/marvell,armada-370-xp-timer.txt deleted file mode 100644 index e9c78ce880e6..000000000000 --- a/Documentation/devicetree/bindings/timer/marvell,armada-370-xp-timer.txt +++ /dev/null @@ -1,44 +0,0 @@ -Marvell Armada 370 and Armada XP Timers ---------------------------------------- - -Required properties: -- compatible: Should be one of the following - "marvell,armada-370-timer", - "marvell,armada-375-timer", - "marvell,armada-xp-timer". -- interrupts: Should contain the list of Global Timer interrupts and - then local timer interrupts -- reg: Should contain location and length for timers register. First - pair for the Global Timer registers, second pair for the - local/private timers. - -Clocks required for compatible = "marvell,armada-370-timer": -- clocks : Must contain a single entry describing the clock input - -Clocks required for compatibles = "marvell,armada-xp-timer", - "marvell,armada-375-timer": -- clocks : Must contain an entry for each entry in clock-names. -- clock-names : Must include the following entries: - "nbclk" (L2/coherency fabric clock), - "fixed" (Reference 25 MHz fixed-clock). - -Examples: - -- Armada 370: - - timer { - compatible = "marvell,armada-370-timer"; - reg = <0x20300 0x30>, <0x21040 0x30>; - interrupts = <37>, <38>, <39>, <40>, <5>, <6>; - clocks = <&coreclk 2>; - }; - -- Armada XP: - - timer { - compatible = "marvell,armada-xp-timer"; - reg = <0x20300 0x30>, <0x21040 0x30>; - interrupts = <37>, <38>, <39>, <40>, <5>, <6>; - clocks = <&coreclk 2>, <&refclk>; - clock-names = "nbclk", "fixed"; - }; diff --git a/Documentation/devicetree/bindings/timer/marvell,orion-timer.txt b/Documentation/devicetree/bindings/timer/marvell,orion-timer.txt deleted file mode 100644 index cd1a0c256f94..000000000000 --- a/Documentation/devicetree/bindings/timer/marvell,orion-timer.txt +++ /dev/null @@ -1,16 +0,0 @@ -Marvell Orion SoC timer - -Required properties: -- compatible: shall be "marvell,orion-timer" -- reg: base address of the timer register starting with TIMERS CONTROL register -- interrupts: should contain the interrupts for Timer0 and Timer1 -- clocks: phandle of timer reference clock (tclk) - -Example: - timer: timer { - compatible = "marvell,orion-timer"; - reg = <0x20300 0x20>; - interrupt-parent = <&bridge_intc>; - interrupts = <1>, <2>; - clocks = <&core_clk 0>; - }; diff --git a/Documentation/devicetree/bindings/timer/marvell,orion-timer.yaml b/Documentation/devicetree/bindings/timer/marvell,orion-timer.yaml new file mode 100644 index 000000000000..f973afffa5ba --- /dev/null +++ b/Documentation/devicetree/bindings/timer/marvell,orion-timer.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/marvell,orion-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Orion SoC timer + +maintainers: + - Andrew Lunn <andrew@lunn.ch> + - Gregory Clement <gregory.clement@bootlin.com> + +properties: + compatible: + const: marvell,orion-timer + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + interrupts: + items: + - description: Timer0 interrupt + - description: Timer1 interrupt + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + timer@20300 { + compatible = "marvell,orion-timer"; + reg = <0x20300 0x20>; + interrupts = <1>, <2>; + clocks = <&core_clk 0>; + }; diff --git a/Documentation/devicetree/bindings/timer/nxp,s32g2-stm.yaml b/Documentation/devicetree/bindings/timer/nxp,s32g2-stm.yaml new file mode 100644 index 000000000000..b44b9794bb85 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/nxp,s32g2-stm.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/nxp,s32g2-stm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP System Timer Module (STM) + +maintainers: + - Daniel Lezcano <daniel.lezcano@kernel.org> + +description: + The System Timer Module supports commonly required system and application + software timing functions. STM includes a 32-bit count-up timer and four + 32-bit compare channels with a separate interrupt source for each channel. + The timer is driven by the STM module clock divided by an 8-bit prescale + value. + +properties: + compatible: + oneOf: + - const: nxp,s32g2-stm + - items: + - const: nxp,s32g3-stm + - const: nxp,s32g2-stm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: Counter clock + - description: Module clock + - description: Register clock + + clock-names: + items: + - const: counter + - const: module + - const: register + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + timer@4011c000 { + compatible = "nxp,s32g2-stm"; + reg = <0x4011c000 0x3000>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; + clock-names = "counter", "module", "register"; + }; diff --git a/Documentation/devicetree/bindings/timer/nxp,sysctr-timer.yaml b/Documentation/devicetree/bindings/timer/nxp,sysctr-timer.yaml index 891cca009528..6b80b060672e 100644 --- a/Documentation/devicetree/bindings/timer/nxp,sysctr-timer.yaml +++ b/Documentation/devicetree/bindings/timer/nxp,sysctr-timer.yaml @@ -18,9 +18,14 @@ description: | properties: compatible: - enum: - - nxp,imx95-sysctr-timer - - nxp,sysctr-timer + oneOf: + - enum: + - nxp,imx95-sysctr-timer + - nxp,sysctr-timer + - items: + - enum: + - nxp,imx94-sysctr-timer + - const: nxp,imx95-sysctr-timer reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/timer/renesas,cmt.yaml b/Documentation/devicetree/bindings/timer/renesas,cmt.yaml index 5e09c04da30e..260b05f213e6 100644 --- a/Documentation/devicetree/bindings/timer/renesas,cmt.yaml +++ b/Documentation/devicetree/bindings/timer/renesas,cmt.yaml @@ -178,29 +178,29 @@ examples: #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/power/r8a7790-sysc.h> cmt0: timer@ffca0000 { - compatible = "renesas,r8a7790-cmt0", "renesas,rcar-gen2-cmt0"; - reg = <0xffca0000 0x1004>; - interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 124>; - clock-names = "fck"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 124>; + compatible = "renesas,r8a7790-cmt0", "renesas,rcar-gen2-cmt0"; + reg = <0xffca0000 0x1004>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 124>; + clock-names = "fck"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 124>; }; cmt1: timer@e6130000 { - compatible = "renesas,r8a7790-cmt1", "renesas,rcar-gen2-cmt1"; - reg = <0xe6130000 0x1004>; - interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 329>; - clock-names = "fck"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 329>; + compatible = "renesas,r8a7790-cmt1", "renesas,rcar-gen2-cmt1"; + reg = <0xe6130000 0x1004>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 329>; + clock-names = "fck"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 329>; }; diff --git a/Documentation/devicetree/bindings/timer/renesas,em-sti.yaml b/Documentation/devicetree/bindings/timer/renesas,em-sti.yaml index 233d74d5402c..a7385d865bca 100644 --- a/Documentation/devicetree/bindings/timer/renesas,em-sti.yaml +++ b/Documentation/devicetree/bindings/timer/renesas,em-sti.yaml @@ -38,9 +38,9 @@ examples: - | #include <dt-bindings/interrupt-controller/arm-gic.h> timer@e0180000 { - compatible = "renesas,em-sti"; - reg = <0xe0180000 0x54>; - interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&sti_sclk>; - clock-names = "sclk"; + compatible = "renesas,em-sti"; + reg = <0xe0180000 0x54>; + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sti_sclk>; + clock-names = "sclk"; }; diff --git a/Documentation/devicetree/bindings/timer/renesas,mtu2.yaml b/Documentation/devicetree/bindings/timer/renesas,mtu2.yaml index 15d8dddf4ae9..e56c12f03f72 100644 --- a/Documentation/devicetree/bindings/timer/renesas,mtu2.yaml +++ b/Documentation/devicetree/bindings/timer/renesas,mtu2.yaml @@ -66,11 +66,11 @@ examples: #include <dt-bindings/clock/r7s72100-clock.h> #include <dt-bindings/interrupt-controller/arm-gic.h> mtu2: timer@fcff0000 { - compatible = "renesas,mtu2-r7s72100", "renesas,mtu2"; - reg = <0xfcff0000 0x400>; - interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "tgi0a"; - clocks = <&mstp3_clks R7S72100_CLK_MTU2>; - clock-names = "fck"; - power-domains = <&cpg_clocks>; + compatible = "renesas,mtu2-r7s72100", "renesas,mtu2"; + reg = <0xfcff0000 0x400>; + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tgi0a"; + clocks = <&mstp3_clks R7S72100_CLK_MTU2>; + clock-names = "fck"; + power-domains = <&cpg_clocks>; }; diff --git a/Documentation/devicetree/bindings/timer/renesas,ostm.yaml b/Documentation/devicetree/bindings/timer/renesas,ostm.yaml index e8c642166462..0983c1efec80 100644 --- a/Documentation/devicetree/bindings/timer/renesas,ostm.yaml +++ b/Documentation/devicetree/bindings/timer/renesas,ostm.yaml @@ -26,6 +26,7 @@ properties: - renesas,r9a07g043-ostm # RZ/G2UL and RZ/Five - renesas,r9a07g044-ostm # RZ/G2{L,LC} - renesas,r9a07g054-ostm # RZ/V2L + - renesas,r9a09g056-ostm # RZ/V2N - renesas,r9a09g057-ostm # RZ/V2H(P) - const: renesas,ostm # Generic @@ -54,12 +55,11 @@ required: if: properties: compatible: - contains: - enum: - - renesas,r9a07g043-ostm - - renesas,r9a07g044-ostm - - renesas,r9a07g054-ostm - - renesas,r9a09g057-ostm + not: + contains: + enum: + - renesas,r7s72100-ostm + - renesas,r7s9210-ostm then: required: - resets @@ -71,9 +71,9 @@ examples: #include <dt-bindings/clock/r7s72100-clock.h> #include <dt-bindings/interrupt-controller/arm-gic.h> ostm0: timer@fcfec000 { - compatible = "renesas,r7s72100-ostm", "renesas,ostm"; - reg = <0xfcfec000 0x30>; - interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>; - clocks = <&mstp5_clks R7S72100_CLK_OSTM0>; - power-domains = <&cpg_clocks>; + compatible = "renesas,r7s72100-ostm", "renesas,ostm"; + reg = <0xfcfec000 0x30>; + interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>; + clocks = <&mstp5_clks R7S72100_CLK_OSTM0>; + power-domains = <&cpg_clocks>; }; diff --git a/Documentation/devicetree/bindings/timer/renesas,tmu.yaml b/Documentation/devicetree/bindings/timer/renesas,tmu.yaml index 75b0e7c70b62..b1229595acfb 100644 --- a/Documentation/devicetree/bindings/timer/renesas,tmu.yaml +++ b/Documentation/devicetree/bindings/timer/renesas,tmu.yaml @@ -122,15 +122,15 @@ examples: #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/power/r8a7779-sysc.h> tmu0: timer@ffd80000 { - compatible = "renesas,tmu-r8a7779", "renesas,tmu"; - reg = <0xffd80000 0x30>; - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; - clocks = <&mstp0_clks R8A7779_CLK_TMU0>; - clock-names = "fck"; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - #renesas,channels = <3>; + compatible = "renesas,tmu-r8a7779", "renesas,tmu"; + reg = <0xffd80000 0x30>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; + clocks = <&mstp0_clks R8A7779_CLK_TMU0>; + clock-names = "fck"; + power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; + #renesas,channels = <3>; }; diff --git a/Documentation/devicetree/bindings/timer/renesas,tpu.yaml b/Documentation/devicetree/bindings/timer/renesas,tpu.yaml deleted file mode 100644 index 01554dff23d8..000000000000 --- a/Documentation/devicetree/bindings/timer/renesas,tpu.yaml +++ /dev/null @@ -1,56 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/timer/renesas,tpu.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Renesas H8/300 Timer Pulse Unit - -maintainers: - - Yoshinori Sato <ysato@users.sourceforge.jp> - -description: - The TPU is a 16bit timer/counter with configurable clock inputs and - programmable compare match. - This implementation supports only cascade mode. - -select: - properties: - compatible: - contains: - const: renesas,tpu - '#pwm-cells': false - required: - - compatible - -properties: - compatible: - const: renesas,tpu - - reg: - items: - - description: First channel - - description: Second channel - - clocks: - maxItems: 1 - - clock-names: - const: fck - -required: - - compatible - - reg - - clocks - - clock-names - -additionalProperties: false - -examples: - - | - tpu: tpu@ffffe0 { - compatible = "renesas,tpu"; - reg = <0xffffe0 16>, <0xfffff0 12>; - clocks = <&pclk>; - clock-names = "fck"; - }; diff --git a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml index 02d1c355808e..10578f544581 100644 --- a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml +++ b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml @@ -27,6 +27,7 @@ properties: - enum: - axis,artpec8-mct - google,gs101-mct + - samsung,exynos2200-mct-peris - samsung,exynos3250-mct - samsung,exynos5250-mct - samsung,exynos5260-mct @@ -34,6 +35,7 @@ properties: - samsung,exynos5433-mct - samsung,exynos850-mct - samsung,exynos8895-mct + - samsung,exynos990-mct - tesla,fsd-mct - const: samsung,exynos4210-mct @@ -130,11 +132,13 @@ allOf: enum: - axis,artpec8-mct - google,gs101-mct + - samsung,exynos2200-mct-peris - samsung,exynos5260-mct - samsung,exynos5420-mct - samsung,exynos5433-mct - samsung,exynos850-mct - samsung,exynos8895-mct + - samsung,exynos990-mct then: properties: interrupts: diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml index 76d83aea4e2b..d85a1a088b35 100644 --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -30,6 +30,7 @@ properties: - items: - enum: - canaan,k210-clint # Canaan Kendryte K210 + - eswin,eic7700-clint # ESWIN EIC7700 - sifive,fu540-c000-clint # SiFive FU540 - spacemit,k1-clint # SpacemiT K1 - starfive,jh7100-clint # StarFive JH7100 @@ -37,6 +38,12 @@ properties: - starfive,jh8100-clint # StarFive JH8100 - const: sifive,clint0 # SiFive CLINT v0 IP block - items: + - {} + - const: sifive,clint2 # SiFive CLINT v2 IP block + description: + SiFive CLINT v2 is the HRT that supports the Zicntr. The control of sifive,clint2 + differs from that of sifive,clint0, making them incompatible. + - items: - enum: - allwinner,sun20i-d1-clint - sophgo,cv1800b-clint @@ -62,6 +69,22 @@ properties: minItems: 1 maxItems: 4095 + sifive,fine-ctr-bits: + maximum: 15 + description: The width in bits of the fine counter. + +if: + properties: + compatible: + contains: + const: sifive,clint2 +then: + required: + - sifive,fine-ctr-bits +else: + properties: + sifive,fine-ctr-bits: false + additionalProperties: false required: @@ -77,6 +100,6 @@ examples: <&cpu2intc 3>, <&cpu2intc 7>, <&cpu3intc 3>, <&cpu3intc 7>, <&cpu4intc 3>, <&cpu4intc 7>; - reg = <0x2000000 0x10000>; + reg = <0x2000000 0x10000>; }; ... diff --git a/Documentation/devicetree/bindings/timer/snps,arc-timer.txt b/Documentation/devicetree/bindings/timer/snps,arc-timer.txt deleted file mode 100644 index b02ab0af10ce..000000000000 --- a/Documentation/devicetree/bindings/timer/snps,arc-timer.txt +++ /dev/null @@ -1,27 +0,0 @@ -Synopsys ARC Local Timer with Interrupt Capabilities -- Found on all ARC CPUs (ARC700/ARCHS) -- Can be optionally programmed to interrupt on Limit -- Two identical copies TIMER0 and TIMER1 exist in ARC cores and historically - TIMER0 used as clockevent provider (true for all ARC cores) - TIMER1 used for clocksource (mandatory for ARC700, optional for ARC HS) - -Required properties: - -- compatible : should be "snps,arc-timer" -- interrupts : single Interrupt going into parent intc - (16 for ARCHS cores, 3 for ARC700 cores) -- clocks : phandle to the source clock - -Example: - - timer0 { - compatible = "snps,arc-timer"; - interrupts = <3>; - interrupt-parent = <&core_intc>; - clocks = <&core_clk>; - }; - - timer1 { - compatible = "snps,arc-timer"; - clocks = <&core_clk>; - }; diff --git a/Documentation/devicetree/bindings/timer/snps,arc-timer.yaml b/Documentation/devicetree/bindings/timer/snps,arc-timer.yaml new file mode 100644 index 000000000000..0d1e37db6f8e --- /dev/null +++ b/Documentation/devicetree/bindings/timer/snps,arc-timer.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/snps,arc-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Synopsys ARC Local Timer + +maintainers: + - Vineet Gupta <vgupta@synopsys.com> + +description: > + Synopsys ARC Local Timer with Interrupt Capabilities + + - Found on all ARC CPUs (ARC700/ARCHS) + - Can be optionally programmed to interrupt on Limit + - Two identical copies TIMER0 and TIMER1 exist in ARC cores and historically + TIMER0 used as clockevent provider (true for all ARC cores) + TIMER1 used for clocksource (mandatory for ARC700, optional for ARC HS) + +properties: + compatible: + const: snps,arc-timer + + interrupts: + maxItems: 1 + description: A single timer interrupt going into the parent interrupt controller. + Use <16> for ARCHS cores, <3> for ARC700 cores. + + clocks: + maxItems: 1 + +required: + - compatible + - clocks + +additionalProperties: false + +examples: + - | + timer0 { + compatible = "snps,arc-timer"; + interrupts = <3>; + clocks = <&core_clk>; + }; diff --git a/Documentation/devicetree/bindings/timer/snps,archs-gfrc.txt b/Documentation/devicetree/bindings/timer/snps,archs-gfrc.txt deleted file mode 100644 index b6cd1b3922de..000000000000 --- a/Documentation/devicetree/bindings/timer/snps,archs-gfrc.txt +++ /dev/null @@ -1,14 +0,0 @@ -Synopsys ARC Free Running 64-bit Global Timer for ARC HS CPUs -- clocksource provider for SMP SoC - -Required properties: - -- compatible : should be "snps,archs-gfrc" -- clocks : phandle to the source clock - -Example: - - gfrc { - compatible = "snps,archs-gfrc"; - clocks = <&core_clk>; - }; diff --git a/Documentation/devicetree/bindings/timer/snps,archs-gfrc.yaml b/Documentation/devicetree/bindings/timer/snps,archs-gfrc.yaml new file mode 100644 index 000000000000..fb16f4aba1c5 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/snps,archs-gfrc.yaml @@ -0,0 +1,30 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/snps,archs-gfrc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Synopsys ARC Free Running 64-bit Global Timer for ARC HS CPUs + +maintainers: + - Vineet Gupta <vgupta@synopsys.com> + +properties: + compatible: + const: snps,archs-gfrc + + clocks: + maxItems: 1 + +required: + - compatible + - clocks + +additionalProperties: false + +examples: + - | + timer { + compatible = "snps,archs-gfrc"; + clocks = <&core_clk>; + }; diff --git a/Documentation/devicetree/bindings/timer/snps,archs-rtc.txt b/Documentation/devicetree/bindings/timer/snps,archs-rtc.txt deleted file mode 100644 index 47bd7a702f3f..000000000000 --- a/Documentation/devicetree/bindings/timer/snps,archs-rtc.txt +++ /dev/null @@ -1,14 +0,0 @@ -Synopsys ARC Free Running 64-bit Local Timer for ARC HS CPUs -- clocksource provider for UP SoC - -Required properties: - -- compatible : should be "snps,archs-rtc" -- clocks : phandle to the source clock - -Example: - - rtc { - compatible = "snps,arc-rtc"; - clocks = <&core_clk>; - }; diff --git a/Documentation/devicetree/bindings/timer/snps,archs-rtc.yaml b/Documentation/devicetree/bindings/timer/snps,archs-rtc.yaml new file mode 100644 index 000000000000..7478810eb24a --- /dev/null +++ b/Documentation/devicetree/bindings/timer/snps,archs-rtc.yaml @@ -0,0 +1,30 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/snps,archs-rtc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Synopsys ARC Free Running 64-bit Local Timer for ARC HS CPUs + +maintainers: + - Vineet Gupta <vgupta@synopsys.com> + +properties: + compatible: + const: snps,archs-rtc + + clocks: + maxItems: 1 + +required: + - compatible + - clocks + +additionalProperties: false + +examples: + - | + rtc { + compatible = "snps,archs-rtc"; + clocks = <&core_clk>; + }; diff --git a/Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.txt b/Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.txt deleted file mode 100644 index ac44c4b67530..000000000000 --- a/Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.txt +++ /dev/null @@ -1,17 +0,0 @@ -Milbeaut SoCs Timer Controller - -Required properties: - -- compatible : should be "socionext,milbeaut-timer". -- reg : Specifies base physical address and size of the registers. -- interrupts : The interrupt of the first timer. -- clocks: phandle to the input clk. - -Example: - -timer { - compatible = "socionext,milbeaut-timer"; - reg = <0x1e000050 0x20> - interrupts = <0 91 4>; - clocks = <&clk 4>; -}; diff --git a/Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.yaml b/Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.yaml new file mode 100644 index 000000000000..9ab72b762314 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/socionext,milbeaut-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Milbeaut SoCs Timer Controller + +maintainers: + - Sugaya Taichi <sugaya.taichi@socionext.com> + +properties: + compatible: + const: socionext,milbeaut-timer + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + timer@1e000050 { + compatible = "socionext,milbeaut-timer"; + reg = <0x1e000050 0x20>; + interrupts = <0 91 4>; + clocks = <&clk 4>; + }; diff --git a/Documentation/devicetree/bindings/timer/st,spear-timer.txt b/Documentation/devicetree/bindings/timer/st,spear-timer.txt deleted file mode 100644 index b5238a07da17..000000000000 --- a/Documentation/devicetree/bindings/timer/st,spear-timer.txt +++ /dev/null @@ -1,16 +0,0 @@ -* SPEAr ARM Timer - -** Timer node required properties: - -- compatible : Should be: - "st,spear-timer" -- reg: Address range of the timer registers -- interrupt: Should contain the timer interrupt number - -Example: - - timer@f0000000 { - compatible = "st,spear-timer"; - reg = <0xf0000000 0x400>; - interrupts = <2>; - }; diff --git a/Documentation/devicetree/bindings/timer/st,spear-timer.yaml b/Documentation/devicetree/bindings/timer/st,spear-timer.yaml new file mode 100644 index 000000000000..9f26b5f2b38a --- /dev/null +++ b/Documentation/devicetree/bindings/timer/st,spear-timer.yaml @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/st,spear-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SPEAr ARM Timer + +maintainers: + - Viresh Kumar <vireshk@kernel.org> + - Shiraz Hashim <shiraz.linux.kernel@gmail.com> + +properties: + compatible: + const: st,spear-timer + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + timer@f0000000 { + compatible = "st,spear-timer"; + reg = <0xf0000000 0x400>; + interrupts = <2>; + }; diff --git a/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml b/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml index 2e92bcdeb423..4ed30efe4052 100644 --- a/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml +++ b/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml @@ -14,6 +14,7 @@ properties: items: - enum: - sophgo,sg2042-aclint-mtimer + - sophgo,sg2044-aclint-mtimer - const: thead,c900-aclint-mtimer reg: diff --git a/Documentation/devicetree/bindings/timer/ti,keystone-timer.txt b/Documentation/devicetree/bindings/timer/ti,keystone-timer.txt deleted file mode 100644 index d3905a5412b8..000000000000 --- a/Documentation/devicetree/bindings/timer/ti,keystone-timer.txt +++ /dev/null @@ -1,29 +0,0 @@ -* Device tree bindings for Texas instruments Keystone timer - -This document provides bindings for the 64-bit timer in the KeyStone -architecture devices. The timer can be configured as a general-purpose 64-bit -timer, dual general-purpose 32-bit timers. When configured as dual 32-bit -timers, each half can operate in conjunction (chain mode) or independently -(unchained mode) of each other. - -It is global timer is a free running up-counter and can generate interrupt -when the counter reaches preset counter values. - -Documentation: -https://www.ti.com/lit/ug/sprugv5a/sprugv5a.pdf - -Required properties: - -- compatible : should be "ti,keystone-timer". -- reg : specifies base physical address and count of the registers. -- interrupts : interrupt generated by the timer. -- clocks : the clock feeding the timer clock. - -Example: - -timer@22f0000 { - compatible = "ti,keystone-timer"; - reg = <0x022f0000 0x80>; - interrupts = <GIC_SPI 110 IRQ_TYPE_EDGE_RISING>; - clocks = <&clktimer15>; -}; diff --git a/Documentation/devicetree/bindings/timer/ti,keystone-timer.yaml b/Documentation/devicetree/bindings/timer/ti,keystone-timer.yaml new file mode 100644 index 000000000000..1caf5ce64f01 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/ti,keystone-timer.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ti,keystone-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI Keystone timer + +maintainers: + - Alexander A. Klimov <grandmaster@al2klimov.de> + - Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> + +description: > + A 64-bit timer in the KeyStone architecture devices. The timer can be + configured as a general-purpose 64-bit timer, dual general-purpose 32-bit + timers. When configured as dual 32-bit timers, each half can operate in + conjunction (chain mode) or independently (unchained mode) of each other. + + It is global timer is a free running up-counter and can generate interrupt + when the counter reaches preset counter values. + + Documentation: + https://www.ti.com/lit/ug/sprugv5a/sprugv5a.pdf + +properties: + compatible: + const: ti,keystone-timer + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-names: + items: + - const: irq + + clocks: + maxItems: 1 + + clock-names: + items: + - const: timer + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + timer@22f0000 { + compatible = "ti,keystone-timer"; + reg = <0x022f0000 0x80>; + interrupts = <110 IRQ_TYPE_EDGE_RISING>; + clocks = <&clktimer15>; + }; diff --git a/Documentation/devicetree/bindings/trigger-source/pwm-trigger.yaml b/Documentation/devicetree/bindings/trigger-source/pwm-trigger.yaml new file mode 100644 index 000000000000..1eac20031dc3 --- /dev/null +++ b/Documentation/devicetree/bindings/trigger-source/pwm-trigger.yaml @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/trigger-source/pwm-trigger.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Generic trigger source using PWM + +description: Remaps a PWM channel as a trigger source. + +maintainers: + - David Lechner <dlechner@baylibre.com> + +properties: + compatible: + const: pwm-trigger + + '#trigger-source-cells': + const: 0 + + pwms: + maxItems: 1 + +required: + - compatible + - '#trigger-source-cells' + - pwms + +additionalProperties: false + +examples: + - | + trigger { + compatible = "pwm-trigger"; + #trigger-source-cells = <0>; + pwms = <&pwm 0 1000000 0>; + }; diff --git a/Documentation/devicetree/bindings/trivial-devices.yaml b/Documentation/devicetree/bindings/trivial-devices.yaml index fadbd3c041c8..27930708ccd5 100644 --- a/Documentation/devicetree/bindings/trivial-devices.yaml +++ b/Documentation/devicetree/bindings/trivial-devices.yaml @@ -85,6 +85,8 @@ properties: - devantech,srf08 # Devantech SRF10 ultrasonic ranger - devantech,srf10 + # DFRobot SEN0322 oxygen sensor + - dfrobot,sen0322 # DH electronics GmbH on-board CPLD trivial SPI device - dh,dhcom-board # DA9053: flexible system level PMIC with multicore support @@ -173,6 +175,8 @@ properties: - maxim,ds3502 # Temperature Sensor, I2C interface - maxim,max1619 + # Digital temperature sensor with 0.1°C accuracy + - maxim,max30208 # 3-Channel Remote Temperature Sensor - maxim,max31730 # 10-bit 10 kOhm linear programmable voltage divider @@ -185,10 +189,20 @@ properties: - maxim,max5484 # PECI-to-I2C translator for PECI-to-SMBus/I2C protocol conversion - maxim,max6621 + # InTune Automatically Compensated Digital PoL Controller with Driver and PMBus Telemetry + - maxim,max15301 + # 6A InTune Automatically Compensated Converter with PMBus Telemetry + - maxim,max15303 + # Multiphase Master with PMBus Interface and Internal Buck Converter + - maxim,max20751 # mCube 3-axis 8-bit digital accelerometer - mcube,mc3230 + # mCube 3-axis 8-bit digital accelerometer + - mcube,mc3510c # Measurement Specialities I2C temperature and humidity sensor - meas,htu21 + # Measurement Specialities I2C temperature and humidity sensor + - meas,htu31 # Measurement Specialities I2C pressure and temperature sensor - meas,ms5637 # Measurement Specialities I2C pressure and temperature sensor @@ -283,8 +297,6 @@ properties: - mps,mp5990 # Monolithic Power Systems Inc. digital step-down converter mp9941 - mps,mp9941 - # Monolithic Power Systems Inc. synchronous step-down converter mpq8785 - - mps,mpq8785 # Temperature sensor with integrated fan control - national,lm63 # Serial Interface ACPI-Compatible Microprocessor System Hardware Monitor @@ -333,6 +345,8 @@ properties: - sensortek,stk8ba50 # SGX Sensortech VZ89X Sensors - sgx,vz89x + # SGX Sensortech VZ89TE Sensors + - sgx,vz89te # Silicon Labs EM3581 Zigbee SoC with SPI interface - silabs,em3581 # Silicon Labs SI3210 Programmable CMOS SLIC/CODEC with SPI interface @@ -380,6 +394,8 @@ properties: - ti,tps53676 # TI Dual channel DCAP+ multiphase controller TPS53679 - ti,tps53679 + # TI Dual channel DCAP+ multiphase controller TPS53681 + - ti,tps53681 # TI Dual channel DCAP+ multiphase controller TPS53688 - ti,tps53688 # TI DC-DC converters on PMBus @@ -387,6 +403,7 @@ properties: - ti,tps544b25 - ti,tps544c20 - ti,tps544c25 + - ti,tps546b24 - ti,tps546d24 # I2C Touch-Screen Controller - ti,tsc2003 diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml index a03fff5df5ef..6c6043d9809e 100644 --- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml +++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml @@ -43,6 +43,7 @@ properties: - qcom,sm8450-ufshc - qcom,sm8550-ufshc - qcom,sm8650-ufshc + - qcom,sm8750-ufshc - const: qcom,ufshc - const: jedec,ufs-2.0 @@ -158,6 +159,7 @@ allOf: - qcom,sm8450-ufshc - qcom,sm8550-ufshc - qcom,sm8650-ufshc + - qcom,sm8750-ufshc then: properties: clocks: diff --git a/Documentation/devicetree/bindings/ufs/renesas,ufs.yaml b/Documentation/devicetree/bindings/ufs/renesas,ufs.yaml index 1949a15e73d2..ac11ac7d1d12 100644 --- a/Documentation/devicetree/bindings/ufs/renesas,ufs.yaml +++ b/Documentation/devicetree/bindings/ufs/renesas,ufs.yaml @@ -33,6 +33,16 @@ properties: resets: maxItems: 1 + nvmem-cells: + maxItems: 1 + + nvmem-cell-names: + items: + - const: calibration + +dependencies: + nvmem-cells: [ nvmem-cell-names ] + required: - compatible - reg @@ -58,4 +68,6 @@ examples: freq-table-hz = <200000000 200000000>, <38400000 38400000>; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; resets = <&cpg 1514>; + nvmem-cells = <&ufs_tune>; + nvmem-cell-names = "calibration"; }; diff --git a/Documentation/devicetree/bindings/ufs/rockchip,rk3576-ufshc.yaml b/Documentation/devicetree/bindings/ufs/rockchip,rk3576-ufshc.yaml new file mode 100644 index 000000000000..c7d17cf4dc42 --- /dev/null +++ b/Documentation/devicetree/bindings/ufs/rockchip,rk3576-ufshc.yaml @@ -0,0 +1,105 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ufs/rockchip,rk3576-ufshc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip UFS Host Controller + +maintainers: + - Shawn Lin <shawn.lin@rock-chips.com> + +allOf: + - $ref: ufs-common.yaml + +properties: + compatible: + const: rockchip,rk3576-ufshc + + reg: + maxItems: 5 + + reg-names: + items: + - const: hci + - const: mphy + - const: hci_grf + - const: mphy_grf + - const: hci_apb + + clocks: + maxItems: 4 + + clock-names: + items: + - const: core + - const: pclk + - const: pclk_mphy + - const: ref_out + + power-domains: + maxItems: 1 + + resets: + maxItems: 4 + + reset-names: + items: + - const: biu + - const: sys + - const: ufs + - const: grf + + reset-gpios: + maxItems: 1 + description: | + GPIO specifiers for host to reset the whole UFS device including PHY and + memory. This gpio is active low and should choose the one whose high output + voltage is lower than 1.5V based on the UFS spec. + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - interrupts + - power-domains + - resets + - reset-names + - reset-gpios + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/rockchip,rk3576-cru.h> + #include <dt-bindings/reset/rockchip,rk3576-cru.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/rockchip,rk3576-power.h> + #include <dt-bindings/pinctrl/rockchip.h> + #include <dt-bindings/gpio/gpio.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + ufshc: ufshc@2a2d0000 { + compatible = "rockchip,rk3576-ufshc"; + reg = <0x0 0x2a2d0000 0x0 0x10000>, + <0x0 0x2b040000 0x0 0x10000>, + <0x0 0x2601f000 0x0 0x1000>, + <0x0 0x2603c000 0x0 0x1000>, + <0x0 0x2a2e0000 0x0 0x10000>; + reg-names = "hci", "mphy", "hci_grf", "mphy_grf", "hci_apb"; + clocks = <&cru ACLK_UFS_SYS>, <&cru PCLK_USB_ROOT>, <&cru PCLK_MPHY>, + <&cru CLK_REF_UFS_CLKOUT>; + clock-names = "core", "pclk", "pclk_mphy", "ref_out"; + interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&power RK3576_PD_USB>; + resets = <&cru SRST_A_UFS_BIU>, <&cru SRST_A_UFS_SYS>, <&cru SRST_A_UFS>, + <&cru SRST_P_UFS_GRF>; + reset-names = "biu", "sys", "ufs", "grf"; + reset-gpios = <&gpio4 RK_PD0 GPIO_ACTIVE_LOW>; + }; + }; diff --git a/Documentation/devicetree/bindings/usb/chipidea,usb2-common.yaml b/Documentation/devicetree/bindings/usb/chipidea,usb2-common.yaml index d2a7d2ecf48a..10020af15afc 100644 --- a/Documentation/devicetree/bindings/usb/chipidea,usb2-common.yaml +++ b/Documentation/devicetree/bindings/usb/chipidea,usb2-common.yaml @@ -42,6 +42,9 @@ properties: phy_type: true + iommus: + maxItems: 1 + itc-setting: description: interrupt threshold control register control, the setting should be diff --git a/Documentation/devicetree/bindings/usb/chipidea,usb2-imx.yaml b/Documentation/devicetree/bindings/usb/chipidea,usb2-imx.yaml index 8f6136f5d72e..51014955ab3c 100644 --- a/Documentation/devicetree/bindings/usb/chipidea,usb2-imx.yaml +++ b/Documentation/devicetree/bindings/usb/chipidea,usb2-imx.yaml @@ -41,6 +41,7 @@ properties: - fsl,imx8mm-usb - fsl,imx8mn-usb - fsl,imx93-usb + - fsl,imx95-usb - const: fsl,imx7d-usb - const: fsl,imx27-usb - items: @@ -54,7 +55,11 @@ properties: maxItems: 1 interrupts: - maxItems: 1 + minItems: 1 + items: + - description: USB controller interrupt or combine USB controller + and wakeup interrupts. + - description: Wakeup interrupt clocks: minItems: 1 @@ -191,6 +196,7 @@ allOf: contains: enum: - fsl,imx93-usb + - fsl,imx95-usb then: properties: clocks: @@ -238,6 +244,22 @@ allOf: maxItems: 1 clock-names: false + # imx95 soc use two interrupts + - if: + properties: + compatible: + contains: + enum: + - fsl,imx95-usb + then: + properties: + interrupts: + minItems: 2 + else: + properties: + interrupts: + maxItems: 1 + unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/usb/cypress,hx3.yaml b/Documentation/devicetree/bindings/usb/cypress,hx3.yaml index 1033b7a4b8f9..d6eac1213228 100644 --- a/Documentation/devicetree/bindings/usb/cypress,hx3.yaml +++ b/Documentation/devicetree/bindings/usb/cypress,hx3.yaml @@ -14,9 +14,22 @@ allOf: properties: compatible: - enum: - - usb4b4,6504 - - usb4b4,6506 + oneOf: + - enum: + - usb4b4,6504 + - usb4b4,6506 + - items: + - enum: + - usb4b4,6500 + - usb4b4,6508 + - const: usb4b4,6504 + - items: + - enum: + - usb4b4,6502 + - usb4b4,6503 + - usb4b4,6507 + - usb4b4,650a + - const: usb4b4,6506 reg: true diff --git a/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml b/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml index 00f87a558c7d..36f5c644d959 100644 --- a/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml +++ b/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml @@ -7,7 +7,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Xilinx SuperSpeed DWC3 USB SoC controller maintainers: - - Mubin Sayyed <mubin.sayyed@amd.com> - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> properties: @@ -27,6 +26,8 @@ properties: ranges: true + dma-coherent: true + power-domains: description: specifies a phandle to PM domain provider node maxItems: 1 @@ -101,7 +102,6 @@ examples: #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h> #include <dt-bindings/power/xlnx-zynqmp-power.h> #include <dt-bindings/reset/xlnx-zynqmp-resets.h> - #include <dt-bindings/clock/xlnx-zynqmp-clk.h> #include <dt-bindings/reset/xlnx-zynqmp-resets.h> #include <dt-bindings/phy/phy.h> axi { @@ -113,7 +113,7 @@ examples: #size-cells = <0x2>; compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9d0000 0x0 0x100>; - clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; + clocks = <&zynqmp_clk 32>, <&zynqmp_clk 34>; clock-names = "bus_clk", "ref_clk"; power-domains = <&zynqmp_firmware PD_USB_0>; resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>, diff --git a/Documentation/devicetree/bindings/usb/fsl,usbmisc.yaml b/Documentation/devicetree/bindings/usb/fsl,usbmisc.yaml index 0a6e7ac1b37e..019435540df0 100644 --- a/Documentation/devicetree/bindings/usb/fsl,usbmisc.yaml +++ b/Documentation/devicetree/bindings/usb/fsl,usbmisc.yaml @@ -34,6 +34,7 @@ properties: - fsl,imx8mm-usbmisc - fsl,imx8mn-usbmisc - fsl,imx8ulp-usbmisc + - fsl,imx95-usbmisc - const: fsl,imx7d-usbmisc - const: fsl,imx6q-usbmisc - items: @@ -45,7 +46,10 @@ properties: maxItems: 1 reg: - maxItems: 1 + minItems: 1 + items: + - description: Base and length of the Wrapper module register + - description: Base and length of the HSIO Block Control register '#index-cells': const: 1 @@ -56,6 +60,23 @@ required: - compatible - reg +allOf: + # imx95 soc needs use HSIO Block Control + - if: + properties: + compatible: + contains: + enum: + - fsl,imx95-usbmisc + then: + properties: + reg: + minItems: 2 + else: + properties: + reg: + maxItems: 1 + additionalProperties: false examples: diff --git a/Documentation/devicetree/bindings/usb/generic-ehci.yaml b/Documentation/devicetree/bindings/usb/generic-ehci.yaml index 223f2abd5e59..508d958e698c 100644 --- a/Documentation/devicetree/bindings/usb/generic-ehci.yaml +++ b/Documentation/devicetree/bindings/usb/generic-ehci.yaml @@ -86,6 +86,7 @@ properties: - nuvoton,npcm845-ehci - ti,ehci-omap - usb-ehci + - via,vt8500-ehci reg: minItems: 1 diff --git a/Documentation/devicetree/bindings/usb/generic-xhci.yaml b/Documentation/devicetree/bindings/usb/generic-xhci.yaml index 6ceafa4af292..a2b94a138999 100644 --- a/Documentation/devicetree/bindings/usb/generic-xhci.yaml +++ b/Documentation/devicetree/bindings/usb/generic-xhci.yaml @@ -51,6 +51,8 @@ properties: - const: core - const: reg + dma-coherent: true + power-domains: maxItems: 1 diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml index ef3143f4b794..004d3ebec091 100644 --- a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml +++ b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml @@ -106,6 +106,10 @@ properties: - description: USB3/SS(P) PHY - description: USB2/HS PHY + port: + $ref: /schemas/graph.yaml#/properties/port + description: Super Speed (SS) Output endpoint to a Type-C connector + vusb33-supply: description: Regulator of USB AVDD3.3v diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml b/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml index d4e187c78a0b..21fc6bbe954f 100644 --- a/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml +++ b/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml @@ -155,6 +155,18 @@ properties: property is used. See graph.txt $ref: /schemas/graph.yaml#/properties/port + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: High Speed (HS) data bus. + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: Super Speed (SS) data bus. + enable-manual-drd: $ref: /schemas/types.yaml#/definitions/flag description: diff --git a/Documentation/devicetree/bindings/usb/microchip,usb2514.yaml b/Documentation/devicetree/bindings/usb/microchip,usb2514.yaml index b14e6f37b298..4e3901efed3f 100644 --- a/Documentation/devicetree/bindings/usb/microchip,usb2514.yaml +++ b/Documentation/devicetree/bindings/usb/microchip,usb2514.yaml @@ -9,16 +9,19 @@ title: Microchip USB2514 Hub Controller maintainers: - Fabio Estevam <festevam@gmail.com> -allOf: - - $ref: usb-device.yaml# - properties: compatible: - enum: - - usb424,2412 - - usb424,2417 - - usb424,2514 - - usb424,2517 + oneOf: + - enum: + - usb424,2412 + - usb424,2417 + - usb424,2514 + - usb424,2517 + - items: + - enum: + - usb424,2512 + - usb424,2513 + - const: usb424,2514 reg: true @@ -28,6 +31,9 @@ properties: vdd-supply: description: 3.3V power supply. + vdda-supply: + description: 3.3V analog power supply. + clocks: description: External 24MHz clock connected to the CLKIN pin. maxItems: 1 @@ -43,6 +49,18 @@ patternProperties: $ref: /schemas/usb/usb-device.yaml additionalProperties: true +allOf: + - $ref: usb-device.yaml# + - if: + not: + properties: + compatible: + contains: + const: usb424,2514 + then: + properties: + vdda-supply: false + unevaluatedProperties: false examples: @@ -60,6 +78,7 @@ examples: clocks = <&clks IMX6QDL_CLK_CKO>; reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; vdd-supply = <®_3v3_hub>; + vdda-supply = <®_3v3a_hub>; #address-cells = <1>; #size-cells = <0>; diff --git a/Documentation/devicetree/bindings/usb/microchip,usb5744.yaml b/Documentation/devicetree/bindings/usb/microchip,usb5744.yaml index e2a72deae776..c68c04da3399 100644 --- a/Documentation/devicetree/bindings/usb/microchip,usb5744.yaml +++ b/Documentation/devicetree/bindings/usb/microchip,usb5744.yaml @@ -17,7 +17,6 @@ description: maintainers: - Michal Simek <michal.simek@amd.com> - - Mubin Sayyed <mubin.sayyed@amd.com> - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> properties: diff --git a/Documentation/devicetree/bindings/usb/parade,ps5511.yaml b/Documentation/devicetree/bindings/usb/parade,ps5511.yaml new file mode 100644 index 000000000000..10d002f09db8 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/parade,ps5511.yaml @@ -0,0 +1,108 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/parade,ps5511.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Parade PS5511 4+1 Port USB 3.2 Gen 1 Hub Controller + +maintainers: + - Pin-yen Lin <treapking@chromium.org> + +properties: + compatible: + enum: + - usb1da0,5511 + - usb1da0,55a1 + + reset-gpios: + items: + - description: GPIO specifier for RESETB pin. + + vddd11-supply: + description: + 1V1 power supply to the hub + + vdd33-supply: + description: + 3V3 power supply to the hub + + peer-hub: true + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + patternProperties: + '^port@': + $ref: /schemas/graph.yaml#/properties/port + + properties: + reg: + minimum: 1 + maximum: 5 + +additionalProperties: + properties: + reg: + minimum: 1 + maximum: 5 + +required: + - peer-hub + +allOf: + - $ref: usb-hub.yaml# + - if: + not: + properties: + compatible: + enum: + - usb1da0,55a1 + then: + properties: + ports: + properties: + port@5: false + + patternProperties: + '^.*@5$': false + +examples: + - | + usb { + #address-cells = <1>; + #size-cells = <0>; + + /* 2.0 hub on port 1 */ + hub_2_0: hub@1 { + compatible = "usb1da0,55a1"; + reg = <1>; + peer-hub = <&hub_3_0>; + #address-cells = <1>; + #size-cells = <0>; + /* USB 2.0 device on port 5 */ + device@5 { + reg = <5>; + compatible = "usb123,4567"; + }; + }; + + /* 3.0 hub on port 2 */ + hub_3_0: hub@2 { + compatible = "usb1da0,5511"; + reg = <2>; + peer-hub = <&hub_2_0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + /* Type-A connector on port 3 */ + port@3 { + reg = <3>; + endpoint { + remote-endpoint = <&usb_a0_ss>; + }; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/usb/parade,ps8830.yaml b/Documentation/devicetree/bindings/usb/parade,ps8830.yaml new file mode 100644 index 000000000000..aeb33667818e --- /dev/null +++ b/Documentation/devicetree/bindings/usb/parade,ps8830.yaml @@ -0,0 +1,143 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/parade,ps8830.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Parade PS883x USB and DisplayPort Retimer + +maintainers: + - Abel Vesa <abel.vesa@linaro.org> + +properties: + compatible: + oneOf: + - items: + - const: parade,ps8833 + - const: parade,ps8830 + - const: parade,ps8830 + + reg: + maxItems: 1 + + clocks: + items: + - description: XO Clock + + reset-gpios: + maxItems: 1 + + vdd-supply: + description: power supply (1.07V) + + vdd33-supply: + description: power supply (3.3V) + + vdd33-cap-supply: + description: power supply (3.3V) + + vddar-supply: + description: power supply (1.07V) + + vddat-supply: + description: power supply (1.07V) + + vddio-supply: + description: power supply (1.2V or 1.8V) + + orientation-switch: true + retimer-switch: true + + ports: + $ref: /schemas/graph.yaml#/properties/ports + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: Super Speed (SS) Output endpoint to the Type-C connector + + port@1: + $ref: /schemas/graph.yaml#/$defs/port-base + description: Super Speed (SS) Input endpoint from the Super-Speed PHY + unevaluatedProperties: false + + port@2: + $ref: /schemas/graph.yaml#/properties/port + description: + Sideband Use (SBU) AUX lines endpoint to the Type-C connector for the purpose of + handling altmode muxing and orientation switching. + +required: + - compatible + - reg + - clocks + - reset-gpios + - vdd-supply + - vdd33-supply + - vdd33-cap-supply + - vddat-supply + - vddio-supply + - orientation-switch + - retimer-switch + +allOf: + - $ref: usb-switch.yaml# + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + typec-mux@8 { + compatible = "parade,ps8830"; + reg = <0x8>; + + clocks = <&clk_rtmr_xo>; + + vdd-supply = <&vreg_rtmr_1p15>; + vdd33-supply = <&vreg_rtmr_3p3>; + vdd33-cap-supply = <&vreg_rtmr_3p3>; + vddar-supply = <&vreg_rtmr_1p15>; + vddat-supply = <&vreg_rtmr_1p15>; + vddio-supply = <&vreg_rtmr_1p8>; + + reset-gpios = <&tlmm 10 GPIO_ACTIVE_LOW>; + + retimer-switch; + orientation-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + endpoint { + remote-endpoint = <&typec_con_ss>; + }; + }; + + port@1 { + reg = <1>; + + endpoint { + remote-endpoint = <&usb_phy_ss>; + }; + }; + + port@2 { + reg = <2>; + + endpoint { + remote-endpoint = <&typec_dp_aux>; + }; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml index a2b3cf625e5b..a792434c59db 100644 --- a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml +++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml @@ -4,11 +4,22 @@ $id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcomm SuperSpeed DWC3 USB SoC controller +title: Legacy Qualcomm SuperSpeed DWC3 USB SoC controller maintainers: - Wesley Cheng <quic_wcheng@quicinc.com> +# Use the combined qcom,snps-dwc3 instead +deprecated: true + +select: + properties: + compatible: + contains: + const: qcom,dwc3 + required: + - compatible + properties: compatible: items: @@ -55,6 +66,7 @@ properties: - qcom,sm8450-dwc3 - qcom,sm8550-dwc3 - qcom,sm8650-dwc3 + - qcom,sm8750-dwc3 - qcom,x1e80100-dwc3 - qcom,x1e80100-dwc3-mp - const: qcom,dwc3 @@ -354,6 +366,7 @@ allOf: - qcom,sm8450-dwc3 - qcom,sm8550-dwc3 - qcom,sm8650-dwc3 + - qcom,sm8750-dwc3 then: properties: clocks: @@ -404,6 +417,7 @@ allOf: minItems: 2 maxItems: 3 interrupt-names: + minItems: 2 items: - const: pwr_event - const: qusb2_phy @@ -425,6 +439,7 @@ allOf: minItems: 3 maxItems: 4 interrupt-names: + minItems: 3 items: - const: pwr_event - const: qusb2_phy @@ -495,6 +510,7 @@ allOf: - qcom,sm8450-dwc3 - qcom,sm8550-dwc3 - qcom,sm8650-dwc3 + - qcom,sm8750-dwc3 then: properties: interrupts: diff --git a/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml new file mode 100644 index 000000000000..8dac5eba61b4 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml @@ -0,0 +1,622 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/qcom,snps-dwc3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SuperSpeed DWC3 USB SoC controller + +maintainers: + - Wesley Cheng <quic_wcheng@quicinc.com> + +description: + Describes the Qualcomm USB block, based on Synopsys DWC3. + +select: + properties: + compatible: + contains: + const: qcom,snps-dwc3 + required: + - compatible + +properties: + compatible: + items: + - enum: + - qcom,ipq4019-dwc3 + - qcom,ipq5018-dwc3 + - qcom,ipq5332-dwc3 + - qcom,ipq5424-dwc3 + - qcom,ipq6018-dwc3 + - qcom,ipq8064-dwc3 + - qcom,ipq8074-dwc3 + - qcom,ipq9574-dwc3 + - qcom,msm8953-dwc3 + - qcom,msm8994-dwc3 + - qcom,msm8996-dwc3 + - qcom,msm8998-dwc3 + - qcom,qcm2290-dwc3 + - qcom,qcs404-dwc3 + - qcom,qcs615-dwc3 + - qcom,qcs8300-dwc3 + - qcom,qdu1000-dwc3 + - qcom,sa8775p-dwc3 + - qcom,sar2130p-dwc3 + - qcom,sc7180-dwc3 + - qcom,sc7280-dwc3 + - qcom,sc8180x-dwc3 + - qcom,sc8180x-dwc3-mp + - qcom,sc8280xp-dwc3 + - qcom,sc8280xp-dwc3-mp + - qcom,sdm660-dwc3 + - qcom,sdm670-dwc3 + - qcom,sdm845-dwc3 + - qcom,sdx55-dwc3 + - qcom,sdx65-dwc3 + - qcom,sdx75-dwc3 + - qcom,sm4250-dwc3 + - qcom,sm6115-dwc3 + - qcom,sm6125-dwc3 + - qcom,sm6350-dwc3 + - qcom,sm6375-dwc3 + - qcom,sm8150-dwc3 + - qcom,sm8250-dwc3 + - qcom,sm8350-dwc3 + - qcom,sm8450-dwc3 + - qcom,sm8550-dwc3 + - qcom,sm8650-dwc3 + - qcom,x1e80100-dwc3 + - const: qcom,snps-dwc3 + + reg: + maxItems: 1 + + power-domains: + maxItems: 1 + + required-opps: + maxItems: 1 + + clocks: + description: | + Several clocks are used, depending on the variant. Typical ones are:: + - cfg_noc:: System Config NOC clock. + - core:: Master/Core clock, has to be >= 125 MHz for SS operation and >= + 60MHz for HS operation. + - iface:: System bus AXI clock. + - sleep:: Sleep clock, used for wakeup when USB3 core goes into low + power mode (U3). + - mock_utmi:: Mock utmi clock needed for ITP/SOF generation in host + mode. Its frequency should be 19.2MHz. + minItems: 1 + maxItems: 9 + + clock-names: + minItems: 1 + maxItems: 9 + + dma-coherent: true + + iommus: + maxItems: 1 + + resets: + maxItems: 1 + + interconnects: + maxItems: 2 + + interconnect-names: + items: + - const: usb-ddr + - const: apps-usb + + interrupts: + description: | + Different types of interrupts are used based on HS PHY used on target: + - dwc_usb3: Core DWC3 interrupt + - pwr_event: Used for wakeup based on other power events. + - hs_phy_irq: Apart from DP/DM/QUSB2 PHY interrupts, there is + hs_phy_irq which is not triggered by default and its + functionality is mutually exclusive to that of + {dp/dm}_hs_phy_irq and qusb2_phy_irq. + - qusb2_phy: SoCs with QUSB2 PHY do not have separate DP/DM IRQs and + expose only a single IRQ whose behavior can be modified + by the QUSB2PHY_INTR_CTRL register. The required DPSE/ + DMSE configuration is done in QUSB2PHY_INTR_CTRL register + of PHY address space. + - {dp/dm}_hs_phy_irq: These IRQ's directly reflect changes on the DP/ + DM pads of the SoC. These are used for wakeup + only on SoCs with non-QUSB2 targets with + exception of SDM670/SDM845/SM6350. + - ss_phy_irq: Used for remote wakeup in Super Speed mode of operation. + minItems: 3 + maxItems: 19 + + interrupt-names: + minItems: 3 + maxItems: 19 + + qcom,select-utmi-as-pipe-clk: + description: + If present, disable USB3 pipe_clk requirement. + Used when dwc3 operates without SSPHY and only + HS/FS/LS modes are supported. + type: boolean + + wakeup-source: true + +# Required child node: + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - interrupt-names + +allOf: + - $ref: snps,dwc3-common.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq4019-dwc3 + - qcom,ipq5332-dwc3 + then: + properties: + clocks: + maxItems: 3 + clock-names: + items: + - const: core + - const: sleep + - const: mock_utmi + + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq8064-dwc3 + then: + properties: + clocks: + items: + - description: Master/Core clock, has to be >= 125 MHz + for SS operation and >= 60MHz for HS operation. + clock-names: + items: + - const: core + + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq9574-dwc3 + - qcom,msm8953-dwc3 + - qcom,msm8996-dwc3 + - qcom,msm8998-dwc3 + - qcom,qcs8300-dwc3 + - qcom,sa8775p-dwc3 + - qcom,sc7180-dwc3 + - qcom,sc7280-dwc3 + - qcom,sdm670-dwc3 + - qcom,sdm845-dwc3 + - qcom,sdx55-dwc3 + - qcom,sdx65-dwc3 + - qcom,sdx75-dwc3 + - qcom,sm6350-dwc3 + then: + properties: + clocks: + maxItems: 5 + clock-names: + items: + - const: cfg_noc + - const: core + - const: iface + - const: sleep + - const: mock_utmi + + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq6018-dwc3 + then: + properties: + clocks: + minItems: 3 + maxItems: 4 + clock-names: + oneOf: + - items: + - const: core + - const: sleep + - const: mock_utmi + - items: + - const: cfg_noc + - const: core + - const: sleep + - const: mock_utmi + + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq8074-dwc3 + - qcom,qdu1000-dwc3 + then: + properties: + clocks: + maxItems: 4 + clock-names: + items: + - const: cfg_noc + - const: core + - const: sleep + - const: mock_utmi + + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq5018-dwc3 + - qcom,msm8994-dwc3 + - qcom,qcs404-dwc3 + then: + properties: + clocks: + maxItems: 4 + clock-names: + items: + - const: core + - const: iface + - const: sleep + - const: mock_utmi + + - if: + properties: + compatible: + contains: + enum: + - qcom,sc8280xp-dwc3 + - qcom,sc8280xp-dwc3-mp + - qcom,x1e80100-dwc3 + - qcom,x1e80100-dwc3-mp + then: + properties: + clocks: + maxItems: 9 + clock-names: + items: + - const: cfg_noc + - const: core + - const: iface + - const: sleep + - const: mock_utmi + - const: noc_aggr + - const: noc_aggr_north + - const: noc_aggr_south + - const: noc_sys + + - if: + properties: + compatible: + contains: + enum: + - qcom,sdm660-dwc3 + then: + properties: + clocks: + minItems: 4 + maxItems: 5 + clock-names: + oneOf: + - items: + - const: cfg_noc + - const: core + - const: iface + - const: sleep + - const: mock_utmi + - items: + - const: cfg_noc + - const: core + - const: sleep + - const: mock_utmi + + - if: + properties: + compatible: + contains: + enum: + - qcom,qcm2290-dwc3 + - qcom,qcs615-dwc3 + - qcom,sar2130p-dwc3 + - qcom,sc8180x-dwc3 + - qcom,sc8180x-dwc3-mp + - qcom,sm6115-dwc3 + - qcom,sm6125-dwc3 + - qcom,sm8150-dwc3 + - qcom,sm8250-dwc3 + - qcom,sm8450-dwc3 + - qcom,sm8550-dwc3 + - qcom,sm8650-dwc3 + then: + properties: + clocks: + minItems: 6 + clock-names: + items: + - const: cfg_noc + - const: core + - const: iface + - const: sleep + - const: mock_utmi + - const: xo + + - if: + properties: + compatible: + contains: + enum: + - qcom,sm8350-dwc3 + then: + properties: + clocks: + minItems: 5 + maxItems: 6 + clock-names: + minItems: 5 + items: + - const: cfg_noc + - const: core + - const: iface + - const: sleep + - const: mock_utmi + - const: xo + + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq5018-dwc3 + - qcom,ipq6018-dwc3 + - qcom,ipq8074-dwc3 + - qcom,msm8953-dwc3 + - qcom,msm8998-dwc3 + then: + properties: + interrupts: + minItems: 3 + maxItems: 4 + interrupt-names: + minItems: 3 + items: + - const: dwc_usb3 + - const: pwr_event + - const: qusb2_phy + - const: ss_phy_irq + + - if: + properties: + compatible: + contains: + enum: + - qcom,msm8996-dwc3 + - qcom,qcs404-dwc3 + - qcom,sdm660-dwc3 + - qcom,sm6115-dwc3 + - qcom,sm6125-dwc3 + then: + properties: + interrupts: + minItems: 4 + maxItems: 5 + interrupt-names: + minItems: 4 + items: + - const: dwc_usb3 + - const: pwr_event + - const: qusb2_phy + - const: hs_phy_irq + - const: ss_phy_irq + + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq5332-dwc3 + then: + properties: + interrupts: + maxItems: 4 + interrupt-names: + items: + - const: dwc_usb3 + - const: pwr_event + - const: dp_hs_phy_irq + - const: dm_hs_phy_irq + + - if: + properties: + compatible: + contains: + enum: + - qcom,x1e80100-dwc3 + then: + properties: + interrupts: + maxItems: 5 + interrupt-names: + items: + - const: dwc_usb3 + - const: pwr_event + - const: dp_hs_phy_irq + - const: dm_hs_phy_irq + - const: ss_phy_irq + + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq4019-dwc3 + - qcom,ipq8064-dwc3 + - qcom,msm8994-dwc3 + - qcom,qcs615-dwc3 + - qcom,qcs8300-dwc3 + - qcom,qdu1000-dwc3 + - qcom,sa8775p-dwc3 + - qcom,sc7180-dwc3 + - qcom,sc7280-dwc3 + - qcom,sc8180x-dwc3 + - qcom,sc8280xp-dwc3 + - qcom,sdm670-dwc3 + - qcom,sdm845-dwc3 + - qcom,sdx55-dwc3 + - qcom,sdx65-dwc3 + - qcom,sdx75-dwc3 + - qcom,sm4250-dwc3 + - qcom,sm6350-dwc3 + - qcom,sm8150-dwc3 + - qcom,sm8250-dwc3 + - qcom,sm8350-dwc3 + - qcom,sm8450-dwc3 + - qcom,sm8550-dwc3 + - qcom,sm8650-dwc3 + then: + properties: + interrupts: + minItems: 5 + maxItems: 6 + interrupt-names: + minItems: 5 + items: + - const: dwc_usb3 + - const: pwr_event + - const: hs_phy_irq + - const: dp_hs_phy_irq + - const: dm_hs_phy_irq + - const: ss_phy_irq + + - if: + properties: + compatible: + contains: + enum: + - qcom,sc8180x-dwc3-mp + - qcom,x1e80100-dwc3-mp + then: + properties: + interrupts: + minItems: 11 + maxItems: 11 + interrupt-names: + items: + - const: dwc_usb3 + - const: pwr_event_1 + - const: pwr_event_2 + - const: hs_phy_1 + - const: hs_phy_2 + - const: dp_hs_phy_1 + - const: dm_hs_phy_1 + - const: dp_hs_phy_2 + - const: dm_hs_phy_2 + - const: ss_phy_1 + - const: ss_phy_2 + + - if: + properties: + compatible: + contains: + enum: + - qcom,sc8280xp-dwc3-mp + then: + properties: + interrupts: + minItems: 19 + maxItems: 19 + interrupt-names: + items: + - const: dwc_usb3 + - const: pwr_event_1 + - const: pwr_event_2 + - const: pwr_event_3 + - const: pwr_event_4 + - const: hs_phy_1 + - const: hs_phy_2 + - const: hs_phy_3 + - const: hs_phy_4 + - const: dp_hs_phy_1 + - const: dm_hs_phy_1 + - const: dp_hs_phy_2 + - const: dm_hs_phy_2 + - const: dp_hs_phy_3 + - const: dm_hs_phy_3 + - const: dp_hs_phy_4 + - const: dm_hs_phy_4 + - const: ss_phy_1 + - const: ss_phy_2 + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-sdm845.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + soc { + #address-cells = <2>; + #size-cells = <2>; + + usb@a600000 { + compatible = "qcom,sdm845-dwc3", "qcom,snps-dwc3"; + reg = <0 0x0a600000 0 0x100000>; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, <150000000>; + + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 489 IRQ_TYPE_EDGE_BOTH>, + <GIC_SPI 488 IRQ_TYPE_EDGE_BOTH>, + <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dwc_usb3", "pwr_event", "hs_phy_irq", + "dp_hs_phy_irq", "dm_hs_phy_irq", "ss_phy_irq"; + + power-domains = <&gcc USB30_PRIM_GDSC>; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + + iommus = <&apps_smmu 0x740 0>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + phys = <&usb_1_hsphy>, <&usb_1_ssphy>; + phy-names = "usb2-phy", "usb3-phy"; + }; + }; +... diff --git a/Documentation/devicetree/bindings/usb/realtek,rts5411.yaml b/Documentation/devicetree/bindings/usb/realtek,rts5411.yaml index 6577a61cc075..a020afaf2d6e 100644 --- a/Documentation/devicetree/bindings/usb/realtek,rts5411.yaml +++ b/Documentation/devicetree/bindings/usb/realtek,rts5411.yaml @@ -10,7 +10,7 @@ maintainers: - Matthias Kaehlcke <mka@chromium.org> allOf: - - $ref: usb-device.yaml# + - $ref: usb-hub.yaml# properties: compatible: @@ -19,61 +19,35 @@ properties: - usbbda,5411 - usbbda,411 - reg: true - - '#address-cells': - const: 1 - - '#size-cells': - const: 0 - vdd-supply: description: phandle to the regulator that provides power to the hub. - peer-hub: - $ref: /schemas/types.yaml#/definitions/phandle - description: - phandle to the peer hub on the controller. + peer-hub: true ports: $ref: /schemas/graph.yaml#/properties/ports - properties: - port@1: - $ref: /schemas/graph.yaml#/properties/port - description: - 1st downstream facing USB port - - port@2: + patternProperties: + '^port@': $ref: /schemas/graph.yaml#/properties/port - description: - 2nd downstream facing USB port - port@3: - $ref: /schemas/graph.yaml#/properties/port - description: - 3rd downstream facing USB port + properties: + reg: + minimum: 1 + maximum: 4 - port@4: - $ref: /schemas/graph.yaml#/properties/port - description: - 4th downstream facing USB port - -patternProperties: - '^.*@[1-4]$': - description: The hard wired USB devices - type: object - $ref: /schemas/usb/usb-device.yaml - additionalProperties: true +additionalProperties: + properties: + reg: + minimum: 1 + maximum: 4 required: - peer-hub - compatible - reg -additionalProperties: false - examples: - | usb { diff --git a/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml b/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml index 980f325341d4..6f4d41ba6ca7 100644 --- a/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml +++ b/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml @@ -27,6 +27,7 @@ properties: - renesas,usbhs-r9a07g044 # RZ/G2{L,LC} - renesas,usbhs-r9a07g054 # RZ/V2L - renesas,usbhs-r9a08g045 # RZ/G3S + - renesas,usbhs-r9a09g057 # RZ/V2H(P) - const: renesas,rzg2l-usbhs - items: @@ -127,11 +128,7 @@ allOf: properties: compatible: contains: - enum: - - renesas,usbhs-r9a07g043 - - renesas,usbhs-r9a07g044 - - renesas,usbhs-r9a07g054 - - renesas,usbhs-r9a08g045 + const: renesas,rzg2l-usbhs then: properties: interrupts: diff --git a/Documentation/devicetree/bindings/usb/richtek,rt1711h.yaml b/Documentation/devicetree/bindings/usb/richtek,rt1711h.yaml index 8da4d2ad1a91..ae611f7e57ca 100644 --- a/Documentation/devicetree/bindings/usb/richtek,rt1711h.yaml +++ b/Documentation/devicetree/bindings/usb/richtek,rt1711h.yaml @@ -30,6 +30,9 @@ properties: interrupts: maxItems: 1 + vbus-supply: + description: VBUS power supply + wakeup-source: type: boolean diff --git a/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml b/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml index a21cc098542d..fd1b13c0ed6b 100644 --- a/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml +++ b/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml @@ -18,7 +18,7 @@ description: Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml Type-C PHY - Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt + Documentation/devicetree/bindings/phy/rockchip,rk3399-typec-phy.yaml select: properties: @@ -26,6 +26,7 @@ select: contains: enum: - rockchip,rk3328-dwc3 + - rockchip,rk3562-dwc3 - rockchip,rk3568-dwc3 - rockchip,rk3576-dwc3 - rockchip,rk3588-dwc3 @@ -37,6 +38,7 @@ properties: items: - enum: - rockchip,rk3328-dwc3 + - rockchip,rk3562-dwc3 - rockchip,rk3568-dwc3 - rockchip,rk3576-dwc3 - rockchip,rk3588-dwc3 @@ -72,6 +74,7 @@ properties: - enum: - grf_clk - utmi + - pipe - const: pipe power-domains: @@ -115,6 +118,22 @@ allOf: properties: compatible: contains: + const: rockchip,rk3562-dwc3 + then: + properties: + clocks: + minItems: 4 + maxItems: 4 + clock-names: + items: + - const: ref_clk + - const: suspend_clk + - const: bus_clk + - const: pipe + - if: + properties: + compatible: + contains: enum: - rockchip,rk3568-dwc3 - rockchip,rk3576-dwc3 diff --git a/Documentation/devicetree/bindings/usb/samsung,exynos-dwc3.yaml b/Documentation/devicetree/bindings/usb/samsung,exynos-dwc3.yaml index 2b3430cebe99..6d39e5066944 100644 --- a/Documentation/devicetree/bindings/usb/samsung,exynos-dwc3.yaml +++ b/Documentation/devicetree/bindings/usb/samsung,exynos-dwc3.yaml @@ -11,12 +11,19 @@ maintainers: properties: compatible: - enum: - - google,gs101-dwusb3 - - samsung,exynos5250-dwusb3 - - samsung,exynos5433-dwusb3 - - samsung,exynos7-dwusb3 - - samsung,exynos850-dwusb3 + oneOf: + - enum: + - google,gs101-dwusb3 + - samsung,exynos2200-dwusb3 + - samsung,exynos5250-dwusb3 + - samsung,exynos5433-dwusb3 + - samsung,exynos7-dwusb3 + - samsung,exynos7870-dwusb3 + - samsung,exynos850-dwusb3 + - samsung,exynosautov920-dwusb3 + - items: + - const: samsung,exynos990-dwusb3 + - const: samsung,exynos850-dwusb3 '#address-cells': const: 1 @@ -52,7 +59,6 @@ required: - clock-names - ranges - '#size-cells' - - vdd10-supply - vdd33-supply allOf: @@ -72,6 +78,21 @@ allOf: - const: susp_clk - const: link_aclk - const: link_pclk + required: + - vdd10-supply + + - if: + properties: + compatible: + contains: + const: samsung,exynos2200-dwusb3 + then: + properties: + clocks: + maxItems: 1 + clock-names: + items: + - const: link_aclk - if: properties: @@ -86,6 +107,8 @@ allOf: clock-names: items: - const: usbdrd30 + required: + - vdd10-supply - if: properties: @@ -103,6 +126,8 @@ allOf: - const: susp_clk - const: phyclk - const: pipe_pclk + required: + - vdd10-supply - if: properties: @@ -119,6 +144,24 @@ allOf: - const: usbdrd30 - const: usbdrd30_susp_clk - const: usbdrd30_axius_clk + required: + - vdd10-supply + + - if: + properties: + compatible: + contains: + const: samsung,exynos7870-dwusb3 + then: + properties: + clocks: + minItems: 3 + maxItems: 3 + clock-names: + items: + - const: bus_early + - const: ref + - const: ctrl - if: properties: @@ -134,6 +177,23 @@ allOf: items: - const: bus_early - const: ref + required: + - vdd10-supply + + - if: + properties: + compatible: + contains: + const: samsung,exynosautov920-dwusb3 + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: ref + - const: susp_clk additionalProperties: false diff --git a/Documentation/devicetree/bindings/usb/smsc,usb3503.yaml b/Documentation/devicetree/bindings/usb/smsc,usb3503.yaml index 6156dc26e65c..18e35122dc1f 100644 --- a/Documentation/devicetree/bindings/usb/smsc,usb3503.yaml +++ b/Documentation/devicetree/bindings/usb/smsc,usb3503.yaml @@ -106,54 +106,54 @@ additionalProperties: false examples: - | - i2c { - #address-cells = <1>; - #size-cells = <0>; - - usb-hub@8 { - compatible = "smsc,usb3503"; - reg = <0x08>; - connect-gpios = <&gpx3 0 1>; - disabled-ports = <2 3>; - intn-gpios = <&gpx3 4 1>; - reset-gpios = <&gpx3 5 1>; - initial-mode = <1>; - clocks = <&clks 80>; - clock-names = "refclk"; - }; - }; + i2c { + #address-cells = <1>; + #size-cells = <0>; + + usb-hub@8 { + compatible = "smsc,usb3503"; + reg = <0x08>; + connect-gpios = <&gpx3 0 1>; + disabled-ports = <2 3>; + intn-gpios = <&gpx3 4 1>; + reset-gpios = <&gpx3 5 1>; + initial-mode = <1>; + clocks = <&clks 80>; + clock-names = "refclk"; + }; + }; - | - i2c { - #address-cells = <1>; - #size-cells = <0>; - - usb-hub@8 { - compatible = "smsc,usb3803"; - reg = <0x08>; - connect-gpios = <&gpx3 0 1>; - disabled-ports = <2 3>; - intn-gpios = <&gpx3 4 1>; - reset-gpios = <&gpx3 5 1>; - bypass-gpios = <&gpx3 6 1>; - initial-mode = <3>; - clocks = <&clks 80>; - clock-names = "refclk"; - }; - }; + i2c { + #address-cells = <1>; + #size-cells = <0>; + + usb-hub@8 { + compatible = "smsc,usb3803"; + reg = <0x08>; + connect-gpios = <&gpx3 0 1>; + disabled-ports = <2 3>; + intn-gpios = <&gpx3 4 1>; + reset-gpios = <&gpx3 5 1>; + bypass-gpios = <&gpx3 6 1>; + initial-mode = <3>; + clocks = <&clks 80>; + clock-names = "refclk"; + }; + }; - | - #include <dt-bindings/gpio/gpio.h> - - usb-hub { - /* I2C is not connected */ - compatible = "smsc,usb3503"; - initial-mode = <1>; /* initialize in HUB mode */ - disabled-ports = <1>; - intn-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ - reset-gpios = <&pio 4 16 GPIO_ACTIVE_LOW>; /* PE16 */ - connect-gpios = <&pio 4 17 GPIO_ACTIVE_HIGH>; /* PE17 */ - refclk-frequency = <19200000>; - }; + #include <dt-bindings/gpio/gpio.h> + + usb-hub { + /* I2C is not connected */ + compatible = "smsc,usb3503"; + initial-mode = <1>; /* initialize in HUB mode */ + disabled-ports = <1>; + intn-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ + reset-gpios = <&pio 4 16 GPIO_ACTIVE_LOW>; /* PE16 */ + connect-gpios = <&pio 4 17 GPIO_ACTIVE_HIGH>; /* PE17 */ + refclk-frequency = <19200000>; + }; ... diff --git a/Documentation/devicetree/bindings/usb/snps,dwc3-common.yaml b/Documentation/devicetree/bindings/usb/snps,dwc3-common.yaml index c956053fd036..6c0b8b653824 100644 --- a/Documentation/devicetree/bindings/usb/snps,dwc3-common.yaml +++ b/Documentation/devicetree/bindings/usb/snps,dwc3-common.yaml @@ -65,6 +65,17 @@ properties: mode. type: boolean + snps,reserved-endpoints: + description: + Reserve endpoints for other needs, e.g, for tracing control and output. + When set, the driver will avoid using them for the regular USB transfers. + $ref: /schemas/types.yaml#/definitions/uint8-array + minItems: 1 + maxItems: 30 + items: + minimum: 2 + maximum: 31 + snps,dis-start-transfer-quirk: description: When set, disable isoc START TRANSFER command failure SW work-around @@ -379,6 +390,12 @@ properties: maximum: 8 default: 1 + connector: + $ref: /schemas/connector/usb-connector.yaml# + description: Connector for dual role switch + type: object + unevaluatedProperties: false + port: $ref: /schemas/graph.yaml#/properties/port description: diff --git a/Documentation/devicetree/bindings/usb/ti,usb8041.yaml b/Documentation/devicetree/bindings/usb/ti,usb8041.yaml index bce730a5e237..5e3eae9c2961 100644 --- a/Documentation/devicetree/bindings/usb/ti,usb8041.yaml +++ b/Documentation/devicetree/bindings/usb/ti,usb8041.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/usb/ti,usb8041.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: TI USB8041 USB 3.0 hub controller +title: TI USB8041 and USB8044 USB 3.0 hub controllers maintainers: - Alexander Stein <alexander.stein@ew.tq-group.com> @@ -17,6 +17,8 @@ properties: enum: - usb451,8140 - usb451,8142 + - usb451,8440 + - usb451,8442 reg: true diff --git a/Documentation/devicetree/bindings/usb/usb-device.yaml b/Documentation/devicetree/bindings/usb/usb-device.yaml index da890ee60ce6..09fceb469f10 100644 --- a/Documentation/devicetree/bindings/usb/usb-device.yaml +++ b/Documentation/devicetree/bindings/usb/usb-device.yaml @@ -28,7 +28,8 @@ description: | properties: compatible: - pattern: "^usb[0-9a-f]{1,4},[0-9a-f]{1,4}$" + contains: + pattern: "^usb[0-9a-f]{1,4},[0-9a-f]{1,4}$" description: Device nodes or combined nodes. "usbVID,PID", where VID is the vendor id and PID the product id. The textual representation of VID and PID shall be in lower case @@ -39,8 +40,10 @@ properties: reg: description: the number of the USB hub port or the USB host-controller - port to which this device is attached. The range is 1-255. - maxItems: 1 + port to which this device is attached. + items: + - minimum: 1 + maximum: 255 "#address-cells": description: should be 1 for hub nodes with device nodes, diff --git a/Documentation/devicetree/bindings/usb/usb-hub.yaml b/Documentation/devicetree/bindings/usb/usb-hub.yaml new file mode 100644 index 000000000000..5238ab105763 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/usb-hub.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/usb-hub.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Generic USB Hub + +maintainers: + - Pin-yen Lin <treapking@chromium.org> + +allOf: + - $ref: usb-device.yaml# + +properties: + '#address-cells': + const: 1 + + peer-hub: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle to the peer hub on the controller. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + description: + The downstream facing USB ports + + patternProperties: + "^port@[1-9a-f][0-9a-f]*$": + $ref: /schemas/graph.yaml#/properties/port + +patternProperties: + '^.*@[1-9a-f][0-9a-f]*$': + description: The hard wired USB devices + type: object + $ref: /schemas/usb/usb-device.yaml + additionalProperties: true + +required: + - compatible + - reg + +additionalProperties: true + +examples: + - | + usb { + #address-cells = <1>; + #size-cells = <0>; + + /* 2.0 hub on port 1 */ + hub_2_0: hub@1 { + compatible = "usb123,4567"; + reg = <1>; + peer-hub = <&hub_3_0>; + #address-cells = <1>; + #size-cells = <0>; + /* USB 2.0 device on port 5 */ + device@5 { + reg = <5>; + compatible = "usb765,4321"; + }; + }; + + /* 3.0 hub on port 2 */ + hub_3_0: hub@2 { + compatible = "usb123,abcd"; + reg = <2>; + peer-hub = <&hub_2_0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + /* Type-A connector on port 3 */ + port@3 { + reg = <3>; + endpoint { + remote-endpoint = <&usb_a0_ss>; + }; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/usb/usb-switch.yaml b/Documentation/devicetree/bindings/usb/usb-switch.yaml index da76118e73a5..896201912630 100644 --- a/Documentation/devicetree/bindings/usb/usb-switch.yaml +++ b/Documentation/devicetree/bindings/usb/usb-switch.yaml @@ -26,11 +26,24 @@ properties: type: boolean port: - $ref: /schemas/graph.yaml#/properties/port + $ref: /schemas/graph.yaml#/$defs/port-base description: A port node to link the device to a TypeC controller for the purpose of handling altmode muxing and orientation switching. + properties: + endpoint: + $ref: /schemas/graph.yaml#/$defs/endpoint-base + unevaluatedProperties: false + properties: + data-lanes: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 8 + uniqueItems: true + items: + maximum: 8 + ports: $ref: /schemas/graph.yaml#/properties/ports properties: diff --git a/Documentation/devicetree/bindings/usb/xlnx,usb2.yaml b/Documentation/devicetree/bindings/usb/xlnx,usb2.yaml index a7f75fe36665..f295aa9d9ee7 100644 --- a/Documentation/devicetree/bindings/usb/xlnx,usb2.yaml +++ b/Documentation/devicetree/bindings/usb/xlnx,usb2.yaml @@ -7,7 +7,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Xilinx udc controller maintainers: - - Mubin Sayyed <mubin.sayyed@amd.com> - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> properties: diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index b5979832ddce..5d2a7a8d3ac6 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -18,7 +18,7 @@ patternProperties: # DO NOT ADD NEW PROPERTIES TO THIS LIST "^(at25|bm|devbus|dmacap|dsa|exynos|fsi[ab]|gpio-fan|gpio-key|gpio|gpmc|hdmi|i2c-gpio),.*": true "^(keypad|m25p|max8952|max8997|max8998|mpmc),.*": true - "^(pinctrl-single|#pinctrl-single|PowerPC),.*": true + "^(pciclass|pinctrl-single|#pinctrl-single|PowerPC),.*": true "^(pl022|pxa-mmc|rcar_sound|rotary-encoder|s5m8767|sdhci),.*": true "^(simple-audio-card|st-plgpio|st-spics|ts),.*": true @@ -129,6 +129,8 @@ patternProperties: description: Andes Technology Corporation "^anvo,.*": description: Anvo-Systems Dresden GmbH + "^aoly,.*": + description: Shenzhen Aoly Technology Co., Ltd. "^aosong,.*": description: Guangzhou Aosong Electronic Co., Ltd. "^apm,.*": @@ -147,6 +149,8 @@ patternProperties: description: Arctic Sand "^arcx,.*": description: arcx Inc. / Archronix Inc. + "^ariaboard,.*": + description: Shanghai Novotech Co., Ltd. (Ariaboard) "^aries,.*": description: Aries Embedded GmbH "^arm,.*": @@ -338,6 +342,8 @@ patternProperties: description: Crystalfontz America, Inc. "^csky,.*": description: Hangzhou C-SKY Microsystems Co., Ltd + "^csot,.*": + description: Guangzhou China Star Optoelectronics Technology Co., Ltd "^csq,.*": description: Shenzen Chuangsiqi Technology Co.,Ltd. "^ctera,.*": @@ -428,6 +434,8 @@ patternProperties: description: EBV Elektronik "^eckelmann,.*": description: Eckelmann AG + "^econet,.*": + description: EcoNet (HK) Limited "^edgeble,.*": description: Edgeble AI Technologies Pvt. Ltd. "^edimax,.*": @@ -860,6 +868,8 @@ patternProperties: description: Linux-specific binding "^linx,.*": description: Linx Technologies + "^liontron,.*": + description: Shenzhen Liontron Technology Co., Ltd "^liteon,.*": description: LITE-ON Technology Corp. "^litex,.*": @@ -1033,6 +1043,8 @@ patternProperties: description: Neofidelity Inc. "^neonode,.*": description: Neonode Inc. + "^netcube,.*": + description: NetCube Systems Austria "^netgear,.*": description: NETGEAR "^netlogic,.*": @@ -1152,6 +1164,8 @@ patternProperties: description: Parallax Inc. "^pda,.*": description: Precision Design Associates, Inc. + "^pegatron,.*": + description: Pegatron Corporation "^pericom,.*": description: Pericom Technology Inc. "^pervasive,.*": @@ -1204,6 +1218,8 @@ patternProperties: description: Primux Trading, S.L. "^probox2,.*": description: PROBOX2 (by W2COMP Co., Ltd.) + "^pri,.*": + description: Priva "^prt,.*": description: Protonic Holland "^pulsedlight,.*": @@ -1254,6 +1270,8 @@ patternProperties: description: Renesas Electronics Corporation "^rervision,.*": description: Shenzhen Rervision Technology Co., Ltd. + "^retronix,.*": + description: Retronix Technology Inc. "^revotics,.*": description: Revolution Robotics, Inc. (Revotics) "^rex,.*": @@ -1269,7 +1287,7 @@ patternProperties: "^riscv,.*": description: RISC-V Foundation "^rockchip,.*": - description: Fuzhou Rockchip Electronics Co., Ltd + description: Rockchip Electronics Co., Ltd. "^rocktech,.*": description: ROCKTECH DISPLAYS LIMITED "^rohm,.*": @@ -1388,6 +1406,8 @@ patternProperties: description: SKOV A/S "^skyworks,.*": description: Skyworks Solutions, Inc. + "^smartfiber,.*": + description: ShenZhen Smartfiber Technology Co, Ltd. "^smartlabs,.*": description: SmartLabs LLC "^smartrg,.*": @@ -1486,6 +1506,8 @@ patternProperties: description: Toby Churchill Ltd. "^tcs,.*": description: Shenzhen City Tang Cheng Technology Co., Ltd. + "^tcu,.*": + description: TC Unterhaltungselektronik AG "^tdo,.*": description: Shangai Top Display Optoelectronics Co., Ltd "^team-source-display,.*": @@ -1599,6 +1621,8 @@ patternProperties: description: Universal Scientific Industrial Co., Ltd. "^usr,.*": description: U.S. Robotics Corporation + "^ultratronik,.*": + description: Ultratronik GmbH "^utoo,.*": description: Aigo Digital Technology Co., Ltd. "^v3,.*": @@ -1681,6 +1705,8 @@ patternProperties: description: Wingtech Technology Co., Ltd. "^winlink,.*": description: WinLink Co., Ltd + "^winsen,.*": + description: Winsen Corp. "^winstar,.*": description: Winstar Display Corp. "^wirelesstag,.*": @@ -1739,6 +1765,10 @@ patternProperties: description: Shenzhen Yashi Changhua Intelligent Technology Co., Ltd. "^ysoft,.*": description: Y Soft Corporation a.s. + "^yuridenki,.*": + description: Yuridenki-Shokai Co. Ltd. + "^yuzukihd,.*": + description: YuzukiHD Open Source Hardware "^zarlink,.*": description: Zarlink Semiconductor "^zealz,.*": diff --git a/Documentation/devicetree/bindings/virtio/pci-iommu.yaml b/Documentation/devicetree/bindings/virtio/pci-iommu.yaml index 972a785a42de..8bd6ad72ac7a 100644 --- a/Documentation/devicetree/bindings/virtio/pci-iommu.yaml +++ b/Documentation/devicetree/bindings/virtio/pci-iommu.yaml @@ -20,6 +20,9 @@ description: | virtio-iommu node doesn't have an "iommus" property, and is omitted from the iommu-map property of the root complex. +allOf: + - $ref: /schemas/pci/pci-device.yaml# + properties: # If compatible is present, it should contain the vendor and device ID # according to the PCI Bus Binding specification. Since PCI provides @@ -33,12 +36,7 @@ properties: - const: pci1af4,1057 reg: - description: | - PCI address of the IOMMU. As defined in the PCI Bus Binding - reference, the reg property is a five-cell address encoded as (phys.hi - phys.mid phys.lo size.hi size.lo). phys.hi should contain the device's - BDF as 0b00000000 bbbbbbbb dddddfff 00000000. The other cells should be - zero. See Documentation/devicetree/bindings/pci/pci.txt + maxItems: 1 '#iommu-cells': const: 1 diff --git a/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml b/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml index 64c8f7393809..b35ac03d5172 100644 --- a/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml @@ -32,6 +32,7 @@ properties: - items: - const: allwinner,sun20i-d1-wdt-reset - const: allwinner,sun20i-d1-wdt + - const: allwinner,sun55i-a523-wdt reg: maxItems: 1 @@ -60,6 +61,7 @@ if: - allwinner,sun20i-d1-wdt-reset - allwinner,sun50i-r329-wdt - allwinner,sun50i-r329-wdt-reset + - allwinner,sun55i-a523-wdt then: properties: diff --git a/Documentation/devicetree/bindings/watchdog/fsl,scu-wdt.yaml b/Documentation/devicetree/bindings/watchdog/fsl,scu-wdt.yaml index 8b7aa922249b..1d9f15ec6657 100644 --- a/Documentation/devicetree/bindings/watchdog/fsl,scu-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/fsl,scu-wdt.yaml @@ -20,6 +20,7 @@ properties: items: - enum: - fsl,imx8dxl-sc-wdt + - fsl,imx8qm-sc-wdt - fsl,imx8qxp-sc-wdt - const: fsl,imx-sc-wdt diff --git a/Documentation/devicetree/bindings/watchdog/fsl-imx-wdt.yaml b/Documentation/devicetree/bindings/watchdog/fsl-imx-wdt.yaml index 0da953cb7127..8a6c3a75a547 100644 --- a/Documentation/devicetree/bindings/watchdog/fsl-imx-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/fsl-imx-wdt.yaml @@ -35,6 +35,7 @@ properties: - fsl,imx8mp-wdt - fsl,imx8mq-wdt - fsl,ls1012a-wdt + - fsl,ls1021a-wdt - fsl,ls1043a-wdt - fsl,vf610-wdt - const: fsl,imx21-wdt @@ -102,6 +103,7 @@ allOf: contains: enum: - fsl,ls1012a-wdt + - fsl,ls1021a-wdt - fsl,ls1043a-wdt then: properties: diff --git a/Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.yaml b/Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.yaml index a09686b3030d..6ec391b9723a 100644 --- a/Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.yaml @@ -22,6 +22,10 @@ properties: - const: fsl,imx8ulp-wdt - const: fsl,imx7ulp-wdt - const: fsl,imx93-wdt + - items: + - enum: + - fsl,imx94-wdt + - const: fsl,imx93-wdt reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/watchdog/nxp,s32g2-swt.yaml b/Documentation/devicetree/bindings/watchdog/nxp,s32g2-swt.yaml new file mode 100644 index 000000000000..8f168a05b50c --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/nxp,s32g2-swt.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/nxp,s32g2-swt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP Software Watchdog Timer (SWT) + +maintainers: + - Daniel Lezcano <daniel.lezcano@kernel.org> + +allOf: + - $ref: watchdog.yaml# + +properties: + compatible: + oneOf: + - const: nxp,s32g2-swt + - items: + - const: nxp,s32g3-swt + - const: nxp,s32g2-swt + + reg: + maxItems: 1 + + clocks: + items: + - description: Counter clock + - description: Module clock + - description: Register clock + + clock-names: + items: + - const: counter + - const: module + - const: register + +required: + - compatible + - reg + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + watchdog@40100000 { + compatible = "nxp,s32g2-swt"; + reg = <0x40100000 0x1000>; + clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3c>; + clock-names = "counter", "module", "register"; + timeout-sec = <10>; + }; diff --git a/Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml b/Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml index 29ada89fdcdc..78874b90c88c 100644 --- a/Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml @@ -75,6 +75,12 @@ properties: - renesas,r8a779h0-wdt # R-Car V4M - const: renesas,rcar-gen4-wdt # R-Car Gen4 + - items: + - enum: + - renesas,r9a09g047-wdt # RZ/G3E + - renesas,r9a09g056-wdt # RZ/V2N + - const: renesas,r9a09g057-wdt # RZ/V2H(P) + - const: renesas,r9a09g057-wdt # RZ/V2H(P) reg: diff --git a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml index d175ae968336..53fc64f5b56d 100644 --- a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml @@ -25,6 +25,7 @@ properties: - samsung,exynos5420-wdt # for Exynos5420 - samsung,exynos7-wdt # for Exynos7 - samsung,exynos850-wdt # for Exynos850 + - samsung,exynos990-wdt # for Exynos990 - samsung,exynosautov9-wdt # for Exynosautov9 - samsung,exynosautov920-wdt # for Exynosautov920 - items: @@ -49,14 +50,14 @@ properties: samsung,cluster-index: $ref: /schemas/types.yaml#/definitions/uint32 description: - Index of CPU cluster on which watchdog is running (in case of Exynos850 - or Google gs101). + Index of CPU cluster on which watchdog is running (in case of Exynos850, + Exynos990 or Google gs101). samsung,syscon-phandle: $ref: /schemas/types.yaml#/definitions/phandle description: Phandle to the PMU system controller node (in case of Exynos5250, - Exynos5420, Exynos7, Exynos850 and gs101). + Exynos5420, Exynos7, Exynos850, Exynos990 and gs101). required: - compatible @@ -77,6 +78,7 @@ allOf: - samsung,exynos5420-wdt - samsung,exynos7-wdt - samsung,exynos850-wdt + - samsung,exynos990-wdt - samsung,exynosautov9-wdt - samsung,exynosautov920-wdt then: @@ -89,6 +91,7 @@ allOf: enum: - google,gs101-wdt - samsung,exynos850-wdt + - samsung,exynos990-wdt - samsung,exynosautov9-wdt - samsung,exynosautov920-wdt then: @@ -102,7 +105,7 @@ allOf: - const: watchdog - const: watchdog_src samsung,cluster-index: - enum: [0, 1] + enum: [0, 1, 2] required: - samsung,cluster-index else: diff --git a/Documentation/devicetree/bindings/watchdog/snps,dw-wdt.yaml b/Documentation/devicetree/bindings/watchdog/snps,dw-wdt.yaml index 1efefd741c06..ef088e0f6917 100644 --- a/Documentation/devicetree/bindings/watchdog/snps,dw-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/snps,dw-wdt.yaml @@ -28,6 +28,7 @@ properties: - rockchip,rk3328-wdt - rockchip,rk3368-wdt - rockchip,rk3399-wdt + - rockchip,rk3562-wdt - rockchip,rk3568-wdt - rockchip,rk3576-wdt - rockchip,rk3588-wdt diff --git a/Documentation/devicetree/bindings/writing-schema.rst b/Documentation/devicetree/bindings/writing-schema.rst index eb8ced400c7e..fc73072f12fc 100644 --- a/Documentation/devicetree/bindings/writing-schema.rst +++ b/Documentation/devicetree/bindings/writing-schema.rst @@ -117,9 +117,14 @@ additionalProperties / unevaluatedProperties should be allowed. * additionalProperties: true - Rare case, used for schemas implementing common set of properties. Such - schemas are supposed to be referenced by other schemas, which then use - 'unevaluatedProperties: false'. Typically bus or common-part schemas. + - Top-level part: + Rare case, used for schemas implementing common set of properties. Such + schemas are supposed to be referenced by other schemas, which then use + 'unevaluatedProperties: false'. Typically bus or common-part schemas. + - Nested node: + When listing only the expected compatible of the nested node and there + is an another schema matching that compatible which ends with one of + two above cases ('false'). examples Optional. A list of one or more DTS hunks implementing this binding only. diff --git a/Documentation/devicetree/bindings/xilinx.txt b/Documentation/devicetree/bindings/xilinx.txt index 28199b31fe5e..0ee9de99b3ae 100644 --- a/Documentation/devicetree/bindings/xilinx.txt +++ b/Documentation/devicetree/bindings/xilinx.txt @@ -102,15 +102,6 @@ Default is <d#1024 d#480>. - rotate-display (empty) : rotate display 180 degrees. - ii) Xilinx SystemACE - - The Xilinx SystemACE device is used to program FPGAs from an FPGA - bitstream stored on a CF card. It can also be used as a generic CF - interface device. - - Optional properties: - - 8-bit (empty) : Set this property for SystemACE in 8 bit mode - iii) Xilinx EMAC and Xilinx TEMAC Xilinx Ethernet devices. In addition to general xilinx properties @@ -118,13 +109,6 @@ property, and may include other common network device properties like local-mac-address. - iv) Xilinx Uartlite - - Xilinx uartlite devices are simple fixed speed serial ports. - - Required properties: - - current-speed : Baud rate of uartlite - v) Xilinx hwicap Xilinx hwicap devices provide access to the configuration logic @@ -141,16 +125,6 @@ - compatible : should contain "xlnx,xps-hwicap-1.00.a" or "xlnx,opb-hwicap-1.00.b". - vi) Xilinx Uart 16550 - - Xilinx UART 16550 devices are very similar to the NS16550 but with - different register spacing and an offset from the base address. - - Required properties: - - clock-frequency : Frequency of the clock input - - reg-offset : A value of 3 is required - - reg-shift : A value of 2 is required - vii) Xilinx USB Host controller The Xilinx USB host controller is EHCI compatible but with a different diff --git a/Documentation/devicetree/overlay-notes.rst b/Documentation/devicetree/overlay-notes.rst index e139f22b363e..35e79242af9a 100644 --- a/Documentation/devicetree/overlay-notes.rst +++ b/Documentation/devicetree/overlay-notes.rst @@ -38,10 +38,10 @@ Lets take an example where we have a foo board with the following base tree:: }; ---- foo.dts --------------------------------------------------------------- -The overlay bar.dts, +The overlay bar.dtso, :: - ---- bar.dts - overlay target location by label ---------------------------- + ---- bar.dtso - overlay target location by label --------------------------- /dts-v1/; /plugin/; &ocp { @@ -51,7 +51,7 @@ The overlay bar.dts, ... /* various properties and child nodes */ }; }; - ---- bar.dts --------------------------------------------------------------- + ---- bar.dtso -------------------------------------------------------------- when loaded (and resolved as described in [1]) should result in foo+bar.dts:: @@ -88,9 +88,9 @@ in the base DT. In this case, the target path can be provided. The target location by label syntax is preferred because the overlay can be applied to any base DT containing the label, no matter where the label occurs in the DT. -The above bar.dts example modified to use target path syntax is:: +The above bar.dtso example modified to use target path syntax is:: - ---- bar.dts - overlay target location by explicit path -------------------- + ---- bar.dtso - overlay target location by explicit path ------------------- /dts-v1/; /plugin/; &{/ocp} { @@ -100,7 +100,7 @@ The above bar.dts example modified to use target path syntax is:: ... /* various properties and child nodes */ } }; - ---- bar.dts --------------------------------------------------------------- + ---- bar.dtso -------------------------------------------------------------- Overlay in-kernel API |