diff options
Diffstat (limited to 'Documentation/devicetree/bindings')
8 files changed, 122 insertions, 27 deletions
diff --git a/Documentation/devicetree/bindings/power/pd-samsung.txt b/Documentation/devicetree/bindings/power/pd-samsung.txt index 4e947372a693..7eb9674e9687 100644 --- a/Documentation/devicetree/bindings/power/pd-samsung.txt +++ b/Documentation/devicetree/bindings/power/pd-samsung.txt @@ -6,12 +6,15 @@ to gate power to one or more peripherals on the processor. Required Properties: - compatible: should be one of the following. * samsung,exynos4210-pd - for exynos4210 type power domain. + * samsung,exynos5433-pd - for exynos5433 type power domain. - reg: physical base address of the controller and length of memory mapped region. - #power-domain-cells: number of cells in power domain specifier; must be 0. Optional Properties: +- label: Human readable string with domain name. Will be visible in userspace + to let user to distinguish between multiple domains in SoC. - clocks: List of clock handles. The parent clocks of the input clocks to the devices in this power domain are set to oscclk before power gating and restored back after powering on a domain. This is required for @@ -38,6 +41,7 @@ Example: compatible = "samsung,exynos4210-pd"; reg = <0x10023C00 0x10>; #power-domain-cells = <0>; + label = "LCD0"; }; mfc_pd: power-domain@10044060 { @@ -46,6 +50,7 @@ Example: clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_USER_ACLK333>; clock-names = "oscclk", "clk0"; #power-domain-cells = <0>; + label = "MFC"; }; See Documentation/devicetree/bindings/power/power_domain.txt for description diff --git a/Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.txt b/Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.txt new file mode 100644 index 000000000000..2bf3344b2a02 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.txt @@ -0,0 +1,43 @@ +Hisilicon System Reset Controller +====================================== + +Please also refer to reset.txt in this directory for common reset +controller binding usage. + +The reset controller registers are part of the system-ctl block on +hi3660 SoC. + +Required properties: +- compatible: should be + "hisilicon,hi3660-reset" +- hisi,rst-syscon: phandle of the reset's syscon. +- #reset-cells : Specifies the number of cells needed to encode a + reset source. The type shall be a <u32> and the value shall be 2. + + Cell #1 : offset of the reset assert control + register from the syscon register base + offset + 4: deassert control register + offset + 8: status control register + Cell #2 : bit position of the reset in the reset control register + +Example: + iomcu: iomcu@ffd7e000 { + compatible = "hisilicon,hi3660-iomcu", "syscon"; + reg = <0x0 0xffd7e000 0x0 0x1000>; + }; + + iomcu_rst: iomcu_rst_controller { + compatible = "hisilicon,hi3660-reset"; + hisi,rst-syscon = <&iomcu>; + #reset-cells = <2>; + }; + +Specifying reset lines connected to IP modules +============================================== +example: + + i2c0: i2c@..... { + ... + resets = <&iomcu_rst 0x20 3>; /* offset: 0x20; bit: 3 */ + ... + }; diff --git a/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt b/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt index 164c7f34c451..c516d24959f2 100644 --- a/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt +++ b/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt @@ -63,7 +63,7 @@ Example: -------- The following example demonstrates a syscon node, the reset controller node using the syscon node, and a consumer (a DSP device) on the TI Keystone 2 -Edison SoC. +66AK2E SoC. / { soc { @@ -71,13 +71,13 @@ Edison SoC. compatible = "syscon", "simple-mfd"; reg = <0x02350000 0x1000>; - pscrst: psc-reset { + pscrst: reset-controller { compatible = "ti,k2e-pscrst", "ti,syscon-reset"; #reset-cells = <1>; ti,reset-bits = < - 0xa3c 8 0xa3c 8 0x83c 8 (ASSERT_SET|DEASSERT_CLEAR|STATUS_SET) /* 0: pcrst-dsp0 */ - 0xa40 5 0xa44 3 0 0 (ASSERT_SET|DEASSERT_CLEAR|STATUS_NONE) /* 1: pcrst-example */ + 0xa3c 8 0xa3c 8 0x83c 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 0: dsp0 */ + 0xa40 5 0xa44 3 0 0 (ASSERT_SET | DEASSERT_CLEAR | STATUS_NONE) /* 1: example */ >; }; }; diff --git a/Documentation/devicetree/bindings/reset/uniphier-reset.txt b/Documentation/devicetree/bindings/reset/uniphier-reset.txt index 5020524cddeb..83ab0f599c40 100644 --- a/Documentation/devicetree/bindings/reset/uniphier-reset.txt +++ b/Documentation/devicetree/bindings/reset/uniphier-reset.txt @@ -6,14 +6,14 @@ System reset Required properties: - compatible: should be one of the following: - "socionext,uniphier-sld3-reset" - for sLD3 SoC. - "socionext,uniphier-ld4-reset" - for LD4 SoC. - "socionext,uniphier-pro4-reset" - for Pro4 SoC. - "socionext,uniphier-sld8-reset" - for sLD8 SoC. - "socionext,uniphier-pro5-reset" - for Pro5 SoC. - "socionext,uniphier-pxs2-reset" - for PXs2/LD6b SoC. - "socionext,uniphier-ld11-reset" - for LD11 SoC. - "socionext,uniphier-ld20-reset" - for LD20 SoC. + "socionext,uniphier-sld3-reset" - for sLD3 SoC + "socionext,uniphier-ld4-reset" - for LD4 SoC + "socionext,uniphier-pro4-reset" - for Pro4 SoC + "socionext,uniphier-sld8-reset" - for sLD8 SoC + "socionext,uniphier-pro5-reset" - for Pro5 SoC + "socionext,uniphier-pxs2-reset" - for PXs2/LD6b SoC + "socionext,uniphier-ld11-reset" - for LD11 SoC + "socionext,uniphier-ld20-reset" - for LD20 SoC - #reset-cells: should be 1. Example: @@ -37,14 +37,15 @@ Media I/O (MIO) reset, SD reset Required properties: - compatible: should be one of the following: - "socionext,uniphier-sld3-mio-reset" - for sLD3 SoC. - "socionext,uniphier-ld4-mio-reset" - for LD4 SoC. - "socionext,uniphier-pro4-mio-reset" - for Pro4 SoC. - "socionext,uniphier-sld8-mio-reset" - for sLD8 SoC. - "socionext,uniphier-pro5-sd-reset" - for Pro5 SoC. - "socionext,uniphier-pxs2-sd-reset" - for PXs2/LD6b SoC. - "socionext,uniphier-ld11-mio-reset" - for LD11 SoC. - "socionext,uniphier-ld20-sd-reset" - for LD20 SoC. + "socionext,uniphier-sld3-mio-reset" - for sLD3 SoC + "socionext,uniphier-ld4-mio-reset" - for LD4 SoC + "socionext,uniphier-pro4-mio-reset" - for Pro4 SoC + "socionext,uniphier-sld8-mio-reset" - for sLD8 SoC + "socionext,uniphier-pro5-sd-reset" - for Pro5 SoC + "socionext,uniphier-pxs2-sd-reset" - for PXs2/LD6b SoC + "socionext,uniphier-ld11-mio-reset" - for LD11 SoC (MIO) + "socionext,uniphier-ld11-sd-reset" - for LD11 SoC (SD) + "socionext,uniphier-ld20-sd-reset" - for LD20 SoC - #reset-cells: should be 1. Example: @@ -68,13 +69,13 @@ Peripheral reset Required properties: - compatible: should be one of the following: - "socionext,uniphier-ld4-peri-reset" - for LD4 SoC. - "socionext,uniphier-pro4-peri-reset" - for Pro4 SoC. - "socionext,uniphier-sld8-peri-reset" - for sLD8 SoC. - "socionext,uniphier-pro5-peri-reset" - for Pro5 SoC. - "socionext,uniphier-pxs2-peri-reset" - for PXs2/LD6b SoC. - "socionext,uniphier-ld11-peri-reset" - for LD11 SoC. - "socionext,uniphier-ld20-peri-reset" - for LD20 SoC. + "socionext,uniphier-ld4-peri-reset" - for LD4 SoC + "socionext,uniphier-pro4-peri-reset" - for Pro4 SoC + "socionext,uniphier-sld8-peri-reset" - for sLD8 SoC + "socionext,uniphier-pro5-peri-reset" - for Pro5 SoC + "socionext,uniphier-pxs2-peri-reset" - for PXs2/LD6b SoC + "socionext,uniphier-ld11-peri-reset" - for LD11 SoC + "socionext,uniphier-ld20-peri-reset" - for LD20 SoC - #reset-cells: should be 1. Example: diff --git a/Documentation/devicetree/bindings/reset/zte,zx2967-reset.txt b/Documentation/devicetree/bindings/reset/zte,zx2967-reset.txt new file mode 100644 index 000000000000..b015508f9780 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/zte,zx2967-reset.txt @@ -0,0 +1,20 @@ +ZTE zx2967 SoCs Reset Controller +======================================= + +Please also refer to reset.txt in this directory for common reset +controller binding usage. + +Required properties: +- compatible: should be one of the following. + * zte,zx296718-reset +- reg: physical base address of the controller and length of memory mapped + region. +- #reset-cells: must be 1. + +example: + + reset: reset-controller@1461060 { + compatible = "zte,zx296718-reset"; + reg = <0x01461060 0x8>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.txt b/Documentation/devicetree/bindings/soc/rockchip/grf.txt index 013e71a2cdc7..c6e62cb30712 100644 --- a/Documentation/devicetree/bindings/soc/rockchip/grf.txt +++ b/Documentation/devicetree/bindings/soc/rockchip/grf.txt @@ -5,11 +5,13 @@ is composed of many registers for system control. From RK3368 SoCs, the GRF is divided into two sections, - GRF, used for general non-secure system, +- SGRF, used for general secure system, - PMUGRF, used for always on system Required Properties: - compatible: GRF should be one of the followings + - "rockchip,rk3036-grf", "syscon": for rk3036 - "rockchip,rk3066-grf", "syscon": for rk3066 - "rockchip,rk3188-grf", "syscon": for rk3188 - "rockchip,rk3228-grf", "syscon": for rk3228 @@ -19,6 +21,8 @@ Required Properties: - compatible: PMUGRF should be one of the followings - "rockchip,rk3368-pmugrf", "syscon": for rk3368 - "rockchip,rk3399-pmugrf", "syscon": for rk3399 +- compatible: SGRF should be one of the following + - "rockchip,rk3288-sgrf", "syscon": for rk3288 - reg: physical base address of the controller and length of memory mapped region. diff --git a/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt b/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt index f909ce06afc4..01bfb6745fbd 100644 --- a/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt +++ b/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt @@ -6,6 +6,7 @@ powered up/down by software based on different application scenes to save power. Required properties for power domain controller: - compatible: Should be one of the following. "rockchip,rk3288-power-controller" - for RK3288 SoCs. + "rockchip,rk3328-power-controller" - for RK3328 SoCs. "rockchip,rk3368-power-controller" - for RK3368 SoCs. "rockchip,rk3399-power-controller" - for RK3399 SoCs. - #power-domain-cells: Number of cells in a power-domain specifier. @@ -16,6 +17,7 @@ Required properties for power domain controller: Required properties for power domain sub nodes: - reg: index of the power domain, should use macros in: "include/dt-bindings/power/rk3288-power.h" - for RK3288 type power domain. + "include/dt-bindings/power/rk3328-power.h" - for RK3328 type power domain. "include/dt-bindings/power/rk3368-power.h" - for RK3368 type power domain. "include/dt-bindings/power/rk3399-power.h" - for RK3399 type power domain. - clocks (optional): phandles to clocks which need to be enabled while power domain @@ -90,6 +92,7 @@ containing a phandle to the power device node and an index specifying which power domain to use. The index should use macros in: "include/dt-bindings/power/rk3288-power.h" - for rk3288 type power domain. + "include/dt-bindings/power/rk3328-power.h" - for rk3328 type power domain. "include/dt-bindings/power/rk3368-power.h" - for rk3368 type power domain. "include/dt-bindings/power/rk3399-power.h" - for rk3399 type power domain. diff --git a/Documentation/devicetree/bindings/soc/zte/pd-2967xx.txt b/Documentation/devicetree/bindings/soc/zte/pd-2967xx.txt new file mode 100644 index 000000000000..7629de1c2c72 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/zte/pd-2967xx.txt @@ -0,0 +1,19 @@ +* ZTE zx2967 family Power Domains + +zx2967 family includes support for multiple power domains which are used +to gate power to one or more peripherals on the processor. + +Required Properties: + - compatible: should be one of the following. + * zte,zx296718-pcu - for zx296718 power domain. + - reg: physical base address of the controller and length of memory mapped + region. + - #power-domain-cells: Must be 1. + +Example: + + pcu_domain: pcu@117000 { + compatible = "zte,zx296718-pcu"; + reg = <0x00117000 0x1000>; + #power-domain-cells = <1>; + }; |