diff options
Diffstat (limited to 'Documentation/devicetree/bindings/dma')
6 files changed, 0 insertions, 8 deletions
diff --git a/Documentation/devicetree/bindings/dma/jz4780-dma.txt b/Documentation/devicetree/bindings/dma/jz4780-dma.txt index f25feee62b15..03e9cf7b42e0 100644 --- a/Documentation/devicetree/bindings/dma/jz4780-dma.txt +++ b/Documentation/devicetree/bindings/dma/jz4780-dma.txt @@ -5,7 +5,6 @@ Required properties: - compatible: Should be "ingenic,jz4780-dma" - reg: Should contain the DMA controller registers location and length. - interrupts: Should contain the interrupt specifier of the DMA controller. -- interrupt-parent: Should be the phandle of the interrupt controller that - clocks: Should contain a clock specifier for the JZ4780 PDMA clock. - #dma-cells: Must be <2>. Number of integer cells in the dmas property of DMA clients (see below). diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.txt b/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.txt index 1e1dc8f972e4..2f35b047f772 100644 --- a/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.txt +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.txt @@ -8,7 +8,6 @@ Required properties: - reg: Should contain DMA registers location and length. This should be a single entry that includes all of the per-channel registers in one contiguous bank. -- interrupt-parent: Phandle to the interrupt parent controller. - interrupts: Should contain all of the per-channel DMA interrupts in ascending order with respect to the DMA channel index. - clocks: Must contain one entry for the ADMA module clock diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt index f237b7928283..dbe160400adc 100644 --- a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt +++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt @@ -5,8 +5,6 @@ Required properties: - reg: Address range of the DMAC registers. This should include all of the per-channel registers. - interrupt: Should contain the DMAC interrupt number. -- interrupt-parent: Should be the phandle for the interrupt controller - that services interrupts for this device. - dma-channels: Number of channels supported by hardware. - snps,dma-masters: Number of AXI masters supported by the hardware. - snps,data-width: Maximum AXI data width supported by hardware. diff --git a/Documentation/devicetree/bindings/dma/snps-dma.txt b/Documentation/devicetree/bindings/dma/snps-dma.txt index 99acc712f83a..39e2b26be344 100644 --- a/Documentation/devicetree/bindings/dma/snps-dma.txt +++ b/Documentation/devicetree/bindings/dma/snps-dma.txt @@ -23,8 +23,6 @@ Deprecated properties: Optional properties: -- interrupt-parent: Should be the phandle for the interrupt controller - that services interrupts for this device - is_private: The device channels should be marked as private and not for by the general purpose DMA channel allocator. False if not passed. - multi-block: Multi block transfers supported by hardware. Array property with diff --git a/Documentation/devicetree/bindings/dma/ti-edma.txt b/Documentation/devicetree/bindings/dma/ti-edma.txt index 3f15f6644527..4bbc94d829c8 100644 --- a/Documentation/devicetree/bindings/dma/ti-edma.txt +++ b/Documentation/devicetree/bindings/dma/ti-edma.txt @@ -201,7 +201,6 @@ Required properties: - #dma-cells: Should be set to <1> Clients should use a single channel number per DMA request. - reg: Memory map for accessing module -- interrupt-parent: Interrupt controller the interrupt is routed through - interrupts: Exactly 3 interrupts need to be specified in the order: 1. Transfer completion interrupt. 2. Memory protection interrupt. diff --git a/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt index a784cdd94790..07a5a7aa9ea0 100644 --- a/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt +++ b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt @@ -5,7 +5,6 @@ control and rate control support for slave/peripheral dma access. Required properties: - compatible : Should be "xlnx,zynqmp-dma-1.0" - reg : Memory map for gdma/adma module access. -- interrupt-parent : Interrupt controller the interrupt is routed through - interrupts : Should contain DMA channel interrupt. - xlnx,bus-width : Axi buswidth in bits. Should contain 128 or 64 - clock-names : List of input clocks "clk_main", "clk_apb" |