diff options
21 files changed, 183 insertions, 293 deletions
diff --git a/Documentation/devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml b/Documentation/devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml index 885d47dd5724..e803a1fc3681 100644 --- a/Documentation/devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml +++ b/Documentation/devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml @@ -34,6 +34,8 @@ properties: - enum: - atmel,at91rm9200-pmc - atmel,at91sam9260-pmc + - atmel,at91sam9261-pmc + - atmel,at91sam9263-pmc - atmel,at91sam9g45-pmc - atmel,at91sam9n12-pmc - atmel,at91sam9rl-pmc @@ -111,6 +113,8 @@ allOf: enum: - atmel,at91rm9200-pmc - atmel,at91sam9260-pmc + - atmel,at91sam9261-pmc + - atmel,at91sam9263-pmc - atmel,at91sam9g20-pmc then: properties: diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml index 860570320545..2985c8c717d7 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml @@ -57,6 +57,27 @@ required: - reg - '#clock-cells' +allOf: + - if: + properties: + compatible: + contains: + enum: + - mediatek,mt8188-camsys-rawa + - mediatek,mt8188-camsys-rawb + - mediatek,mt8188-camsys-yuva + - mediatek,mt8188-camsys-yuvb + - mediatek,mt8188-imgsys-wpe1 + - mediatek,mt8188-imgsys-wpe2 + - mediatek,mt8188-imgsys-wpe3 + - mediatek,mt8188-imgsys1-dip-nr + - mediatek,mt8188-imgsys1-dip-top + - mediatek,mt8188-ipesys + + then: + required: + - '#reset-cells' + additionalProperties: false examples: diff --git a/Documentation/devicetree/bindings/clock/ti,clkctrl.yaml b/Documentation/devicetree/bindings/clock/ti,clkctrl.yaml new file mode 100644 index 000000000000..49787550ce45 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ti,clkctrl.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/ti,clkctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments clkctrl clock + +maintainers: + - Tony Lindgren <tony@atomide.com> + - Andreas Kemnade <andreas@kemnade.info> + +description: | + Texas Instruments SoCs can have a clkctrl clock controller for each + interconnect target module. The clkctrl clock controller manages functional + and interface clocks for each module. Each clkctrl controller can also + gate one or more optional functional clocks for a module, and can have one + or more clock muxes. There is a clkctrl clock controller typically for each + interconnect target module on omap4 and later variants. + + The clock consumers can specify the index of the clkctrl clock using + the hardware offset from the clkctrl instance register space. The optional + clocks can be specified by clkctrl hardware offset and the index of the + optional clock. + +properties: + compatible: + enum: + - ti,clkctrl + - ti,clkctrl-l4-cfg + - ti,clkctrl-l4-per + - ti,clkctrl-l4-secure + - ti,clkctrl-l4-wkup + + "#clock-cells": + const: 2 + + clock-output-names: + maxItems: 1 + + reg: + minItems: 1 + maxItems: 8 # arbitrary, should be enough + +required: + - compatible + - "#clock-cells" + - clock-output-names + - reg + +additionalProperties: false + +examples: + - | + bus { + #address-cells = <1>; + #size-cells = <1>; + + clock@20 { + compatible = "ti,clkctrl"; + clock-output-names = "l4_per"; + reg = <0x20 0x1b0>; + #clock-cells = <2>; + }; + }; diff --git a/Documentation/devicetree/bindings/clock/ti-clkctrl.txt b/Documentation/devicetree/bindings/clock/ti-clkctrl.txt deleted file mode 100644 index d20db7974a38..000000000000 --- a/Documentation/devicetree/bindings/clock/ti-clkctrl.txt +++ /dev/null @@ -1,63 +0,0 @@ -Texas Instruments clkctrl clock binding - -Texas Instruments SoCs can have a clkctrl clock controller for each -interconnect target module. The clkctrl clock controller manages functional -and interface clocks for each module. Each clkctrl controller can also -gate one or more optional functional clocks for a module, and can have one -or more clock muxes. There is a clkctrl clock controller typically for each -interconnect target module on omap4 and later variants. - -The clock consumers can specify the index of the clkctrl clock using -the hardware offset from the clkctrl instance register space. The optional -clocks can be specified by clkctrl hardware offset and the index of the -optional clock. - -For more information, please see the Linux clock framework binding at -Documentation/devicetree/bindings/clock/clock-bindings.txt. - -Required properties : -- compatible : shall be "ti,clkctrl" or a clock domain specific name: - "ti,clkctrl-l4-cfg" - "ti,clkctrl-l4-per" - "ti,clkctrl-l4-secure" - "ti,clkctrl-l4-wkup" -- clock-output-names : from common clock binding -- #clock-cells : shall contain 2 with the first entry being the instance - offset from the clock domain base and the second being the - clock index -- reg : clock registers - -Example: Clock controller node on omap 4430: - -&cm2 { - l4per: cm@1400 { - cm_l4per@0 { - cm_l4per_clkctrl: clock@20 { - compatible = "ti,clkctrl"; - clock-output-names = "l4_per"; - reg = <0x20 0x1b0>; - #clock-cells = <2>; - }; - }; - }; -}; - -Example: Preprocessor helper macros in dt-bindings/clock/ti-clkctrl.h - -#define OMAP4_CLKCTRL_OFFSET 0x20 -#define OMAP4_CLKCTRL_INDEX(offset) ((offset) - OMAP4_CLKCTRL_OFFSET) -#define MODULEMODE_HWCTRL 1 -#define MODULEMODE_SWCTRL 2 - -#define OMAP4_GPTIMER10_CLKTRL OMAP4_CLKCTRL_INDEX(0x28) -#define OMAP4_GPTIMER11_CLKTRL OMAP4_CLKCTRL_INDEX(0x30) -#define OMAP4_GPTIMER2_CLKTRL OMAP4_CLKCTRL_INDEX(0x38) -... -#define OMAP4_GPIO2_CLKCTRL OMAP_CLKCTRL_INDEX(0x60) - -Example: Clock consumer node for GPIO2: - -&gpio2 { - clocks = <&cm_l4per_clkctrl OMAP4_GPIO2_CLKCTRL 0 - &cm_l4per_clkctrl OMAP4_GPIO2_CLKCTRL 8>; -}; diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c index f476883bc93b..85e23961ec34 100644 --- a/drivers/clk/clk-stm32f4.c +++ b/drivers/clk/clk-stm32f4.c @@ -888,7 +888,6 @@ static int __init stm32f4_pll_ssc_parse_dt(struct device_node *np, struct stm32f4_pll_ssc *conf) { int ret; - const char *s; if (!conf) return -EINVAL; @@ -916,7 +915,8 @@ static int __init stm32f4_pll_ssc_parse_dt(struct device_node *np, conf->mod_type = ret; pr_debug("%pOF: SSCG settings: mod_freq: %d, mod_depth: %d mod_method: %s [%d]\n", - np, conf->mod_freq, conf->mod_depth, s, conf->mod_type); + np, conf->mod_freq, conf->mod_depth, + stm32f4_ssc_mod_methods[ret], conf->mod_type); return 0; } diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index cf7720b9172f..0565c87656cf 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -2283,7 +2283,7 @@ static struct clk_core *clk_calc_new_rates(struct clk_core *core, unsigned long min_rate; unsigned long max_rate; int p_index = 0; - long ret; + int ret; /* sanity */ if (IS_ERR_OR_NULL(core)) @@ -4397,6 +4397,13 @@ fail_ops: fail_name: kref_put(&core->ref, __clk_release); fail_out: + if (dev) { + dev_err_probe(dev, ret, "failed to register clk '%s' (%pS)\n", + init->name, hw); + } else { + pr_err("%pOF: error %pe: failed to register clk '%s' (%pS)\n", + np, ERR_PTR(ret), init->name, hw); + } return ERR_PTR(ret); } @@ -5258,6 +5265,10 @@ of_clk_get_hw_from_clkspec(struct of_phandle_args *clkspec) if (!clkspec) return ERR_PTR(-EINVAL); + /* Check if node in clkspec is in disabled/fail state */ + if (!of_device_is_available(clkspec->np)) + return ERR_PTR(-ENOENT); + mutex_lock(&of_clk_mutex); list_for_each_entry(provider, &of_clk_providers, link) { if (provider->node == clkspec->np) { diff --git a/drivers/clk/davinci/Makefile b/drivers/clk/davinci/Makefile index 5d0ae1ee72ec..f9d5c9a392e4 100644 --- a/drivers/clk/davinci/Makefile +++ b/drivers/clk/davinci/Makefile @@ -4,10 +4,8 @@ ifeq ($(CONFIG_COMMON_CLK), y) obj-$(CONFIG_ARCH_DAVINCI_DA8XX) += da8xx-cfgchip.o obj-y += pll.o -obj-$(CONFIG_ARCH_DAVINCI_DA830) += pll-da830.o obj-$(CONFIG_ARCH_DAVINCI_DA850) += pll-da850.o obj-y += psc.o -obj-$(CONFIG_ARCH_DAVINCI_DA830) += psc-da830.o obj-$(CONFIG_ARCH_DAVINCI_DA850) += psc-da850.o endif diff --git a/drivers/clk/davinci/pll-da830.c b/drivers/clk/davinci/pll-da830.c deleted file mode 100644 index 0a0d06fb25fd..000000000000 --- a/drivers/clk/davinci/pll-da830.c +++ /dev/null @@ -1,71 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * PLL clock descriptions for TI DA830/OMAP-L137/AM17XX - * - * Copyright (C) 2018 David Lechner <david@lechnology.com> - */ - -#include <linux/clkdev.h> -#include <linux/clk/davinci.h> -#include <linux/bitops.h> -#include <linux/init.h> -#include <linux/types.h> - -#include "pll.h" - -static const struct davinci_pll_clk_info da830_pll_info = { - .name = "pll0", - .pllm_mask = GENMASK(4, 0), - .pllm_min = 4, - .pllm_max = 32, - .pllout_min_rate = 300000000, - .pllout_max_rate = 600000000, - .flags = PLL_HAS_CLKMODE | PLL_HAS_PREDIV | PLL_HAS_POSTDIV, -}; - -/* - * NB: Technically, the clocks flagged as SYSCLK_FIXED_DIV are "fixed ratio", - * meaning that we could change the divider as long as we keep the correct - * ratio between all of the clocks, but we don't support that because there is - * currently not a need for it. - */ - -SYSCLK(2, pll0_sysclk2, pll0_pllen, 5, SYSCLK_FIXED_DIV); -SYSCLK(3, pll0_sysclk3, pll0_pllen, 5, 0); -SYSCLK(4, pll0_sysclk4, pll0_pllen, 5, SYSCLK_FIXED_DIV); -SYSCLK(5, pll0_sysclk5, pll0_pllen, 5, 0); -SYSCLK(6, pll0_sysclk6, pll0_pllen, 5, SYSCLK_FIXED_DIV); -SYSCLK(7, pll0_sysclk7, pll0_pllen, 5, 0); - -int da830_pll_init(struct device *dev, void __iomem *base, struct regmap *cfgchip) -{ - struct clk *clk; - - davinci_pll_clk_register(dev, &da830_pll_info, "ref_clk", base, cfgchip); - - clk = davinci_pll_sysclk_register(dev, &pll0_sysclk2, base); - clk_register_clkdev(clk, "pll0_sysclk2", "da830-psc0"); - clk_register_clkdev(clk, "pll0_sysclk2", "da830-psc1"); - - clk = davinci_pll_sysclk_register(dev, &pll0_sysclk3, base); - clk_register_clkdev(clk, "pll0_sysclk3", "da830-psc0"); - - clk = davinci_pll_sysclk_register(dev, &pll0_sysclk4, base); - clk_register_clkdev(clk, "pll0_sysclk4", "da830-psc0"); - clk_register_clkdev(clk, "pll0_sysclk4", "da830-psc1"); - - clk = davinci_pll_sysclk_register(dev, &pll0_sysclk5, base); - clk_register_clkdev(clk, "pll0_sysclk5", "da830-psc1"); - - clk = davinci_pll_sysclk_register(dev, &pll0_sysclk6, base); - clk_register_clkdev(clk, "pll0_sysclk6", "da830-psc0"); - - clk = davinci_pll_sysclk_register(dev, &pll0_sysclk7, base); - - clk = davinci_pll_auxclk_register(dev, "pll0_auxclk", base); - clk_register_clkdev(clk, NULL, "i2c_davinci.1"); - clk_register_clkdev(clk, "timer0", NULL); - clk_register_clkdev(clk, NULL, "davinci-wdt"); - - return 0; -} diff --git a/drivers/clk/davinci/pll.c b/drivers/clk/davinci/pll.c index 82727b1fc67a..6807a2efa93b 100644 --- a/drivers/clk/davinci/pll.c +++ b/drivers/clk/davinci/pll.c @@ -840,25 +840,16 @@ int of_davinci_pll_init(struct device *dev, struct device_node *node, } /* needed in early boot for clocksource/clockevent */ -#ifdef CONFIG_ARCH_DAVINCI_DA850 CLK_OF_DECLARE(da850_pll0, "ti,da850-pll0", of_da850_pll0_init); -#endif static const struct of_device_id davinci_pll_of_match[] = { -#ifdef CONFIG_ARCH_DAVINCI_DA850 { .compatible = "ti,da850-pll1", .data = of_da850_pll1_init }, -#endif { } }; static const struct platform_device_id davinci_pll_id_table[] = { -#ifdef CONFIG_ARCH_DAVINCI_DA830 - { .name = "da830-pll", .driver_data = (kernel_ulong_t)da830_pll_init }, -#endif -#ifdef CONFIG_ARCH_DAVINCI_DA850 { .name = "da850-pll0", .driver_data = (kernel_ulong_t)da850_pll0_init }, { .name = "da850-pll1", .driver_data = (kernel_ulong_t)da850_pll1_init }, -#endif { } }; diff --git a/drivers/clk/davinci/psc-da830.c b/drivers/clk/davinci/psc-da830.c deleted file mode 100644 index 6481337382a6..000000000000 --- a/drivers/clk/davinci/psc-da830.c +++ /dev/null @@ -1,118 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * PSC clock descriptions for TI DA830/OMAP-L137/AM17XX - * - * Copyright (C) 2018 David Lechner <david@lechnology.com> - */ - -#include <linux/clk-provider.h> -#include <linux/clk.h> -#include <linux/clkdev.h> -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/types.h> - -#include "psc.h" - -LPSC_CLKDEV1(aemif_clkdev, NULL, "ti-aemif"); -LPSC_CLKDEV1(spi0_clkdev, NULL, "spi_davinci.0"); -LPSC_CLKDEV1(mmcsd_clkdev, NULL, "da830-mmc.0"); -LPSC_CLKDEV1(uart0_clkdev, NULL, "serial8250.0"); - -static const struct davinci_lpsc_clk_info da830_psc0_info[] = { - LPSC(0, 0, tpcc, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED), - LPSC(1, 0, tptc0, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED), - LPSC(2, 0, tptc1, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED), - LPSC(3, 0, aemif, pll0_sysclk3, aemif_clkdev, LPSC_ALWAYS_ENABLED), - LPSC(4, 0, spi0, pll0_sysclk2, spi0_clkdev, 0), - LPSC(5, 0, mmcsd, pll0_sysclk2, mmcsd_clkdev, 0), - LPSC(6, 0, aintc, pll0_sysclk4, NULL, LPSC_ALWAYS_ENABLED), - LPSC(7, 0, arm_rom, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED), - LPSC(8, 0, secu_mgr, pll0_sysclk4, NULL, LPSC_ALWAYS_ENABLED), - LPSC(9, 0, uart0, pll0_sysclk2, uart0_clkdev, 0), - LPSC(10, 0, scr0_ss, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED), - LPSC(11, 0, scr1_ss, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED), - LPSC(12, 0, scr2_ss, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED), - LPSC(13, 0, pruss, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED), - LPSC(14, 0, arm, pll0_sysclk6, NULL, LPSC_ALWAYS_ENABLED), - { } -}; - -static int da830_psc0_init(struct device *dev, void __iomem *base) -{ - return davinci_psc_register_clocks(dev, da830_psc0_info, 16, base); -} - -static struct clk_bulk_data da830_psc0_parent_clks[] = { - { .id = "pll0_sysclk2" }, - { .id = "pll0_sysclk3" }, - { .id = "pll0_sysclk4" }, - { .id = "pll0_sysclk6" }, -}; - -const struct davinci_psc_init_data da830_psc0_init_data = { - .parent_clks = da830_psc0_parent_clks, - .num_parent_clks = ARRAY_SIZE(da830_psc0_parent_clks), - .psc_init = &da830_psc0_init, -}; - -LPSC_CLKDEV3(usb0_clkdev, "fck", "da830-usb-phy-clks", - NULL, "musb-da8xx", - NULL, "cppi41-dmaengine"); -LPSC_CLKDEV1(usb1_clkdev, NULL, "ohci-da8xx"); -/* REVISIT: gpio-davinci.c should be modified to drop con_id */ -LPSC_CLKDEV1(gpio_clkdev, "gpio", NULL); -LPSC_CLKDEV2(emac_clkdev, NULL, "davinci_emac.1", - "fck", "davinci_mdio.0"); -LPSC_CLKDEV1(mcasp0_clkdev, NULL, "davinci-mcasp.0"); -LPSC_CLKDEV1(mcasp1_clkdev, NULL, "davinci-mcasp.1"); -LPSC_CLKDEV1(mcasp2_clkdev, NULL, "davinci-mcasp.2"); -LPSC_CLKDEV1(spi1_clkdev, NULL, "spi_davinci.1"); -LPSC_CLKDEV1(i2c1_clkdev, NULL, "i2c_davinci.2"); -LPSC_CLKDEV1(uart1_clkdev, NULL, "serial8250.1"); -LPSC_CLKDEV1(uart2_clkdev, NULL, "serial8250.2"); -LPSC_CLKDEV1(lcdc_clkdev, "fck", "da8xx_lcdc.0"); -LPSC_CLKDEV2(pwm_clkdev, "fck", "ehrpwm.0", - "fck", "ehrpwm.1"); -LPSC_CLKDEV3(ecap_clkdev, "fck", "ecap.0", - "fck", "ecap.1", - "fck", "ecap.2"); -LPSC_CLKDEV2(eqep_clkdev, NULL, "eqep.0", - NULL, "eqep.1"); - -static const struct davinci_lpsc_clk_info da830_psc1_info[] = { - LPSC(1, 0, usb0, pll0_sysclk2, usb0_clkdev, 0), - LPSC(2, 0, usb1, pll0_sysclk4, usb1_clkdev, 0), - LPSC(3, 0, gpio, pll0_sysclk4, gpio_clkdev, 0), - LPSC(5, 0, emac, pll0_sysclk4, emac_clkdev, 0), - LPSC(6, 0, emif3, pll0_sysclk5, NULL, LPSC_ALWAYS_ENABLED), - LPSC(7, 0, mcasp0, pll0_sysclk2, mcasp0_clkdev, 0), - LPSC(8, 0, mcasp1, pll0_sysclk2, mcasp1_clkdev, 0), - LPSC(9, 0, mcasp2, pll0_sysclk2, mcasp2_clkdev, 0), - LPSC(10, 0, spi1, pll0_sysclk2, spi1_clkdev, 0), - LPSC(11, 0, i2c1, pll0_sysclk4, i2c1_clkdev, 0), - LPSC(12, 0, uart1, pll0_sysclk2, uart1_clkdev, 0), - LPSC(13, 0, uart2, pll0_sysclk2, uart2_clkdev, 0), - LPSC(16, 0, lcdc, pll0_sysclk2, lcdc_clkdev, 0), - LPSC(17, 0, pwm, pll0_sysclk2, pwm_clkdev, 0), - LPSC(20, 0, ecap, pll0_sysclk2, ecap_clkdev, 0), - LPSC(21, 0, eqep, pll0_sysclk2, eqep_clkdev, 0), - { } -}; - -static int da830_psc1_init(struct device *dev, void __iomem *base) -{ - return davinci_psc_register_clocks(dev, da830_psc1_info, 32, base); -} - -static struct clk_bulk_data da830_psc1_parent_clks[] = { - { .id = "pll0_sysclk2" }, - { .id = "pll0_sysclk4" }, - { .id = "pll0_sysclk5" }, -}; - -const struct davinci_psc_init_data da830_psc1_init_data = { - .parent_clks = da830_psc1_parent_clks, - .num_parent_clks = ARRAY_SIZE(da830_psc1_parent_clks), - .psc_init = &da830_psc1_init, -}; diff --git a/drivers/clk/davinci/psc.c b/drivers/clk/davinci/psc.c index 355d1be0b5d8..b48322176c21 100644 --- a/drivers/clk/davinci/psc.c +++ b/drivers/clk/davinci/psc.c @@ -494,22 +494,14 @@ int of_davinci_psc_clk_init(struct device *dev, } static const struct of_device_id davinci_psc_of_match[] = { -#ifdef CONFIG_ARCH_DAVINCI_DA850 { .compatible = "ti,da850-psc0", .data = &of_da850_psc0_init_data }, { .compatible = "ti,da850-psc1", .data = &of_da850_psc1_init_data }, -#endif { } }; static const struct platform_device_id davinci_psc_id_table[] = { -#ifdef CONFIG_ARCH_DAVINCI_DA830 - { .name = "da830-psc0", .driver_data = (kernel_ulong_t)&da830_psc0_init_data }, - { .name = "da830-psc1", .driver_data = (kernel_ulong_t)&da830_psc1_init_data }, -#endif -#ifdef CONFIG_ARCH_DAVINCI_DA850 { .name = "da850-psc0", .driver_data = (kernel_ulong_t)&da850_psc0_init_data }, { .name = "da850-psc1", .driver_data = (kernel_ulong_t)&da850_psc1_init_data }, -#endif { } }; diff --git a/drivers/clk/davinci/psc.h b/drivers/clk/davinci/psc.h index bd23f6fd56df..742672843776 100644 --- a/drivers/clk/davinci/psc.h +++ b/drivers/clk/davinci/psc.h @@ -94,14 +94,9 @@ struct davinci_psc_init_data { int (*psc_init)(struct device *dev, void __iomem *base); }; -#ifdef CONFIG_ARCH_DAVINCI_DA830 -extern const struct davinci_psc_init_data da830_psc0_init_data; -extern const struct davinci_psc_init_data da830_psc1_init_data; -#endif -#ifdef CONFIG_ARCH_DAVINCI_DA850 extern const struct davinci_psc_init_data da850_psc0_init_data; extern const struct davinci_psc_init_data da850_psc1_init_data; extern const struct davinci_psc_init_data of_da850_psc0_init_data; extern const struct davinci_psc_init_data of_da850_psc1_init_data; -#endif + #endif /* __CLK_DAVINCI_PSC_H__ */ diff --git a/drivers/clk/imgtec/clk-boston.c b/drivers/clk/imgtec/clk-boston.c index b00cbd045af5..db96f8bea630 100644 --- a/drivers/clk/imgtec/clk-boston.c +++ b/drivers/clk/imgtec/clk-boston.c @@ -67,21 +67,21 @@ static void __init clk_boston_setup(struct device_node *np) hw = clk_hw_register_fixed_rate(NULL, "input", NULL, 0, in_freq); if (IS_ERR(hw)) { - pr_err("failed to register input clock: %ld\n", PTR_ERR(hw)); + pr_err("failed to register input clock: %pe\n", hw); goto fail_input; } onecell->hws[BOSTON_CLK_INPUT] = hw; hw = clk_hw_register_fixed_rate(NULL, "sys", "input", 0, sys_freq); if (IS_ERR(hw)) { - pr_err("failed to register sys clock: %ld\n", PTR_ERR(hw)); + pr_err("failed to register sys clock: %pe\n", hw); goto fail_sys; } onecell->hws[BOSTON_CLK_SYS] = hw; hw = clk_hw_register_fixed_rate(NULL, "cpu", "input", 0, cpu_freq); if (IS_ERR(hw)) { - pr_err("failed to register cpu clock: %ld\n", PTR_ERR(hw)); + pr_err("failed to register cpu clock: %pe\n", hw); goto fail_cpu; } onecell->hws[BOSTON_CLK_CPU] = hw; diff --git a/drivers/clk/keystone/syscon-clk.c b/drivers/clk/keystone/syscon-clk.c index 935d9a2d8c2b..c509929da854 100644 --- a/drivers/clk/keystone/syscon-clk.c +++ b/drivers/clk/keystone/syscon-clk.c @@ -105,6 +105,12 @@ static struct clk_hw return &priv->hw; } +static const struct regmap_config ti_syscon_regmap_cfg = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, +}; + static int ti_syscon_gate_clk_probe(struct platform_device *pdev) { const struct ti_syscon_gate_clk_data *data, *p; @@ -113,12 +119,17 @@ static int ti_syscon_gate_clk_probe(struct platform_device *pdev) int num_clks, num_parents, i; const char *parent_name; struct regmap *regmap; + void __iomem *base; data = device_get_match_data(dev); if (!data) return -EINVAL; - regmap = device_node_to_regmap(dev->of_node); + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + regmap = regmap_init_mmio(dev, base, &ti_syscon_regmap_cfg); if (IS_ERR(regmap)) return dev_err_probe(dev, PTR_ERR(regmap), "failed to get regmap\n"); diff --git a/drivers/clk/mediatek/clk-mt8188-cam.c b/drivers/clk/mediatek/clk-mt8188-cam.c index 7500bd25387f..9b029fdd584e 100644 --- a/drivers/clk/mediatek/clk-mt8188-cam.c +++ b/drivers/clk/mediatek/clk-mt8188-cam.c @@ -20,6 +20,8 @@ static const struct mtk_gate_regs cam_cg_regs = { #define GATE_CAM(_id, _name, _parent, _shift) \ GATE_MTK(_id, _name, _parent, &cam_cg_regs, _shift, &mtk_clk_gate_ops_setclr) +#define CAM_SYS_SMI_LARB_RST_OFF (0xA0) + static const struct mtk_gate cam_main_clks[] = { GATE_CAM(CLK_CAM_MAIN_LARB13, "cam_main_larb13", "top_cam", 0), GATE_CAM(CLK_CAM_MAIN_LARB14, "cam_main_larb14", "top_cam", 1), @@ -72,6 +74,17 @@ static const struct mtk_gate cam_yuvb_clks[] = { GATE_CAM(CLK_CAM_YUVB_CAMTG, "cam_yuvb_camtg", "top_cam", 2), }; +/* Reset for SMI larb 16a/16b/17a/17b */ +static u16 cam_sys_rst_ofs[] = { + CAM_SYS_SMI_LARB_RST_OFF, +}; + +static const struct mtk_clk_rst_desc cam_sys_rst_desc = { + .version = MTK_RST_SIMPLE, + .rst_bank_ofs = cam_sys_rst_ofs, + .rst_bank_nr = ARRAY_SIZE(cam_sys_rst_ofs), +}; + static const struct mtk_clk_desc cam_main_desc = { .clks = cam_main_clks, .num_clks = ARRAY_SIZE(cam_main_clks), @@ -80,21 +93,25 @@ static const struct mtk_clk_desc cam_main_desc = { static const struct mtk_clk_desc cam_rawa_desc = { .clks = cam_rawa_clks, .num_clks = ARRAY_SIZE(cam_rawa_clks), + .rst_desc = &cam_sys_rst_desc, }; static const struct mtk_clk_desc cam_rawb_desc = { .clks = cam_rawb_clks, .num_clks = ARRAY_SIZE(cam_rawb_clks), + .rst_desc = &cam_sys_rst_desc, }; static const struct mtk_clk_desc cam_yuva_desc = { .clks = cam_yuva_clks, .num_clks = ARRAY_SIZE(cam_yuva_clks), + .rst_desc = &cam_sys_rst_desc, }; static const struct mtk_clk_desc cam_yuvb_desc = { .clks = cam_yuvb_clks, .num_clks = ARRAY_SIZE(cam_yuvb_clks), + .rst_desc = &cam_sys_rst_desc, }; static const struct of_device_id of_match_clk_mt8188_cam[] = { diff --git a/drivers/clk/mediatek/clk-mt8188-img.c b/drivers/clk/mediatek/clk-mt8188-img.c index cb2fbd4136b9..d44bfbd8308a 100644 --- a/drivers/clk/mediatek/clk-mt8188-img.c +++ b/drivers/clk/mediatek/clk-mt8188-img.c @@ -20,6 +20,8 @@ static const struct mtk_gate_regs imgsys_cg_regs = { #define GATE_IMGSYS(_id, _name, _parent, _shift) \ GATE_MTK(_id, _name, _parent, &imgsys_cg_regs, _shift, &mtk_clk_gate_ops_setclr) +#define IMG_SYS_SMI_LARB_RST_OFF (0xC) + static const struct mtk_gate imgsys_main_clks[] = { GATE_IMGSYS(CLK_IMGSYS_MAIN_LARB9, "imgsys_main_larb9", "top_img", 0), GATE_IMGSYS(CLK_IMGSYS_MAIN_TRAW0, "imgsys_main_traw0", "top_img", 1), @@ -58,6 +60,17 @@ static const struct mtk_gate imgsys1_dip_nr_clks[] = { GATE_IMGSYS(CLK_IMGSYS1_DIP_NR_DIP_NR, "imgsys1_dip_nr_dip_nr", "top_img", 1), }; +/* Reset for SMI larb 10/11a/11b/11c/15 */ +static u16 img_sys_rst_ofs[] = { + IMG_SYS_SMI_LARB_RST_OFF, +}; + +static const struct mtk_clk_rst_desc img_sys_rst_desc = { + .version = MTK_RST_SIMPLE, + .rst_bank_ofs = img_sys_rst_ofs, + .rst_bank_nr = ARRAY_SIZE(img_sys_rst_ofs), +}; + static const struct mtk_clk_desc imgsys_main_desc = { .clks = imgsys_main_clks, .num_clks = ARRAY_SIZE(imgsys_main_clks), @@ -66,26 +79,31 @@ static const struct mtk_clk_desc imgsys_main_desc = { static const struct mtk_clk_desc imgsys_wpe1_desc = { .clks = imgsys_wpe1_clks, .num_clks = ARRAY_SIZE(imgsys_wpe1_clks), + .rst_desc = &img_sys_rst_desc, }; static const struct mtk_clk_desc imgsys_wpe2_desc = { .clks = imgsys_wpe2_clks, .num_clks = ARRAY_SIZE(imgsys_wpe2_clks), + .rst_desc = &img_sys_rst_desc, }; static const struct mtk_clk_desc imgsys_wpe3_desc = { .clks = imgsys_wpe3_clks, .num_clks = ARRAY_SIZE(imgsys_wpe3_clks), + .rst_desc = &img_sys_rst_desc, }; static const struct mtk_clk_desc imgsys1_dip_top_desc = { .clks = imgsys1_dip_top_clks, .num_clks = ARRAY_SIZE(imgsys1_dip_top_clks), + .rst_desc = &img_sys_rst_desc, }; static const struct mtk_clk_desc imgsys1_dip_nr_desc = { .clks = imgsys1_dip_nr_clks, .num_clks = ARRAY_SIZE(imgsys1_dip_nr_clks), + .rst_desc = &img_sys_rst_desc, }; static const struct of_device_id of_match_clk_mt8188_imgsys_main[] = { diff --git a/drivers/clk/mediatek/clk-mt8188-ipe.c b/drivers/clk/mediatek/clk-mt8188-ipe.c index 8f1933b71e28..70a011c1f9ce 100644 --- a/drivers/clk/mediatek/clk-mt8188-ipe.c +++ b/drivers/clk/mediatek/clk-mt8188-ipe.c @@ -20,6 +20,8 @@ static const struct mtk_gate_regs ipe_cg_regs = { #define GATE_IPE(_id, _name, _parent, _shift) \ GATE_MTK(_id, _name, _parent, &ipe_cg_regs, _shift, &mtk_clk_gate_ops_setclr) +#define IPE_SYS_SMI_LARB_RST_OFF (0xC) + static const struct mtk_gate ipe_clks[] = { GATE_IPE(CLK_IPE_DPE, "ipe_dpe", "top_ipe", 0), GATE_IPE(CLK_IPE_FDVT, "ipe_fdvt", "top_ipe", 1), @@ -28,9 +30,21 @@ static const struct mtk_gate ipe_clks[] = { GATE_IPE(CLK_IPE_SMI_LARB12, "ipe_smi_larb12", "top_ipe", 4), }; +/* Reset for SMI larb 12 */ +static u16 ipe_sys_rst_ofs[] = { + IPE_SYS_SMI_LARB_RST_OFF, +}; + +static const struct mtk_clk_rst_desc ipe_sys_rst_desc = { + .version = MTK_RST_SIMPLE, + .rst_bank_ofs = ipe_sys_rst_ofs, + .rst_bank_nr = ARRAY_SIZE(ipe_sys_rst_ofs), +}; + static const struct mtk_clk_desc ipe_desc = { .clks = ipe_clks, .num_clks = ARRAY_SIZE(ipe_clks), + .rst_desc = &ipe_sys_rst_desc, }; static const struct of_device_id of_match_clk_mt8188_ipe[] = { diff --git a/drivers/clk/mediatek/clk-mt8188-vdo1.c b/drivers/clk/mediatek/clk-mt8188-vdo1.c index 4fa355f8f0c2..f715d45e545e 100644 --- a/drivers/clk/mediatek/clk-mt8188-vdo1.c +++ b/drivers/clk/mediatek/clk-mt8188-vdo1.c @@ -43,6 +43,12 @@ static const struct mtk_gate_regs vdo1_4_cg_regs = { .sta_ofs = 0x140, }; +static const struct mtk_gate_regs vdo1_5_cg_regs = { + .set_ofs = 0x400, + .clr_ofs = 0x400, + .sta_ofs = 0x400, +}; + #define GATE_VDO1_0(_id, _name, _parent, _shift) \ GATE_MTK(_id, _name, _parent, &vdo1_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr) @@ -62,6 +68,9 @@ static const struct mtk_gate_regs vdo1_4_cg_regs = { #define GATE_VDO1_4(_id, _name, _parent, _shift) \ GATE_MTK(_id, _name, _parent, &vdo1_4_cg_regs, _shift, &mtk_clk_gate_ops_setclr) +#define GATE_VDO1_5(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &vdo1_5_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + static const struct mtk_gate vdo1_clks[] = { /* VDO1_0 */ GATE_VDO1_0(CLK_VDO1_SMI_LARB2, "vdo1_smi_larb2", "top_vpp", 0), @@ -129,6 +138,8 @@ static const struct mtk_gate vdo1_clks[] = { GATE_VDO1_3(CLK_VDO1_DISP_MONITOR_DPINTF, "vdo1_disp_monitor_dpintf_ck", "top_vpp", 17), /* VDO1_4 */ GATE_VDO1_4(CLK_VDO1_26M_SLOW, "vdo1_26m_slow_ck", "clk26m", 8), + /* VDO1_5 */ + GATE_VDO1_5(CLK_VDO1_DPI1_HDMI, "vdo1_dpi1_hdmi", "hdmi_txpll", 0), }; static const struct mtk_clk_desc vdo1_desc = { diff --git a/drivers/clk/mmp/clk-pxa1908-apmu.c b/drivers/clk/mmp/clk-pxa1908-apmu.c index 8cfb1258202f..d3a070687fc5 100644 --- a/drivers/clk/mmp/clk-pxa1908-apmu.c +++ b/drivers/clk/mmp/clk-pxa1908-apmu.c @@ -87,8 +87,8 @@ static int pxa1908_apmu_probe(struct platform_device *pdev) struct pxa1908_clk_unit *pxa_unit; pxa_unit = devm_kzalloc(&pdev->dev, sizeof(*pxa_unit), GFP_KERNEL); - if (IS_ERR(pxa_unit)) - return PTR_ERR(pxa_unit); + if (!pxa_unit) + return -ENOMEM; pxa_unit->base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(pxa_unit->base)) diff --git a/include/dt-bindings/clock/mediatek,mt8188-clk.h b/include/dt-bindings/clock/mediatek,mt8188-clk.h index bd5cd100b796..0e87f61c90f4 100644 --- a/include/dt-bindings/clock/mediatek,mt8188-clk.h +++ b/include/dt-bindings/clock/mediatek,mt8188-clk.h @@ -721,6 +721,6 @@ #define CLK_VDO1_DPINTF 58 #define CLK_VDO1_DISP_MONITOR_DPINTF 59 #define CLK_VDO1_26M_SLOW 60 -#define CLK_VDO1_NR_CLK 61 +#define CLK_VDO1_DPI1_HDMI 61 #endif /* _DT_BINDINGS_CLK_MT8188_H */ diff --git a/include/linux/clk/davinci.h b/include/linux/clk/davinci.h index e1d37451e03f..787a81116b00 100644 --- a/include/linux/clk/davinci.h +++ b/include/linux/clk/davinci.h @@ -12,12 +12,6 @@ #include <linux/regmap.h> /* function for registering clocks in early boot */ - -#ifdef CONFIG_ARCH_DAVINCI_DA830 -int da830_pll_init(struct device *dev, void __iomem *base, struct regmap *cfgchip); -#endif -#ifdef CONFIG_ARCH_DAVINCI_DA850 int da850_pll0_init(struct device *dev, void __iomem *base, struct regmap *cfgchip); -#endif #endif /* __LINUX_CLK_DAVINCI_PLL_H___ */ |