diff options
| -rw-r--r-- | arch/arm/mach-omap2/omap_l3_noc.c | 11 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/omap_l3_noc.h | 12 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/omap_l3_smx.h | 6 |
3 files changed, 15 insertions, 14 deletions
diff --git a/arch/arm/mach-omap2/omap_l3_noc.c b/arch/arm/mach-omap2/omap_l3_noc.c index 1f68e95c3e80..8f1835711676 100644 --- a/arch/arm/mach-omap2/omap_l3_noc.c +++ b/arch/arm/mach-omap2/omap_l3_noc.c @@ -58,7 +58,8 @@ static irqreturn_t l3_interrupt_handler(int irq, void *_l3) struct omap4_l3 *l3 = _l3; int inttype, i; int err_src = 0; - u32 std_err_main, err_reg, clear, base, l3_targ_base; + u32 std_err_main, err_reg, clear; + void __iomem *base, *l3_targ_base; char *source_name; /* Get the Type of interrupt */ @@ -69,8 +70,8 @@ static irqreturn_t l3_interrupt_handler(int irq, void *_l3) * Read the regerr register of the clock domain * to determine the source */ - base = (u32)l3->l3_base[i]; - err_reg = readl(base + l3_flagmux[i] + + base = l3->l3_base[i]; + err_reg = __raw_readl(base + l3_flagmux[i] + + L3_FLAGMUX_REGERR0 + (inttype << 3)); /* Get the corresponding error and analyse */ @@ -80,7 +81,7 @@ static irqreturn_t l3_interrupt_handler(int irq, void *_l3) /* Read the stderrlog_main_source from clk domain */ l3_targ_base = base + *(l3_targ[i] + err_src); - std_err_main = readl(l3_targ_base + + std_err_main = __raw_readl(l3_targ_base + L3_TARG_STDERRLOG_MAIN); switch (std_err_main & CUSTOM_ERROR) { @@ -89,7 +90,7 @@ static irqreturn_t l3_interrupt_handler(int irq, void *_l3) l3_targ_inst_name[i][err_src]; WARN(true, "L3 standard error: SOURCE:%s at address 0x%x\n", source_name, - readl(l3_targ_base + + __raw_readl(l3_targ_base + L3_TARG_STDERRLOG_SLVOFSLSB)); /* clear the std error log*/ clear = std_err_main | CLEAR_STDERR_LOG; diff --git a/arch/arm/mach-omap2/omap_l3_noc.h b/arch/arm/mach-omap2/omap_l3_noc.h index 9120e70aa08a..74c16434f2bc 100644 --- a/arch/arm/mach-omap2/omap_l3_noc.h +++ b/arch/arm/mach-omap2/omap_l3_noc.h @@ -36,14 +36,14 @@ #define L3_TARG_STDERRLOG_SLVOFSLSB 0x5c #define L3_FLAGMUX_REGERR0 0xc -u32 l3_flagmux[L3_MODULES] = { +static u32 l3_flagmux[L3_MODULES] = { 0x500, 0x1000, 0X0200 }; /* L3 Target standard Error register offsets */ -u32 l3_targ_inst_clk1[] = { +static u32 l3_targ_inst_clk1[] = { 0x100, /* DMM1 */ 0x200, /* DMM2 */ 0x300, /* ABE */ @@ -51,7 +51,7 @@ u32 l3_targ_inst_clk1[] = { 0x600 /* CLK2 PWR DISC */ }; -u32 l3_targ_inst_clk2[] = { +static u32 l3_targ_inst_clk2[] = { 0x500, /* CORTEX M3 */ 0x300, /* DSS */ 0x100, /* GPMC */ @@ -72,11 +72,11 @@ u32 l3_targ_inst_clk2[] = { 0xB00 /* L4 PER2*/ }; -u32 l3_targ_inst_clk3[] = { +static u32 l3_targ_inst_clk3[] = { 0x0100 /* EMUSS */ }; -char *l3_targ_inst_name[L3_MODULES][18] = { +static char *l3_targ_inst_name[L3_MODULES][18] = { { "DMM1", "DMM2", @@ -109,7 +109,7 @@ char *l3_targ_inst_name[L3_MODULES][18] = { }, }; -u32 *l3_targ[L3_MODULES] = { +static u32 *l3_targ[L3_MODULES] = { l3_targ_inst_clk1, l3_targ_inst_clk2, l3_targ_inst_clk3, diff --git a/arch/arm/mach-omap2/omap_l3_smx.h b/arch/arm/mach-omap2/omap_l3_smx.h index 18e5ec2629ca..4f3cebca4179 100644 --- a/arch/arm/mach-omap2/omap_l3_smx.h +++ b/arch/arm/mach-omap2/omap_l3_smx.h @@ -206,7 +206,7 @@ struct omap3_l3 { }; /* offsets for l3 agents in order with the Flag status register */ -unsigned int __iomem omap3_l3_app_bases[] = { +static unsigned int omap3_l3_app_bases[] = { /* MPU IA */ 0x1400, 0x1400, @@ -305,7 +305,7 @@ unsigned int __iomem omap3_l3_app_bases[] = { 0, }; -unsigned int __iomem omap3_l3_debug_bases[] = { +static unsigned int omap3_l3_debug_bases[] = { /* MPU DATA IA */ 0x1400, /* RESERVED */ @@ -321,7 +321,7 @@ unsigned int __iomem omap3_l3_debug_bases[] = { /* REST RESERVED */ }; -u32 *omap3_l3_bases[] = { +static u32 *omap3_l3_bases[] = { omap3_l3_app_bases, omap3_l3_debug_bases, }; |