diff options
238 files changed, 602 insertions, 12476 deletions
@@ -178,6 +178,7 @@ Morten Welinder <welinder@darter.rentec.com> Morten Welinder <welinder@troll.com> Mythri P K <mythripk@ti.com> Nguyen Anh Quynh <aquynh@gmail.com> +Nicolas Ferre <nicolas.ferre@microchip.com> <nicolas.ferre@atmel.com> Nicolas Pitre <nico@fluxnic.net> <nicolas.pitre@linaro.org> Nicolas Pitre <nico@fluxnic.net> <nico@linaro.org> Paolo 'Blaisorblade' Giarrusso <blaisorblade@yahoo.it> diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index aa40b074b864..727e0ffc702b 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -175,6 +175,7 @@ properties: - amlogic,meson8-smp - amlogic,meson8b-smp - arm,realview-smp + - aspeed,ast2600-smp - brcm,bcm11351-cpu-method - brcm,bcm23550 - brcm,bcm2836-smp diff --git a/MAINTAINERS b/MAINTAINERS index 0e814418da0a..1dc49553238c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1740,20 +1740,11 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained F: arch/arm/mach-pxa/colibri-pxa270-income.c -ARM/INTEL IOP13XX ARM ARCHITECTURE -M: Lennert Buytenhek <kernel@wantstofly.org> -L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -S: Maintained - ARM/INTEL IOP32X ARM ARCHITECTURE M: Lennert Buytenhek <kernel@wantstofly.org> L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained -ARM/INTEL IOP33X ARM ARCHITECTURE -L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -S: Orphan - ARM/INTEL IQ81342EX MACHINE SUPPORT M: Lennert Buytenhek <kernel@wantstofly.org> L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) @@ -1912,12 +1903,6 @@ S: Maintained F: drivers/phy/mediatek/ F: Documentation/devicetree/bindings/phy/phy-mtk-* -ARM/MICREL KS8695 ARCHITECTURE -M: Greg Ungerer <gerg@uclinux.org> -L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -F: arch/arm/mach-ks8695/ -S: Odd Fixes - ARM/Microchip (AT91) SoC support M: Nicolas Ferre <nicolas.ferre@microchip.com> M: Alexandre Belloni <alexandre.belloni@bootlin.com> @@ -1959,6 +1944,7 @@ F: Documentation/devicetree/bindings/i2c/i2c-stu300.txt F: arch/arm/mach-nomadik/ F: arch/arm/mach-u300/ F: arch/arm/mach-ux500/ +F: drivers/soc/ux500/ F: arch/arm/boot/dts/ste-* F: drivers/clk/clk-nomadik.c F: drivers/clk/clk-u300.c @@ -2002,22 +1988,6 @@ F: drivers/*/*npcm* F: Documentation/devicetree/bindings/*/*npcm* F: Documentation/devicetree/bindings/*/*/*npcm* -ARM/NUVOTON W90X900 ARM ARCHITECTURE -M: Wan ZongShun <mcuos.com@gmail.com> -L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -W: http://www.mcuos.com -S: Maintained -F: arch/arm/mach-w90x900/ -F: drivers/input/keyboard/w90p910_keypad.c -F: drivers/input/touchscreen/w90p910_ts.c -F: drivers/watchdog/nuc900_wdt.c -F: drivers/net/ethernet/nuvoton/w90p910_ether.c -F: drivers/mtd/nand/raw/nuc900_nand.c -F: drivers/rtc/rtc-nuc900.c -F: drivers/spi/spi-nuc900.c -F: drivers/usb/host/ehci-w90x900.c -F: drivers/video/fbdev/nuc900fb.c - ARM/OPENMOKO NEO FREERUNNER (GTA02) MACHINE SUPPORT L: openmoko-kernel@lists.openmoko.org (subscribers-only) W: http://wiki.openmoko.org/wiki/Neo_FreeRunner @@ -2210,8 +2180,9 @@ F: drivers/*/*s3c24* F: drivers/*/*/*s3c24* F: drivers/*/*s3c64xx* F: drivers/*/*s5pv210* -F: drivers/memory/samsung/* -F: drivers/soc/samsung/* +F: drivers/memory/samsung/ +F: drivers/soc/samsung/ +F: include/linux/soc/samsung/ F: Documentation/arm/samsung/ F: Documentation/devicetree/bindings/arm/samsung/ F: Documentation/devicetree/bindings/sram/samsung-sram.txt @@ -10628,12 +10599,6 @@ M: Nicolas Ferre <nicolas.ferre@microchip.com> S: Supported F: drivers/power/reset/at91-sama5d2_shdwc.c -MICROCHIP SAMA5D2-COMPATIBLE PIOBU GPIO -M: Andrei Stefanescu <andrei.stefanescu@microchip.com> -L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -L: linux-gpio@vger.kernel.org -F: drivers/gpio/gpio-sama5d2-piobu.c - MICROCHIP SPI DRIVER M: Nicolas Ferre <nicolas.ferre@microchip.com> S: Supported @@ -10646,13 +10611,6 @@ S: Supported F: drivers/misc/atmel-ssc.c F: include/linux/atmel-ssc.h -MICROCHIP TIMER COUNTER (TC) AND CLOCKSOURCE DRIVERS -M: Nicolas Ferre <nicolas.ferre@microchip.com> -L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -S: Supported -F: drivers/misc/atmel_tclib.c -F: drivers/clocksource/tcb_clksrc.c - MICROCHIP USBA UDC DRIVER M: Cristian Birsan <cristian.birsan@microchip.com> L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) @@ -12694,6 +12652,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) L: linux-gpio@vger.kernel.org S: Supported F: drivers/pinctrl/pinctrl-at91* +F: drivers/gpio/gpio-sama5d2-piobu.c PIN CONTROLLER - FREESCALE M: Dong Aisheng <aisheng.dong@nxp.com> @@ -14127,6 +14086,8 @@ M: Kamil Konieczny <k.konieczny@partner.samsung.com> L: linux-crypto@vger.kernel.org L: linux-samsung-soc@vger.kernel.org S: Maintained +F: Documentation/devicetree/bindings/crypto/samsung-slimsss.txt +F: Documentation/devicetree/bindings/crypto/samsung-sss.txt F: drivers/crypto/s5p-sss.c SAMSUNG S5P/EXYNOS4 SOC SERIES CAMERA SUBSYSTEM DRIVERS @@ -14147,6 +14108,8 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk.git F: drivers/clk/samsung/ F: include/dt-bindings/clock/exynos*.h F: Documentation/devicetree/bindings/clock/exynos*.txt +F: Documentation/devicetree/bindings/clock/samsung,s3c* +F: Documentation/devicetree/bindings/clock/samsung,s5p* SAMSUNG SPI DRIVERS M: Kukjin Kim <kgene@kernel.org> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 24360211534a..2ae7f8adcac4 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -267,8 +267,6 @@ config PHYS_OFFSET default 0x00000000 if ARCH_EBSA110 || \ ARCH_FOOTBRIDGE || \ ARCH_INTEGRATOR || \ - ARCH_IOP13XX || \ - ARCH_KS8695 || \ ARCH_REALVIEW default 0x10000000 if ARCH_OMAP1 || ARCH_RPC default 0x20000000 if ARCH_S5PV210 @@ -381,19 +379,6 @@ config ARCH_FOOTBRIDGE Support for systems based on the DC21285 companion chip ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. -config ARCH_IOP13XX - bool "IOP13xx-based" - depends on MMU - select CPU_XSC3 - select NEED_MACH_MEMORY_H - select NEED_RET_TO_USER - select FORCE_PCI - select PLAT_IOP - select VMSPLIT_1G - select SPARSE_IRQ - help - Support for Intel's IOP13XX (XScale) family of processors. - config ARCH_IOP32X bool "IOP32x-based" depends on MMU @@ -407,18 +392,6 @@ config ARCH_IOP32X Support for Intel's 80219 and IOP32X (XScale) family of processors. -config ARCH_IOP33X - bool "IOP33x-based" - depends on MMU - select CPU_XSCALE - select GPIO_IOP - select GPIOLIB - select NEED_RET_TO_USER - select FORCE_PCI - select PLAT_IOP - help - Support for Intel's IOP33X (XScale) family of processors. - config ARCH_IXP4XX bool "IXP4xx-based" depends on MMU @@ -455,48 +428,6 @@ config ARCH_DOVE help Support for the Marvell Dove SoC 88AP510 -config ARCH_KS8695 - bool "Micrel/Kendin KS8695" - select CLKSRC_MMIO - select CPU_ARM922T - select GENERIC_CLOCKEVENTS - select GPIOLIB - select NEED_MACH_MEMORY_H - help - Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based - System-on-Chip devices. - -config ARCH_W90X900 - bool "Nuvoton W90X900 CPU" - select CLKDEV_LOOKUP - select CLKSRC_MMIO - select CPU_ARM926T - select GENERIC_CLOCKEVENTS - select GPIOLIB - help - Support for Nuvoton (Winbond logic dept.) ARM9 processor, - At present, the w90x900 has been renamed nuc900, regarding - the ARM series product line, you can login the following - link address to know more. - - <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ - ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller> - -config ARCH_LPC32XX - bool "NXP LPC32XX" - select ARM_AMBA - select CLKDEV_LOOKUP - select CLKSRC_LPC32XX - select COMMON_CLK - select CPU_ARM926T - select GENERIC_CLOCKEVENTS - select GENERIC_IRQ_MULTI_HANDLER - select GPIOLIB - select SPARSE_IRQ - select USE_OF - help - Support for the NXP LPC32XX family of processors - config ARCH_PXA bool "PXA2xx/PXA3xx-based" depends on MMU @@ -582,27 +513,6 @@ config ARCH_S3C24XX (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the Samsung SMDK2410 development board (and derivatives). -config ARCH_DAVINCI - bool "TI DaVinci" - select ARCH_HAS_HOLES_MEMORYMODEL - select COMMON_CLK - select CPU_ARM926T - select GENERIC_ALLOCATOR - select GENERIC_CLOCKEVENTS - select GENERIC_IRQ_CHIP - select GENERIC_IRQ_MULTI_HANDLER - select GPIOLIB - select HAVE_IDE - select PM_GENERIC_DOMAINS if PM - select PM_GENERIC_DOMAINS_OF if PM && OF - select REGMAP_MMIO - select RESET_CONTROLLER - select SPARSE_IRQ - select USE_OF - select ZONE_DMA - help - Support for TI's DaVinci platform. - config ARCH_OMAP1 bool "TI OMAP1" depends on MMU @@ -738,17 +648,13 @@ source "arch/arm/mach-imx/Kconfig" source "arch/arm/mach-integrator/Kconfig" -source "arch/arm/mach-iop13xx/Kconfig" - source "arch/arm/mach-iop32x/Kconfig" -source "arch/arm/mach-iop33x/Kconfig" - source "arch/arm/mach-ixp4xx/Kconfig" source "arch/arm/mach-keystone/Kconfig" -source "arch/arm/mach-ks8695/Kconfig" +source "arch/arm/mach-lpc32xx/Kconfig" source "arch/arm/mach-mediatek/Kconfig" @@ -834,8 +740,6 @@ source "arch/arm/plat-versatile/Kconfig" source "arch/arm/mach-vt8500/Kconfig" -source "arch/arm/mach-w90x900/Kconfig" - source "arch/arm/mach-zx/Kconfig" source "arch/arm/mach-zynq/Kconfig" diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 85710e078afb..fe7e9b583e63 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -509,13 +509,6 @@ choice Say Y here if you want the debug print routines to direct their output to UART1 serial port on KEYSTONE2 devices. - config DEBUG_KS8695_UART - bool "KS8695 Debug UART" - depends on ARCH_KS8695 - help - Say Y here if you want kernel low-level debugging support - on KS8695. - config DEBUG_LPC18XX_UART0 bool "Kernel low-level debugging via LPC18xx/43xx UART0" depends on ARCH_LPC18XX @@ -924,6 +917,20 @@ choice Say Y here if you want kernel low-level debugging support via SCIF2 on Renesas RZ/A1H (R7S72100). + config DEBUG_R7S9210_SCIF2 + bool "Kernel low-level debugging messages via SCIF2 on R7S9210" + depends on ARCH_R7S9210 + help + Say Y here if you want kernel low-level debugging support + via SCIF2 on Renesas RZ/A2M (R7S9210). + + config DEBUG_R7S9210_SCIF4 + bool "Kernel low-level debugging messages via SCIF4 on R7S9210" + depends on ARCH_R7S9210 + help + Say Y here if you want kernel low-level debugging support + via SCIF4 on Renesas RZ/A2M (R7S9210). + config DEBUG_RCAR_GEN1_SCIF0 bool "Kernel low-level debugging messages via SCIF0 on R8A7778" depends on ARCH_R8A7778 @@ -1533,10 +1540,11 @@ config DEBUG_LL_INCLUDE DEBUG_IMX6SX_UART || \ DEBUG_IMX6UL_UART || \ DEBUG_IMX7D_UART - default "debug/ks8695.S" if DEBUG_KS8695_UART default "debug/msm.S" if DEBUG_QCOM_UARTDM default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART default "debug/renesas-scif.S" if DEBUG_R7S72100_SCIF2 + default "debug/renesas-scif.S" if DEBUG_R7S9210_SCIF2 + default "debug/renesas-scif.S" if DEBUG_R7S9210_SCIF4 default "debug/renesas-scif.S" if DEBUG_RCAR_GEN1_SCIF0 default "debug/renesas-scif.S" if DEBUG_RCAR_GEN1_SCIF2 default "debug/renesas-scif.S" if DEBUG_RCAR_GEN2_SCIF0 @@ -1568,9 +1576,7 @@ config DEBUG_UART_PL01X # Compatibility options for 8250 config DEBUG_UART_8250 - def_bool ARCH_EBSA110 || \ - ARCH_IOP13XX || ARCH_IOP32X || ARCH_IOP33X || ARCH_IXP4XX || \ - ARCH_RPC + def_bool ARCH_EBSA110 || ARCH_IOP32X || ARCH_IXP4XX || ARCH_RPC config DEBUG_UART_PHYS hex "Physical base address of debug UART" @@ -1666,7 +1672,8 @@ config DEBUG_UART_PHYS default 0xe6e60000 if DEBUG_RCAR_GEN2_SCIF0 default 0xe6e68000 if DEBUG_RCAR_GEN2_SCIF1 default 0xe6ee0000 if DEBUG_RCAR_GEN2_SCIF4 - default 0xe8008000 if DEBUG_R7S72100_SCIF2 + default 0xe8008000 if DEBUG_R7S72100_SCIF2 || DEBUG_R7S9210_SCIF2 + default 0xe8009000 if DEBUG_R7S9210_SCIF4 default 0xf0000000 if DEBUG_DIGICOLOR_UA0 default 0xf0000be0 if ARCH_EBSA110 default 0xf1012000 if DEBUG_MVEBU_UART0_ALTERNATE @@ -1683,7 +1690,6 @@ config DEBUG_UART_PHYS default 0xffc02000 if DEBUG_SOCFPGA_UART0 default 0xffc02100 if DEBUG_SOCFPGA_ARRIA10_UART1 default 0xffc03000 if DEBUG_SOCFPGA_CYCLONE5_UART1 - default 0xffd82340 if ARCH_IOP13XX default 0xffe40000 if DEBUG_RCAR_GEN1_SCIF0 default 0xffe42000 if DEBUG_RCAR_GEN1_SCIF2 default 0xfff36000 if DEBUG_HIGHBANK_UART @@ -1693,12 +1699,12 @@ config DEBUG_UART_PHYS default 0xfffe8600 if DEBUG_BCM63XX_UART default 0xffffee00 if DEBUG_AT91_SAM9263_DBGU default 0xfffff200 if DEBUG_AT91_RM9200_DBGU - default 0xfffff700 if ARCH_IOP33X depends on ARCH_EP93XX || \ DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \ DEBUG_LL_UART_EFM32 || \ DEBUG_UART_8250 || DEBUG_UART_PL01X || DEBUG_MESON_UARTAO || \ DEBUG_QCOM_UARTDM || DEBUG_R7S72100_SCIF2 || \ + DEBUG_R7S9210_SCIF2 || DEBUG_R7S9210_SCIF4 || \ DEBUG_RCAR_GEN1_SCIF0 || DEBUG_RCAR_GEN1_SCIF2 || \ DEBUG_RCAR_GEN2_SCIF0 || DEBUG_RCAR_GEN2_SCIF1 || \ DEBUG_RCAR_GEN2_SCIF2 || DEBUG_RCAR_GEN2_SCIF4 || \ @@ -1772,10 +1778,7 @@ config DEBUG_UART_VIRT default 0xfc705000 if DEBUG_ZTE_ZX default 0xfcfe8600 if DEBUG_BCM63XX_UART default 0xfd000000 if DEBUG_SPEAR3XX || DEBUG_SPEAR13XX - default 0xfd012000 if DEBUG_MVEBU_UART0_ALTERNATE && ARCH_MV78XX0 default 0xfd883000 if DEBUG_ALPINE_UART0 - default 0xfde12000 if DEBUG_MVEBU_UART0_ALTERNATE && ARCH_DOVE - default 0xfe012000 if DEBUG_MVEBU_UART0_ALTERNATE && ARCH_ORION5X default 0xfe017000 if DEBUG_MMP_UART2 default 0xfe018000 if DEBUG_MMP_UART3 default 0xfe100000 if DEBUG_IMX23_UART || DEBUG_IMX28_UART @@ -1790,7 +1793,7 @@ config DEBUG_UART_VIRT default 0xfec02000 if DEBUG_SOCFPGA_UART0 default 0xfec02100 if DEBUG_SOCFPGA_ARRIA10_UART1 default 0xfec03000 if DEBUG_SOCFPGA_CYCLONE5_UART1 - default 0xfec12000 if (DEBUG_MVEBU_UART0 || DEBUG_MVEBU_UART0_ALTERNATE) && ARCH_MVEBU + default 0xfec12000 if DEBUG_MVEBU_UART0 || DEBUG_MVEBU_UART0_ALTERNATE default 0xfec12100 if DEBUG_MVEBU_UART1_ALTERNATE default 0xfec10000 if DEBUG_SIRFATLAS7_UART0 default 0xfec20000 if DEBUG_DAVINCI_DMx_UART0 @@ -1805,14 +1808,12 @@ config DEBUG_UART_VIRT default 0xfedc0000 if DEBUG_EP93XX default 0xfee003f8 if DEBUG_FOOTBRIDGE_COM1 default 0xfee20000 if DEBUG_NSPIRE_CLASSIC_UART || DEBUG_NSPIRE_CX_UART - default 0xfee82340 if ARCH_IOP13XX default 0xfef00000 if ARCH_IXP4XX && !CPU_BIG_ENDIAN default 0xfef00003 if ARCH_IXP4XX && CPU_BIG_ENDIAN default 0xfef36000 if DEBUG_HIGHBANK_UART default 0xfefb0000 if DEBUG_OMAP1UART1 || DEBUG_OMAP7XXUART1 default 0xfefb0800 if DEBUG_OMAP1UART2 || DEBUG_OMAP7XXUART2 default 0xfefb9800 if DEBUG_OMAP1UART3 || DEBUG_OMAP7XXUART3 - default 0xfefff700 if ARCH_IOP33X default 0xff003000 if DEBUG_U300_UART default 0xffd01000 if DEBUG_HIP01_UART default DEBUG_UART_PHYS if !MMU diff --git a/arch/arm/Makefile b/arch/arm/Makefile index c3624ca6c0bc..f9002e44f18f 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -155,6 +155,7 @@ textofs-$(CONFIG_ARCH_AXXIA) := 0x00308000 machine-$(CONFIG_ARCH_ACTIONS) += actions machine-$(CONFIG_ARCH_ALPINE) += alpine machine-$(CONFIG_ARCH_ARTPEC) += artpec +machine-$(CONFIG_ARCH_ASPEED) += aspeed machine-$(CONFIG_ARCH_AT91) += at91 machine-$(CONFIG_ARCH_AXXIA) += axxia machine-$(CONFIG_ARCH_BCM) += bcm @@ -173,12 +174,9 @@ machine-$(CONFIG_ARCH_GEMINI) += gemini machine-$(CONFIG_ARCH_HIGHBANK) += highbank machine-$(CONFIG_ARCH_HISI) += hisi machine-$(CONFIG_ARCH_INTEGRATOR) += integrator -machine-$(CONFIG_ARCH_IOP13XX) += iop13xx machine-$(CONFIG_ARCH_IOP32X) += iop32x -machine-$(CONFIG_ARCH_IOP33X) += iop33x machine-$(CONFIG_ARCH_IXP4XX) += ixp4xx machine-$(CONFIG_ARCH_KEYSTONE) += keystone -machine-$(CONFIG_ARCH_KS8695) += ks8695 machine-$(CONFIG_ARCH_LPC18XX) += lpc18xx machine-$(CONFIG_ARCH_LPC32XX) += lpc32xx machine-$(CONFIG_ARCH_MESON) += meson @@ -222,7 +220,6 @@ machine-$(CONFIG_ARCH_U8500) += ux500 machine-$(CONFIG_ARCH_VERSATILE) += versatile machine-$(CONFIG_ARCH_VEXPRESS) += vexpress machine-$(CONFIG_ARCH_VT8500) += vt8500 -machine-$(CONFIG_ARCH_W90X900) += w90x900 machine-$(CONFIG_ARCH_ZX) += zx machine-$(CONFIG_ARCH_ZYNQ) += zynq machine-$(CONFIG_PLAT_SPEAR) += spear @@ -233,7 +230,6 @@ plat-$(CONFIG_ARCH_EXYNOS) += samsung plat-$(CONFIG_ARCH_OMAP) += omap plat-$(CONFIG_ARCH_S3C64XX) += samsung plat-$(CONFIG_ARCH_S5PV210) += samsung -plat-$(CONFIG_PLAT_IOP) += iop plat-$(CONFIG_PLAT_ORION) += orion plat-$(CONFIG_PLAT_PXA) += pxa plat-$(CONFIG_PLAT_S3C24XX) += samsung diff --git a/arch/arm/configs/acs5k_defconfig b/arch/arm/configs/acs5k_defconfig deleted file mode 100644 index bcb8bda09158..000000000000 --- a/arch/arm/configs/acs5k_defconfig +++ /dev/null @@ -1,77 +0,0 @@ -# CONFIG_SWAP is not set -CONFIG_SYSVIPC=y -CONFIG_POSIX_MQUEUE=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_SYSFS_DEPRECATED_V2=y -CONFIG_BLK_DEV_INITRD=y -CONFIG_SLAB=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set -CONFIG_ARCH_KS8695=y -CONFIG_MACH_KS8695=y -CONFIG_MACH_DSM320=y -CONFIG_MACH_ACS5K=y -# CONFIG_ARM_THUMB is not set -CONFIG_PCI=y -CONFIG_PCI_DEBUG=y -CONFIG_PCCARD=y -CONFIG_YENTA=y -CONFIG_AEABI=y -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="mem=32M console=ttyS0,115200 initrd=0x20410000,3145728 root=/dev/ram0 rw" -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -# CONFIG_IPV6 is not set -CONFIG_MTD=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_JEDECPROBE=y -CONFIG_MTD_CFI_ADV_OPTIONS=y -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_CFI_AMDSTD=y -CONFIG_MTD_PHYSMAP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=8192 -CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y -CONFIG_ARM_KS8695_ETHER=y -CONFIG_PRISM54=m -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO is not set -CONFIG_SERIAL_KS8695=y -CONFIG_SERIAL_KS8695_CONSOLE=y -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_GPIO=y -CONFIG_GPIO_SYSFS=y -CONFIG_GPIO_PCA953X=y -CONFIG_WATCHDOG=y -CONFIG_KS8695_WATCHDOG=y -# CONFIG_VGA_CONSOLE is not set -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_PCF8563=y -CONFIG_EXT2_FS=y -CONFIG_TMPFS=y -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_SUMMARY=y -CONFIG_JFFS2_COMPRESSION_OPTIONS=y -CONFIG_JFFS2_RUBIN=y -CONFIG_CRAMFS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_ROOT_NFS=y -CONFIG_DEBUG_KERNEL=y -CONFIG_DEBUG_MUTEXES=y -# CONFIG_FTRACE is not set -CONFIG_DEBUG_USER=y -CONFIG_DEBUG_LL=y diff --git a/arch/arm/configs/acs5k_tiny_defconfig b/arch/arm/configs/acs5k_tiny_defconfig deleted file mode 100644 index e802cdebfd0b..000000000000 --- a/arch/arm/configs/acs5k_tiny_defconfig +++ /dev/null @@ -1,69 +0,0 @@ -# CONFIG_SWAP is not set -CONFIG_SYSVIPC=y -CONFIG_POSIX_MQUEUE=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_SYSFS_DEPRECATED_V2=y -CONFIG_SLAB=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set -CONFIG_ARCH_KS8695=y -CONFIG_MACH_ACS5K=y -# CONFIG_ARM_THUMB is not set -CONFIG_AEABI=y -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="console=ttyAM0,115200 init=/bin/sh" -CONFIG_FPE_NWFPE=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_IPV6 is not set -CONFIG_MTD=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_JEDECPROBE=y -CONFIG_MTD_CFI_ADV_OPTIONS=y -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_CFI_AMDSTD=y -CONFIG_MTD_PHYSMAP=y -# CONFIG_BLK_DEV is not set -CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y -CONFIG_ARM_KS8695_ETHER=y -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO is not set -CONFIG_SERIAL_KS8695=y -CONFIG_SERIAL_KS8695_CONSOLE=y -# CONFIG_HW_RANDOM is not set -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_GPIO=y -CONFIG_GPIO_SYSFS=y -CONFIG_GPIO_PCA953X=y -# CONFIG_HWMON is not set -CONFIG_WATCHDOG=y -CONFIG_KS8695_WATCHDOG=y -# CONFIG_VGA_CONSOLE is not set -# CONFIG_USB_SUPPORT is not set -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_PCF8563=y -CONFIG_TMPFS=y -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_SUMMARY=y -CONFIG_JFFS2_COMPRESSION_OPTIONS=y -CONFIG_JFFS2_RUBIN=y -CONFIG_SQUASHFS=y -# CONFIG_NETWORK_FILESYSTEMS is not set -CONFIG_DEBUG_KERNEL=y -CONFIG_DEBUG_MUTEXES=y -# CONFIG_FTRACE is not set -CONFIG_DEBUG_USER=y diff --git a/arch/arm/configs/davinci_all_defconfig b/arch/arm/configs/davinci_all_defconfig index 9a32a8c0f873..b34970ce6b31 100644 --- a/arch/arm/configs/davinci_all_defconfig +++ b/arch/arm/configs/davinci_all_defconfig @@ -17,6 +17,9 @@ CONFIG_MODVERSIONS=y CONFIG_PARTITION_ADVANCED=y # CONFIG_IOSCHED_DEADLINE is not set # CONFIG_IOSCHED_CFQ is not set +CONFIG_ARCH_MULTIPLATFORM=y +CONFIG_ARCH_MULTI_V7=n +CONFIG_ARCH_MULTI_V5=y CONFIG_ARCH_DAVINCI=y CONFIG_ARCH_DAVINCI_DM644x=y CONFIG_ARCH_DAVINCI_DM355=y @@ -129,9 +132,11 @@ CONFIG_SPI=y CONFIG_SPI_DAVINCI=m CONFIG_PINCTRL_DA850_PUPD=m CONFIG_PINCTRL_SINGLE=y +CONFIG_GPIOLIB=y CONFIG_GPIO_SYSFS=y CONFIG_GPIO_PCA953X=y CONFIG_GPIO_PCA953X_IRQ=y +CONFIG_RESET_CONTROLLER=y CONFIG_POWER_RESET=y CONFIG_POWER_RESET_GPIO=y CONFIG_SYSCON_REBOOT_MODE=m diff --git a/arch/arm/configs/iop13xx_defconfig b/arch/arm/configs/iop13xx_defconfig deleted file mode 100644 index 30cdb287e1b4..000000000000 --- a/arch/arm/configs/iop13xx_defconfig +++ /dev/null @@ -1,118 +0,0 @@ -# CONFIG_LOCALVERSION_AUTO is not set -CONFIG_SYSVIPC=y -CONFIG_POSIX_MQUEUE=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_BLK_DEV_INITRD=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_SLAB=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODVERSIONS=y -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_IOSCHED_CFQ is not set -CONFIG_ARCH_IOP13XX=y -CONFIG_MACH_IQ81340SC=y -CONFIG_MACH_IQ81340MC=y -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="ip=bootp root=nfs console=ttyS0,115200 nfsroot=,tcp,v3,wsize=8192,rsize=8192" -CONFIG_FPE_NWFPE=y -CONFIG_BINFMT_AOUT=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_NET_KEY=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IPV6=y -# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET6_XFRM_MODE_TUNNEL is not set -# CONFIG_INET6_XFRM_MODE_BEET is not set -# CONFIG_IPV6_SIT is not set -CONFIG_MTD=y -CONFIG_MTD_REDBOOT_PARTS=y -CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y -CONFIG_MTD_REDBOOT_PARTS_READONLY=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_ADV_OPTIONS=y -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_PHYSMAP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=2 -CONFIG_BLK_DEV_RAM_SIZE=8192 -CONFIG_SCSI=y -CONFIG_BLK_DEV_SD=y -CONFIG_CHR_DEV_SG=y -CONFIG_SCSI_CONSTANTS=y -CONFIG_SCSI_ISCSI_ATTRS=y -CONFIG_MD=y -CONFIG_BLK_DEV_MD=y -CONFIG_MD_RAID0=y -CONFIG_MD_RAID1=y -CONFIG_MD_RAID10=y -CONFIG_MD_RAID456=y -CONFIG_BLK_DEV_DM=y -CONFIG_NETDEVICES=y -CONFIG_E1000=y -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO is not set -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=2 -CONFIG_HW_RANDOM=y -CONFIG_I2C=y -CONFIG_I2C_IOP3XX=y -# CONFIG_VGA_CONSOLE is not set -CONFIG_DMADEVICES=y -CONFIG_INTEL_IOP_ADMA=y -CONFIG_EXT2_FS=y -CONFIG_EXT3_FS=y -CONFIG_TMPFS=y -CONFIG_ECRYPT_FS=y -CONFIG_JFFS2_FS=y -CONFIG_CRAMFS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_ROOT_NFS=y -CONFIG_NFSD=y -CONFIG_NFSD_V3=y -CONFIG_SMB_FS=m -CONFIG_CIFS=m -CONFIG_PARTITION_ADVANCED=y -CONFIG_NLS=y -CONFIG_DEBUG_USER=y -CONFIG_KEYS=y -CONFIG_CRYPTO_NULL=y -CONFIG_CRYPTO_LRW=y -CONFIG_CRYPTO_PCBC=m -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_XCBC=y -CONFIG_CRYPTO_MD4=y -CONFIG_CRYPTO_MICHAEL_MIC=y -CONFIG_CRYPTO_SHA1=y -CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_SHA512=y -CONFIG_CRYPTO_TGR192=y -CONFIG_CRYPTO_WP512=y -CONFIG_CRYPTO_AES=y -CONFIG_CRYPTO_ANUBIS=y -CONFIG_CRYPTO_ARC4=y -CONFIG_CRYPTO_BLOWFISH=y -CONFIG_CRYPTO_CAST5=y -CONFIG_CRYPTO_CAST6=y -CONFIG_CRYPTO_DES=y -CONFIG_CRYPTO_KHAZAD=y -CONFIG_CRYPTO_SERPENT=y -CONFIG_CRYPTO_TEA=y -CONFIG_CRYPTO_TWOFISH=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRC_CCITT=y -CONFIG_LIBCRC32C=y diff --git a/arch/arm/configs/iop33x_defconfig b/arch/arm/configs/iop33x_defconfig deleted file mode 100644 index 089eca43214a..000000000000 --- a/arch/arm/configs/iop33x_defconfig +++ /dev/null @@ -1,85 +0,0 @@ -CONFIG_SYSVIPC=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_BLK_DEV_INITRD=y -CONFIG_KALLSYMS_ALL=y -CONFIG_SLAB=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_BLK_DEV_BSG is not set -CONFIG_ARCH_IOP33X=y -CONFIG_ARCH_IQ80331=y -CONFIG_MACH_IQ80332=y -# CONFIG_ARM_THUMB is not set -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="console=ttyS0,115200 root=/dev/nfs ip=bootp cachepolicy=writealloc iop3xx_init_atu=y" -CONFIG_FPE_NWFPE=y -CONFIG_BINFMT_AOUT=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IPV6=y -# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET6_XFRM_MODE_TUNNEL is not set -# CONFIG_INET6_XFRM_MODE_BEET is not set -# CONFIG_IPV6_SIT is not set -CONFIG_MTD=y -CONFIG_MTD_REDBOOT_PARTS=y -CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y -CONFIG_MTD_REDBOOT_PARTS_READONLY=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_ADV_OPTIONS=y -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_PHYSMAP=y -CONFIG_BLK_DEV_NBD=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=8192 -CONFIG_SCSI=y -CONFIG_BLK_DEV_SD=y -CONFIG_CHR_DEV_SG=y -CONFIG_MD=y -CONFIG_BLK_DEV_MD=y -CONFIG_MD_LINEAR=y -CONFIG_MD_RAID0=y -CONFIG_MD_RAID1=y -CONFIG_MD_RAID456=y -CONFIG_BLK_DEV_DM=y -CONFIG_NETDEVICES=y -CONFIG_E1000=y -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO is not set -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_HW_RANDOM=y -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_IOP3XX=y -# CONFIG_VGA_CONSOLE is not set -CONFIG_DMADEVICES=y -CONFIG_INTEL_IOP_ADMA=y -CONFIG_NET_DMA=y -CONFIG_EXT2_FS=y -CONFIG_EXT3_FS=y -CONFIG_TMPFS=y -CONFIG_CRAMFS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_ROOT_NFS=y -CONFIG_NFSD=y -CONFIG_NFSD_V3=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_KERNEL=y -CONFIG_DEBUG_USER=y -CONFIG_DEBUG_LL=y -CONFIG_DEBUG_LL_UART_8250=y -# CONFIG_CRYPTO_ANSI_CPRNG is not set -# CONFIG_CRC32 is not set diff --git a/arch/arm/configs/ks8695_defconfig b/arch/arm/configs/ks8695_defconfig deleted file mode 100644 index df62d4dfbbb7..000000000000 --- a/arch/arm/configs/ks8695_defconfig +++ /dev/null @@ -1,67 +0,0 @@ -# CONFIG_SWAP is not set -CONFIG_SYSVIPC=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_SYSFS_DEPRECATED_V2=y -CONFIG_BLK_DEV_INITRD=y -CONFIG_SLAB=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set -CONFIG_ARCH_KS8695=y -CONFIG_MACH_KS8695=y -CONFIG_MACH_DSM320=y -# CONFIG_ARM_THUMB is not set -CONFIG_PCI=y -CONFIG_PCI_DEBUG=y -CONFIG_PCCARD=y -CONFIG_YENTA=y -CONFIG_AEABI=y -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="mem=32M console=ttyS0,115200 initrd=0x20410000,3145728 root=/dev/ram0 rw" -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -# CONFIG_IPV6 is not set -CONFIG_MTD=y -CONFIG_MTD_REDBOOT_PARTS=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_JEDECPROBE=y -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_PHYSMAP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=8192 -CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -CONFIG_PRISM54=m -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO is not set -CONFIG_SERIAL_KS8695=y -CONFIG_SERIAL_KS8695_CONSOLE=y -# CONFIG_HWMON is not set -# CONFIG_VGA_CONSOLE is not set -CONFIG_EXT2_FS=y -CONFIG_TMPFS=y -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_SUMMARY=y -CONFIG_JFFS2_COMPRESSION_OPTIONS=y -CONFIG_JFFS2_RUBIN=y -CONFIG_CRAMFS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_ROOT_NFS=y -CONFIG_DEBUG_KERNEL=y -CONFIG_DEBUG_MUTEXES=y -# CONFIG_FTRACE is not set -CONFIG_DEBUG_USER=y -CONFIG_DEBUG_LL=y diff --git a/arch/arm/configs/lpc32xx_defconfig b/arch/arm/configs/lpc32xx_defconfig index 3772d5a8975a..09deb57db942 100644 --- a/arch/arm/configs/lpc32xx_defconfig +++ b/arch/arm/configs/lpc32xx_defconfig @@ -12,6 +12,7 @@ CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_SYSCTL_SYSCALL=y CONFIG_EMBEDDED=y CONFIG_SLAB=y +# CONFIG_ARCH_MULTI_V7 is not set CONFIG_ARCH_LPC32XX=y CONFIG_AEABI=y CONFIG_ZBOOT_ROM_TEXT=0x0 diff --git a/arch/arm/configs/multi_v5_defconfig b/arch/arm/configs/multi_v5_defconfig index 201237002c65..bd018873e47a 100644 --- a/arch/arm/configs/multi_v5_defconfig +++ b/arch/arm/configs/multi_v5_defconfig @@ -14,6 +14,18 @@ CONFIG_ARCH_ASPEED=y CONFIG_MACH_ASPEED_G4=y CONFIG_ARCH_AT91=y CONFIG_SOC_AT91SAM9=y +CONFIG_ARCH_DAVINCI=y +CONFIG_ARCH_DAVINCI_DM644x=y +CONFIG_ARCH_DAVINCI_DM355=y +CONFIG_ARCH_DAVINCI_DM646x=y +CONFIG_ARCH_DAVINCI_DA830=y +CONFIG_ARCH_DAVINCI_DA850=y +CONFIG_ARCH_DAVINCI_DM365=y +CONFIG_MACH_SFFSDR=y +CONFIG_MACH_NEUROS_OSD2=y +CONFIG_MACH_DM355_LEOPARD=y +CONFIG_MACH_MITYOMAPL138=y +CONFIG_MACH_OMAPL138_HAWKBOARD=y CONFIG_ARCH_MXC=y CONFIG_MACH_MX21ADS=y CONFIG_MACH_MX27ADS=y diff --git a/arch/arm/configs/nuc910_defconfig b/arch/arm/configs/nuc910_defconfig deleted file mode 100644 index 63dba62c3326..000000000000 --- a/arch/arm/configs/nuc910_defconfig +++ /dev/null @@ -1,51 +0,0 @@ -# CONFIG_LOCALVERSION_AUTO is not set -CONFIG_SYSVIPC=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_SYSFS_DEPRECATED_V2=y -CONFIG_RELAY=y -CONFIG_USER_NS=y -CONFIG_BLK_DEV_INITRD=y -CONFIG_KALLSYMS_EXTRA_PASS=y -CONFIG_SLAB=y -CONFIG_ARCH_W90X900=y -CONFIG_PREEMPT=y -CONFIG_AEABI=y -CONFIG_CMDLINE="root=/dev/ram0 console=ttyS0,115200n8 rdinit=/sbin/init mem=64M" -CONFIG_KEXEC=y -CONFIG_FPE_NWFPE=y -CONFIG_MTD=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_AMDSTD=y -CONFIG_MTD_PHYSMAP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=16384 -CONFIG_SCSI=y -# CONFIG_SCSI_PROC_FS is not set -CONFIG_BLK_DEV_SD=y -# CONFIG_SCSI_LOWLEVEL is not set -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO is not set -# CONFIG_DEVKMEM is not set -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=1 -# CONFIG_LEGACY_PTYS is not set -# CONFIG_HW_RANDOM is not set -# CONFIG_HWMON is not set -# CONFIG_VGA_CONSOLE is not set -CONFIG_USB=y -CONFIG_USB_MON=y -CONFIG_USB_STORAGE=y -# CONFIG_DNOTIFY is not set -CONFIG_TMPFS=y -CONFIG_TMPFS_POSIX_ACL=y -CONFIG_ROMFS_FS=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ISO8859_1=y -# CONFIG_ENABLE_MUST_CHECK is not set -CONFIG_DEBUG_FS=y -# CONFIG_CRC32 is not set diff --git a/arch/arm/configs/nuc950_defconfig b/arch/arm/configs/nuc950_defconfig deleted file mode 100644 index cb5a8788ebe8..000000000000 --- a/arch/arm/configs/nuc950_defconfig +++ /dev/null @@ -1,67 +0,0 @@ -# CONFIG_LOCALVERSION_AUTO is not set -CONFIG_SYSVIPC=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_SYSFS_DEPRECATED_V2=y -CONFIG_RELAY=y -CONFIG_USER_NS=y -CONFIG_BLK_DEV_INITRD=y -CONFIG_KALLSYMS_EXTRA_PASS=y -CONFIG_SLAB=y -CONFIG_ARCH_W90X900=y -# CONFIG_MACH_W90P910EVB is not set -CONFIG_MACH_W90P950EVB=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_PREEMPT=y -CONFIG_AEABI=y -CONFIG_CMDLINE="root=/dev/ram0 console=ttyS0,115200n8 rdinit=/sbin/init mem=64M" -CONFIG_KEXEC=y -CONFIG_FPE_NWFPE=y -CONFIG_BINFMT_AOUT=y -CONFIG_BINFMT_MISC=y -CONFIG_MTD=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_AMDSTD=y -CONFIG_MTD_PHYSMAP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=16384 -CONFIG_SCSI=y -# CONFIG_SCSI_PROC_FS is not set -CONFIG_BLK_DEV_SD=y -# CONFIG_SCSI_LOWLEVEL is not set -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO is not set -# CONFIG_DEVKMEM is not set -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=1 -# CONFIG_LEGACY_PTYS is not set -# CONFIG_HW_RANDOM is not set -# CONFIG_HWMON is not set -CONFIG_FB=y -CONFIG_FB_NUC900=y -CONFIG_GPM1040A0_320X240=y -CONFIG_FB_NUC900_DEBUG=y -# CONFIG_VGA_CONSOLE is not set -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y -CONFIG_FONTS=y -CONFIG_FONT_8x16=y -CONFIG_LOGO=y -# CONFIG_LOGO_LINUX_MONO is not set -# CONFIG_LOGO_LINUX_VGA16 is not set -CONFIG_USB=y -CONFIG_USB_MON=y -CONFIG_USB_STORAGE=y -# CONFIG_DNOTIFY is not set -CONFIG_TMPFS=y -CONFIG_TMPFS_POSIX_ACL=y -CONFIG_ROMFS_FS=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ISO8859_1=y -# CONFIG_ENABLE_MUST_CHECK is not set -CONFIG_DEBUG_FS=y diff --git a/arch/arm/configs/nuc960_defconfig b/arch/arm/configs/nuc960_defconfig deleted file mode 100644 index f7af84e23a05..000000000000 --- a/arch/arm/configs/nuc960_defconfig +++ /dev/null @@ -1,57 +0,0 @@ -# CONFIG_LOCALVERSION_AUTO is not set -CONFIG_SYSVIPC=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_SYSFS_DEPRECATED_V2=y -CONFIG_RELAY=y -CONFIG_USER_NS=y -CONFIG_BLK_DEV_INITRD=y -CONFIG_KALLSYMS_EXTRA_PASS=y -CONFIG_SLAB=y -CONFIG_ARCH_W90X900=y -# CONFIG_MACH_W90P910EVB is not set -CONFIG_MACH_W90N960EVB=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_PREEMPT=y -CONFIG_AEABI=y -CONFIG_CMDLINE="root=/dev/ram0 console=ttyS0,115200n8 rdinit=/sbin/init mem=64M" -CONFIG_KEXEC=y -CONFIG_FPE_NWFPE=y -CONFIG_BINFMT_AOUT=y -CONFIG_BINFMT_MISC=y -CONFIG_MTD=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_AMDSTD=y -CONFIG_MTD_PHYSMAP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=16384 -CONFIG_SCSI=y -# CONFIG_SCSI_PROC_FS is not set -CONFIG_BLK_DEV_SD=y -# CONFIG_SCSI_LOWLEVEL is not set -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO is not set -# CONFIG_DEVKMEM is not set -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=1 -# CONFIG_LEGACY_PTYS is not set -# CONFIG_HW_RANDOM is not set -# CONFIG_HWMON is not set -# CONFIG_VGA_CONSOLE is not set -CONFIG_USB=y -CONFIG_USB_MON=y -CONFIG_USB_STORAGE=y -# CONFIG_DNOTIFY is not set -CONFIG_TMPFS=y -CONFIG_TMPFS_POSIX_ACL=y -CONFIG_ROMFS_FS=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ISO8859_1=y -# CONFIG_ENABLE_MUST_CHECK is not set -CONFIG_DEBUG_FS=y -# CONFIG_CRC32 is not set diff --git a/arch/arm/include/debug/ks8695.S b/arch/arm/include/debug/ks8695.S deleted file mode 100644 index eb4d371b5eea..000000000000 --- a/arch/arm/include/debug/ks8695.S +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * arch/arm/include/debug/ks8695.S - * - * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> - * Copyright (C) 2006 Simtec Electronics - * - * KS8695 - Debug macros - */ - -#define KS8695_UART_PA 0x03ffe000 -#define KS8695_UART_VA 0xf00fe000 -#define KS8695_URTH (0x04) -#define KS8695_URLS (0x14) -#define URLS_URTE (1 << 6) -#define URLS_URTHRE (1 << 5) - - .macro addruart, rp, rv, tmp - ldr \rp, =KS8695_UART_PA @ physical base address - ldr \rv, =KS8695_UART_VA @ virtual base address - .endm - - .macro senduart, rd, rx - str \rd, [\rx, #KS8695_URTH] @ Write to Transmit Holding Register - .endm - - .macro busyuart, rd, rx -1001: ldr \rd, [\rx, #KS8695_URLS] @ Read Line Status Register - tst \rd, #URLS_URTE @ Holding & Shift registers empty? - beq 1001b - .endm - - .macro waituart, rd, rx -1001: ldr \rd, [\rx, #KS8695_URLS] @ Read Line Status Register - tst \rd, #URLS_URTHRE @ Holding Register empty? - beq 1001b - .endm diff --git a/arch/arm/include/debug/renesas-scif.S b/arch/arm/include/debug/renesas-scif.S index 1c5f795587fc..25f06663a9a4 100644 --- a/arch/arm/include/debug/renesas-scif.S +++ b/arch/arm/include/debug/renesas-scif.S @@ -11,7 +11,11 @@ #define SCIF_PHYS CONFIG_DEBUG_UART_PHYS #define SCIF_VIRT ((SCIF_PHYS & 0x00ffffff) | 0xfd000000) -#if CONFIG_DEBUG_UART_PHYS < 0xe6e00000 +#if defined(CONFIG_DEBUG_R7S9210_SCIF2) || defined(CONFIG_DEBUG_R7S9210_SCIF4) +/* RZ/A2 SCIFA */ +#define FTDR 0x06 +#define FSR 0x08 +#elif CONFIG_DEBUG_UART_PHYS < 0xe6e00000 /* SCIFA */ #define FTDR 0x20 #define FSR 0x14 diff --git a/arch/arm/include/debug/ux500.S b/arch/arm/include/debug/ux500.S index c626f89b3e4a..c516900947bb 100644 --- a/arch/arm/include/debug/ux500.S +++ b/arch/arm/include/debug/ux500.S @@ -20,21 +20,16 @@ #define U8500_UART0_PHYS_BASE (0x80120000) #define U8500_UART1_PHYS_BASE (0x80121000) #define U8500_UART2_PHYS_BASE (0x80007000) -#define U8500_UART0_VIRT_BASE (0xf8120000) -#define U8500_UART1_VIRT_BASE (0xf8121000) -#define U8500_UART2_VIRT_BASE (0xf8007000) #define __UX500_PHYS_UART(n) U8500_UART##n##_PHYS_BASE -#define __UX500_VIRT_UART(n) U8500_UART##n##_VIRT_BASE #endif -#if !defined(__UX500_PHYS_UART) || !defined(__UX500_VIRT_UART) +#if !defined(__UX500_PHYS_UART) #error Unknown SOC #endif #define UX500_PHYS_UART(n) __UX500_PHYS_UART(n) -#define UX500_VIRT_UART(n) __UX500_VIRT_UART(n) #define UART_PHYS_BASE UX500_PHYS_UART(CONFIG_UX500_DEBUG_UART) -#define UART_VIRT_BASE UX500_VIRT_UART(CONFIG_UX500_DEBUG_UART) +#define UART_VIRT_BASE (0xfff07000) .macro addruart, rp, rv, tmp ldr \rp, =UART_PHYS_BASE @ no, physical address diff --git a/arch/arm/mach-aspeed/Kconfig b/arch/arm/mach-aspeed/Kconfig index a15c3a291386..56007b0b6120 100644 --- a/arch/arm/mach-aspeed/Kconfig +++ b/arch/arm/mach-aspeed/Kconfig @@ -1,11 +1,10 @@ # SPDX-License-Identifier: GPL-2.0-only menuconfig ARCH_ASPEED bool "Aspeed BMC architectures" - depends on ARCH_MULTI_V5 || ARCH_MULTI_V6 + depends on ARCH_MULTI_V5 || ARCH_MULTI_V6 || ARCH_MULTI_V7 select SRAM select WATCHDOG select ASPEED_WATCHDOG - select FTTMR010_TIMER select MFD_SYSCON select PINCTRL help @@ -18,6 +17,7 @@ config MACH_ASPEED_G4 depends on ARCH_MULTI_V5 select CPU_ARM926T select PINCTRL_ASPEED_G4 + select FTTMR010_TIMER help Say yes if you intend to run on an Aspeed ast2400 or similar fourth generation BMCs, such as those used by OpenPower Power8 @@ -28,8 +28,21 @@ config MACH_ASPEED_G5 depends on ARCH_MULTI_V6 select CPU_V6 select PINCTRL_ASPEED_G5 + select FTTMR010_TIMER help Say yes if you intend to run on an Aspeed ast2500 or similar fifth generation Aspeed BMCs. +config MACH_ASPEED_G6 + bool "Aspeed SoC 6th Generation" + depends on ARCH_MULTI_V7 + select CPU_V7 + select PINCTRL_ASPEED_G6 + select ARM_GIC + select HAVE_ARM_ARCH_TIMER + select HAVE_SMP + help + Say yes if you intend to run on an Aspeed ast2600 or similar + sixth generation Aspeed BMCs. + endif diff --git a/arch/arm/mach-aspeed/Makefile b/arch/arm/mach-aspeed/Makefile new file mode 100644 index 000000000000..1951b3317a76 --- /dev/null +++ b/arch/arm/mach-aspeed/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Copyright (C) ASPEED Technology Inc. +# Copyright IBM Corp. + +obj-$(CONFIG_SMP) += platsmp.o diff --git a/arch/arm/mach-aspeed/platsmp.c b/arch/arm/mach-aspeed/platsmp.c new file mode 100644 index 000000000000..2324becf7991 --- /dev/null +++ b/arch/arm/mach-aspeed/platsmp.c @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright (C) ASPEED Technology Inc. +// Copyright IBM Corp. + +#include <linux/of_address.h> +#include <linux/io.h> +#include <linux/of.h> +#include <linux/smp.h> + +#define BOOT_ADDR 0x00 +#define BOOT_SIG 0x04 + +static struct device_node *secboot_node; + +static int aspeed_g6_boot_secondary(unsigned int cpu, struct task_struct *idle) +{ + void __iomem *base; + + base = of_iomap(secboot_node, 0); + if (!base) { + pr_err("could not map the secondary boot base!"); + return -ENODEV; + } + + writel_relaxed(0, base + BOOT_ADDR); + writel_relaxed(__pa_symbol(secondary_startup_arm), base + BOOT_ADDR); + writel_relaxed((0xABBAAB00 | (cpu & 0xff)), base + BOOT_SIG); + + dsb_sev(); + + iounmap(base); + + return 0; +} + +static void __init aspeed_g6_smp_prepare_cpus(unsigned int max_cpus) +{ + void __iomem *base; + + secboot_node = of_find_compatible_node(NULL, NULL, "aspeed,ast2600-smpmem"); + if (!secboot_node) { + pr_err("secboot device node found!!\n"); + return; + } + + base = of_iomap(secboot_node, 0); + if (!base) { + pr_err("could not map the secondary boot base!"); + return; + } + __raw_writel(0xBADABABA, base + BOOT_SIG); + + iounmap(base); +} + +static const struct smp_operations aspeed_smp_ops __initconst = { + .smp_prepare_cpus = aspeed_g6_smp_prepare_cpus, + .smp_boot_secondary = aspeed_g6_boot_secondary, +}; + +CPU_METHOD_OF_DECLARE(aspeed_smp, "aspeed,ast2600-smp", &aspeed_smp_ops); diff --git a/arch/arm/mach-at91/.gitignore b/arch/arm/mach-at91/.gitignore new file mode 100644 index 000000000000..2ecd6f51c8a9 --- /dev/null +++ b/arch/arm/mach-at91/.gitignore @@ -0,0 +1 @@ +pm_data-offsets.h diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index 31b61f0e1c07..de64301dcff2 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -19,9 +19,10 @@ ifeq ($(CONFIG_PM_DEBUG),y) CFLAGS_pm.o += -DDEBUG endif -include/generated/at91_pm_data-offsets.h: arch/arm/mach-at91/pm_data-offsets.s FORCE +$(obj)/pm_data-offsets.h: $(obj)/pm_data-offsets.s FORCE $(call filechk,offsets,__PM_DATA_OFFSETS_H__) -arch/arm/mach-at91/pm_suspend.o: include/generated/at91_pm_data-offsets.h +$(obj)/pm_suspend.o: $(obj)/pm_data-offsets.h targets += pm_data-offsets.s +clean-files += pm_data-offsets.h diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspend.S index c751f047b116..ed57c879d4e1 100644 --- a/arch/arm/mach-at91/pm_suspend.S +++ b/arch/arm/mach-at91/pm_suspend.S @@ -10,7 +10,7 @@ #include <linux/linkage.h> #include <linux/clk/at91_pmc.h> #include "pm.h" -#include "generated/at91_pm_data-offsets.h" +#include "pm_data-offsets.h" #define SRAMC_SELF_FRESH_ACTIVE 0x01 #define SRAMC_SELF_FRESH_EXIT 0x00 diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index 5a59cebc7d0a..dd427bd2768c 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig @@ -1,11 +1,22 @@ # SPDX-License-Identifier: GPL-2.0 + +menuconfig ARCH_DAVINCI + bool "TI DaVinci" + depends on ARCH_MULTI_V5 + select DAVINCI_TIMER + select ZONE_DMA + select ARCH_HAS_HOLES_MEMORYMODEL + select PM_GENERIC_DOMAINS if PM + select PM_GENERIC_DOMAINS_OF if PM && OF + select REGMAP_MMIO + select HAVE_IDE + select PINCTRL_SINGLE + if ARCH_DAVINCI config ARCH_DAVINCI_DMx bool -menu "TI DaVinci Implementations" - comment "DaVinci Core Type" config ARCH_DAVINCI_DM644x @@ -225,6 +236,4 @@ config DAVINCI_MUX_WARNINGS to change the pin multiplexing setup. When there are no warnings printed, it's safe to deselect DAVINCI_MUX for your product. -endmenu - endif diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile index f76a8482784f..a03d8443ef08 100644 --- a/arch/arm/mach-davinci/Makefile +++ b/arch/arm/mach-davinci/Makefile @@ -4,6 +4,8 @@ # # +ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include + # Common objects obj-y := time.o serial.o usb.o \ common.o sram.o diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c index e6b8ffd934a1..018ab4b549f1 100644 --- a/arch/arm/mach-davinci/da830.c +++ b/arch/arm/mach-davinci/da830.c @@ -21,7 +21,8 @@ #include <mach/common.h> #include <mach/cputype.h> #include <mach/da8xx.h> -#include <mach/time.h> + +#include <clocksource/timer-davinci.h> #include "irqs.h" #include "mux.h" @@ -676,32 +677,17 @@ int __init da830_register_gpio(void) return da8xx_register_gpio(&da830_gpio_platform_data); } -static struct davinci_timer_instance da830_timer_instance[2] = { - { - .base = DA8XX_TIMER64P0_BASE, - .bottom_irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT12_0), - .top_irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT34_0), - .cmp_off = DA830_CMP12_0, - .cmp_irq = DAVINCI_INTC_IRQ(IRQ_DA830_T12CMPINT0_0), - }, - { - .base = DA8XX_TIMER64P1_BASE, - .bottom_irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT12_1), - .top_irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT34_1), - .cmp_off = DA830_CMP12_0, - .cmp_irq = DAVINCI_INTC_IRQ(IRQ_DA830_T12CMPINT0_1), - }, -}; - /* - * T0_BOT: Timer 0, bottom : Used for clock_event & clocksource - * T0_TOP: Timer 0, top : Used by DSP - * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer + * Bottom half of timer0 is used both for clock even and clocksource. + * Top half is used by DSP. */ -static struct davinci_timer_info da830_timer_info = { - .timers = da830_timer_instance, - .clockevent_id = T0_BOT, - .clocksource_id = T0_BOT, +static const struct davinci_timer_cfg da830_timer_cfg = { + .reg = DEFINE_RES_IO(DA8XX_TIMER64P0_BASE, SZ_4K), + .irq = { + DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_DA830_T12CMPINT0_0)), + DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT12_0)), + }, + .cmp_off = DA830_CMP12_0, }; static const struct davinci_soc_info davinci_soc_info_da830 = { @@ -713,7 +699,6 @@ static const struct davinci_soc_info davinci_soc_info_da830 = { .pinmux_base = DA8XX_SYSCFG0_BASE + 0x120, .pinmux_pins = da830_pins, .pinmux_pins_num = ARRAY_SIZE(da830_pins), - .timer_info = &da830_timer_info, .emac_pdata = &da8xx_emac_pdata, }; @@ -743,6 +728,7 @@ void __init da830_init_time(void) { void __iomem *pll; struct clk *clk; + int rv; clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DA830_REF_FREQ); @@ -751,8 +737,13 @@ void __init da830_init_time(void) da830_pll_init(NULL, pll, NULL); clk = clk_get(NULL, "timer0"); + if (WARN_ON(IS_ERR(clk))) { + pr_err("Unable to get the timer clock\n"); + return; + } - davinci_timer_init(clk); + rv = davinci_timer_register(clk, &da830_timer_cfg); + WARN(rv, "Unable to register the timer: %d\n", rv); } static struct resource da830_psc0_resources[] = { diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c index 77bc64d6e39b..73b7cc53f966 100644 --- a/arch/arm/mach-davinci/da850.c +++ b/arch/arm/mach-davinci/da850.c @@ -35,7 +35,8 @@ #include <mach/cputype.h> #include <mach/da8xx.h> #include <mach/pm.h> -#include <mach/time.h> + +#include <clocksource/timer-davinci.h> #include "irqs.h" #include "mux.h" @@ -333,38 +334,16 @@ static struct davinci_id da850_ids[] = { }, }; -static struct davinci_timer_instance da850_timer_instance[4] = { - { - .base = DA8XX_TIMER64P0_BASE, - .bottom_irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT12_0), - .top_irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT34_0), - }, - { - .base = DA8XX_TIMER64P1_BASE, - .bottom_irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT12_1), - .top_irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT34_1), - }, - { - .base = DA850_TIMER64P2_BASE, - .bottom_irq = DAVINCI_INTC_IRQ(IRQ_DA850_TINT12_2), - .top_irq = DAVINCI_INTC_IRQ(IRQ_DA850_TINT34_2), - }, - { - .base = DA850_TIMER64P3_BASE, - .bottom_irq = DAVINCI_INTC_IRQ(IRQ_DA850_TINT12_3), - .top_irq = DAVINCI_INTC_IRQ(IRQ_DA850_TINT34_3), - }, -}; - /* - * T0_BOT: Timer 0, bottom : Used for clock_event - * T0_TOP: Timer 0, top : Used for clocksource - * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer + * Bottom half of timer 0 is used for clock_event, top half for + * clocksource. */ -static struct davinci_timer_info da850_timer_info = { - .timers = da850_timer_instance, - .clockevent_id = T0_BOT, - .clocksource_id = T0_TOP, +static const struct davinci_timer_cfg da850_timer_cfg = { + .reg = DEFINE_RES_IO(DA8XX_TIMER64P0_BASE, SZ_4K), + .irq = { + DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT12_0)), + DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT34_0)), + }, }; #ifdef CONFIG_CPU_FREQ @@ -635,7 +614,6 @@ static const struct davinci_soc_info davinci_soc_info_da850 = { .pinmux_base = DA8XX_SYSCFG0_BASE + 0x120, .pinmux_pins = da850_pins, .pinmux_pins_num = ARRAY_SIZE(da850_pins), - .timer_info = &da850_timer_info, .emac_pdata = &da8xx_emac_pdata, .sram_dma = DA8XX_SHARED_RAM_BASE, .sram_len = SZ_128K, @@ -672,6 +650,7 @@ void __init da850_init_time(void) void __iomem *pll0; struct regmap *cfgchip; struct clk *clk; + int rv; clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DA850_REF_FREQ); @@ -681,8 +660,13 @@ void __init da850_init_time(void) da850_pll0_init(NULL, pll0, cfgchip); clk = clk_get(NULL, "timer0"); + if (WARN_ON(IS_ERR(clk))) { + pr_err("Unable to get the timer clock\n"); + return; + } - davinci_timer_init(clk); + rv = davinci_timer_register(clk, &da850_timer_cfg); + WARN(rv, "Unable to register the timer: %d\n", rv); } static struct resource da850_pll1_resources[] = { diff --git a/arch/arm/mach-davinci/davinci.h b/arch/arm/mach-davinci/davinci.h index 56c1835c42e5..208d7a4d3597 100644 --- a/arch/arm/mach-davinci/davinci.h +++ b/arch/arm/mach-davinci/davinci.h @@ -60,6 +60,9 @@ void davinci_map_sysmod(void); #define DAVINCI_GPIO_BASE 0x01C67000 int davinci_gpio_register(struct resource *res, int size, void *pdata); +#define DAVINCI_TIMER0_BASE (IO_PHYS + 0x21400) +#define DAVINCI_WDOG_BASE (IO_PHYS + 0x21C00) + /* DM355 base addresses */ #define DM355_ASYNC_EMIF_CONTROL_BASE 0x01e10000 #define DM355_ASYNC_EMIF_DATA_CE0_BASE 0x02000000 diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c index c6073326be2e..5de72d2fa8f0 100644 --- a/arch/arm/mach-davinci/dm355.c +++ b/arch/arm/mach-davinci/dm355.c @@ -30,7 +30,8 @@ #include <mach/cputype.h> #include <mach/mux.h> #include <mach/serial.h> -#include <mach/time.h> + +#include <clocksource/timer-davinci.h> #include "asp.h" #include "davinci.h" @@ -620,15 +621,15 @@ static struct davinci_id dm355_ids[] = { }; /* - * T0_BOT: Timer 0, bottom: clockevent source for hrtimers - * T0_TOP: Timer 0, top : clocksource for generic timekeeping - * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code) - * T1_TOP: Timer 1, top : <unused> + * Bottom half of timer0 is used for clockevent, top half is used for + * clocksource. */ -static struct davinci_timer_info dm355_timer_info = { - .timers = davinci_timer_instance, - .clockevent_id = T0_BOT, - .clocksource_id = T0_TOP, +static const struct davinci_timer_cfg dm355_timer_cfg = { + .reg = DEFINE_RES_IO(DAVINCI_TIMER0_BASE, SZ_4K), + .irq = { + DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT12)), + DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT34)), + }, }; static struct plat_serial8250_port dm355_serial0_platform_data[] = { @@ -706,7 +707,6 @@ static const struct davinci_soc_info davinci_soc_info_dm355 = { .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE, .pinmux_pins = dm355_pins, .pinmux_pins_num = ARRAY_SIZE(dm355_pins), - .timer_info = &dm355_timer_info, .sram_dma = 0x00010000, .sram_len = SZ_32K, }; @@ -733,6 +733,7 @@ void __init dm355_init_time(void) { void __iomem *pll1, *psc; struct clk *clk; + int rv; clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DM355_REF_FREQ); @@ -743,8 +744,13 @@ void __init dm355_init_time(void) dm355_psc_init(NULL, psc); clk = clk_get(NULL, "timer0"); + if (WARN_ON(IS_ERR(clk))) { + pr_err("Unable to get the timer clock\n"); + return; + } - davinci_timer_init(clk); + rv = davinci_timer_register(clk, &dm355_timer_cfg); + WARN(rv, "Unable to register the timer: %d\n", rv); } static struct resource dm355_pll2_resources[] = { diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c index 2f9ae6431bf5..8062412be70f 100644 --- a/arch/arm/mach-davinci/dm365.c +++ b/arch/arm/mach-davinci/dm365.c @@ -784,6 +784,10 @@ void __init dm365_init_time(void) dm365_psc_init(NULL, psc); clk = clk_get(NULL, "timer0"); + if (WARN_ON(IS_ERR(clk))) { + pr_err("Unable to get the timer clock\n"); + return; + } davinci_timer_init(clk); } diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c index 1b9e9a6192ef..24988939ae46 100644 --- a/arch/arm/mach-davinci/dm644x.c +++ b/arch/arm/mach-davinci/dm644x.c @@ -27,7 +27,8 @@ #include <mach/cputype.h> #include <mach/mux.h> #include <mach/serial.h> -#include <mach/time.h> + +#include <clocksource/timer-davinci.h> #include "asp.h" #include "davinci.h" @@ -561,15 +562,15 @@ static struct davinci_id dm644x_ids[] = { }; /* - * T0_BOT: Timer 0, bottom: clockevent source for hrtimers - * T0_TOP: Timer 0, top : clocksource for generic timekeeping - * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code) - * T1_TOP: Timer 1, top : <unused> + * Bottom half of timer0 is used for clockevent, top half is used for + * clocksource. */ -static struct davinci_timer_info dm644x_timer_info = { - .timers = davinci_timer_instance, - .clockevent_id = T0_BOT, - .clocksource_id = T0_TOP, +static const struct davinci_timer_cfg dm644x_timer_cfg = { + .reg = DEFINE_RES_IO(DAVINCI_TIMER0_BASE, SZ_4K), + .irq = { + DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT12)), + DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT34)), + }, }; static struct plat_serial8250_port dm644x_serial0_platform_data[] = { @@ -647,7 +648,6 @@ static const struct davinci_soc_info davinci_soc_info_dm644x = { .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE, .pinmux_pins = dm644x_pins, .pinmux_pins_num = ARRAY_SIZE(dm644x_pins), - .timer_info = &dm644x_timer_info, .emac_pdata = &dm644x_emac_pdata, .sram_dma = 0x00008000, .sram_len = SZ_16K, @@ -669,6 +669,7 @@ void __init dm644x_init_time(void) { void __iomem *pll1, *psc; struct clk *clk; + int rv; clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DM644X_REF_FREQ); @@ -679,8 +680,13 @@ void __init dm644x_init_time(void) dm644x_psc_init(NULL, psc); clk = clk_get(NULL, "timer0"); + if (WARN_ON(IS_ERR(clk))) { + pr_err("Unable to get the timer clock\n"); + return; + } - davinci_timer_init(clk); + rv = davinci_timer_register(clk, &dm644x_timer_cfg); + WARN(rv, "Unable to register the timer: %d\n", rv); } static struct resource dm644x_pll2_resources[] = { diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c index 62ca952fe161..4ffd028ed997 100644 --- a/arch/arm/mach-davinci/dm646x.c +++ b/arch/arm/mach-davinci/dm646x.c @@ -1,5 +1,5 @@ /* - * TI DaVinci DM644x chip specific setup + * TI DaVinci DM646x chip specific setup * * Author: Kevin Hilman, Deep Root Systems, LLC * @@ -28,7 +28,8 @@ #include <mach/cputype.h> #include <mach/mux.h> #include <mach/serial.h> -#include <mach/time.h> + +#include <clocksource/timer-davinci.h> #include "asp.h" #include "davinci.h" @@ -501,15 +502,15 @@ static struct davinci_id dm646x_ids[] = { }; /* - * T0_BOT: Timer 0, bottom: clockevent source for hrtimers - * T0_TOP: Timer 0, top : clocksource for generic timekeeping - * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code) - * T1_TOP: Timer 1, top : <unused> + * Bottom half of timer0 is used for clockevent, top half is used for + * clocksource. */ -static struct davinci_timer_info dm646x_timer_info = { - .timers = davinci_timer_instance, - .clockevent_id = T0_BOT, - .clocksource_id = T0_TOP, +static const struct davinci_timer_cfg dm646x_timer_cfg = { + .reg = DEFINE_RES_IO(DAVINCI_TIMER0_BASE, SZ_4K), + .irq = { + DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT12)), + DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT34)), + }, }; static struct plat_serial8250_port dm646x_serial0_platform_data[] = { @@ -587,7 +588,6 @@ static const struct davinci_soc_info davinci_soc_info_dm646x = { .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE, .pinmux_pins = dm646x_pins, .pinmux_pins_num = ARRAY_SIZE(dm646x_pins), - .timer_info = &dm646x_timer_info, .emac_pdata = &dm646x_emac_pdata, .sram_dma = 0x10010000, .sram_len = SZ_32K, @@ -652,6 +652,7 @@ void __init dm646x_init_time(unsigned long ref_clk_rate, { void __iomem *pll1, *psc; struct clk *clk; + int rv; clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, ref_clk_rate); clk_register_fixed_rate(NULL, "aux_clkin", NULL, 0, aux_clkin_rate); @@ -663,8 +664,13 @@ void __init dm646x_init_time(unsigned long ref_clk_rate, dm646x_psc_init(NULL, psc); clk = clk_get(NULL, "timer0"); + if (WARN_ON(IS_ERR(clk))) { + pr_err("Unable to get the timer clock\n"); + return; + } - davinci_timer_init(clk); + rv = davinci_timer_register(clk, &dm646x_timer_cfg); + WARN(rv, "Unable to register the timer: %d\n", rv); } static struct resource dm646x_pll2_resources[] = { diff --git a/arch/arm/mach-davinci/include/mach/time.h b/arch/arm/mach-davinci/include/mach/time.h index 1c971d8d8ba8..ba913736990f 100644 --- a/arch/arm/mach-davinci/include/mach/time.h +++ b/arch/arm/mach-davinci/include/mach/time.h @@ -11,9 +11,7 @@ #ifndef __ARCH_ARM_MACH_DAVINCI_TIME_H #define __ARCH_ARM_MACH_DAVINCI_TIME_H -#define DAVINCI_TIMER0_BASE (IO_PHYS + 0x21400) #define DAVINCI_TIMER1_BASE (IO_PHYS + 0x21800) -#define DAVINCI_WDOG_BASE (IO_PHYS + 0x21C00) enum { T0_BOT, diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c index 5a6de5368ab0..740410a3bb6a 100644 --- a/arch/arm/mach-davinci/time.c +++ b/arch/arm/mach-davinci/time.c @@ -398,17 +398,3 @@ void __init davinci_timer_init(struct clk *timer_clk) for (i=0; i< ARRAY_SIZE(timers); i++) timer32_config(&timers[i]); } - -static int __init of_davinci_timer_init(struct device_node *np) -{ - struct clk *clk; - - clk = of_clk_get(np, 0); - if (IS_ERR(clk)) - return PTR_ERR(clk); - - davinci_timer_init(clk); - - return 0; -} -TIMER_OF_DECLARE(davinci_timer, "ti,da830-timer", of_davinci_timer_init); diff --git a/arch/arm/mach-dove/include/mach/bridge-regs.h b/arch/arm/mach-dove/bridge-regs.h index f4a5b34489b7..ace0b0bfbf11 100644 --- a/arch/arm/mach-dove/include/mach/bridge-regs.h +++ b/arch/arm/mach-dove/bridge-regs.h @@ -1,6 +1,4 @@ /* - * arch/arm/mach-dove/include/mach/bridge-regs.h - * * Mbus-L to Mbus Bridge Registers * * This file is licensed under the terms of the GNU General Public @@ -11,7 +9,7 @@ #ifndef __ASM_ARCH_BRIDGE_REGS_H #define __ASM_ARCH_BRIDGE_REGS_H -#include <mach/dove.h> +#include "dove.h" #define CPU_CONFIG (BRIDGE_VIRT_BASE + 0x0000) diff --git a/arch/arm/mach-dove/cm-a510.c b/arch/arm/mach-dove/cm-a510.c index b9a7c33db29a..9f25c993d863 100644 --- a/arch/arm/mach-dove/cm-a510.c +++ b/arch/arm/mach-dove/cm-a510.c @@ -22,8 +22,7 @@ #include <asm/mach-types.h> #include <asm/mach/arch.h> -#include <mach/dove.h> - +#include "dove.h" #include "common.h" static struct mv643xx_eth_platform_data cm_a510_ge00_data = { diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c index d7b826d2695c..01b830afcea9 100644 --- a/arch/arm/mach-dove/common.c +++ b/arch/arm/mach-dove/common.c @@ -22,11 +22,11 @@ #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <asm/mach/time.h> -#include <mach/bridge-regs.h> -#include <mach/pm.h> #include <plat/common.h> #include <plat/irq.h> #include <plat/time.h> +#include "bridge-regs.h" +#include "pm.h" #include "common.h" /* These can go away once Dove uses the mvebu-mbus DT binding */ diff --git a/arch/arm/mach-dove/dove-db-setup.c b/arch/arm/mach-dove/dove-db-setup.c index 8971c3c0f0fe..418ab21b9d9b 100644 --- a/arch/arm/mach-dove/dove-db-setup.c +++ b/arch/arm/mach-dove/dove-db-setup.c @@ -24,7 +24,7 @@ #include <linux/gpio.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> -#include <mach/dove.h> +#include "dove.h" #include "common.h" static struct mv643xx_eth_platform_data dove_db_ge00_data = { diff --git a/arch/arm/mach-dove/include/mach/dove.h b/arch/arm/mach-dove/dove.h index 00f45458b3ec..320ed1696abd 100644 --- a/arch/arm/mach-dove/include/mach/dove.h +++ b/arch/arm/mach-dove/dove.h @@ -1,6 +1,4 @@ /* - * arch/arm/mach-dove/include/mach/dove.h - * * Generic definitions for Marvell Dove 88AP510 SoC * * This file is licensed under the terms of the GNU General Public @@ -11,7 +9,7 @@ #ifndef __ASM_ARCH_DOVE_H #define __ASM_ARCH_DOVE_H -#include <mach/irqs.h> +#include "irqs.h" /* * Marvell Dove address maps. @@ -20,8 +18,8 @@ * c8000000 fdb00000 1M Cryptographic SRAM * e0000000 @runtime 128M PCIe-0 Memory space * e8000000 @runtime 128M PCIe-1 Memory space - * f1000000 fde00000 8M on-chip south-bridge registers - * f1800000 fe600000 8M on-chip north-bridge registers + * f1000000 fec00000 1M on-chip south-bridge registers + * f1800000 fe400000 8M on-chip north-bridge registers * f2000000 fee00000 1M PCIe-0 I/O space * f2100000 fef00000 1M PCIe-1 I/O space */ @@ -44,11 +42,11 @@ #define DOVE_SCRATCHPAD_SIZE SZ_1M #define DOVE_SB_REGS_PHYS_BASE 0xf1000000 -#define DOVE_SB_REGS_VIRT_BASE IOMEM(0xfde00000) -#define DOVE_SB_REGS_SIZE SZ_8M +#define DOVE_SB_REGS_VIRT_BASE IOMEM(0xfec00000) +#define DOVE_SB_REGS_SIZE SZ_1M #define DOVE_NB_REGS_PHYS_BASE 0xf1800000 -#define DOVE_NB_REGS_VIRT_BASE IOMEM(0xfe600000) +#define DOVE_NB_REGS_VIRT_BASE IOMEM(0xfe400000) #define DOVE_NB_REGS_SIZE SZ_8M #define DOVE_PCIE0_IO_PHYS_BASE 0xf2000000 diff --git a/arch/arm/mach-dove/include/mach/hardware.h b/arch/arm/mach-dove/include/mach/hardware.h deleted file mode 100644 index f1368b9a8ece..000000000000 --- a/arch/arm/mach-dove/include/mach/hardware.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * arch/arm/mach-dove/include/mach/hardware.h - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -#include "dove.h" - -/* Macros below are required for compatibility with PXA AC'97 driver. */ -#define __REG(x) (*((volatile u32 *)((x) - DOVE_SB_REGS_PHYS_BASE + \ - DOVE_SB_REGS_VIRT_BASE))) -#define __PREG(x) (((u32)&(x)) - DOVE_SB_REGS_VIRT_BASE + \ - DOVE_SB_REGS_PHYS_BASE) -#endif diff --git a/arch/arm/mach-dove/include/mach/uncompress.h b/arch/arm/mach-dove/include/mach/uncompress.h index 5c8ae9b9d39a..7a4bd8838036 100644 --- a/arch/arm/mach-dove/include/mach/uncompress.h +++ b/arch/arm/mach-dove/include/mach/uncompress.h @@ -1,15 +1,13 @@ /* - * arch/arm/mach-dove/include/mach/uncompress.h - * * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ -#include <mach/dove.h> +#define UART0_PHYS_BASE (0xf1000000 + 0x12000) -#define UART_THR ((volatile unsigned char *)(DOVE_UART0_PHYS_BASE + 0x0)) -#define UART_LSR ((volatile unsigned char *)(DOVE_UART0_PHYS_BASE + 0x14)) +#define UART_THR ((volatile unsigned char *)(UART0_PHYS_BASE + 0x0)) +#define UART_LSR ((volatile unsigned char *)(UART0_PHYS_BASE + 0x14)) #define LSR_THRE 0x20 diff --git a/arch/arm/mach-dove/irq.c b/arch/arm/mach-dove/irq.c index d6627c1f7f30..31ccbcee2627 100644 --- a/arch/arm/mach-dove/irq.c +++ b/arch/arm/mach-dove/irq.c @@ -11,9 +11,12 @@ #include <linux/irq.h> #include <linux/io.h> #include <asm/exception.h> + #include <plat/irq.h> -#include <mach/bridge-regs.h> #include <plat/orion-gpio.h> + +#include "pm.h" +#include "bridge-regs.h" #include "common.h" static int __initdata gpio0_irqs[4] = { diff --git a/arch/arm/mach-dove/include/mach/irqs.h b/arch/arm/mach-dove/irqs.h index 8ff0fa8b4fcd..a0742179faff 100644 --- a/arch/arm/mach-dove/include/mach/irqs.h +++ b/arch/arm/mach-dove/irqs.h @@ -1,6 +1,4 @@ /* - * arch/arm/mach-dove/include/mach/irqs.h - * * IRQ definitions for Marvell Dove 88AP510 SoC * * This file is licensed under the terms of the GNU General Public diff --git a/arch/arm/mach-dove/mpp.c b/arch/arm/mach-dove/mpp.c index 8a433a51289c..6acd8488bb05 100644 --- a/arch/arm/mach-dove/mpp.c +++ b/arch/arm/mach-dove/mpp.c @@ -12,8 +12,8 @@ #include <linux/gpio.h> #include <linux/io.h> #include <plat/mpp.h> -#include <mach/dove.h> #include <plat/orion-gpio.h> +#include "dove.h" #include "mpp.h" struct dove_mpp_grp { diff --git a/arch/arm/mach-dove/pcie.c b/arch/arm/mach-dove/pcie.c index dfb62f3f5dcf..ee91ac6b5ebf 100644 --- a/arch/arm/mach-dove/pcie.c +++ b/arch/arm/mach-dove/pcie.c @@ -17,9 +17,9 @@ #include <asm/setup.h> #include <asm/delay.h> #include <plat/pcie.h> -#include <mach/irqs.h> -#include <mach/bridge-regs.h> #include <plat/addr-map.h> +#include "irqs.h" +#include "bridge-regs.h" #include "common.h" struct pcie_port { diff --git a/arch/arm/mach-dove/include/mach/pm.h b/arch/arm/mach-dove/pm.h index d22b9b174007..01267746d707 100644 --- a/arch/arm/mach-dove/include/mach/pm.h +++ b/arch/arm/mach-dove/pm.h @@ -1,6 +1,4 @@ /* - * arch/arm/mach-dove/include/mach/pm.h - * * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. @@ -10,7 +8,7 @@ #define __ASM_ARCH_PM_H #include <asm/errno.h> -#include <mach/irqs.h> +#include "irqs.h" #define CLOCK_GATING_CONTROL (DOVE_PMU_VIRT_BASE + 0x38) #define CLOCK_GATING_BIT_USB0 0 diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index d7422233a130..f83786640f94 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -13,6 +13,7 @@ menuconfig ARCH_EXYNOS select ARM_AMBA select ARM_GIC select COMMON_CLK_SAMSUNG + select EXYNOS_CHIPID select EXYNOS_THERMAL select EXYNOS_PMU select EXYNOS_SROM diff --git a/arch/arm/mach-imx/mach-imx7d.c b/arch/arm/mach-imx/mach-imx7d.c index 95713450591a..ebb27592a9f7 100644 --- a/arch/arm/mach-imx/mach-imx7d.c +++ b/arch/arm/mach-imx/mach-imx7d.c @@ -30,12 +30,6 @@ static int ar8031_phy_fixup(struct phy_device *dev) val &= ~(0x1 << 8); phy_write(dev, 0xe, val); - /* introduce tx clock delay */ - phy_write(dev, 0x1d, 0x5); - val = phy_read(dev, 0x1e); - val |= 0x0100; - phy_write(dev, 0x1e, val); - return 0; } diff --git a/arch/arm/mach-iop13xx/Kconfig b/arch/arm/mach-iop13xx/Kconfig deleted file mode 100644 index c4f04070b4c1..000000000000 --- a/arch/arm/mach-iop13xx/Kconfig +++ /dev/null @@ -1,21 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -if ARCH_IOP13XX - -menu "IOP13XX Implementation Options" - -comment "IOP13XX Platform Support" - -config MACH_IQ81340SC - bool "Enable IQ81340SC Hardware Support" - help - Say Y here if you want to support running on the Intel IQ81340SC - evaluation kit. - -config MACH_IQ81340MC - bool "Enable IQ81340MC Hardware Support" - help - Say Y here if you want to support running on the Intel IQ81340MC - evaluation kit. - -endmenu -endif diff --git a/arch/arm/mach-iop13xx/Makefile b/arch/arm/mach-iop13xx/Makefile deleted file mode 100644 index 5757c8f6e371..000000000000 --- a/arch/arm/mach-iop13xx/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -obj-$(CONFIG_ARCH_IOP13XX) += setup.o -obj-$(CONFIG_ARCH_IOP13XX) += irq.o -obj-$(CONFIG_ARCH_IOP13XX) += pci.o -obj-$(CONFIG_ARCH_IOP13XX) += io.o -obj-$(CONFIG_ARCH_IOP13XX) += tpmi.o -obj-$(CONFIG_MACH_IQ81340SC) += iq81340sc.o -obj-$(CONFIG_MACH_IQ81340MC) += iq81340mc.o -obj-$(CONFIG_PCI_MSI) += msi.o diff --git a/arch/arm/mach-iop13xx/Makefile.boot b/arch/arm/mach-iop13xx/Makefile.boot deleted file mode 100644 index 4f29554c8401..000000000000 --- a/arch/arm/mach-iop13xx/Makefile.boot +++ /dev/null @@ -1,4 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - zreladdr-y += 0x00008000 -params_phys-y := 0x00000100 -initrd_phys-y := 0x00800000 diff --git a/arch/arm/mach-iop13xx/include/mach/adma.h b/arch/arm/mach-iop13xx/include/mach/adma.h deleted file mode 100644 index 51d206f5b093..000000000000 --- a/arch/arm/mach-iop13xx/include/mach/adma.h +++ /dev/null @@ -1,608 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright(c) 2006, Intel Corporation. - */ -#ifndef _ADMA_H -#define _ADMA_H -#include <linux/types.h> -#include <linux/io.h> -#include <mach/hardware.h> -#include <asm/hardware/iop_adma.h> - -#define ADMA_ACCR(chan) (chan->mmr_base + 0x0) -#define ADMA_ACSR(chan) (chan->mmr_base + 0x4) -#define ADMA_ADAR(chan) (chan->mmr_base + 0x8) -#define ADMA_IIPCR(chan) (chan->mmr_base + 0x18) -#define ADMA_IIPAR(chan) (chan->mmr_base + 0x1c) -#define ADMA_IIPUAR(chan) (chan->mmr_base + 0x20) -#define ADMA_ANDAR(chan) (chan->mmr_base + 0x24) -#define ADMA_ADCR(chan) (chan->mmr_base + 0x28) -#define ADMA_CARMD(chan) (chan->mmr_base + 0x2c) -#define ADMA_ABCR(chan) (chan->mmr_base + 0x30) -#define ADMA_DLADR(chan) (chan->mmr_base + 0x34) -#define ADMA_DUADR(chan) (chan->mmr_base + 0x38) -#define ADMA_SLAR(src, chan) (chan->mmr_base + (0x3c + (src << 3))) -#define ADMA_SUAR(src, chan) (chan->mmr_base + (0x40 + (src << 3))) - -struct iop13xx_adma_src { - u32 src_addr; - union { - u32 upper_src_addr; - struct { - unsigned int pq_upper_src_addr:24; - unsigned int pq_dmlt:8; - }; - }; -}; - -struct iop13xx_adma_desc_ctrl { - unsigned int int_en:1; - unsigned int xfer_dir:2; - unsigned int src_select:4; - unsigned int zero_result:1; - unsigned int block_fill_en:1; - unsigned int crc_gen_en:1; - unsigned int crc_xfer_dis:1; - unsigned int crc_seed_fetch_dis:1; - unsigned int status_write_back_en:1; - unsigned int endian_swap_en:1; - unsigned int reserved0:2; - unsigned int pq_update_xfer_en:1; - unsigned int dual_xor_en:1; - unsigned int pq_xfer_en:1; - unsigned int p_xfer_dis:1; - unsigned int reserved1:10; - unsigned int relax_order_en:1; - unsigned int no_snoop_en:1; -}; - -struct iop13xx_adma_byte_count { - unsigned int byte_count:24; - unsigned int host_if:3; - unsigned int reserved:2; - unsigned int zero_result_err_q:1; - unsigned int zero_result_err:1; - unsigned int tx_complete:1; -}; - -struct iop13xx_adma_desc_hw { - u32 next_desc; - union { - u32 desc_ctrl; - struct iop13xx_adma_desc_ctrl desc_ctrl_field; - }; - union { - u32 crc_addr; - u32 block_fill_data; - u32 q_dest_addr; - }; - union { - u32 byte_count; - struct iop13xx_adma_byte_count byte_count_field; - }; - union { - u32 dest_addr; - u32 p_dest_addr; - }; - union { - u32 upper_dest_addr; - u32 pq_upper_dest_addr; - }; - struct iop13xx_adma_src src[1]; -}; - -struct iop13xx_adma_desc_dual_xor { - u32 next_desc; - u32 desc_ctrl; - u32 reserved; - u32 byte_count; - u32 h_dest_addr; - u32 h_upper_dest_addr; - u32 src0_addr; - u32 upper_src0_addr; - u32 src1_addr; - u32 upper_src1_addr; - u32 h_src_addr; - u32 h_upper_src_addr; - u32 d_src_addr; - u32 d_upper_src_addr; - u32 d_dest_addr; - u32 d_upper_dest_addr; -}; - -struct iop13xx_adma_desc_pq_update { - u32 next_desc; - u32 desc_ctrl; - u32 reserved; - u32 byte_count; - u32 p_dest_addr; - u32 p_upper_dest_addr; - u32 src0_addr; - u32 upper_src0_addr; - u32 src1_addr; - u32 upper_src1_addr; - u32 p_src_addr; - u32 p_upper_src_addr; - u32 q_src_addr; - struct { - unsigned int q_upper_src_addr:24; - unsigned int q_dmlt:8; - }; - u32 q_dest_addr; - u32 q_upper_dest_addr; -}; - -static inline int iop_adma_get_max_xor(void) -{ - return 16; -} - -#define iop_adma_get_max_pq iop_adma_get_max_xor - -static inline u32 iop_chan_get_current_descriptor(struct iop_adma_chan *chan) -{ - return __raw_readl(ADMA_ADAR(chan)); -} - -static inline void iop_chan_set_next_descriptor(struct iop_adma_chan *chan, - u32 next_desc_addr) -{ - __raw_writel(next_desc_addr, ADMA_ANDAR(chan)); -} - -#define ADMA_STATUS_BUSY (1 << 13) - -static inline char iop_chan_is_busy(struct iop_adma_chan *chan) -{ - if (__raw_readl(ADMA_ACSR(chan)) & - ADMA_STATUS_BUSY) - return 1; - else - return 0; -} - -static inline int -iop_chan_get_desc_align(struct iop_adma_chan *chan, int num_slots) -{ - return 1; -} -#define iop_desc_is_aligned(x, y) 1 - -static inline int -iop_chan_memcpy_slot_count(size_t len, int *slots_per_op) -{ - *slots_per_op = 1; - return 1; -} - -#define iop_chan_interrupt_slot_count(s, c) iop_chan_memcpy_slot_count(0, s) - -static inline int -iop_chan_memset_slot_count(size_t len, int *slots_per_op) -{ - *slots_per_op = 1; - return 1; -} - -static inline int -iop_chan_xor_slot_count(size_t len, int src_cnt, int *slots_per_op) -{ - static const char slot_count_table[] = { 1, 2, 2, 2, - 2, 3, 3, 3, - 3, 4, 4, 4, - 4, 5, 5, 5, - }; - *slots_per_op = slot_count_table[src_cnt - 1]; - return *slots_per_op; -} - -#define ADMA_MAX_BYTE_COUNT (16 * 1024 * 1024) -#define IOP_ADMA_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT -#define IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT -#define IOP_ADMA_XOR_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT -#define IOP_ADMA_PQ_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT -#define iop_chan_zero_sum_slot_count(l, s, o) iop_chan_xor_slot_count(l, s, o) -#define iop_chan_pq_slot_count iop_chan_xor_slot_count -#define iop_chan_pq_zero_sum_slot_count iop_chan_xor_slot_count - -static inline u32 iop_desc_get_byte_count(struct iop_adma_desc_slot *desc, - struct iop_adma_chan *chan) -{ - struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; - return hw_desc->byte_count_field.byte_count; -} - -static inline u32 iop_desc_get_src_addr(struct iop_adma_desc_slot *desc, - struct iop_adma_chan *chan, - int src_idx) -{ - struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; - return hw_desc->src[src_idx].src_addr; -} - -static inline u32 iop_desc_get_src_count(struct iop_adma_desc_slot *desc, - struct iop_adma_chan *chan) -{ - struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; - return hw_desc->desc_ctrl_field.src_select + 1; -} - -static inline void -iop_desc_init_memcpy(struct iop_adma_desc_slot *desc, unsigned long flags) -{ - struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; - union { - u32 value; - struct iop13xx_adma_desc_ctrl field; - } u_desc_ctrl; - - u_desc_ctrl.value = 0; - u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */ - u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT; - hw_desc->desc_ctrl = u_desc_ctrl.value; - hw_desc->crc_addr = 0; -} - -static inline void -iop_desc_init_memset(struct iop_adma_desc_slot *desc, unsigned long flags) -{ - struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; - union { - u32 value; - struct iop13xx_adma_desc_ctrl field; - } u_desc_ctrl; - - u_desc_ctrl.value = 0; - u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */ - u_desc_ctrl.field.block_fill_en = 1; - u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT; - hw_desc->desc_ctrl = u_desc_ctrl.value; - hw_desc->crc_addr = 0; -} - -/* to do: support buffers larger than ADMA_MAX_BYTE_COUNT */ -static inline void -iop_desc_init_xor(struct iop_adma_desc_slot *desc, int src_cnt, - unsigned long flags) -{ - struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; - union { - u32 value; - struct iop13xx_adma_desc_ctrl field; - } u_desc_ctrl; - - u_desc_ctrl.value = 0; - u_desc_ctrl.field.src_select = src_cnt - 1; - u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */ - u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT; - hw_desc->desc_ctrl = u_desc_ctrl.value; - hw_desc->crc_addr = 0; - -} -#define iop_desc_init_null_xor(d, s, i) iop_desc_init_xor(d, s, i) - -/* to do: support buffers larger than ADMA_MAX_BYTE_COUNT */ -static inline int -iop_desc_init_zero_sum(struct iop_adma_desc_slot *desc, int src_cnt, - unsigned long flags) -{ - struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; - union { - u32 value; - struct iop13xx_adma_desc_ctrl field; - } u_desc_ctrl; - - u_desc_ctrl.value = 0; - u_desc_ctrl.field.src_select = src_cnt - 1; - u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */ - u_desc_ctrl.field.zero_result = 1; - u_desc_ctrl.field.status_write_back_en = 1; - u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT; - hw_desc->desc_ctrl = u_desc_ctrl.value; - hw_desc->crc_addr = 0; - - return 1; -} - -static inline void -iop_desc_init_pq(struct iop_adma_desc_slot *desc, int src_cnt, - unsigned long flags) -{ - struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; - union { - u32 value; - struct iop13xx_adma_desc_ctrl field; - } u_desc_ctrl; - - u_desc_ctrl.value = 0; - u_desc_ctrl.field.src_select = src_cnt - 1; - u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */ - u_desc_ctrl.field.pq_xfer_en = 1; - u_desc_ctrl.field.p_xfer_dis = !!(flags & DMA_PREP_PQ_DISABLE_P); - u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT; - hw_desc->desc_ctrl = u_desc_ctrl.value; -} - -static inline void -iop_desc_init_pq_zero_sum(struct iop_adma_desc_slot *desc, int src_cnt, - unsigned long flags) -{ - struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; - union { - u32 value; - struct iop13xx_adma_desc_ctrl field; - } u_desc_ctrl; - - u_desc_ctrl.value = 0; - u_desc_ctrl.field.src_select = src_cnt - 1; - u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */ - u_desc_ctrl.field.zero_result = 1; - u_desc_ctrl.field.status_write_back_en = 1; - u_desc_ctrl.field.pq_xfer_en = 1; - u_desc_ctrl.field.p_xfer_dis = !!(flags & DMA_PREP_PQ_DISABLE_P); - u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT; - hw_desc->desc_ctrl = u_desc_ctrl.value; -} - -static inline void iop_desc_set_byte_count(struct iop_adma_desc_slot *desc, - struct iop_adma_chan *chan, - u32 byte_count) -{ - struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; - hw_desc->byte_count = byte_count; -} - -static inline void -iop_desc_set_zero_sum_byte_count(struct iop_adma_desc_slot *desc, u32 len) -{ - int slots_per_op = desc->slots_per_op; - struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc, *iter; - int i = 0; - - if (len <= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT) { - hw_desc->byte_count = len; - } else { - do { - iter = iop_hw_desc_slot_idx(hw_desc, i); - iter->byte_count = IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT; - len -= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT; - i += slots_per_op; - } while (len > IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT); - - if (len) { - iter = iop_hw_desc_slot_idx(hw_desc, i); - iter->byte_count = len; - } - } -} - -#define iop_desc_set_pq_zero_sum_byte_count iop_desc_set_zero_sum_byte_count - -static inline void iop_desc_set_dest_addr(struct iop_adma_desc_slot *desc, - struct iop_adma_chan *chan, - dma_addr_t addr) -{ - struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; - hw_desc->dest_addr = addr; - hw_desc->upper_dest_addr = 0; -} - -static inline void -iop_desc_set_pq_addr(struct iop_adma_desc_slot *desc, dma_addr_t *addr) -{ - struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; - - hw_desc->dest_addr = addr[0]; - hw_desc->q_dest_addr = addr[1]; - hw_desc->upper_dest_addr = 0; -} - -static inline void iop_desc_set_memcpy_src_addr(struct iop_adma_desc_slot *desc, - dma_addr_t addr) -{ - struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; - hw_desc->src[0].src_addr = addr; - hw_desc->src[0].upper_src_addr = 0; -} - -static inline void iop_desc_set_xor_src_addr(struct iop_adma_desc_slot *desc, - int src_idx, dma_addr_t addr) -{ - int slot_cnt = desc->slot_cnt, slots_per_op = desc->slots_per_op; - struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc, *iter; - int i = 0; - - do { - iter = iop_hw_desc_slot_idx(hw_desc, i); - iter->src[src_idx].src_addr = addr; - iter->src[src_idx].upper_src_addr = 0; - slot_cnt -= slots_per_op; - if (slot_cnt) { - i += slots_per_op; - addr += IOP_ADMA_XOR_MAX_BYTE_COUNT; - } - } while (slot_cnt); -} - -static inline void -iop_desc_set_pq_src_addr(struct iop_adma_desc_slot *desc, int src_idx, - dma_addr_t addr, unsigned char coef) -{ - int slot_cnt = desc->slot_cnt, slots_per_op = desc->slots_per_op; - struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc, *iter; - struct iop13xx_adma_src *src; - int i = 0; - - do { - iter = iop_hw_desc_slot_idx(hw_desc, i); - src = &iter->src[src_idx]; - src->src_addr = addr; - src->pq_upper_src_addr = 0; - src->pq_dmlt = coef; - slot_cnt -= slots_per_op; - if (slot_cnt) { - i += slots_per_op; - addr += IOP_ADMA_PQ_MAX_BYTE_COUNT; - } - } while (slot_cnt); -} - -static inline void -iop_desc_init_interrupt(struct iop_adma_desc_slot *desc, - struct iop_adma_chan *chan) -{ - iop_desc_init_memcpy(desc, 1); - iop_desc_set_byte_count(desc, chan, 0); - iop_desc_set_dest_addr(desc, chan, 0); - iop_desc_set_memcpy_src_addr(desc, 0); -} - -#define iop_desc_set_zero_sum_src_addr iop_desc_set_xor_src_addr -#define iop_desc_set_pq_zero_sum_src_addr iop_desc_set_pq_src_addr - -static inline void -iop_desc_set_pq_zero_sum_addr(struct iop_adma_desc_slot *desc, int pq_idx, - dma_addr_t *src) -{ - iop_desc_set_xor_src_addr(desc, pq_idx, src[pq_idx]); - iop_desc_set_xor_src_addr(desc, pq_idx+1, src[pq_idx+1]); -} - -static inline void iop_desc_set_next_desc(struct iop_adma_desc_slot *desc, - u32 next_desc_addr) -{ - struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; - - iop_paranoia(hw_desc->next_desc); - hw_desc->next_desc = next_desc_addr; -} - -static inline u32 iop_desc_get_next_desc(struct iop_adma_desc_slot *desc) -{ - struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; - return hw_desc->next_desc; -} - -static inline void iop_desc_clear_next_desc(struct iop_adma_desc_slot *desc) -{ - struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; - hw_desc->next_desc = 0; -} - -static inline void iop_desc_set_block_fill_val(struct iop_adma_desc_slot *desc, - u32 val) -{ - struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; - hw_desc->block_fill_data = val; -} - -static inline enum sum_check_flags -iop_desc_get_zero_result(struct iop_adma_desc_slot *desc) -{ - struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; - struct iop13xx_adma_desc_ctrl desc_ctrl = hw_desc->desc_ctrl_field; - struct iop13xx_adma_byte_count byte_count = hw_desc->byte_count_field; - enum sum_check_flags flags; - - BUG_ON(!(byte_count.tx_complete && desc_ctrl.zero_result)); - - flags = byte_count.zero_result_err_q << SUM_CHECK_Q; - flags |= byte_count.zero_result_err << SUM_CHECK_P; - - return flags; -} - -static inline void iop_chan_append(struct iop_adma_chan *chan) -{ - u32 adma_accr; - - adma_accr = __raw_readl(ADMA_ACCR(chan)); - adma_accr |= 0x2; - __raw_writel(adma_accr, ADMA_ACCR(chan)); -} - -static inline u32 iop_chan_get_status(struct iop_adma_chan *chan) -{ - return __raw_readl(ADMA_ACSR(chan)); -} - -static inline void iop_chan_disable(struct iop_adma_chan *chan) -{ - u32 adma_chan_ctrl = __raw_readl(ADMA_ACCR(chan)); - adma_chan_ctrl &= ~0x1; - __raw_writel(adma_chan_ctrl, ADMA_ACCR(chan)); -} - -static inline void iop_chan_enable(struct iop_adma_chan *chan) -{ - u32 adma_chan_ctrl; - - adma_chan_ctrl = __raw_readl(ADMA_ACCR(chan)); - adma_chan_ctrl |= 0x1; - __raw_writel(adma_chan_ctrl, ADMA_ACCR(chan)); -} - -static inline void iop_adma_device_clear_eot_status(struct iop_adma_chan *chan) -{ - u32 status = __raw_readl(ADMA_ACSR(chan)); - status &= (1 << 12); - __raw_writel(status, ADMA_ACSR(chan)); -} - -static inline void iop_adma_device_clear_eoc_status(struct iop_adma_chan *chan) -{ - u32 status = __raw_readl(ADMA_ACSR(chan)); - status &= (1 << 11); - __raw_writel(status, ADMA_ACSR(chan)); -} - -static inline void iop_adma_device_clear_err_status(struct iop_adma_chan *chan) -{ - u32 status = __raw_readl(ADMA_ACSR(chan)); - status &= (1 << 9) | (1 << 5) | (1 << 4) | (1 << 3); - __raw_writel(status, ADMA_ACSR(chan)); -} - -static inline int -iop_is_err_int_parity(unsigned long status, struct iop_adma_chan *chan) -{ - return test_bit(9, &status); -} - -static inline int -iop_is_err_mcu_abort(unsigned long status, struct iop_adma_chan *chan) -{ - return test_bit(5, &status); -} - -static inline int -iop_is_err_int_tabort(unsigned long status, struct iop_adma_chan *chan) -{ - return test_bit(4, &status); -} - -static inline int -iop_is_err_int_mabort(unsigned long status, struct iop_adma_chan *chan) -{ - return test_bit(3, &status); -} - -static inline int -iop_is_err_pci_tabort(unsigned long status, struct iop_adma_chan *chan) -{ - return 0; -} - -static inline int -iop_is_err_pci_mabort(unsigned long status, struct iop_adma_chan *chan) -{ - return 0; -} - -static inline int -iop_is_err_split_tx(unsigned long status, struct iop_adma_chan *chan) -{ - return 0; -} - -#endif /* _ADMA_H */ diff --git a/arch/arm/mach-iop13xx/include/mach/entry-macro.S b/arch/arm/mach-iop13xx/include/mach/entry-macro.S deleted file mode 100644 index 9f4ecb8861bd..000000000000 --- a/arch/arm/mach-iop13xx/include/mach/entry-macro.S +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * iop13xx low level irq macros - * Copyright (c) 2005-2006, Intel Corporation. - */ - .macro get_irqnr_preamble, base, tmp - mrc p15, 0, \tmp, c15, c1, 0 - orr \tmp, \tmp, #(1 << 6) - mcr p15, 0, \tmp, c15, c1, 0 @ Enable cp6 access - .endm - - /* - * Note: a 1-cycle window exists where iintvec will return the value - * of iintbase, so we explicitly check for "bad zeros" - */ - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - mrc p6, 0, \irqnr, c3, c2, 0 @ Read IINTVEC - cmp \irqnr, #0 - mrceq p6, 0, \irqnr, c3, c2, 0 @ Re-read on potentially bad zero - adds \irqstat, \irqnr, #1 @ Check for 0xffffffff - movne \irqnr, \irqnr, lsr #2 @ Convert to irqnr - .endm - - .macro arch_ret_to_user, tmp1, tmp2 - mrc p15, 0, \tmp1, c15, c1, 0 - ands \tmp2, \tmp1, #(1 << 6) - bicne \tmp1, \tmp1, #(1 << 6) - mcrne p15, 0, \tmp1, c15, c1, 0 @ Disable cp6 access - .endm diff --git a/arch/arm/mach-iop13xx/include/mach/hardware.h b/arch/arm/mach-iop13xx/include/mach/hardware.h deleted file mode 100644 index 8c943fa6bbd7..000000000000 --- a/arch/arm/mach-iop13xx/include/mach/hardware.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H -#include <asm/types.h> - -#ifndef __ASSEMBLY__ -extern u16 iop13xx_dev_id(void); -extern void iop13xx_set_atu_mmr_bases(void); -#endif - -/* - * Generic chipset bits - * - */ -#include "iop13xx.h" - -/* - * Board specific bits - */ -#include "iq81340.h" - -#endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/mach-iop13xx/include/mach/iop13xx.h b/arch/arm/mach-iop13xx/include/mach/iop13xx.h deleted file mode 100644 index 04bb6aca12c5..000000000000 --- a/arch/arm/mach-iop13xx/include/mach/iop13xx.h +++ /dev/null @@ -1,508 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _IOP13XX_HW_H_ -#define _IOP13XX_HW_H_ - -#ifndef __ASSEMBLY__ - -enum reboot_mode; - -/* The ATU offsets can change based on the strapping */ -extern u32 iop13xx_atux_pmmr_offset; -extern u32 iop13xx_atue_pmmr_offset; -void iop13xx_init_early(void); -void iop13xx_init_irq(void); -void iop13xx_map_io(void); -void iop13xx_platform_init(void); -void iop13xx_add_tpmi_devices(void); -void iop13xx_init_irq(void); -void iop13xx_restart(enum reboot_mode, const char *); - -/* CPUID CP6 R0 Page 0 */ -static inline int iop13xx_cpu_id(void) -{ - int id; - asm volatile("mrc p6, 0, %0, c0, c0, 0":"=r" (id)); - return id; -} - -/* WDTCR CP6 R7 Page 9 */ -static inline u32 read_wdtcr(void) -{ - u32 val; - asm volatile("mrc p6, 0, %0, c7, c9, 0":"=r" (val)); - return val; -} -static inline void write_wdtcr(u32 val) -{ - asm volatile("mcr p6, 0, %0, c7, c9, 0"::"r" (val)); -} - -/* WDTSR CP6 R8 Page 9 */ -static inline u32 read_wdtsr(void) -{ - u32 val; - asm volatile("mrc p6, 0, %0, c8, c9, 0":"=r" (val)); - return val; -} -static inline void write_wdtsr(u32 val) -{ - asm volatile("mcr p6, 0, %0, c8, c9, 0"::"r" (val)); -} - -/* RCSR - Reset Cause Status Register */ -static inline u32 read_rcsr(void) -{ - u32 val; - asm volatile("mrc p6, 0, %0, c0, c1, 0":"=r" (val)); - return val; -} - -extern unsigned long get_iop_tick_rate(void); -#endif - -/* - * IOP13XX I/O and Mem space regions for PCI autoconfiguration - */ -#define IOP13XX_MAX_RAM_SIZE 0x80000000UL /* 2GB */ -#define IOP13XX_PCI_OFFSET IOP13XX_MAX_RAM_SIZE - -/* PCI MAP - * bus range cpu phys cpu virt note - * 0x0000.0000 + 2GB (n/a) (n/a) inbound, 1:1 mapping with Physical RAM - * 0x8000.0000 + 928M 0x1.8000.0000 (ioremap) PCIX outbound memory window - * 0x8000.0000 + 928M 0x2.8000.0000 (ioremap) PCIE outbound memory window - * - * IO MAP - * 0x00000 + 64K 0x0.fffb.0000 0xfee0.0000 PCIX outbound i/o window - * 0x10000 + 64K 0x0.fffd.0000 0xfee1.0000 PCIE outbound i/o window - */ -#define IOP13XX_PCIX_LOWER_IO_PA 0xfffb0000UL -#define IOP13XX_PCIX_LOWER_IO_BA 0x0UL /* OIOTVR */ - -#define IOP13XX_PCIX_MEM_PHYS_OFFSET 0x100000000ULL -#define IOP13XX_PCIX_MEM_WINDOW_SIZE 0x3a000000UL -#define IOP13XX_PCIX_LOWER_MEM_BA (PHYS_OFFSET + IOP13XX_PCI_OFFSET) -#define IOP13XX_PCIX_LOWER_MEM_PA (IOP13XX_PCIX_MEM_PHYS_OFFSET +\ - IOP13XX_PCIX_LOWER_MEM_BA) -#define IOP13XX_PCIX_UPPER_MEM_PA (IOP13XX_PCIX_LOWER_MEM_PA +\ - IOP13XX_PCIX_MEM_WINDOW_SIZE - 1) -#define IOP13XX_PCIX_UPPER_MEM_BA (IOP13XX_PCIX_LOWER_MEM_BA +\ - IOP13XX_PCIX_MEM_WINDOW_SIZE - 1) - -#define IOP13XX_PCIX_MEM_COOKIE 0x80000000UL -#define IOP13XX_PCIX_LOWER_MEM_RA IOP13XX_PCIX_MEM_COOKIE -#define IOP13XX_PCIX_UPPER_MEM_RA (IOP13XX_PCIX_LOWER_MEM_RA +\ - IOP13XX_PCIX_MEM_WINDOW_SIZE - 1) -#define IOP13XX_PCIX_MEM_OFFSET (IOP13XX_PCIX_MEM_COOKIE -\ - IOP13XX_PCIX_LOWER_MEM_BA) - -/* PCI-E ranges */ -#define IOP13XX_PCIE_LOWER_IO_PA 0xfffd0000UL -#define IOP13XX_PCIE_LOWER_IO_BA 0x10000UL /* OIOTVR */ - -#define IOP13XX_PCIE_MEM_PHYS_OFFSET 0x200000000ULL -#define IOP13XX_PCIE_MEM_WINDOW_SIZE 0x3a000000UL -#define IOP13XX_PCIE_LOWER_MEM_BA (PHYS_OFFSET + IOP13XX_PCI_OFFSET) -#define IOP13XX_PCIE_LOWER_MEM_PA (IOP13XX_PCIE_MEM_PHYS_OFFSET +\ - IOP13XX_PCIE_LOWER_MEM_BA) -#define IOP13XX_PCIE_UPPER_MEM_PA (IOP13XX_PCIE_LOWER_MEM_PA +\ - IOP13XX_PCIE_MEM_WINDOW_SIZE - 1) -#define IOP13XX_PCIE_UPPER_MEM_BA (IOP13XX_PCIE_LOWER_MEM_BA +\ - IOP13XX_PCIE_MEM_WINDOW_SIZE - 1) - -/* All 0xc000.0000 - 0xfdff.ffff addresses belong to PCIe */ -#define IOP13XX_PCIE_MEM_COOKIE 0xc0000000UL -#define IOP13XX_PCIE_LOWER_MEM_RA IOP13XX_PCIE_MEM_COOKIE -#define IOP13XX_PCIE_UPPER_MEM_RA (IOP13XX_PCIE_LOWER_MEM_RA +\ - IOP13XX_PCIE_MEM_WINDOW_SIZE - 1) -#define IOP13XX_PCIE_MEM_OFFSET (IOP13XX_PCIE_MEM_COOKIE -\ - IOP13XX_PCIE_LOWER_MEM_BA) - -/* PBI Ranges */ -#define IOP13XX_PBI_LOWER_MEM_PA 0xf0000000UL -#define IOP13XX_PBI_MEM_WINDOW_SIZE 0x04000000UL -#define IOP13XX_PBI_MEM_COOKIE 0xfa000000UL -#define IOP13XX_PBI_LOWER_MEM_RA IOP13XX_PBI_MEM_COOKIE -#define IOP13XX_PBI_UPPER_MEM_RA (IOP13XX_PBI_LOWER_MEM_RA +\ - IOP13XX_PBI_MEM_WINDOW_SIZE - 1) - -/* - * IOP13XX chipset registers - */ -#define IOP13XX_PMMR_PHYS_MEM_BASE 0xffd80000UL /* PMMR phys. address */ -#define IOP13XX_PMMR_VIRT_MEM_BASE (void __iomem *)(0xfee80000UL) /* PMMR phys. address */ -#define IOP13XX_PMMR_MEM_WINDOW_SIZE 0x80000 -#define IOP13XX_PMMR_UPPER_MEM_VA (IOP13XX_PMMR_VIRT_MEM_BASE +\ - IOP13XX_PMMR_MEM_WINDOW_SIZE - 1) -#define IOP13XX_PMMR_UPPER_MEM_PA (IOP13XX_PMMR_PHYS_MEM_BASE +\ - IOP13XX_PMMR_MEM_WINDOW_SIZE - 1) -#define IOP13XX_PMMR_VIRT_TO_PHYS(addr) (((addr) - IOP13XX_PMMR_VIRT_MEM_BASE)\ - + IOP13XX_PMMR_PHYS_MEM_BASE) -#define IOP13XX_PMMR_PHYS_TO_VIRT(addr) (((addr) - IOP13XX_PMMR_PHYS_MEM_BASE)\ - + IOP13XX_PMMR_VIRT_MEM_BASE) -#define IOP13XX_REG_ADDR32(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg)) -#define IOP13XX_REG_ADDR16(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg)) -#define IOP13XX_REG_ADDR8(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg)) -#define IOP13XX_REG_ADDR32_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg)) -#define IOP13XX_REG_ADDR16_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg)) -#define IOP13XX_REG_ADDR8_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg)) -#define IOP13XX_PMMR_SIZE 0x00080000 - -/*=================== Defines for Platform Devices =====================*/ -#define IOP13XX_UART0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE + 0x00002300) -#define IOP13XX_UART1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE + 0x00002340) -#define IOP13XX_UART0_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE + 0x00002300) -#define IOP13XX_UART1_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE + 0x00002340) - -#define IOP13XX_I2C0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002500) -#define IOP13XX_I2C1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002520) -#define IOP13XX_I2C2_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002540) -#define IOP13XX_I2C0_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002500) -#define IOP13XX_I2C1_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002520) -#define IOP13XX_I2C2_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002540) - -/* ATU selection flags */ -/* IOP13XX_INIT_ATU_DEFAULT = Rely on CONFIG_IOP13XX_ATU* */ -#define IOP13XX_INIT_ATU_DEFAULT (0) -#define IOP13XX_INIT_ATU_ATUX (1 << 0) -#define IOP13XX_INIT_ATU_ATUE (1 << 1) -#define IOP13XX_INIT_ATU_NONE (1 << 2) - -/* UART selection flags */ -/* IOP13XX_INIT_UART_DEFAULT = Rely on CONFIG_IOP13XX_UART* */ -#define IOP13XX_INIT_UART_DEFAULT (0) -#define IOP13XX_INIT_UART_0 (1 << 0) -#define IOP13XX_INIT_UART_1 (1 << 1) - -/* I2C selection flags */ -/* IOP13XX_INIT_I2C_DEFAULT = Rely on CONFIG_IOP13XX_I2C* */ -#define IOP13XX_INIT_I2C_DEFAULT (0) -#define IOP13XX_INIT_I2C_0 (1 << 0) -#define IOP13XX_INIT_I2C_1 (1 << 1) -#define IOP13XX_INIT_I2C_2 (1 << 2) - -/* ADMA selection flags */ -/* INIT_ADMA_DEFAULT = Rely on CONFIG_IOP13XX_ADMA* */ -#define IOP13XX_INIT_ADMA_DEFAULT (0) -#define IOP13XX_INIT_ADMA_0 (1 << 0) -#define IOP13XX_INIT_ADMA_1 (1 << 1) -#define IOP13XX_INIT_ADMA_2 (1 << 2) - -/* Platform devices */ -#define IQ81340_NUM_UART 2 -#define IQ81340_NUM_I2C 3 -#define IQ81340_NUM_PHYS_MAP_FLASH 1 -#define IQ81340_NUM_ADMA 3 -#define IQ81340_MAX_PLAT_DEVICES (IQ81340_NUM_UART + \ - IQ81340_NUM_I2C + \ - IQ81340_NUM_PHYS_MAP_FLASH + \ - IQ81340_NUM_ADMA) - -/*========================== PMMR offsets for key registers ============*/ -#define IOP13XX_ATU0_PMMR_OFFSET 0x00048000 -#define IOP13XX_ATU1_PMMR_OFFSET 0x0004c000 -#define IOP13XX_ATU2_PMMR_OFFSET 0x0004d000 -#define IOP13XX_ADMA0_PMMR_OFFSET 0x00000000 -#define IOP13XX_ADMA1_PMMR_OFFSET 0x00000200 -#define IOP13XX_ADMA2_PMMR_OFFSET 0x00000400 -#define IOP13XX_PBI_PMMR_OFFSET 0x00001580 -#define IOP13XX_MU_PMMR_OFFSET 0x00004000 -#define IOP13XX_ESSR0_PMMR_OFFSET 0x00002188 -#define IOP13XX_ESSR0 IOP13XX_REG_ADDR32(0x00002188) - -#define IOP13XX_ESSR0_IFACE_MASK 0x00004000 /* Interface PCI-X / PCI-E */ -#define IOP13XX_CONTROLLER_ONLY (1 << 14) -#define IOP13XX_INTERFACE_SEL_PCIX (1 << 15) - -#define IOP13XX_PMON_PMMR_OFFSET 0x0001A000 -#define IOP13XX_PMON_BASE (IOP13XX_PMMR_VIRT_MEM_BASE +\ - IOP13XX_PMON_PMMR_OFFSET) -#define IOP13XX_PMON_PHYSBASE (IOP13XX_PMMR_PHYS_MEM_BASE +\ - IOP13XX_PMON_PMMR_OFFSET) - -#define IOP13XX_PMON_CMD0 (IOP13XX_PMON_BASE + 0x0) -#define IOP13XX_PMON_EVR0 (IOP13XX_PMON_BASE + 0x4) -#define IOP13XX_PMON_STS0 (IOP13XX_PMON_BASE + 0x8) -#define IOP13XX_PMON_DATA0 (IOP13XX_PMON_BASE + 0xC) - -#define IOP13XX_PMON_CMD3 (IOP13XX_PMON_BASE + 0x30) -#define IOP13XX_PMON_EVR3 (IOP13XX_PMON_BASE + 0x34) -#define IOP13XX_PMON_STS3 (IOP13XX_PMON_BASE + 0x38) -#define IOP13XX_PMON_DATA3 (IOP13XX_PMON_BASE + 0x3C) - -#define IOP13XX_PMON_CMD7 (IOP13XX_PMON_BASE + 0x70) -#define IOP13XX_PMON_EVR7 (IOP13XX_PMON_BASE + 0x74) -#define IOP13XX_PMON_STS7 (IOP13XX_PMON_BASE + 0x78) -#define IOP13XX_PMON_DATA7 (IOP13XX_PMON_BASE + 0x7C) - -#define IOP13XX_PMONEN (IOP13XX_PMMR_VIRT_MEM_BASE + 0x4E040) -#define IOP13XX_PMONSTAT (IOP13XX_PMMR_VIRT_MEM_BASE + 0x4E044) - -/*================================ATU===================================*/ -#define IOP13XX_ATUX_OFFSET(ofs) IOP13XX_REG_ADDR32(\ - iop13xx_atux_pmmr_offset + (ofs)) - -#define IOP13XX_ATUX_DID IOP13XX_REG_ADDR16(\ - iop13xx_atux_pmmr_offset + 0x2) - -#define IOP13XX_ATUX_ATUCMD IOP13XX_REG_ADDR16(\ - iop13xx_atux_pmmr_offset + 0x4) -#define IOP13XX_ATUX_ATUSR IOP13XX_REG_ADDR16(\ - iop13xx_atux_pmmr_offset + 0x6) - -#define IOP13XX_ATUX_IABAR0 IOP13XX_ATUX_OFFSET(0x10) -#define IOP13XX_ATUX_IAUBAR0 IOP13XX_ATUX_OFFSET(0x14) -#define IOP13XX_ATUX_IABAR1 IOP13XX_ATUX_OFFSET(0x18) -#define IOP13XX_ATUX_IAUBAR1 IOP13XX_ATUX_OFFSET(0x1c) -#define IOP13XX_ATUX_IABAR2 IOP13XX_ATUX_OFFSET(0x20) -#define IOP13XX_ATUX_IAUBAR2 IOP13XX_ATUX_OFFSET(0x24) -#define IOP13XX_ATUX_IALR0 IOP13XX_ATUX_OFFSET(0x40) -#define IOP13XX_ATUX_IATVR0 IOP13XX_ATUX_OFFSET(0x44) -#define IOP13XX_ATUX_IAUTVR0 IOP13XX_ATUX_OFFSET(0x48) -#define IOP13XX_ATUX_IALR1 IOP13XX_ATUX_OFFSET(0x4c) -#define IOP13XX_ATUX_IATVR1 IOP13XX_ATUX_OFFSET(0x50) -#define IOP13XX_ATUX_IAUTVR1 IOP13XX_ATUX_OFFSET(0x54) -#define IOP13XX_ATUX_IALR2 IOP13XX_ATUX_OFFSET(0x58) -#define IOP13XX_ATUX_IATVR2 IOP13XX_ATUX_OFFSET(0x5c) -#define IOP13XX_ATUX_IAUTVR2 IOP13XX_ATUX_OFFSET(0x60) -#define IOP13XX_ATUX_ATUCR IOP13XX_ATUX_OFFSET(0x70) -#define IOP13XX_ATUX_PCSR IOP13XX_ATUX_OFFSET(0x74) -#define IOP13XX_ATUX_ATUISR IOP13XX_ATUX_OFFSET(0x78) -#define IOP13XX_ATUX_PCIXSR IOP13XX_ATUX_OFFSET(0xD4) -#define IOP13XX_ATUX_IABAR3 IOP13XX_ATUX_OFFSET(0x200) -#define IOP13XX_ATUX_IAUBAR3 IOP13XX_ATUX_OFFSET(0x204) -#define IOP13XX_ATUX_IALR3 IOP13XX_ATUX_OFFSET(0x208) -#define IOP13XX_ATUX_IATVR3 IOP13XX_ATUX_OFFSET(0x20c) -#define IOP13XX_ATUX_IAUTVR3 IOP13XX_ATUX_OFFSET(0x210) - -#define IOP13XX_ATUX_OIOBAR IOP13XX_ATUX_OFFSET(0x300) -#define IOP13XX_ATUX_OIOWTVR IOP13XX_ATUX_OFFSET(0x304) -#define IOP13XX_ATUX_OUMBAR0 IOP13XX_ATUX_OFFSET(0x308) -#define IOP13XX_ATUX_OUMWTVR0 IOP13XX_ATUX_OFFSET(0x30c) -#define IOP13XX_ATUX_OUMBAR1 IOP13XX_ATUX_OFFSET(0x310) -#define IOP13XX_ATUX_OUMWTVR1 IOP13XX_ATUX_OFFSET(0x314) -#define IOP13XX_ATUX_OUMBAR2 IOP13XX_ATUX_OFFSET(0x318) -#define IOP13XX_ATUX_OUMWTVR2 IOP13XX_ATUX_OFFSET(0x31c) -#define IOP13XX_ATUX_OUMBAR3 IOP13XX_ATUX_OFFSET(0x320) -#define IOP13XX_ATUX_OUMWTVR3 IOP13XX_ATUX_OFFSET(0x324) -#define IOP13XX_ATUX_OUDMABAR IOP13XX_ATUX_OFFSET(0x328) -#define IOP13XX_ATUX_OUMSIBAR IOP13XX_ATUX_OFFSET(0x32c) -#define IOP13XX_ATUX_OCCAR IOP13XX_ATUX_OFFSET(0x330) -#define IOP13XX_ATUX_OCCDR IOP13XX_ATUX_OFFSET(0x334) - -#define IOP13XX_ATUX_ATUCR_OUT_EN (1 << 1) -#define IOP13XX_ATUX_PCSR_CENTRAL_RES (1 << 25) -#define IOP13XX_ATUX_PCSR_P_RSTOUT (1 << 21) -#define IOP13XX_ATUX_PCSR_OUT_Q_BUSY (1 << 15) -#define IOP13XX_ATUX_PCSR_IN_Q_BUSY (1 << 14) -#define IOP13XX_ATUX_PCSR_FREQ_OFFSET (16) - -#define IOP13XX_ATUX_STAT_PCI_IFACE_ERR (1 << 18) -#define IOP13XX_ATUX_STAT_VPD_ADDR (1 << 17) -#define IOP13XX_ATUX_STAT_INT_PAR_ERR (1 << 16) -#define IOP13XX_ATUX_STAT_CFG_WRITE (1 << 15) -#define IOP13XX_ATUX_STAT_ERR_COR (1 << 14) -#define IOP13XX_ATUX_STAT_TX_SCEM (1 << 13) -#define IOP13XX_ATUX_STAT_REC_SCEM (1 << 12) -#define IOP13XX_ATUX_STAT_POWER_TRAN (1 << 11) -#define IOP13XX_ATUX_STAT_TX_SERR (1 << 10) -#define IOP13XX_ATUX_STAT_DET_PAR_ERR (1 << 9 ) -#define IOP13XX_ATUX_STAT_BIST (1 << 8 ) -#define IOP13XX_ATUX_STAT_INT_REC_MABORT (1 << 7 ) -#define IOP13XX_ATUX_STAT_REC_SERR (1 << 4 ) -#define IOP13XX_ATUX_STAT_EXT_REC_MABORT (1 << 3 ) -#define IOP13XX_ATUX_STAT_EXT_REC_TABORT (1 << 2 ) -#define IOP13XX_ATUX_STAT_EXT_SIG_TABORT (1 << 1 ) -#define IOP13XX_ATUX_STAT_MASTER_DATA_PAR (1 << 0 ) - -#define IOP13XX_ATUX_PCIXSR_BUS_NUM (8) -#define IOP13XX_ATUX_PCIXSR_DEV_NUM (3) -#define IOP13XX_ATUX_PCIXSR_FUNC_NUM (0) - -#define IOP13XX_ATUX_IALR_DISABLE 0x00000001 -#define IOP13XX_ATUX_OUMBAR_ENABLE 0x80000000 - -#define IOP13XX_ATUE_OFFSET(ofs) IOP13XX_REG_ADDR32(\ - iop13xx_atue_pmmr_offset + (ofs)) - -#define IOP13XX_ATUE_DID IOP13XX_REG_ADDR16(\ - iop13xx_atue_pmmr_offset + 0x2) -#define IOP13XX_ATUE_ATUCMD IOP13XX_REG_ADDR16(\ - iop13xx_atue_pmmr_offset + 0x4) -#define IOP13XX_ATUE_ATUSR IOP13XX_REG_ADDR16(\ - iop13xx_atue_pmmr_offset + 0x6) - -#define IOP13XX_ATUE_IABAR0 IOP13XX_ATUE_OFFSET(0x10) -#define IOP13XX_ATUE_IAUBAR0 IOP13XX_ATUE_OFFSET(0x14) -#define IOP13XX_ATUE_IABAR1 IOP13XX_ATUE_OFFSET(0x18) -#define IOP13XX_ATUE_IAUBAR1 IOP13XX_ATUE_OFFSET(0x1c) -#define IOP13XX_ATUE_IABAR2 IOP13XX_ATUE_OFFSET(0x20) -#define IOP13XX_ATUE_IAUBAR2 IOP13XX_ATUE_OFFSET(0x24) -#define IOP13XX_ATUE_IALR0 IOP13XX_ATUE_OFFSET(0x40) -#define IOP13XX_ATUE_IATVR0 IOP13XX_ATUE_OFFSET(0x44) -#define IOP13XX_ATUE_IAUTVR0 IOP13XX_ATUE_OFFSET(0x48) -#define IOP13XX_ATUE_IALR1 IOP13XX_ATUE_OFFSET(0x4c) -#define IOP13XX_ATUE_IATVR1 IOP13XX_ATUE_OFFSET(0x50) -#define IOP13XX_ATUE_IAUTVR1 IOP13XX_ATUE_OFFSET(0x54) -#define IOP13XX_ATUE_IALR2 IOP13XX_ATUE_OFFSET(0x58) -#define IOP13XX_ATUE_IATVR2 IOP13XX_ATUE_OFFSET(0x5c) -#define IOP13XX_ATUE_IAUTVR2 IOP13XX_ATUE_OFFSET(0x60) -#define IOP13XX_ATUE_PE_LSTS IOP13XX_REG_ADDR16(\ - iop13xx_atue_pmmr_offset + 0xe2) -#define IOP13XX_ATUE_OIOWTVR IOP13XX_ATUE_OFFSET(0x304) -#define IOP13XX_ATUE_OUMBAR0 IOP13XX_ATUE_OFFSET(0x308) -#define IOP13XX_ATUE_OUMWTVR0 IOP13XX_ATUE_OFFSET(0x30c) -#define IOP13XX_ATUE_OUMBAR1 IOP13XX_ATUE_OFFSET(0x310) -#define IOP13XX_ATUE_OUMWTVR1 IOP13XX_ATUE_OFFSET(0x314) -#define IOP13XX_ATUE_OUMBAR2 IOP13XX_ATUE_OFFSET(0x318) -#define IOP13XX_ATUE_OUMWTVR2 IOP13XX_ATUE_OFFSET(0x31c) -#define IOP13XX_ATUE_OUMBAR3 IOP13XX_ATUE_OFFSET(0x320) -#define IOP13XX_ATUE_OUMWTVR3 IOP13XX_ATUE_OFFSET(0x324) - -#define IOP13XX_ATUE_ATUCR IOP13XX_ATUE_OFFSET(0x70) -#define IOP13XX_ATUE_PCSR IOP13XX_ATUE_OFFSET(0x74) -#define IOP13XX_ATUE_ATUISR IOP13XX_ATUE_OFFSET(0x78) -#define IOP13XX_ATUE_OIOBAR IOP13XX_ATUE_OFFSET(0x300) -#define IOP13XX_ATUE_OCCAR IOP13XX_ATUE_OFFSET(0x32c) -#define IOP13XX_ATUE_OCCDR IOP13XX_ATUE_OFFSET(0x330) - -#define IOP13XX_ATUE_PIE_STS IOP13XX_ATUE_OFFSET(0x384) -#define IOP13XX_ATUE_PIE_MSK IOP13XX_ATUE_OFFSET(0x388) - -#define IOP13XX_ATUE_ATUCR_IVM (1 << 6) -#define IOP13XX_ATUE_ATUCR_OUT_EN (1 << 1) -#define IOP13XX_ATUE_OCCAR_BUS_NUM (24) -#define IOP13XX_ATUE_OCCAR_DEV_NUM (19) -#define IOP13XX_ATUE_OCCAR_FUNC_NUM (16) -#define IOP13XX_ATUE_OCCAR_EXT_REG (8) -#define IOP13XX_ATUE_OCCAR_REG (2) - -#define IOP13XX_ATUE_PCSR_BUS_NUM (24) -#define IOP13XX_ATUE_PCSR_DEV_NUM (19) -#define IOP13XX_ATUE_PCSR_FUNC_NUM (16) -#define IOP13XX_ATUE_PCSR_OUT_Q_BUSY (1 << 15) -#define IOP13XX_ATUE_PCSR_IN_Q_BUSY (1 << 14) -#define IOP13XX_ATUE_PCSR_END_POINT (1 << 13) -#define IOP13XX_ATUE_PCSR_LLRB_BUSY (1 << 12) - -#define IOP13XX_ATUE_PCSR_BUS_NUM_MASK (0xff) -#define IOP13XX_ATUE_PCSR_DEV_NUM_MASK (0x1f) -#define IOP13XX_ATUE_PCSR_FUNC_NUM_MASK (0x7) - -#define IOP13XX_ATUE_PCSR_CORE_RESET (8) -#define IOP13XX_ATUE_PCSR_FUNC_NUM (16) - -#define IOP13XX_ATUE_LSTS_TRAINING (1 << 11) -#define IOP13XX_ATUE_STAT_SLOT_PWR_MSG (1 << 28) -#define IOP13XX_ATUE_STAT_PME (1 << 27) -#define IOP13XX_ATUE_STAT_HOT_PLUG_MSG (1 << 26) -#define IOP13XX_ATUE_STAT_IVM (1 << 25) -#define IOP13XX_ATUE_STAT_BIST (1 << 24) -#define IOP13XX_ATUE_STAT_CFG_WRITE (1 << 18) -#define IOP13XX_ATUE_STAT_VPD_ADDR (1 << 17) -#define IOP13XX_ATUE_STAT_POWER_TRAN (1 << 16) -#define IOP13XX_ATUE_STAT_HALT_ON_ERROR (1 << 13) -#define IOP13XX_ATUE_STAT_ROOT_SYS_ERR (1 << 12) -#define IOP13XX_ATUE_STAT_ROOT_ERR_MSG (1 << 11) -#define IOP13XX_ATUE_STAT_PCI_IFACE_ERR (1 << 10) -#define IOP13XX_ATUE_STAT_ERR_COR (1 << 9 ) -#define IOP13XX_ATUE_STAT_ERR_UNCOR (1 << 8 ) -#define IOP13XX_ATUE_STAT_CRS (1 << 7 ) -#define IOP13XX_ATUE_STAT_LNK_DWN (1 << 6 ) -#define IOP13XX_ATUE_STAT_INT_REC_MABORT (1 << 5 ) -#define IOP13XX_ATUE_STAT_DET_PAR_ERR (1 << 4 ) -#define IOP13XX_ATUE_STAT_EXT_REC_MABORT (1 << 3 ) -#define IOP13XX_ATUE_STAT_SIG_TABORT (1 << 2 ) -#define IOP13XX_ATUE_STAT_EXT_REC_TABORT (1 << 1 ) -#define IOP13XX_ATUE_STAT_MASTER_DATA_PAR (1 << 0 ) - -#define IOP13XX_ATUE_ESTAT_REC_UNSUPPORTED_COMP_REQ (1 << 31) -#define IOP13XX_ATUE_ESTAT_REC_COMPLETER_ABORT (1 << 30) -#define IOP13XX_ATUE_ESTAT_TX_POISONED_TLP (1 << 29) -#define IOP13XX_ATUE_ESTAT_TX_PAR_ERR (1 << 28) -#define IOP13XX_ATUE_ESTAT_REC_UNSUPPORTED_REQ (1 << 20) -#define IOP13XX_ATUE_ESTAT_REC_ECRC_ERR (1 << 19) -#define IOP13XX_ATUE_ESTAT_REC_MALFORMED_TLP (1 << 18) -#define IOP13XX_ATUE_ESTAT_TX_RECEIVER_OVERFLOW (1 << 17) -#define IOP13XX_ATUE_ESTAT_REC_UNEXPECTED_COMP (1 << 16) -#define IOP13XX_ATUE_ESTAT_INT_COMP_ABORT (1 << 15) -#define IOP13XX_ATUE_ESTAT_COMP_TIMEOUT (1 << 14) -#define IOP13XX_ATUE_ESTAT_FLOW_CONTROL_ERR (1 << 13) -#define IOP13XX_ATUE_ESTAT_REC_POISONED_TLP (1 << 12) -#define IOP13XX_ATUE_ESTAT_DATA_LNK_ERR (1 << 4 ) -#define IOP13XX_ATUE_ESTAT_TRAINING_ERR (1 << 0 ) - -#define IOP13XX_ATUE_IALR_DISABLE (0x00000001) -#define IOP13XX_ATUE_OUMBAR_ENABLE (0x80000000) -#define IOP13XX_ATU_OUMBAR_FUNC_NUM (28) -#define IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK (0x7) -/*=======================================================================*/ - -/*============================MESSAGING UNIT=============================*/ -#define IOP13XX_MU_OFFSET(ofs) IOP13XX_REG_ADDR32(IOP13XX_MU_PMMR_OFFSET +\ - (ofs)) - -#define IOP13XX_MU_IMR0 IOP13XX_MU_OFFSET(0x10) -#define IOP13XX_MU_IMR1 IOP13XX_MU_OFFSET(0x14) -#define IOP13XX_MU_OMR0 IOP13XX_MU_OFFSET(0x18) -#define IOP13XX_MU_OMR1 IOP13XX_MU_OFFSET(0x1C) -#define IOP13XX_MU_IDR IOP13XX_MU_OFFSET(0x20) -#define IOP13XX_MU_IISR IOP13XX_MU_OFFSET(0x24) -#define IOP13XX_MU_IIMR IOP13XX_MU_OFFSET(0x28) -#define IOP13XX_MU_ODR IOP13XX_MU_OFFSET(0x2C) -#define IOP13XX_MU_OISR IOP13XX_MU_OFFSET(0x30) -#define IOP13XX_MU_OIMR IOP13XX_MU_OFFSET(0x34) -#define IOP13XX_MU_IRCSR IOP13XX_MU_OFFSET(0x38) -#define IOP13XX_MU_ORCSR IOP13XX_MU_OFFSET(0x3C) -#define IOP13XX_MU_MIMR IOP13XX_MU_OFFSET(0x48) -#define IOP13XX_MU_MUCR IOP13XX_MU_OFFSET(0x50) -#define IOP13XX_MU_QBAR IOP13XX_MU_OFFSET(0x54) -#define IOP13XX_MU_MUBAR IOP13XX_MU_OFFSET(0x84) - -#define IOP13XX_MU_WINDOW_SIZE (8 * 1024) -#define IOP13XX_MU_BASE_PHYS (0xff000000) -#define IOP13XX_MU_BASE_PCI (0xff000000) -#define IOP13XX_MU_MIMR_PCI (IOP13XX_MU_BASE_PCI + 0x48) -#define IOP13XX_MU_MIMR_CORE_SELECT (15) -/*=======================================================================*/ - -/*==============================ADMA UNITS===============================*/ -#define IOP13XX_ADMA_PHYS_BASE(chan) IOP13XX_REG_ADDR32_PHYS((chan << 9)) -#define IOP13XX_ADMA_UPPER_PA(chan) (IOP13XX_ADMA_PHYS_BASE(chan) + 0xc0) - -/*==============================XSI BRIDGE===============================*/ -#define IOP13XX_XBG_BECSR IOP13XX_REG_ADDR32(0x178c) -#define IOP13XX_XBG_BERAR IOP13XX_REG_ADDR32(0x1790) -#define IOP13XX_XBG_BERUAR IOP13XX_REG_ADDR32(0x1794) -#define is_atue_occdr_error(x) ((__raw_readl(IOP13XX_XBG_BERAR) == \ - IOP13XX_PMMR_VIRT_TO_PHYS(\ - IOP13XX_ATUE_OCCDR))\ - && (__raw_readl(IOP13XX_XBG_BECSR) & 1)) -#define is_atux_occdr_error(x) ((__raw_readl(IOP13XX_XBG_BERAR) == \ - IOP13XX_PMMR_VIRT_TO_PHYS(\ - IOP13XX_ATUX_OCCDR))\ - && (__raw_readl(IOP13XX_XBG_BECSR) & 1)) -/*=======================================================================*/ - -#define IOP13XX_PBI_OFFSET(ofs) IOP13XX_REG_ADDR32(IOP13XX_PBI_PMMR_OFFSET +\ - (ofs)) - -#define IOP13XX_PBI_CR IOP13XX_PBI_OFFSET(0x0) -#define IOP13XX_PBI_SR IOP13XX_PBI_OFFSET(0x4) -#define IOP13XX_PBI_BAR0 IOP13XX_PBI_OFFSET(0x8) -#define IOP13XX_PBI_LR0 IOP13XX_PBI_OFFSET(0xc) -#define IOP13XX_PBI_BAR1 IOP13XX_PBI_OFFSET(0x10) -#define IOP13XX_PBI_LR1 IOP13XX_PBI_OFFSET(0x14) - -#define IOP13XX_PROCESSOR_FREQ IOP13XX_REG_ADDR32(0x2180) - -/* Watchdog timer definitions */ -#define IOP_WDTCR_EN_ARM 0x1e1e1e1e -#define IOP_WDTCR_EN 0xe1e1e1e1 -#define IOP_WDTCR_DIS_ARM 0x1f1f1f1f -#define IOP_WDTCR_DIS 0xf1f1f1f1 -#define IOP_RCSR_WDT (1 << 5) /* reset caused by watchdog timer */ -#define IOP13XX_WDTSR_WRITE_EN (1 << 31) /* used to speed up reset requests */ -#define IOP13XX_WDTCR_IB_RESET (1 << 0) - -#endif /* _IOP13XX_HW_H_ */ diff --git a/arch/arm/mach-iop13xx/include/mach/iq81340.h b/arch/arm/mach-iop13xx/include/mach/iq81340.h deleted file mode 100644 index d7ad27a95558..000000000000 --- a/arch/arm/mach-iop13xx/include/mach/iq81340.h +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _IQ81340_H_ -#define _IQ81340_H_ - -#define IQ81340_PCE_BAR0 IOP13XX_PBI_LOWER_MEM_RA -#define IQ81340_PCE_BAR1 (IQ81340_PCE_BAR0 + 0x02000000) - -#define IQ81340_FLASHBASE IQ81340_PCE_BAR0 /* Flash */ - -#define IQ81340_PCE_BAR1_OFFSET(a) (IQ81340_PCE_BAR1 + (a)) - -#define IQ81340_PRD_CODE IQ81340_PCE_BAR1_OFFSET(0) -#define IQ81340_BRD_STEP IQ81340_PCE_BAR1_OFFSET(0x10000) -#define IQ81340_CPLD_REV IQ81340_PCE_BAR1_OFFSET(0x20000) -#define IQ81340_LED IQ81340_PCE_BAR1_OFFSET(0x30000) -#define IQ81340_LHEX IQ81340_PCE_BAR1_OFFSET(0x40000) -#define IQ81340_RHEX IQ81340_PCE_BAR1_OFFSET(0x50000) -#define IQ81340_BUZZER IQ81340_PCE_BAR1_OFFSET(0x60000) -#define IQ81340_32K_NVRAM IQ81340_PCE_BAR1_OFFSET(0x70000) -#define IQ81340_256K_NVRAM IQ81340_PCE_BAR1_OFFSET(0x80000) -#define IQ81340_ROTARY_SW IQ81340_PCE_BAR1_OFFSET(0xd0000) -#define IQ81340_BATT_STAT IQ81340_PCE_BAR1_OFFSET(0xf0000) -#define IQ81340_CMP_FLSH IQ81340_PCE_BAR1_OFFSET(0x1000000) /* 16MB */ - -#define PBI_CF_IDE_BASE (IQ81340_CMP_FLSH) -#define PBI_CF_BAR_ADDR (IOP13XX_PBI_BAR1) - - -#endif /* _IQ81340_H_ */ diff --git a/arch/arm/mach-iop13xx/include/mach/irqs.h b/arch/arm/mach-iop13xx/include/mach/irqs.h deleted file mode 100644 index cd6b6375c050..000000000000 --- a/arch/arm/mach-iop13xx/include/mach/irqs.h +++ /dev/null @@ -1,195 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _IOP13XX_IRQS_H_ -#define _IOP13XX_IRQS_H_ - -#ifndef __ASSEMBLER__ -#include <linux/types.h> - -/* INTPND0 CP6 R0 Page 3 - */ -static inline u32 read_intpnd_0(void) -{ - u32 val; - asm volatile("mrc p6, 0, %0, c0, c3, 0":"=r" (val)); - return val; -} - -/* INTPND1 CP6 R1 Page 3 - */ -static inline u32 read_intpnd_1(void) -{ - u32 val; - asm volatile("mrc p6, 0, %0, c1, c3, 0":"=r" (val)); - return val; -} - -/* INTPND2 CP6 R2 Page 3 - */ -static inline u32 read_intpnd_2(void) -{ - u32 val; - asm volatile("mrc p6, 0, %0, c2, c3, 0":"=r" (val)); - return val; -} - -/* INTPND3 CP6 R3 Page 3 - */ -static inline u32 read_intpnd_3(void) -{ - u32 val; - asm volatile("mrc p6, 0, %0, c3, c3, 0":"=r" (val)); - return val; -} -#endif - -#define INTBASE 0 -#define INTSIZE_4 1 - -/* - * iop34x chipset interrupts - */ -#define IOP13XX_IRQ(x) (IOP13XX_IRQ_OFS + (x)) - -/* - * On IRQ or FIQ register - */ -#define IRQ_IOP13XX_ADMA0_EOT (0) -#define IRQ_IOP13XX_ADMA0_EOC (1) -#define IRQ_IOP13XX_ADMA1_EOT (2) -#define IRQ_IOP13XX_ADMA1_EOC (3) -#define IRQ_IOP13XX_ADMA2_EOT (4) -#define IRQ_IOP13XX_ADMA2_EOC (5) -#define IRQ_IOP134_WATCHDOG (6) -#define IRQ_IOP13XX_RSVD_7 (7) -#define IRQ_IOP13XX_TIMER0 (8) -#define IRQ_IOP13XX_TIMER1 (9) -#define IRQ_IOP13XX_I2C_0 (10) -#define IRQ_IOP13XX_I2C_1 (11) -#define IRQ_IOP13XX_MSG (12) -#define IRQ_IOP13XX_MSGIBQ (13) -#define IRQ_IOP13XX_ATU_IM (14) -#define IRQ_IOP13XX_ATU_BIST (15) -#define IRQ_IOP13XX_PPMU (16) -#define IRQ_IOP13XX_COREPMU (17) -#define IRQ_IOP13XX_CORECACHE (18) -#define IRQ_IOP13XX_RSVD_19 (19) -#define IRQ_IOP13XX_RSVD_20 (20) -#define IRQ_IOP13XX_RSVD_21 (21) -#define IRQ_IOP13XX_RSVD_22 (22) -#define IRQ_IOP13XX_RSVD_23 (23) -#define IRQ_IOP13XX_XINT0 (24) -#define IRQ_IOP13XX_XINT1 (25) -#define IRQ_IOP13XX_XINT2 (26) -#define IRQ_IOP13XX_XINT3 (27) -#define IRQ_IOP13XX_XINT4 (28) -#define IRQ_IOP13XX_XINT5 (29) -#define IRQ_IOP13XX_XINT6 (30) -#define IRQ_IOP13XX_XINT7 (31) - /* IINTSRC1 bit */ -#define IRQ_IOP13XX_XINT8 (32) /* 0 */ -#define IRQ_IOP13XX_XINT9 (33) /* 1 */ -#define IRQ_IOP13XX_XINT10 (34) /* 2 */ -#define IRQ_IOP13XX_XINT11 (35) /* 3 */ -#define IRQ_IOP13XX_XINT12 (36) /* 4 */ -#define IRQ_IOP13XX_XINT13 (37) /* 5 */ -#define IRQ_IOP13XX_XINT14 (38) /* 6 */ -#define IRQ_IOP13XX_XINT15 (39) /* 7 */ -#define IRQ_IOP13XX_RSVD_40 (40) /* 8 */ -#define IRQ_IOP13XX_RSVD_41 (41) /* 9 */ -#define IRQ_IOP13XX_RSVD_42 (42) /* 10 */ -#define IRQ_IOP13XX_RSVD_43 (43) /* 11 */ -#define IRQ_IOP13XX_RSVD_44 (44) /* 12 */ -#define IRQ_IOP13XX_RSVD_45 (45) /* 13 */ -#define IRQ_IOP13XX_RSVD_46 (46) /* 14 */ -#define IRQ_IOP13XX_RSVD_47 (47) /* 15 */ -#define IRQ_IOP13XX_RSVD_48 (48) /* 16 */ -#define IRQ_IOP13XX_RSVD_49 (49) /* 17 */ -#define IRQ_IOP13XX_RSVD_50 (50) /* 18 */ -#define IRQ_IOP13XX_UART0 (51) /* 19 */ -#define IRQ_IOP13XX_UART1 (52) /* 20 */ -#define IRQ_IOP13XX_PBIE (53) /* 21 */ -#define IRQ_IOP13XX_ATU_CRW (54) /* 22 */ -#define IRQ_IOP13XX_ATU_ERR (55) /* 23 */ -#define IRQ_IOP13XX_MCU_ERR (56) /* 24 */ -#define IRQ_IOP13XX_ADMA0_ERR (57) /* 25 */ -#define IRQ_IOP13XX_ADMA1_ERR (58) /* 26 */ -#define IRQ_IOP13XX_ADMA2_ERR (59) /* 27 */ -#define IRQ_IOP13XX_RSVD_60 (60) /* 28 */ -#define IRQ_IOP13XX_RSVD_61 (61) /* 29 */ -#define IRQ_IOP13XX_MSG_ERR (62) /* 30 */ -#define IRQ_IOP13XX_RSVD_63 (63) /* 31 */ - /* IINTSRC2 bit */ -#define IRQ_IOP13XX_INTERPROC (64) /* 0 */ -#define IRQ_IOP13XX_RSVD_65 (65) /* 1 */ -#define IRQ_IOP13XX_RSVD_66 (66) /* 2 */ -#define IRQ_IOP13XX_RSVD_67 (67) /* 3 */ -#define IRQ_IOP13XX_RSVD_68 (68) /* 4 */ -#define IRQ_IOP13XX_RSVD_69 (69) /* 5 */ -#define IRQ_IOP13XX_RSVD_70 (70) /* 6 */ -#define IRQ_IOP13XX_RSVD_71 (71) /* 7 */ -#define IRQ_IOP13XX_RSVD_72 (72) /* 8 */ -#define IRQ_IOP13XX_RSVD_73 (73) /* 9 */ -#define IRQ_IOP13XX_RSVD_74 (74) /* 10 */ -#define IRQ_IOP13XX_RSVD_75 (75) /* 11 */ -#define IRQ_IOP13XX_RSVD_76 (76) /* 12 */ -#define IRQ_IOP13XX_RSVD_77 (77) /* 13 */ -#define IRQ_IOP13XX_RSVD_78 (78) /* 14 */ -#define IRQ_IOP13XX_RSVD_79 (79) /* 15 */ -#define IRQ_IOP13XX_RSVD_80 (80) /* 16 */ -#define IRQ_IOP13XX_RSVD_81 (81) /* 17 */ -#define IRQ_IOP13XX_RSVD_82 (82) /* 18 */ -#define IRQ_IOP13XX_RSVD_83 (83) /* 19 */ -#define IRQ_IOP13XX_RSVD_84 (84) /* 20 */ -#define IRQ_IOP13XX_RSVD_85 (85) /* 21 */ -#define IRQ_IOP13XX_RSVD_86 (86) /* 22 */ -#define IRQ_IOP13XX_RSVD_87 (87) /* 23 */ -#define IRQ_IOP13XX_RSVD_88 (88) /* 24 */ -#define IRQ_IOP13XX_RSVD_89 (89) /* 25 */ -#define IRQ_IOP13XX_RSVD_90 (90) /* 26 */ -#define IRQ_IOP13XX_RSVD_91 (91) /* 27 */ -#define IRQ_IOP13XX_RSVD_92 (92) /* 28 */ -#define IRQ_IOP13XX_RSVD_93 (93) /* 29 */ -#define IRQ_IOP13XX_SIB_ERR (94) /* 30 */ -#define IRQ_IOP13XX_SRAM_ERR (95) /* 31 */ - /* IINTSRC3 bit */ -#define IRQ_IOP13XX_I2C_2 (96) /* 0 */ -#define IRQ_IOP13XX_ATUE_BIST (97) /* 1 */ -#define IRQ_IOP13XX_ATUE_CRW (98) /* 2 */ -#define IRQ_IOP13XX_ATUE_ERR (99) /* 3 */ -#define IRQ_IOP13XX_IMU (100) /* 4 */ -#define IRQ_IOP13XX_RSVD_101 (101) /* 5 */ -#define IRQ_IOP13XX_RSVD_102 (102) /* 6 */ -#define IRQ_IOP13XX_TPMI0_OUT (103) /* 7 */ -#define IRQ_IOP13XX_TPMI1_OUT (104) /* 8 */ -#define IRQ_IOP13XX_TPMI2_OUT (105) /* 9 */ -#define IRQ_IOP13XX_TPMI3_OUT (106) /* 10 */ -#define IRQ_IOP13XX_ATUE_IMA (107) /* 11 */ -#define IRQ_IOP13XX_ATUE_IMB (108) /* 12 */ -#define IRQ_IOP13XX_ATUE_IMC (109) /* 13 */ -#define IRQ_IOP13XX_ATUE_IMD (110) /* 14 */ -#define IRQ_IOP13XX_MU_MSI_TB (111) /* 15 */ -#define IRQ_IOP13XX_RSVD_112 (112) /* 16 */ -#define IRQ_IOP13XX_INBD_MSI (113) /* 17 */ -#define IRQ_IOP13XX_RSVD_114 (114) /* 18 */ -#define IRQ_IOP13XX_RSVD_115 (115) /* 19 */ -#define IRQ_IOP13XX_RSVD_116 (116) /* 20 */ -#define IRQ_IOP13XX_RSVD_117 (117) /* 21 */ -#define IRQ_IOP13XX_RSVD_118 (118) /* 22 */ -#define IRQ_IOP13XX_RSVD_119 (119) /* 23 */ -#define IRQ_IOP13XX_RSVD_120 (120) /* 24 */ -#define IRQ_IOP13XX_RSVD_121 (121) /* 25 */ -#define IRQ_IOP13XX_RSVD_122 (122) /* 26 */ -#define IRQ_IOP13XX_RSVD_123 (123) /* 27 */ -#define IRQ_IOP13XX_RSVD_124 (124) /* 28 */ -#define IRQ_IOP13XX_RSVD_125 (125) /* 29 */ -#define IRQ_IOP13XX_RSVD_126 (126) /* 30 */ -#define IRQ_IOP13XX_HPI (127) /* 31 */ - -#ifdef CONFIG_PCI_MSI -#define IRQ_IOP13XX_MSI_0 (IRQ_IOP13XX_HPI + 1) -#define NR_IOP13XX_IRQS (IRQ_IOP13XX_MSI_0 + 128) -#else -#define NR_IOP13XX_IRQS (IRQ_IOP13XX_HPI + 1) -#endif - -#endif /* _IOP13XX_IRQ_H_ */ diff --git a/arch/arm/mach-iop13xx/include/mach/memory.h b/arch/arm/mach-iop13xx/include/mach/memory.h deleted file mode 100644 index 32da0e09c6a3..000000000000 --- a/arch/arm/mach-iop13xx/include/mach/memory.h +++ /dev/null @@ -1,68 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ASM_ARCH_MEMORY_H -#define __ASM_ARCH_MEMORY_H - -#include <mach/hardware.h> - -#ifndef __ASSEMBLY__ - -#if defined(CONFIG_ARCH_IOP13XX) -#define IOP13XX_PMMR_V_START (IOP13XX_PMMR_VIRT_MEM_BASE) -#define IOP13XX_PMMR_V_END (IOP13XX_PMMR_VIRT_MEM_BASE + IOP13XX_PMMR_SIZE) -#define IOP13XX_PMMR_P_START (IOP13XX_PMMR_PHYS_MEM_BASE) -#define IOP13XX_PMMR_P_END (IOP13XX_PMMR_PHYS_MEM_BASE + IOP13XX_PMMR_SIZE) - -static inline dma_addr_t __virt_to_lbus(void __iomem *x) -{ - return x + IOP13XX_PMMR_PHYS_MEM_BASE - IOP13XX_PMMR_VIRT_MEM_BASE; -} - -static inline void __iomem *__lbus_to_virt(dma_addr_t x) -{ - return x + IOP13XX_PMMR_VIRT_MEM_BASE - IOP13XX_PMMR_PHYS_MEM_BASE; -} - -#define __is_lbus_dma(a) \ - ((a) >= IOP13XX_PMMR_P_START && (a) < IOP13XX_PMMR_P_END) - -#define __is_lbus_virt(a) \ - ((a) >= IOP13XX_PMMR_V_START && (a) < IOP13XX_PMMR_V_END) - -/* Device is an lbus device if it is on the platform bus of the IOP13XX */ -#define is_lbus_device(dev) \ - (dev && strncmp(dev->bus->name, "platform", 8) == 0) - -#define __arch_dma_to_virt(dev, addr) \ - ({ \ - void * __virt; \ - dma_addr_t __dma = addr; \ - if (is_lbus_device(dev) && __is_lbus_dma(__dma)) \ - __virt = __lbus_to_virt(__dma); \ - else \ - __virt = (void *)__phys_to_virt(__dma); \ - __virt; \ - }) - -#define __arch_virt_to_dma(dev, addr) \ - ({ \ - void * __virt = addr; \ - dma_addr_t __dma; \ - if (is_lbus_device(dev) && __is_lbus_virt(__virt)) \ - __dma = __virt_to_lbus(__virt); \ - else \ - __dma = __virt_to_phys((unsigned long)__virt); \ - __dma; \ - }) - -#define __arch_pfn_to_dma(dev, pfn) \ - ({ \ - /* __is_lbus_virt() can never be true for RAM pages */ \ - (dma_addr_t)__pfn_to_phys(pfn); \ - }) - -#define __arch_dma_to_pfn(dev, addr) __phys_to_pfn(addr) - -#endif /* CONFIG_ARCH_IOP13XX */ -#endif /* !ASSEMBLY */ - -#endif diff --git a/arch/arm/mach-iop13xx/include/mach/time.h b/arch/arm/mach-iop13xx/include/mach/time.h deleted file mode 100644 index 2c2d7532d5c3..000000000000 --- a/arch/arm/mach-iop13xx/include/mach/time.h +++ /dev/null @@ -1,127 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _IOP13XX_TIME_H_ -#define _IOP13XX_TIME_H_ - -#include <mach/irqs.h> - -#define IRQ_IOP_TIMER0 IRQ_IOP13XX_TIMER0 - -#define IOP_TMR_EN 0x02 -#define IOP_TMR_RELOAD 0x04 -#define IOP_TMR_PRIVILEGED 0x08 -#define IOP_TMR_RATIO_1_1 0x00 - -#define IOP13XX_XSI_FREQ_RATIO_MASK (3 << 19) -#define IOP13XX_XSI_FREQ_RATIO_2 (0 << 19) -#define IOP13XX_XSI_FREQ_RATIO_3 (1 << 19) -#define IOP13XX_XSI_FREQ_RATIO_4 (2 << 19) -#define IOP13XX_CORE_FREQ_MASK (7 << 16) -#define IOP13XX_CORE_FREQ_600 (0 << 16) -#define IOP13XX_CORE_FREQ_667 (1 << 16) -#define IOP13XX_CORE_FREQ_800 (2 << 16) -#define IOP13XX_CORE_FREQ_933 (3 << 16) -#define IOP13XX_CORE_FREQ_1000 (4 << 16) -#define IOP13XX_CORE_FREQ_1200 (5 << 16) - -void iop_init_time(unsigned long tickrate); - -static inline unsigned long iop13xx_core_freq(void) -{ - unsigned long freq = __raw_readl(IOP13XX_PROCESSOR_FREQ); - freq &= IOP13XX_CORE_FREQ_MASK; - switch (freq) { - case IOP13XX_CORE_FREQ_600: - return 600000000; - case IOP13XX_CORE_FREQ_667: - return 667000000; - case IOP13XX_CORE_FREQ_800: - return 800000000; - case IOP13XX_CORE_FREQ_933: - return 933000000; - case IOP13XX_CORE_FREQ_1000: - return 1000000000; - case IOP13XX_CORE_FREQ_1200: - return 1200000000; - default: - printk("%s: warning unknown frequency, defaulting to 800MHz\n", - __func__); - } - - return 800000000; -} - -static inline unsigned long iop13xx_xsi_bus_ratio(void) -{ - unsigned long ratio = __raw_readl(IOP13XX_PROCESSOR_FREQ); - ratio &= IOP13XX_XSI_FREQ_RATIO_MASK; - switch (ratio) { - case IOP13XX_XSI_FREQ_RATIO_2: - return 2; - case IOP13XX_XSI_FREQ_RATIO_3: - return 3; - case IOP13XX_XSI_FREQ_RATIO_4: - return 4; - default: - printk("%s: warning unknown ratio, defaulting to 2\n", - __func__); - } - - return 2; -} - -static inline u32 read_tmr0(void) -{ - u32 val; - asm volatile("mrc p6, 0, %0, c0, c9, 0" : "=r" (val)); - return val; -} - -static inline void write_tmr0(u32 val) -{ - asm volatile("mcr p6, 0, %0, c0, c9, 0" : : "r" (val)); -} - -static inline void write_tmr1(u32 val) -{ - asm volatile("mcr p6, 0, %0, c1, c9, 0" : : "r" (val)); -} - -static inline u32 read_tcr0(void) -{ - u32 val; - asm volatile("mrc p6, 0, %0, c2, c9, 0" : "=r" (val)); - return val; -} - -static inline void write_tcr0(u32 val) -{ - asm volatile("mcr p6, 0, %0, c2, c9, 0" : : "r" (val)); -} - -static inline u32 read_tcr1(void) -{ - u32 val; - asm volatile("mrc p6, 0, %0, c3, c9, 0" : "=r" (val)); - return val; -} - -static inline void write_tcr1(u32 val) -{ - asm volatile("mcr p6, 0, %0, c3, c9, 0" : : "r" (val)); -} - -static inline void write_trr0(u32 val) -{ - asm volatile("mcr p6, 0, %0, c4, c9, 0" : : "r" (val)); -} - -static inline void write_trr1(u32 val) -{ - asm volatile("mcr p6, 0, %0, c5, c9, 0" : : "r" (val)); -} - -static inline void write_tisr(u32 val) -{ - asm volatile("mcr p6, 0, %0, c6, c9, 0" : : "r" (val)); -} -#endif diff --git a/arch/arm/mach-iop13xx/include/mach/uncompress.h b/arch/arm/mach-iop13xx/include/mach/uncompress.h deleted file mode 100644 index c62903041d11..000000000000 --- a/arch/arm/mach-iop13xx/include/mach/uncompress.h +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#include <asm/types.h> -#include <linux/serial_reg.h> -#include <mach/hardware.h> - -#define UART_BASE ((volatile u32 *)IOP13XX_UART1_PHYS) -#define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE) - -static inline void putc(char c) -{ - while ((UART_BASE[UART_LSR] & TX_DONE) != TX_DONE) - barrier(); - UART_BASE[UART_TX] = c; -} - -static inline void flush(void) -{ -} - -/* - * nothing to do - */ -#define arch_decomp_setup() diff --git a/arch/arm/mach-iop13xx/io.c b/arch/arm/mach-iop13xx/io.c deleted file mode 100644 index 253d446b1f3f..000000000000 --- a/arch/arm/mach-iop13xx/io.c +++ /dev/null @@ -1,77 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * iop13xx custom ioremap implementation - * Copyright (c) 2005-2006, Intel Corporation. - */ -#include <linux/kernel.h> -#include <linux/module.h> -#include <linux/io.h> -#include <mach/hardware.h> - -#include "pci.h" - -static void __iomem *__iop13xx_ioremap_caller(phys_addr_t cookie, - size_t size, unsigned int mtype, void *caller) -{ - void __iomem * retval; - - switch (cookie) { - case IOP13XX_PCIX_LOWER_MEM_RA ... IOP13XX_PCIX_UPPER_MEM_RA: - if (unlikely(!iop13xx_atux_mem_base)) - retval = NULL; - else - retval = (iop13xx_atux_mem_base + - (cookie - IOP13XX_PCIX_LOWER_MEM_RA)); - break; - case IOP13XX_PCIE_LOWER_MEM_RA ... IOP13XX_PCIE_UPPER_MEM_RA: - if (unlikely(!iop13xx_atue_mem_base)) - retval = NULL; - else - retval = (iop13xx_atue_mem_base + - (cookie - IOP13XX_PCIE_LOWER_MEM_RA)); - break; - case IOP13XX_PBI_LOWER_MEM_RA ... IOP13XX_PBI_UPPER_MEM_RA: - retval = __arm_ioremap_caller(IOP13XX_PBI_LOWER_MEM_PA + - (cookie - IOP13XX_PBI_LOWER_MEM_RA), - size, mtype, __builtin_return_address(0)); - break; - case IOP13XX_PMMR_PHYS_MEM_BASE ... IOP13XX_PMMR_UPPER_MEM_PA: - retval = IOP13XX_PMMR_PHYS_TO_VIRT(cookie); - break; - default: - retval = __arm_ioremap_caller(cookie, size, mtype, - caller); - } - - return retval; -} - -static void __iop13xx_iounmap(volatile void __iomem *addr) -{ - if (iop13xx_atue_mem_base) - if (addr >= (void __iomem *) iop13xx_atue_mem_base && - addr < (void __iomem *) (iop13xx_atue_mem_base + - iop13xx_atue_mem_size)) - goto skip; - - if (iop13xx_atux_mem_base) - if (addr >= (void __iomem *) iop13xx_atux_mem_base && - addr < (void __iomem *) (iop13xx_atux_mem_base + - iop13xx_atux_mem_size)) - goto skip; - - switch ((u32) addr) { - case (u32)IOP13XX_PMMR_VIRT_MEM_BASE ... (u32)IOP13XX_PMMR_UPPER_MEM_VA: - goto skip; - } - __iounmap(addr); - -skip: - return; -} - -void __init iop13xx_init_early(void) -{ - arch_ioremap_caller = __iop13xx_ioremap_caller; - arch_iounmap = __iop13xx_iounmap; -} diff --git a/arch/arm/mach-iop13xx/iq81340mc.c b/arch/arm/mach-iop13xx/iq81340mc.c deleted file mode 100644 index b3ce5cb228cc..000000000000 --- a/arch/arm/mach-iop13xx/iq81340mc.c +++ /dev/null @@ -1,84 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * iq81340mc board support - * Copyright (c) 2005-2006, Intel Corporation. - */ -#include <linux/pci.h> - -#include <mach/hardware.h> -#include <asm/irq.h> -#include <asm/mach/pci.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include "pci.h" -#include <asm/mach/time.h> -#include <mach/time.h> - -extern int init_atu; /* Flag to select which ATU(s) to initialize / disable */ - -static int __init -iq81340mc_pcix_map_irq(const struct pci_dev *dev, u8 idsel, u8 pin) -{ - switch (idsel) { - case 1: - switch (pin) { - case 1: return ATUX_INTB; - case 2: return ATUX_INTC; - case 3: return ATUX_INTD; - case 4: return ATUX_INTA; - default: return -1; - } - case 2: - switch (pin) { - case 1: return ATUX_INTC; - case 2: return ATUX_INTD; - case 3: return ATUX_INTC; - case 4: return ATUX_INTD; - default: return -1; - } - default: return -1; - } -} - -static struct hw_pci iq81340mc_pci __initdata = { - .nr_controllers = 0, - .setup = iop13xx_pci_setup, - .map_irq = iq81340mc_pcix_map_irq, - .scan = iop13xx_scan_bus, - .preinit = iop13xx_pci_init, -}; - -static int __init iq81340mc_pci_init(void) -{ - iop13xx_atu_select(&iq81340mc_pci); - pci_common_init(&iq81340mc_pci); - iop13xx_map_pci_memory(); - - return 0; -} - -static void __init iq81340mc_init(void) -{ - iop13xx_platform_init(); - iq81340mc_pci_init(); - iop13xx_add_tpmi_devices(); -} - -static void __init iq81340mc_timer_init(void) -{ - unsigned long bus_freq = iop13xx_core_freq() / iop13xx_xsi_bus_ratio(); - printk(KERN_DEBUG "%s: bus frequency: %lu\n", __func__, bus_freq); - iop_init_time(bus_freq); -} - -MACHINE_START(IQ81340MC, "Intel IQ81340MC") - /* Maintainer: Dan Williams <dan.j.williams@intel.com> */ - .atag_offset = 0x100, - .init_early = iop13xx_init_early, - .map_io = iop13xx_map_io, - .init_irq = iop13xx_init_irq, - .init_time = iq81340mc_timer_init, - .init_machine = iq81340mc_init, - .restart = iop13xx_restart, - .nr_irqs = NR_IOP13XX_IRQS, -MACHINE_END diff --git a/arch/arm/mach-iop13xx/iq81340sc.c b/arch/arm/mach-iop13xx/iq81340sc.c deleted file mode 100644 index 123845dcf2d3..000000000000 --- a/arch/arm/mach-iop13xx/iq81340sc.c +++ /dev/null @@ -1,86 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * iq81340sc board support - * Copyright (c) 2005-2006, Intel Corporation. - */ -#include <linux/pci.h> - -#include <mach/hardware.h> -#include <asm/irq.h> -#include <asm/mach/pci.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include "pci.h" -#include <asm/mach/time.h> -#include <mach/time.h> - -extern int init_atu; - -static int __init -iq81340sc_atux_map_irq(const struct pci_dev *dev, u8 idsel, u8 pin) -{ - WARN_ON(idsel < 1 || idsel > 2); - - switch (idsel) { - case 1: - switch (pin) { - case 1: return ATUX_INTB; - case 2: return ATUX_INTC; - case 3: return ATUX_INTD; - case 4: return ATUX_INTA; - default: return -1; - } - case 2: - switch (pin) { - case 1: return ATUX_INTC; - case 2: return ATUX_INTC; - case 3: return ATUX_INTC; - case 4: return ATUX_INTC; - default: return -1; - } - default: return -1; - } -} - -static struct hw_pci iq81340sc_pci __initdata = { - .nr_controllers = 0, - .setup = iop13xx_pci_setup, - .scan = iop13xx_scan_bus, - .map_irq = iq81340sc_atux_map_irq, - .preinit = iop13xx_pci_init -}; - -static int __init iq81340sc_pci_init(void) -{ - iop13xx_atu_select(&iq81340sc_pci); - pci_common_init(&iq81340sc_pci); - iop13xx_map_pci_memory(); - - return 0; -} - -static void __init iq81340sc_init(void) -{ - iop13xx_platform_init(); - iq81340sc_pci_init(); - iop13xx_add_tpmi_devices(); -} - -static void __init iq81340sc_timer_init(void) -{ - unsigned long bus_freq = iop13xx_core_freq() / iop13xx_xsi_bus_ratio(); - printk(KERN_DEBUG "%s: bus frequency: %lu\n", __func__, bus_freq); - iop_init_time(bus_freq); -} - -MACHINE_START(IQ81340SC, "Intel IQ81340SC") - /* Maintainer: Dan Williams <dan.j.williams@intel.com> */ - .atag_offset = 0x100, - .init_early = iop13xx_init_early, - .map_io = iop13xx_map_io, - .init_irq = iop13xx_init_irq, - .init_time = iq81340sc_timer_init, - .init_machine = iq81340sc_init, - .restart = iop13xx_restart, - .nr_irqs = NR_IOP13XX_IRQS, -MACHINE_END diff --git a/arch/arm/mach-iop13xx/irq.c b/arch/arm/mach-iop13xx/irq.c deleted file mode 100644 index 0e24ba7a1309..000000000000 --- a/arch/arm/mach-iop13xx/irq.c +++ /dev/null @@ -1,227 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * iop13xx IRQ handling / support functions - * Copyright (c) 2005-2006, Intel Corporation. - */ -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/list.h> -#include <linux/sysctl.h> -#include <linux/uaccess.h> -#include <asm/mach/irq.h> -#include <asm/irq.h> -#include <mach/hardware.h> -#include <mach/irqs.h> -#include "msi.h" - -/* INTCTL0 CP6 R0 Page 4 - */ -static u32 read_intctl_0(void) -{ - u32 val; - asm volatile("mrc p6, 0, %0, c0, c4, 0":"=r" (val)); - return val; -} -static void write_intctl_0(u32 val) -{ - asm volatile("mcr p6, 0, %0, c0, c4, 0"::"r" (val)); -} - -/* INTCTL1 CP6 R1 Page 4 - */ -static u32 read_intctl_1(void) -{ - u32 val; - asm volatile("mrc p6, 0, %0, c1, c4, 0":"=r" (val)); - return val; -} -static void write_intctl_1(u32 val) -{ - asm volatile("mcr p6, 0, %0, c1, c4, 0"::"r" (val)); -} - -/* INTCTL2 CP6 R2 Page 4 - */ -static u32 read_intctl_2(void) -{ - u32 val; - asm volatile("mrc p6, 0, %0, c2, c4, 0":"=r" (val)); - return val; -} -static void write_intctl_2(u32 val) -{ - asm volatile("mcr p6, 0, %0, c2, c4, 0"::"r" (val)); -} - -/* INTCTL3 CP6 R3 Page 4 - */ -static u32 read_intctl_3(void) -{ - u32 val; - asm volatile("mrc p6, 0, %0, c3, c4, 0":"=r" (val)); - return val; -} -static void write_intctl_3(u32 val) -{ - asm volatile("mcr p6, 0, %0, c3, c4, 0"::"r" (val)); -} - -/* INTSTR0 CP6 R0 Page 5 - */ -static void write_intstr_0(u32 val) -{ - asm volatile("mcr p6, 0, %0, c0, c5, 0"::"r" (val)); -} - -/* INTSTR1 CP6 R1 Page 5 - */ -static void write_intstr_1(u32 val) -{ - asm volatile("mcr p6, 0, %0, c1, c5, 0"::"r" (val)); -} - -/* INTSTR2 CP6 R2 Page 5 - */ -static void write_intstr_2(u32 val) -{ - asm volatile("mcr p6, 0, %0, c2, c5, 0"::"r" (val)); -} - -/* INTSTR3 CP6 R3 Page 5 - */ -static void write_intstr_3(u32 val) -{ - asm volatile("mcr p6, 0, %0, c3, c5, 0"::"r" (val)); -} - -/* INTBASE CP6 R0 Page 2 - */ -static void write_intbase(u32 val) -{ - asm volatile("mcr p6, 0, %0, c0, c2, 0"::"r" (val)); -} - -/* INTSIZE CP6 R2 Page 2 - */ -static void write_intsize(u32 val) -{ - asm volatile("mcr p6, 0, %0, c2, c2, 0"::"r" (val)); -} - -/* 0 = Interrupt Masked and 1 = Interrupt not masked */ -static void -iop13xx_irq_mask0 (struct irq_data *d) -{ - write_intctl_0(read_intctl_0() & ~(1 << (d->irq - 0))); -} - -static void -iop13xx_irq_mask1 (struct irq_data *d) -{ - write_intctl_1(read_intctl_1() & ~(1 << (d->irq - 32))); -} - -static void -iop13xx_irq_mask2 (struct irq_data *d) -{ - write_intctl_2(read_intctl_2() & ~(1 << (d->irq - 64))); -} - -static void -iop13xx_irq_mask3 (struct irq_data *d) -{ - write_intctl_3(read_intctl_3() & ~(1 << (d->irq - 96))); -} - -static void -iop13xx_irq_unmask0(struct irq_data *d) -{ - write_intctl_0(read_intctl_0() | (1 << (d->irq - 0))); -} - -static void -iop13xx_irq_unmask1(struct irq_data *d) -{ - write_intctl_1(read_intctl_1() | (1 << (d->irq - 32))); -} - -static void -iop13xx_irq_unmask2(struct irq_data *d) -{ - write_intctl_2(read_intctl_2() | (1 << (d->irq - 64))); -} - -static void -iop13xx_irq_unmask3(struct irq_data *d) -{ - write_intctl_3(read_intctl_3() | (1 << (d->irq - 96))); -} - -static struct irq_chip iop13xx_irqchip1 = { - .name = "IOP13xx-1", - .irq_ack = iop13xx_irq_mask0, - .irq_mask = iop13xx_irq_mask0, - .irq_unmask = iop13xx_irq_unmask0, -}; - -static struct irq_chip iop13xx_irqchip2 = { - .name = "IOP13xx-2", - .irq_ack = iop13xx_irq_mask1, - .irq_mask = iop13xx_irq_mask1, - .irq_unmask = iop13xx_irq_unmask1, -}; - -static struct irq_chip iop13xx_irqchip3 = { - .name = "IOP13xx-3", - .irq_ack = iop13xx_irq_mask2, - .irq_mask = iop13xx_irq_mask2, - .irq_unmask = iop13xx_irq_unmask2, -}; - -static struct irq_chip iop13xx_irqchip4 = { - .name = "IOP13xx-4", - .irq_ack = iop13xx_irq_mask3, - .irq_mask = iop13xx_irq_mask3, - .irq_unmask = iop13xx_irq_unmask3, -}; - -extern void iop_init_cp6_handler(void); - -void __init iop13xx_init_irq(void) -{ - unsigned int i; - - iop_init_cp6_handler(); - - /* disable all interrupts */ - write_intctl_0(0); - write_intctl_1(0); - write_intctl_2(0); - write_intctl_3(0); - - /* treat all as IRQ */ - write_intstr_0(0); - write_intstr_1(0); - write_intstr_2(0); - write_intstr_3(0); - - /* initialize the interrupt vector generator */ - write_intbase(INTBASE); - write_intsize(INTSIZE_4); - - for(i = 0; i <= IRQ_IOP13XX_HPI; i++) { - if (i < 32) - irq_set_chip(i, &iop13xx_irqchip1); - else if (i < 64) - irq_set_chip(i, &iop13xx_irqchip2); - else if (i < 96) - irq_set_chip(i, &iop13xx_irqchip3); - else - irq_set_chip(i, &iop13xx_irqchip4); - - irq_set_handler(i, handle_level_irq); - irq_clear_status_flags(i, IRQ_NOREQUEST | IRQ_NOPROBE); - } - - iop13xx_msi_init(); -} diff --git a/arch/arm/mach-iop13xx/msi.c b/arch/arm/mach-iop13xx/msi.c deleted file mode 100644 index f4d70cba1dd1..000000000000 --- a/arch/arm/mach-iop13xx/msi.c +++ /dev/null @@ -1,152 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * arch/arm/mach-iop13xx/msi.c - * - * PCI MSI support for the iop13xx processor - * - * Copyright (c) 2006, Intel Corporation. - */ -#include <linux/pci.h> -#include <linux/msi.h> -#include <asm/mach/irq.h> -#include <asm/irq.h> -#include <mach/irqs.h> - -/* IMIPR0 CP6 R8 Page 1 - */ -static u32 read_imipr_0(void) -{ - u32 val; - asm volatile("mrc p6, 0, %0, c8, c1, 0":"=r" (val)); - return val; -} -static void write_imipr_0(u32 val) -{ - asm volatile("mcr p6, 0, %0, c8, c1, 0"::"r" (val)); -} - -/* IMIPR1 CP6 R9 Page 1 - */ -static u32 read_imipr_1(void) -{ - u32 val; - asm volatile("mrc p6, 0, %0, c9, c1, 0":"=r" (val)); - return val; -} -static void write_imipr_1(u32 val) -{ - asm volatile("mcr p6, 0, %0, c9, c1, 0"::"r" (val)); -} - -/* IMIPR2 CP6 R10 Page 1 - */ -static u32 read_imipr_2(void) -{ - u32 val; - asm volatile("mrc p6, 0, %0, c10, c1, 0":"=r" (val)); - return val; -} -static void write_imipr_2(u32 val) -{ - asm volatile("mcr p6, 0, %0, c10, c1, 0"::"r" (val)); -} - -/* IMIPR3 CP6 R11 Page 1 - */ -static u32 read_imipr_3(void) -{ - u32 val; - asm volatile("mrc p6, 0, %0, c11, c1, 0":"=r" (val)); - return val; -} -static void write_imipr_3(u32 val) -{ - asm volatile("mcr p6, 0, %0, c11, c1, 0"::"r" (val)); -} - -static u32 (*read_imipr[])(void) = { - read_imipr_0, - read_imipr_1, - read_imipr_2, - read_imipr_3, -}; - -static void (*write_imipr[])(u32) = { - write_imipr_0, - write_imipr_1, - write_imipr_2, - write_imipr_3, -}; - -static void iop13xx_msi_handler(struct irq_desc *desc) -{ - int i, j; - unsigned long status; - - /* read IMIPR registers and find any active interrupts, - * then call ISR for each active interrupt - */ - for (i = 0; i < ARRAY_SIZE(read_imipr); i++) { - status = (read_imipr[i])(); - if (!status) - continue; - - do { - j = find_first_bit(&status, 32); - (write_imipr[i])(1 << j); /* write back to clear bit */ - generic_handle_irq(IRQ_IOP13XX_MSI_0 + j + (32*i)); - status = (read_imipr[i])(); - } while (status); - } -} - -void __init iop13xx_msi_init(void) -{ - irq_set_chained_handler(IRQ_IOP13XX_INBD_MSI, iop13xx_msi_handler); -} - -static void iop13xx_msi_nop(struct irq_data *d) -{ - return; -} - -static struct irq_chip iop13xx_msi_chip = { - .name = "PCI-MSI", - .irq_ack = iop13xx_msi_nop, - .irq_enable = pci_msi_unmask_irq, - .irq_disable = pci_msi_mask_irq, - .irq_mask = pci_msi_mask_irq, - .irq_unmask = pci_msi_unmask_irq, -}; - -int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) -{ - int id, irq = irq_alloc_desc_from(IRQ_IOP13XX_MSI_0, -1); - struct msi_msg msg; - - if (irq < 0) - return irq; - - if (irq >= NR_IOP13XX_IRQS) { - irq_free_desc(irq); - return -ENOSPC; - } - - irq_set_msi_desc(irq, desc); - - msg.address_hi = 0x0; - msg.address_lo = IOP13XX_MU_MIMR_PCI; - - id = iop13xx_cpu_id(); - msg.data = (id << IOP13XX_MU_MIMR_CORE_SELECT) | (irq & 0x7f); - - pci_write_msi_msg(irq, &msg); - irq_set_chip_and_handler(irq, &iop13xx_msi_chip, handle_simple_irq); - - return 0; -} - -void arch_teardown_msi_irq(unsigned int irq) -{ - irq_free_desc(irq); -} diff --git a/arch/arm/mach-iop13xx/msi.h b/arch/arm/mach-iop13xx/msi.h deleted file mode 100644 index 766dcfaaa353..000000000000 --- a/arch/arm/mach-iop13xx/msi.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _IOP13XX_MSI_H_ -#define _IOP13XX_MSI_H_ -#ifdef CONFIG_PCI_MSI -void iop13xx_msi_init(void); -#else -static inline void iop13xx_msi_init(void) -{ - return; -} -#endif -#endif diff --git a/arch/arm/mach-iop13xx/pci.c b/arch/arm/mach-iop13xx/pci.c deleted file mode 100644 index 46ea06e906cc..000000000000 --- a/arch/arm/mach-iop13xx/pci.c +++ /dev/null @@ -1,1115 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * iop13xx PCI support - * Copyright (c) 2005-2006, Intel Corporation. - */ - -#include <linux/pci.h> -#include <linux/slab.h> -#include <linux/delay.h> -#include <linux/jiffies.h> -#include <linux/export.h> -#include <asm/irq.h> -#include <mach/hardware.h> -#include <linux/sizes.h> -#include <asm/signal.h> -#include <asm/mach/pci.h> -#include "pci.h" - -#define IOP13XX_PCI_DEBUG 0 -#define PRINTK(x...) ((void)(IOP13XX_PCI_DEBUG && printk(x))) - -u32 iop13xx_atux_pmmr_offset; /* This offset can change based on strapping */ -u32 iop13xx_atue_pmmr_offset; /* This offset can change based on strapping */ -static struct pci_bus *pci_bus_atux = 0; -static struct pci_bus *pci_bus_atue = 0; -void __iomem *iop13xx_atue_mem_base; -void __iomem *iop13xx_atux_mem_base; -size_t iop13xx_atue_mem_size; -size_t iop13xx_atux_mem_size; - -EXPORT_SYMBOL(iop13xx_atue_mem_base); -EXPORT_SYMBOL(iop13xx_atux_mem_base); -EXPORT_SYMBOL(iop13xx_atue_mem_size); -EXPORT_SYMBOL(iop13xx_atux_mem_size); - -int init_atu = 0; /* Flag to select which ATU(s) to initialize / disable */ -static unsigned long atux_trhfa_timeout = 0; /* Trhfa = RST# high to first - access */ - -/* Scan the initialized busses and ioremap the requested memory range - */ -void iop13xx_map_pci_memory(void) -{ - int atu; - struct pci_bus *bus; - struct pci_dev *dev; - resource_size_t end = 0; - - for (atu = 0; atu < 2; atu++) { - bus = atu ? pci_bus_atue : pci_bus_atux; - if (bus) { - list_for_each_entry(dev, &bus->devices, bus_list) { - int i; - int max = 7; - - if (dev->subordinate) - max = DEVICE_COUNT_RESOURCE; - - for (i = 0; i < max; i++) { - struct resource *res = &dev->resource[i]; - if (res->flags & IORESOURCE_MEM) - end = max(res->end, end); - } - } - - switch(atu) { - case 0: - iop13xx_atux_mem_size = - (end - IOP13XX_PCIX_LOWER_MEM_RA) + 1; - - /* 16MB align the request */ - if (iop13xx_atux_mem_size & (SZ_16M - 1)) { - iop13xx_atux_mem_size &= ~(SZ_16M - 1); - iop13xx_atux_mem_size += SZ_16M; - } - - if (end) { - iop13xx_atux_mem_base = __arm_ioremap_pfn( - __phys_to_pfn(IOP13XX_PCIX_LOWER_MEM_PA) - , 0, iop13xx_atux_mem_size, MT_DEVICE); - if (!iop13xx_atux_mem_base) { - printk("%s: atux allocation " - "failed\n", __func__); - BUG(); - } - } else - iop13xx_atux_mem_size = 0; - PRINTK("%s: atu: %d bus_size: %d mem_base: %p\n", - __func__, atu, iop13xx_atux_mem_size, - iop13xx_atux_mem_base); - break; - case 1: - iop13xx_atue_mem_size = - (end - IOP13XX_PCIE_LOWER_MEM_RA) + 1; - - /* 16MB align the request */ - if (iop13xx_atue_mem_size & (SZ_16M - 1)) { - iop13xx_atue_mem_size &= ~(SZ_16M - 1); - iop13xx_atue_mem_size += SZ_16M; - } - - if (end) { - iop13xx_atue_mem_base = __arm_ioremap_pfn( - __phys_to_pfn(IOP13XX_PCIE_LOWER_MEM_PA) - , 0, iop13xx_atue_mem_size, MT_DEVICE); - if (!iop13xx_atue_mem_base) { - printk("%s: atue allocation " - "failed\n", __func__); - BUG(); - } - } else - iop13xx_atue_mem_size = 0; - PRINTK("%s: atu: %d bus_size: %d mem_base: %p\n", - __func__, atu, iop13xx_atue_mem_size, - iop13xx_atue_mem_base); - break; - } - - printk("%s: Initialized (%uM @ resource/virtual: %08lx/%p)\n", - atu ? "ATUE" : "ATUX", - (atu ? iop13xx_atue_mem_size : iop13xx_atux_mem_size) / - SZ_1M, - atu ? IOP13XX_PCIE_LOWER_MEM_RA : - IOP13XX_PCIX_LOWER_MEM_RA, - atu ? iop13xx_atue_mem_base : - iop13xx_atux_mem_base); - end = 0; - } - - } -} - -static int iop13xx_atu_function(int atu) -{ - int func = 0; - /* the function number depends on the value of the - * IOP13XX_INTERFACE_SEL_PCIX reset strap - * see C-Spec section 3.17 - */ - switch(atu) { - case IOP13XX_INIT_ATU_ATUX: - if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX) - func = 5; - else - func = 0; - break; - case IOP13XX_INIT_ATU_ATUE: - if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX) - func = 0; - else - func = 5; - break; - default: - BUG(); - } - - return func; -} - -/* iop13xx_atux_cfg_address - format a configuration address for atux - * @bus: Target bus to access - * @devfn: Combined device number and function number - * @where: Desired register's address offset - * - * Convert the parameters to a configuration address formatted - * according the PCI-X 2.0 specification - */ -static u32 iop13xx_atux_cfg_address(struct pci_bus *bus, int devfn, int where) -{ - struct pci_sys_data *sys = bus->sysdata; - u32 addr; - - if (sys->busnr == bus->number) - addr = 1 << (PCI_SLOT(devfn) + 16) | (PCI_SLOT(devfn) << 11); - else - addr = bus->number << 16 | PCI_SLOT(devfn) << 11 | 1; - - addr |= PCI_FUNC(devfn) << 8 | ((where & 0xff) & ~3); - addr |= ((where & 0xf00) >> 8) << 24; /* upper register number */ - - return addr; -} - -/* iop13xx_atue_cfg_address - format a configuration address for atue - * @bus: Target bus to access - * @devfn: Combined device number and function number - * @where: Desired register's address offset - * - * Convert the parameters to an address usable by the ATUE_OCCAR - */ -static u32 iop13xx_atue_cfg_address(struct pci_bus *bus, int devfn, int where) -{ - struct pci_sys_data *sys = bus->sysdata; - u32 addr; - - PRINTK("iop13xx_atue_cfg_address: bus: %d dev: %d func: %d", - bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn)); - addr = ((u32) bus->number) << IOP13XX_ATUE_OCCAR_BUS_NUM | - ((u32) PCI_SLOT(devfn)) << IOP13XX_ATUE_OCCAR_DEV_NUM | - ((u32) PCI_FUNC(devfn)) << IOP13XX_ATUE_OCCAR_FUNC_NUM | - (where & ~0x3); - - if (sys->busnr != bus->number) - addr |= 1; /* type 1 access */ - - return addr; -} - -/* This routine checks the status of the last configuration cycle. If an error - * was detected it returns >0, else it returns a 0. The errors being checked - * are parity, master abort, target abort (master and target). These types of - * errors occur during a config cycle where there is no device, like during - * the discovery stage. - */ -static int iop13xx_atux_pci_status(int clear) -{ - unsigned int status; - int err = 0; - - /* - * Check the status registers. - */ - status = __raw_readw(IOP13XX_ATUX_ATUSR); - if (status & IOP_PCI_STATUS_ERROR) - { - PRINTK("\t\t\tPCI error: ATUSR %#08x", status); - if(clear) - __raw_writew(status & IOP_PCI_STATUS_ERROR, - IOP13XX_ATUX_ATUSR); - err = 1; - } - status = __raw_readl(IOP13XX_ATUX_ATUISR); - if (status & IOP13XX_ATUX_ATUISR_ERROR) - { - PRINTK("\t\t\tPCI error interrupt: ATUISR %#08x", status); - if(clear) - __raw_writel(status & IOP13XX_ATUX_ATUISR_ERROR, - IOP13XX_ATUX_ATUISR); - err = 1; - } - return err; -} - -/* Simply write the address register and read the configuration - * data. Note that the data dependency on %0 encourages an abort - * to be detected before we return. - */ -static u32 iop13xx_atux_read(unsigned long addr) -{ - u32 val; - - __asm__ __volatile__( - "str %1, [%2]\n\t" - "ldr %0, [%3]\n\t" - "mov %0, %0\n\t" - : "=r" (val) - : "r" (addr), "r" (IOP13XX_ATUX_OCCAR), "r" (IOP13XX_ATUX_OCCDR)); - - return val; -} - -/* The read routines must check the error status of the last configuration - * cycle. If there was an error, the routine returns all hex f's. - */ -static int -iop13xx_atux_read_config(struct pci_bus *bus, unsigned int devfn, int where, - int size, u32 *value) -{ - unsigned long addr = iop13xx_atux_cfg_address(bus, devfn, where); - u32 val = iop13xx_atux_read(addr) >> ((where & 3) * 8); - - if (iop13xx_atux_pci_status(1) || is_atux_occdr_error()) { - __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3, - IOP13XX_XBG_BECSR); - val = 0xffffffff; - } - - *value = val; - - return PCIBIOS_SUCCESSFUL; -} - -static int -iop13xx_atux_write_config(struct pci_bus *bus, unsigned int devfn, int where, - int size, u32 value) -{ - unsigned long addr = iop13xx_atux_cfg_address(bus, devfn, where); - u32 val; - - if (size != 4) { - val = iop13xx_atux_read(addr); - if (!iop13xx_atux_pci_status(1) == 0) - return PCIBIOS_SUCCESSFUL; - - where = (where & 3) * 8; - - if (size == 1) - val &= ~(0xff << where); - else - val &= ~(0xffff << where); - - __raw_writel(val | value << where, IOP13XX_ATUX_OCCDR); - } else { - __raw_writel(addr, IOP13XX_ATUX_OCCAR); - __raw_writel(value, IOP13XX_ATUX_OCCDR); - } - - return PCIBIOS_SUCCESSFUL; -} - -static struct pci_ops iop13xx_atux_ops = { - .read = iop13xx_atux_read_config, - .write = iop13xx_atux_write_config, -}; - -/* This routine checks the status of the last configuration cycle. If an error - * was detected it returns >0, else it returns a 0. The errors being checked - * are parity, master abort, target abort (master and target). These types of - * errors occur during a config cycle where there is no device, like during - * the discovery stage. - */ -static int iop13xx_atue_pci_status(int clear) -{ - unsigned int status; - int err = 0; - - /* - * Check the status registers. - */ - - /* standard pci status register */ - status = __raw_readw(IOP13XX_ATUE_ATUSR); - if (status & IOP_PCI_STATUS_ERROR) { - PRINTK("\t\t\tPCI error: ATUSR %#08x", status); - if(clear) - __raw_writew(status & IOP_PCI_STATUS_ERROR, - IOP13XX_ATUE_ATUSR); - err++; - } - - /* check the normal status bits in the ATUISR */ - status = __raw_readl(IOP13XX_ATUE_ATUISR); - if (status & IOP13XX_ATUE_ATUISR_ERROR) { - PRINTK("\t\t\tPCI error: ATUISR %#08x", status); - if (clear) - __raw_writew(status & IOP13XX_ATUE_ATUISR_ERROR, - IOP13XX_ATUE_ATUISR); - err++; - - /* check the PCI-E status if the ATUISR reports an interface error */ - if (status & IOP13XX_ATUE_STAT_PCI_IFACE_ERR) { - /* get the unmasked errors */ - status = __raw_readl(IOP13XX_ATUE_PIE_STS) & - ~(__raw_readl(IOP13XX_ATUE_PIE_MSK)); - - if (status) { - PRINTK("\t\t\tPCI-E error: ATUE_PIE_STS %#08x", - __raw_readl(IOP13XX_ATUE_PIE_STS)); - err++; - } else { - PRINTK("\t\t\tPCI-E error: ATUE_PIE_STS %#08x", - __raw_readl(IOP13XX_ATUE_PIE_STS)); - PRINTK("\t\t\tPCI-E error: ATUE_PIE_MSK %#08x", - __raw_readl(IOP13XX_ATUE_PIE_MSK)); - BUG(); - } - - if(clear) - __raw_writel(status, IOP13XX_ATUE_PIE_STS); - } - } - - return err; -} - -static int -iop13xx_pcie_map_irq(const struct pci_dev *dev, u8 idsel, u8 pin) -{ - WARN_ON(idsel != 0); - - switch (pin) { - case 1: return ATUE_INTA; - case 2: return ATUE_INTB; - case 3: return ATUE_INTC; - case 4: return ATUE_INTD; - default: return -1; - } -} - -static u32 iop13xx_atue_read(unsigned long addr) -{ - u32 val; - - __raw_writel(addr, IOP13XX_ATUE_OCCAR); - val = __raw_readl(IOP13XX_ATUE_OCCDR); - - rmb(); - - return val; -} - -/* The read routines must check the error status of the last configuration - * cycle. If there was an error, the routine returns all hex f's. - */ -static int -iop13xx_atue_read_config(struct pci_bus *bus, unsigned int devfn, int where, - int size, u32 *value) -{ - u32 val; - unsigned long addr = iop13xx_atue_cfg_address(bus, devfn, where); - - /* Hide device numbers > 0 on the local PCI-E bus (Type 0 access) */ - if (!PCI_SLOT(devfn) || (addr & 1)) { - val = iop13xx_atue_read(addr) >> ((where & 3) * 8); - if( iop13xx_atue_pci_status(1) || is_atue_occdr_error() ) { - __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3, - IOP13XX_XBG_BECSR); - val = 0xffffffff; - } - - PRINTK("addr=%#0lx, val=%#010x", addr, val); - } else - val = 0xffffffff; - - *value = val; - - return PCIBIOS_SUCCESSFUL; -} - -static int -iop13xx_atue_write_config(struct pci_bus *bus, unsigned int devfn, int where, - int size, u32 value) -{ - unsigned long addr = iop13xx_atue_cfg_address(bus, devfn, where); - u32 val; - - if (size != 4) { - val = iop13xx_atue_read(addr); - if (!iop13xx_atue_pci_status(1) == 0) - return PCIBIOS_SUCCESSFUL; - - where = (where & 3) * 8; - - if (size == 1) - val &= ~(0xff << where); - else - val &= ~(0xffff << where); - - __raw_writel(val | value << where, IOP13XX_ATUE_OCCDR); - } else { - __raw_writel(addr, IOP13XX_ATUE_OCCAR); - __raw_writel(value, IOP13XX_ATUE_OCCDR); - } - - return PCIBIOS_SUCCESSFUL; -} - -static struct pci_ops iop13xx_atue_ops = { - .read = iop13xx_atue_read_config, - .write = iop13xx_atue_write_config, -}; - -/* When a PCI device does not exist during config cycles, the XScale gets a - * bus error instead of returning 0xffffffff. We can't rely on the ATU status - * bits to tell us that it was indeed a configuration cycle that caused this - * error especially in the case when the ATUE link is down. Instead we rely - * on data from the south XSI bridge to validate the abort - */ -int -iop13xx_pci_abort(unsigned long addr, unsigned int fsr, struct pt_regs *regs) -{ - PRINTK("Data abort: address = 0x%08lx " - "fsr = 0x%03x PC = 0x%08lx LR = 0x%08lx", - addr, fsr, regs->ARM_pc, regs->ARM_lr); - - PRINTK("IOP13XX_XBG_BECSR: %#10x", __raw_readl(IOP13XX_XBG_BECSR)); - PRINTK("IOP13XX_XBG_BERAR: %#10x", __raw_readl(IOP13XX_XBG_BERAR)); - PRINTK("IOP13XX_XBG_BERUAR: %#10x", __raw_readl(IOP13XX_XBG_BERUAR)); - - /* If it was an imprecise abort, then we need to correct the - * return address to be _after_ the instruction. - */ - if (fsr & (1 << 10)) - regs->ARM_pc += 4; - - if (is_atue_occdr_error() || is_atux_occdr_error()) - return 0; - else - return 1; -} - -/* Scan an IOP13XX PCI bus. nr selects which ATU we use. - */ -int iop13xx_scan_bus(int nr, struct pci_host_bridge *bridge) -{ - int which_atu, ret; - struct pci_sys_data *sys = pci_host_bridge_priv(bridge); - - switch (init_atu) { - case IOP13XX_INIT_ATU_ATUX: - which_atu = nr ? 0 : IOP13XX_INIT_ATU_ATUX; - break; - case IOP13XX_INIT_ATU_ATUE: - which_atu = nr ? 0 : IOP13XX_INIT_ATU_ATUE; - break; - case (IOP13XX_INIT_ATU_ATUX | IOP13XX_INIT_ATU_ATUE): - which_atu = nr ? IOP13XX_INIT_ATU_ATUE : IOP13XX_INIT_ATU_ATUX; - break; - default: - which_atu = 0; - } - - if (!which_atu) { - BUG(); - return -ENODEV; - } - - list_splice_init(&sys->resources, &bridge->windows); - bridge->dev.parent = NULL; - bridge->sysdata = sys; - bridge->busnr = sys->busnr; - - switch (which_atu) { - case IOP13XX_INIT_ATU_ATUX: - if (time_after_eq(jiffies + msecs_to_jiffies(1000), - atux_trhfa_timeout)) /* ensure not wrap */ - while(time_before(jiffies, atux_trhfa_timeout)) - udelay(100); - - bridge->ops = &iop13xx_atux_ops; - ret = pci_scan_root_bus_bridge(bridge); - if (!ret) - pci_bus_atux = bridge->bus; - break; - case IOP13XX_INIT_ATU_ATUE: - bridge->ops = &iop13xx_atue_ops; - ret = pci_scan_root_bus_bridge(bridge); - if (!ret) - pci_bus_atue = bridge->bus; - break; - default: - ret = -EINVAL; - } - - return ret; -} - -/* This function is called from iop13xx_pci_init() after assigning valid - * values to iop13xx_atue_pmmr_offset. This is the location for common - * setup of ATUE for all IOP13XX implementations. - */ -void __init iop13xx_atue_setup(void) -{ - int func = iop13xx_atu_function(IOP13XX_INIT_ATU_ATUE); - u32 reg_val; - -#ifdef CONFIG_PCI_MSI - /* BAR 0 (inbound msi window) */ - __raw_writel(IOP13XX_MU_BASE_PHYS, IOP13XX_MU_MUBAR); - __raw_writel(~(IOP13XX_MU_WINDOW_SIZE - 1), IOP13XX_ATUE_IALR0); - __raw_writel(IOP13XX_MU_BASE_PHYS, IOP13XX_ATUE_IATVR0); - __raw_writel(IOP13XX_MU_BASE_PCI, IOP13XX_ATUE_IABAR0); -#endif - - /* BAR 1 (1:1 mapping with Physical RAM) */ - /* Set limit and enable */ - __raw_writel(~(IOP13XX_MAX_RAM_SIZE - PHYS_OFFSET - 1) & ~0x1, - IOP13XX_ATUE_IALR1); - __raw_writel(0x0, IOP13XX_ATUE_IAUBAR1); - - /* Set base at the top of the reserved address space */ - __raw_writel(PHYS_OFFSET | PCI_BASE_ADDRESS_MEM_TYPE_64 | - PCI_BASE_ADDRESS_MEM_PREFETCH, IOP13XX_ATUE_IABAR1); - - /* 1:1 mapping with physical ram - * (leave big endian byte swap disabled) - */ - __raw_writel(0x0, IOP13XX_ATUE_IAUTVR1); - __raw_writel(PHYS_OFFSET, IOP13XX_ATUE_IATVR1); - - /* Outbound window 1 (PCIX/PCIE memory window) */ - /* 32 bit Address Space */ - __raw_writel(0x0, IOP13XX_ATUE_OUMWTVR1); - /* PA[35:32] */ - __raw_writel(IOP13XX_ATUE_OUMBAR_ENABLE | - (IOP13XX_PCIE_MEM_PHYS_OFFSET >> 32), - IOP13XX_ATUE_OUMBAR1); - - /* Setup the I/O Bar - * A[35-16] in 31-12 - */ - __raw_writel(((IOP13XX_PCIE_LOWER_IO_PA >> 0x4) & 0xfffff000), - IOP13XX_ATUE_OIOBAR); - __raw_writel(IOP13XX_PCIE_LOWER_IO_BA, IOP13XX_ATUE_OIOWTVR); - - /* clear startup errors */ - iop13xx_atue_pci_status(1); - - /* OIOBAR function number - */ - reg_val = __raw_readl(IOP13XX_ATUE_OIOBAR); - reg_val &= ~0x7; - reg_val |= func; - __raw_writel(reg_val, IOP13XX_ATUE_OIOBAR); - - /* OUMBAR function numbers - */ - reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR0); - reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK << - IOP13XX_ATU_OUMBAR_FUNC_NUM); - reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM; - __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR0); - - reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR1); - reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK << - IOP13XX_ATU_OUMBAR_FUNC_NUM); - reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM; - __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR1); - - reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR2); - reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK << - IOP13XX_ATU_OUMBAR_FUNC_NUM); - reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM; - __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR2); - - reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR3); - reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK << - IOP13XX_ATU_OUMBAR_FUNC_NUM); - reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM; - __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR3); - - /* Enable inbound and outbound cycles - */ - reg_val = __raw_readw(IOP13XX_ATUE_ATUCMD); - reg_val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | - PCI_COMMAND_PARITY | PCI_COMMAND_SERR; - __raw_writew(reg_val, IOP13XX_ATUE_ATUCMD); - - reg_val = __raw_readl(IOP13XX_ATUE_ATUCR); - reg_val |= IOP13XX_ATUE_ATUCR_OUT_EN | - IOP13XX_ATUE_ATUCR_IVM; - __raw_writel(reg_val, IOP13XX_ATUE_ATUCR); -} - -void __init iop13xx_atue_disable(void) -{ - u32 reg_val; - - __raw_writew(0x0, IOP13XX_ATUE_ATUCMD); - __raw_writel(IOP13XX_ATUE_ATUCR_IVM, IOP13XX_ATUE_ATUCR); - - /* wait for cycles to quiesce */ - while (__raw_readl(IOP13XX_ATUE_PCSR) & (IOP13XX_ATUE_PCSR_OUT_Q_BUSY | - IOP13XX_ATUE_PCSR_IN_Q_BUSY | - IOP13XX_ATUE_PCSR_LLRB_BUSY)) - cpu_relax(); - - /* BAR 0 ( Disabled ) */ - __raw_writel(0x0, IOP13XX_ATUE_IAUBAR0); - __raw_writel(0x0, IOP13XX_ATUE_IABAR0); - __raw_writel(0x0, IOP13XX_ATUE_IAUTVR0); - __raw_writel(0x0, IOP13XX_ATUE_IATVR0); - __raw_writel(0x0, IOP13XX_ATUE_IALR0); - reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR0); - reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE; - __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR0); - - /* BAR 1 ( Disabled ) */ - __raw_writel(0x0, IOP13XX_ATUE_IAUBAR1); - __raw_writel(0x0, IOP13XX_ATUE_IABAR1); - __raw_writel(0x0, IOP13XX_ATUE_IAUTVR1); - __raw_writel(0x0, IOP13XX_ATUE_IATVR1); - __raw_writel(0x0, IOP13XX_ATUE_IALR1); - reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR1); - reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE; - __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR1); - - /* BAR 2 ( Disabled ) */ - __raw_writel(0x0, IOP13XX_ATUE_IAUBAR2); - __raw_writel(0x0, IOP13XX_ATUE_IABAR2); - __raw_writel(0x0, IOP13XX_ATUE_IAUTVR2); - __raw_writel(0x0, IOP13XX_ATUE_IATVR2); - __raw_writel(0x0, IOP13XX_ATUE_IALR2); - reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR2); - reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE; - __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR2); - - /* BAR 3 ( Disabled ) */ - reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR3); - reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE; - __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR3); - - /* Setup the I/O Bar - * A[35-16] in 31-12 - */ - __raw_writel((IOP13XX_PCIE_LOWER_IO_PA >> 0x4) & 0xfffff000, - IOP13XX_ATUE_OIOBAR); - __raw_writel(IOP13XX_PCIE_LOWER_IO_BA, IOP13XX_ATUE_OIOWTVR); -} - -/* This function is called from iop13xx_pci_init() after assigning valid - * values to iop13xx_atux_pmmr_offset. This is the location for common - * setup of ATUX for all IOP13XX implementations. - */ -void __init iop13xx_atux_setup(void) -{ - u32 reg_val; - int func = iop13xx_atu_function(IOP13XX_INIT_ATU_ATUX); - - /* Take PCI-X bus out of reset if bootloader hasn't already. - * According to spec, we should wait for 2^25 PCI clocks to meet - * the PCI timing parameter Trhfa (RST# high to first access). - * This is rarely necessary and often ignored. - */ - reg_val = __raw_readl(IOP13XX_ATUX_PCSR); - if (reg_val & IOP13XX_ATUX_PCSR_P_RSTOUT) { - int msec = (reg_val >> IOP13XX_ATUX_PCSR_FREQ_OFFSET) & 0x7; - msec = 1000 / (8-msec); /* bits 100=133MHz, 111=>33MHz */ - __raw_writel(reg_val & ~IOP13XX_ATUX_PCSR_P_RSTOUT, - IOP13XX_ATUX_PCSR); - atux_trhfa_timeout = jiffies + msecs_to_jiffies(msec); - } - else - atux_trhfa_timeout = jiffies; - -#ifdef CONFIG_PCI_MSI - /* BAR 0 (inbound msi window) */ - __raw_writel(IOP13XX_MU_BASE_PHYS, IOP13XX_MU_MUBAR); - __raw_writel(~(IOP13XX_MU_WINDOW_SIZE - 1), IOP13XX_ATUX_IALR0); - __raw_writel(IOP13XX_MU_BASE_PHYS, IOP13XX_ATUX_IATVR0); - __raw_writel(IOP13XX_MU_BASE_PCI, IOP13XX_ATUX_IABAR0); -#endif - - /* BAR 1 (1:1 mapping with Physical RAM) */ - /* Set limit and enable */ - __raw_writel(~(IOP13XX_MAX_RAM_SIZE - PHYS_OFFSET - 1) & ~0x1, - IOP13XX_ATUX_IALR1); - __raw_writel(0x0, IOP13XX_ATUX_IAUBAR1); - - /* Set base at the top of the reserved address space */ - __raw_writel(PHYS_OFFSET | PCI_BASE_ADDRESS_MEM_TYPE_64 | - PCI_BASE_ADDRESS_MEM_PREFETCH, IOP13XX_ATUX_IABAR1); - - /* 1:1 mapping with physical ram - * (leave big endian byte swap disabled) - */ - __raw_writel(0x0, IOP13XX_ATUX_IAUTVR1); - __raw_writel(PHYS_OFFSET, IOP13XX_ATUX_IATVR1); - - /* Outbound window 1 (PCIX/PCIE memory window) */ - /* 32 bit Address Space */ - __raw_writel(0x0, IOP13XX_ATUX_OUMWTVR1); - /* PA[35:32] */ - __raw_writel(IOP13XX_ATUX_OUMBAR_ENABLE | - IOP13XX_PCIX_MEM_PHYS_OFFSET >> 32, - IOP13XX_ATUX_OUMBAR1); - - /* Setup the I/O Bar - * A[35-16] in 31-12 - */ - __raw_writel((IOP13XX_PCIX_LOWER_IO_PA >> 0x4) & 0xfffff000, - IOP13XX_ATUX_OIOBAR); - __raw_writel(IOP13XX_PCIX_LOWER_IO_BA, IOP13XX_ATUX_OIOWTVR); - - /* clear startup errors */ - iop13xx_atux_pci_status(1); - - /* OIOBAR function number - */ - reg_val = __raw_readl(IOP13XX_ATUX_OIOBAR); - reg_val &= ~0x7; - reg_val |= func; - __raw_writel(reg_val, IOP13XX_ATUX_OIOBAR); - - /* OUMBAR function numbers - */ - reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR0); - reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK << - IOP13XX_ATU_OUMBAR_FUNC_NUM); - reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM; - __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR0); - - reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR1); - reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK << - IOP13XX_ATU_OUMBAR_FUNC_NUM); - reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM; - __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR1); - - reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR2); - reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK << - IOP13XX_ATU_OUMBAR_FUNC_NUM); - reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM; - __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR2); - - reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR3); - reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK << - IOP13XX_ATU_OUMBAR_FUNC_NUM); - reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM; - __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR3); - - /* Enable inbound and outbound cycles - */ - reg_val = __raw_readw(IOP13XX_ATUX_ATUCMD); - reg_val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | - PCI_COMMAND_PARITY | PCI_COMMAND_SERR; - __raw_writew(reg_val, IOP13XX_ATUX_ATUCMD); - - reg_val = __raw_readl(IOP13XX_ATUX_ATUCR); - reg_val |= IOP13XX_ATUX_ATUCR_OUT_EN; - __raw_writel(reg_val, IOP13XX_ATUX_ATUCR); -} - -void __init iop13xx_atux_disable(void) -{ - u32 reg_val; - - __raw_writew(0x0, IOP13XX_ATUX_ATUCMD); - __raw_writel(0x0, IOP13XX_ATUX_ATUCR); - - /* wait for cycles to quiesce */ - while (__raw_readl(IOP13XX_ATUX_PCSR) & (IOP13XX_ATUX_PCSR_OUT_Q_BUSY | - IOP13XX_ATUX_PCSR_IN_Q_BUSY)) - cpu_relax(); - - /* BAR 0 ( Disabled ) */ - __raw_writel(0x0, IOP13XX_ATUX_IAUBAR0); - __raw_writel(0x0, IOP13XX_ATUX_IABAR0); - __raw_writel(0x0, IOP13XX_ATUX_IAUTVR0); - __raw_writel(0x0, IOP13XX_ATUX_IATVR0); - __raw_writel(0x0, IOP13XX_ATUX_IALR0); - reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR0); - reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE; - __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR0); - - /* BAR 1 ( Disabled ) */ - __raw_writel(0x0, IOP13XX_ATUX_IAUBAR1); - __raw_writel(0x0, IOP13XX_ATUX_IABAR1); - __raw_writel(0x0, IOP13XX_ATUX_IAUTVR1); - __raw_writel(0x0, IOP13XX_ATUX_IATVR1); - __raw_writel(0x0, IOP13XX_ATUX_IALR1); - reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR1); - reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE; - __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR1); - - /* BAR 2 ( Disabled ) */ - __raw_writel(0x0, IOP13XX_ATUX_IAUBAR2); - __raw_writel(0x0, IOP13XX_ATUX_IABAR2); - __raw_writel(0x0, IOP13XX_ATUX_IAUTVR2); - __raw_writel(0x0, IOP13XX_ATUX_IATVR2); - __raw_writel(0x0, IOP13XX_ATUX_IALR2); - reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR2); - reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE; - __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR2); - - /* BAR 3 ( Disabled ) */ - __raw_writel(0x0, IOP13XX_ATUX_IAUBAR3); - __raw_writel(0x0, IOP13XX_ATUX_IABAR3); - __raw_writel(0x0, IOP13XX_ATUX_IAUTVR3); - __raw_writel(0x0, IOP13XX_ATUX_IATVR3); - __raw_writel(0x0, IOP13XX_ATUX_IALR3); - reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR3); - reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE; - __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR3); - - /* Setup the I/O Bar - * A[35-16] in 31-12 - */ - __raw_writel((IOP13XX_PCIX_LOWER_IO_PA >> 0x4) & 0xfffff000, - IOP13XX_ATUX_OIOBAR); - __raw_writel(IOP13XX_PCIX_LOWER_IO_BA, IOP13XX_ATUX_OIOWTVR); -} - -void __init iop13xx_set_atu_mmr_bases(void) -{ - /* Based on ESSR0, determine the ATU X/E offsets */ - switch(__raw_readl(IOP13XX_ESSR0) & - (IOP13XX_CONTROLLER_ONLY | IOP13XX_INTERFACE_SEL_PCIX)) { - /* both asserted */ - case 0: - iop13xx_atux_pmmr_offset = IOP13XX_ATU1_PMMR_OFFSET; - iop13xx_atue_pmmr_offset = IOP13XX_ATU2_PMMR_OFFSET; - break; - /* IOP13XX_CONTROLLER_ONLY = deasserted - * IOP13XX_INTERFACE_SEL_PCIX = asserted - */ - case IOP13XX_CONTROLLER_ONLY: - iop13xx_atux_pmmr_offset = IOP13XX_ATU0_PMMR_OFFSET; - iop13xx_atue_pmmr_offset = IOP13XX_ATU2_PMMR_OFFSET; - break; - /* IOP13XX_CONTROLLER_ONLY = asserted - * IOP13XX_INTERFACE_SEL_PCIX = deasserted - */ - case IOP13XX_INTERFACE_SEL_PCIX: - iop13xx_atux_pmmr_offset = IOP13XX_ATU1_PMMR_OFFSET; - iop13xx_atue_pmmr_offset = IOP13XX_ATU2_PMMR_OFFSET; - break; - /* both deasserted */ - case IOP13XX_CONTROLLER_ONLY | IOP13XX_INTERFACE_SEL_PCIX: - iop13xx_atux_pmmr_offset = IOP13XX_ATU2_PMMR_OFFSET; - iop13xx_atue_pmmr_offset = IOP13XX_ATU0_PMMR_OFFSET; - break; - default: - BUG(); - } -} - -void __init iop13xx_atu_select(struct hw_pci *plat_pci) -{ - int i; - - /* set system defaults - * note: if "iop13xx_init_atu=" is specified this autodetect - * sequence will be bypassed - */ - if (init_atu == IOP13XX_INIT_ATU_DEFAULT) { - /* check for single/dual interface */ - if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX) { - /* ATUE must be present check the device id - * to see if ATUX is present. - */ - init_atu |= IOP13XX_INIT_ATU_ATUE; - switch (__raw_readw(IOP13XX_ATUE_DID) & 0xf0) { - case 0x70: - case 0x80: - case 0xc0: - init_atu |= IOP13XX_INIT_ATU_ATUX; - break; - } - } else { - /* ATUX must be present check the device id - * to see if ATUE is present. - */ - init_atu |= IOP13XX_INIT_ATU_ATUX; - switch (__raw_readw(IOP13XX_ATUX_DID) & 0xf0) { - case 0x70: - case 0x80: - case 0xc0: - init_atu |= IOP13XX_INIT_ATU_ATUE; - break; - } - } - - /* check central resource and root complex capability */ - if (init_atu & IOP13XX_INIT_ATU_ATUX) - if (!(__raw_readl(IOP13XX_ATUX_PCSR) & - IOP13XX_ATUX_PCSR_CENTRAL_RES)) - init_atu &= ~IOP13XX_INIT_ATU_ATUX; - - if (init_atu & IOP13XX_INIT_ATU_ATUE) - if (__raw_readl(IOP13XX_ATUE_PCSR) & - IOP13XX_ATUE_PCSR_END_POINT) - init_atu &= ~IOP13XX_INIT_ATU_ATUE; - } - - for (i = 0; i < 2; i++) { - if((init_atu & (1 << i)) == (1 << i)) - plat_pci->nr_controllers++; - } -} - -void __init iop13xx_pci_init(void) -{ - /* clear pre-existing south bridge errors */ - __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3, IOP13XX_XBG_BECSR); - - /* Setup the Min Address for PCI memory... */ - pcibios_min_mem = IOP13XX_PCIX_LOWER_MEM_BA; - - /* if Linux is given control of an ATU - * clear out its prior configuration, - * otherwise do not touch the registers - */ - if (init_atu & IOP13XX_INIT_ATU_ATUE) { - iop13xx_atue_disable(); - iop13xx_atue_setup(); - } - - if (init_atu & IOP13XX_INIT_ATU_ATUX) { - iop13xx_atux_disable(); - iop13xx_atux_setup(); - } - - hook_fault_code(16+6, iop13xx_pci_abort, SIGBUS, 0, - "imprecise external abort"); -} - -/* initialize the pci memory space. handle any combination of - * atue and atux enabled/disabled - */ -int iop13xx_pci_setup(int nr, struct pci_sys_data *sys) -{ - struct resource *res; - int which_atu; - u32 pcixsr, pcsr; - - if (nr > 1) - return 0; - - res = kzalloc(sizeof(struct resource), GFP_KERNEL); - if (!res) - panic("PCI: unable to alloc resources"); - - - /* 'nr' assumptions: - * ATUX is always 0 - * ATUE is 1 when ATUX is also enabled - * ATUE is 0 when ATUX is disabled - */ - switch(init_atu) { - case IOP13XX_INIT_ATU_ATUX: - which_atu = nr ? 0 : IOP13XX_INIT_ATU_ATUX; - break; - case IOP13XX_INIT_ATU_ATUE: - which_atu = nr ? 0 : IOP13XX_INIT_ATU_ATUE; - break; - case (IOP13XX_INIT_ATU_ATUX | IOP13XX_INIT_ATU_ATUE): - which_atu = nr ? IOP13XX_INIT_ATU_ATUE : IOP13XX_INIT_ATU_ATUX; - break; - default: - which_atu = 0; - } - - if (!which_atu) { - kfree(res); - return 0; - } - - switch(which_atu) { - case IOP13XX_INIT_ATU_ATUX: - pcixsr = __raw_readl(IOP13XX_ATUX_PCIXSR); - pcixsr &= ~0xffff; - pcixsr |= sys->busnr << IOP13XX_ATUX_PCIXSR_BUS_NUM | - 0 << IOP13XX_ATUX_PCIXSR_DEV_NUM | - iop13xx_atu_function(IOP13XX_INIT_ATU_ATUX) - << IOP13XX_ATUX_PCIXSR_FUNC_NUM; - __raw_writel(pcixsr, IOP13XX_ATUX_PCIXSR); - - pci_ioremap_io(0, IOP13XX_PCIX_LOWER_IO_PA); - - res->start = IOP13XX_PCIX_LOWER_MEM_RA; - res->end = IOP13XX_PCIX_UPPER_MEM_RA; - res->name = "IQ81340 ATUX PCI Memory Space"; - res->flags = IORESOURCE_MEM; - sys->mem_offset = IOP13XX_PCIX_MEM_OFFSET; - break; - case IOP13XX_INIT_ATU_ATUE: - /* Note: the function number field in the PCSR is ro */ - pcsr = __raw_readl(IOP13XX_ATUE_PCSR); - pcsr &= ~(0xfff8 << 16); - pcsr |= sys->busnr << IOP13XX_ATUE_PCSR_BUS_NUM | - 0 << IOP13XX_ATUE_PCSR_DEV_NUM; - - __raw_writel(pcsr, IOP13XX_ATUE_PCSR); - - pci_ioremap_io(SZ_64K, IOP13XX_PCIE_LOWER_IO_PA); - - res->start = IOP13XX_PCIE_LOWER_MEM_RA; - res->end = IOP13XX_PCIE_UPPER_MEM_RA; - res->name = "IQ81340 ATUE PCI Memory Space"; - res->flags = IORESOURCE_MEM; - sys->mem_offset = IOP13XX_PCIE_MEM_OFFSET; - sys->map_irq = iop13xx_pcie_map_irq; - break; - default: - kfree(res); - return 0; - } - - request_resource(&iomem_resource, res); - - pci_add_resource_offset(&sys->resources, res, sys->mem_offset); - - return 1; -} - -u16 iop13xx_dev_id(void) -{ - if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX) - return __raw_readw(IOP13XX_ATUE_DID); - else - return __raw_readw(IOP13XX_ATUX_DID); -} - -static int __init iop13xx_init_atu_setup(char *str) -{ - init_atu = IOP13XX_INIT_ATU_NONE; - if (str) { - while (*str != '\0') { - switch (*str) { - case 'x': - case 'X': - init_atu |= IOP13XX_INIT_ATU_ATUX; - init_atu &= ~IOP13XX_INIT_ATU_NONE; - break; - case 'e': - case 'E': - init_atu |= IOP13XX_INIT_ATU_ATUE; - init_atu &= ~IOP13XX_INIT_ATU_NONE; - break; - case ',': - case '=': - break; - default: - PRINTK("\"iop13xx_init_atu\" malformed at " - "character: \'%c\'", *str); - *(str + 1) = '\0'; - init_atu = IOP13XX_INIT_ATU_DEFAULT; - } - str++; - } - } - return 1; -} - -__setup("iop13xx_init_atu", iop13xx_init_atu_setup); diff --git a/arch/arm/mach-iop13xx/pci.h b/arch/arm/mach-iop13xx/pci.h deleted file mode 100644 index 736168d8c7ac..000000000000 --- a/arch/arm/mach-iop13xx/pci.h +++ /dev/null @@ -1,66 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _IOP13XX_PCI_H_ -#define _IOP13XX_PCI_H_ -#include <linux/io.h> -#include <mach/irqs.h> - -#include <linux/types.h> - -extern void __iomem *iop13xx_atue_mem_base; -extern void __iomem *iop13xx_atux_mem_base; -extern size_t iop13xx_atue_mem_size; -extern size_t iop13xx_atux_mem_size; - -struct pci_sys_data; -struct pci_host_bridge; -struct hw_pci; -int iop13xx_pci_setup(int nr, struct pci_sys_data *sys); -int iop13xx_scan_bus(int nr, struct pci_host_bridge *bridge); -void iop13xx_atu_select(struct hw_pci *plat_pci); -void iop13xx_pci_init(void); -void iop13xx_map_pci_memory(void); - -#define IOP_PCI_STATUS_ERROR (PCI_STATUS_PARITY | \ - PCI_STATUS_SIG_TARGET_ABORT | \ - PCI_STATUS_REC_TARGET_ABORT | \ - PCI_STATUS_REC_TARGET_ABORT | \ - PCI_STATUS_REC_MASTER_ABORT | \ - PCI_STATUS_SIG_SYSTEM_ERROR | \ - PCI_STATUS_DETECTED_PARITY) - -#define IOP13XX_ATUE_ATUISR_ERROR (IOP13XX_ATUE_STAT_HALT_ON_ERROR | \ - IOP13XX_ATUE_STAT_ROOT_SYS_ERR | \ - IOP13XX_ATUE_STAT_PCI_IFACE_ERR | \ - IOP13XX_ATUE_STAT_ERR_COR | \ - IOP13XX_ATUE_STAT_ERR_UNCOR | \ - IOP13XX_ATUE_STAT_CRS | \ - IOP13XX_ATUE_STAT_DET_PAR_ERR | \ - IOP13XX_ATUE_STAT_EXT_REC_MABORT | \ - IOP13XX_ATUE_STAT_SIG_TABORT | \ - IOP13XX_ATUE_STAT_EXT_REC_TABORT | \ - IOP13XX_ATUE_STAT_MASTER_DATA_PAR) - -#define IOP13XX_ATUX_ATUISR_ERROR (IOP13XX_ATUX_STAT_TX_SCEM | \ - IOP13XX_ATUX_STAT_REC_SCEM | \ - IOP13XX_ATUX_STAT_TX_SERR | \ - IOP13XX_ATUX_STAT_DET_PAR_ERR | \ - IOP13XX_ATUX_STAT_INT_REC_MABORT | \ - IOP13XX_ATUX_STAT_REC_SERR | \ - IOP13XX_ATUX_STAT_EXT_REC_MABORT | \ - IOP13XX_ATUX_STAT_EXT_REC_TABORT | \ - IOP13XX_ATUX_STAT_EXT_SIG_TABORT | \ - IOP13XX_ATUX_STAT_MASTER_DATA_PAR) - -/* PCI interrupts - */ -#define ATUX_INTA IRQ_IOP13XX_XINT0 -#define ATUX_INTB IRQ_IOP13XX_XINT1 -#define ATUX_INTC IRQ_IOP13XX_XINT2 -#define ATUX_INTD IRQ_IOP13XX_XINT3 - -#define ATUE_INTA IRQ_IOP13XX_ATUE_IMA -#define ATUE_INTB IRQ_IOP13XX_ATUE_IMB -#define ATUE_INTC IRQ_IOP13XX_ATUE_IMC -#define ATUE_INTD IRQ_IOP13XX_ATUE_IMD - -#endif /* _IOP13XX_PCI_H_ */ diff --git a/arch/arm/mach-iop13xx/setup.c b/arch/arm/mach-iop13xx/setup.c deleted file mode 100644 index c5c84c9ec9ee..000000000000 --- a/arch/arm/mach-iop13xx/setup.c +++ /dev/null @@ -1,595 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * iop13xx platform Initialization - * Copyright (c) 2005-2006, Intel Corporation. - */ - -#include <linux/dma-mapping.h> -#include <linux/serial_8250.h> -#include <linux/io.h> -#include <linux/reboot.h> -#ifdef CONFIG_MTD_PHYSMAP -#include <linux/mtd/physmap.h> -#endif -#include <asm/mach/map.h> -#include <mach/hardware.h> -#include <asm/irq.h> -#include <asm/hardware/iop_adma.h> -#include <mach/irqs.h> - -#define IOP13XX_UART_XTAL 33334000 -#define IOP13XX_SETUP_DEBUG 0 -#define PRINTK(x...) ((void)(IOP13XX_SETUP_DEBUG && printk(x))) - -/* Standard IO mapping for all IOP13XX based systems - */ -static struct map_desc iop13xx_std_desc[] __initdata = { - { /* mem mapped registers */ - .virtual = (unsigned long)IOP13XX_PMMR_VIRT_MEM_BASE, - .pfn = __phys_to_pfn(IOP13XX_PMMR_PHYS_MEM_BASE), - .length = IOP13XX_PMMR_SIZE, - .type = MT_DEVICE, - }, -}; - -static struct resource iop13xx_uart0_resources[] = { - [0] = { - .start = IOP13XX_UART0_PHYS, - .end = IOP13XX_UART0_PHYS + 0x3f, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_IOP13XX_UART0, - .end = IRQ_IOP13XX_UART0, - .flags = IORESOURCE_IRQ - } -}; - -static struct resource iop13xx_uart1_resources[] = { - [0] = { - .start = IOP13XX_UART1_PHYS, - .end = IOP13XX_UART1_PHYS + 0x3f, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_IOP13XX_UART1, - .end = IRQ_IOP13XX_UART1, - .flags = IORESOURCE_IRQ - } -}; - -static struct plat_serial8250_port iop13xx_uart0_data[] = { - { - .membase = IOP13XX_UART0_VIRT, - .mapbase = IOP13XX_UART0_PHYS, - .irq = IRQ_IOP13XX_UART0, - .uartclk = IOP13XX_UART_XTAL, - .regshift = 2, - .iotype = UPIO_MEM, - .flags = UPF_SKIP_TEST, - }, - { }, -}; - -static struct plat_serial8250_port iop13xx_uart1_data[] = { - { - .membase = IOP13XX_UART1_VIRT, - .mapbase = IOP13XX_UART1_PHYS, - .irq = IRQ_IOP13XX_UART1, - .uartclk = IOP13XX_UART_XTAL, - .regshift = 2, - .iotype = UPIO_MEM, - .flags = UPF_SKIP_TEST, - }, - { }, -}; - -/* The ids are fixed up later in iop13xx_platform_init */ -static struct platform_device iop13xx_uart0 = { - .name = "serial8250", - .id = 0, - .dev.platform_data = iop13xx_uart0_data, - .num_resources = 2, - .resource = iop13xx_uart0_resources, -}; - -static struct platform_device iop13xx_uart1 = { - .name = "serial8250", - .id = 0, - .dev.platform_data = iop13xx_uart1_data, - .num_resources = 2, - .resource = iop13xx_uart1_resources -}; - -static struct resource iop13xx_i2c_0_resources[] = { - [0] = { - .start = IOP13XX_I2C0_PHYS, - .end = IOP13XX_I2C0_PHYS + 0x18, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_IOP13XX_I2C_0, - .end = IRQ_IOP13XX_I2C_0, - .flags = IORESOURCE_IRQ - } -}; - -static struct resource iop13xx_i2c_1_resources[] = { - [0] = { - .start = IOP13XX_I2C1_PHYS, - .end = IOP13XX_I2C1_PHYS + 0x18, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_IOP13XX_I2C_1, - .end = IRQ_IOP13XX_I2C_1, - .flags = IORESOURCE_IRQ - } -}; - -static struct resource iop13xx_i2c_2_resources[] = { - [0] = { - .start = IOP13XX_I2C2_PHYS, - .end = IOP13XX_I2C2_PHYS + 0x18, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_IOP13XX_I2C_2, - .end = IRQ_IOP13XX_I2C_2, - .flags = IORESOURCE_IRQ - } -}; - -/* I2C controllers. The IOP13XX uses the same block as the IOP3xx, so - * we just use the same device name. - */ - -/* The ids are fixed up later in iop13xx_platform_init */ -static struct platform_device iop13xx_i2c_0_controller = { - .name = "IOP3xx-I2C", - .id = 0, - .num_resources = 2, - .resource = iop13xx_i2c_0_resources -}; - -static struct platform_device iop13xx_i2c_1_controller = { - .name = "IOP3xx-I2C", - .id = 0, - .num_resources = 2, - .resource = iop13xx_i2c_1_resources -}; - -static struct platform_device iop13xx_i2c_2_controller = { - .name = "IOP3xx-I2C", - .id = 0, - .num_resources = 2, - .resource = iop13xx_i2c_2_resources -}; - -#ifdef CONFIG_MTD_PHYSMAP -/* PBI Flash Device - */ -static struct physmap_flash_data iq8134x_flash_data = { - .width = 2, -}; - -static struct resource iq8134x_flash_resource = { - .start = IQ81340_FLASHBASE, - .end = 0, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device iq8134x_flash = { - .name = "physmap-flash", - .id = 0, - .dev = { .platform_data = &iq8134x_flash_data, }, - .num_resources = 1, - .resource = &iq8134x_flash_resource, -}; - -static unsigned long iq8134x_probe_flash_size(void) -{ - uint8_t __iomem *flash_addr = ioremap(IQ81340_FLASHBASE, PAGE_SIZE); - int i; - char query[3]; - unsigned long size = 0; - int width = iq8134x_flash_data.width; - - if (flash_addr) { - /* send CFI 'query' command */ - writew(0x98, flash_addr); - - /* check for CFI compliance */ - for (i = 0; i < 3 * width; i += width) - query[i / width] = readb(flash_addr + (0x10 * width) + i); - - /* read the size */ - if (memcmp(query, "QRY", 3) == 0) - size = 1 << readb(flash_addr + (0x27 * width)); - - /* send CFI 'read array' command */ - writew(0xff, flash_addr); - - iounmap(flash_addr); - } - - return size; -} -#endif - -/* ADMA Channels */ -static struct resource iop13xx_adma_0_resources[] = { - [0] = { - .start = IOP13XX_ADMA_PHYS_BASE(0), - .end = IOP13XX_ADMA_UPPER_PA(0), - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_IOP13XX_ADMA0_EOT, - .end = IRQ_IOP13XX_ADMA0_EOT, - .flags = IORESOURCE_IRQ - }, - [2] = { - .start = IRQ_IOP13XX_ADMA0_EOC, - .end = IRQ_IOP13XX_ADMA0_EOC, - .flags = IORESOURCE_IRQ - }, - [3] = { - .start = IRQ_IOP13XX_ADMA0_ERR, - .end = IRQ_IOP13XX_ADMA0_ERR, - .flags = IORESOURCE_IRQ - } -}; - -static struct resource iop13xx_adma_1_resources[] = { - [0] = { - .start = IOP13XX_ADMA_PHYS_BASE(1), - .end = IOP13XX_ADMA_UPPER_PA(1), - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_IOP13XX_ADMA1_EOT, - .end = IRQ_IOP13XX_ADMA1_EOT, - .flags = IORESOURCE_IRQ - }, - [2] = { - .start = IRQ_IOP13XX_ADMA1_EOC, - .end = IRQ_IOP13XX_ADMA1_EOC, - .flags = IORESOURCE_IRQ - }, - [3] = { - .start = IRQ_IOP13XX_ADMA1_ERR, - .end = IRQ_IOP13XX_ADMA1_ERR, - .flags = IORESOURCE_IRQ - } -}; - -static struct resource iop13xx_adma_2_resources[] = { - [0] = { - .start = IOP13XX_ADMA_PHYS_BASE(2), - .end = IOP13XX_ADMA_UPPER_PA(2), - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_IOP13XX_ADMA2_EOT, - .end = IRQ_IOP13XX_ADMA2_EOT, - .flags = IORESOURCE_IRQ - }, - [2] = { - .start = IRQ_IOP13XX_ADMA2_EOC, - .end = IRQ_IOP13XX_ADMA2_EOC, - .flags = IORESOURCE_IRQ - }, - [3] = { - .start = IRQ_IOP13XX_ADMA2_ERR, - .end = IRQ_IOP13XX_ADMA2_ERR, - .flags = IORESOURCE_IRQ - } -}; - -static u64 iop13xx_adma_dmamask = DMA_BIT_MASK(32); -static struct iop_adma_platform_data iop13xx_adma_0_data = { - .hw_id = 0, - .pool_size = PAGE_SIZE, -}; - -static struct iop_adma_platform_data iop13xx_adma_1_data = { - .hw_id = 1, - .pool_size = PAGE_SIZE, -}; - -static struct iop_adma_platform_data iop13xx_adma_2_data = { - .hw_id = 2, - .pool_size = PAGE_SIZE, -}; - -/* The ids are fixed up later in iop13xx_platform_init */ -static struct platform_device iop13xx_adma_0_channel = { - .name = "iop-adma", - .id = 0, - .num_resources = 4, - .resource = iop13xx_adma_0_resources, - .dev = { - .dma_mask = &iop13xx_adma_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = (void *) &iop13xx_adma_0_data, - }, -}; - -static struct platform_device iop13xx_adma_1_channel = { - .name = "iop-adma", - .id = 0, - .num_resources = 4, - .resource = iop13xx_adma_1_resources, - .dev = { - .dma_mask = &iop13xx_adma_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = (void *) &iop13xx_adma_1_data, - }, -}; - -static struct platform_device iop13xx_adma_2_channel = { - .name = "iop-adma", - .id = 0, - .num_resources = 4, - .resource = iop13xx_adma_2_resources, - .dev = { - .dma_mask = &iop13xx_adma_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = (void *) &iop13xx_adma_2_data, - }, -}; - -void __init iop13xx_map_io(void) -{ - /* Initialize the Static Page Table maps */ - iotable_init(iop13xx_std_desc, ARRAY_SIZE(iop13xx_std_desc)); -} - -static int init_uart; -static int init_i2c; -static int init_adma; - -void __init iop13xx_platform_init(void) -{ - int i; - u32 uart_idx, i2c_idx, adma_idx, plat_idx; - struct platform_device *iop13xx_devices[IQ81340_MAX_PLAT_DEVICES]; - - /* set the bases so we can read the device id */ - iop13xx_set_atu_mmr_bases(); - - memset(iop13xx_devices, 0, sizeof(iop13xx_devices)); - - if (init_uart == IOP13XX_INIT_UART_DEFAULT) { - switch (iop13xx_dev_id()) { - /* enable both uarts on iop341 */ - case 0x3380: - case 0x3384: - case 0x3388: - case 0x338c: - init_uart |= IOP13XX_INIT_UART_0; - init_uart |= IOP13XX_INIT_UART_1; - break; - /* only enable uart 1 */ - default: - init_uart |= IOP13XX_INIT_UART_1; - } - } - - if (init_i2c == IOP13XX_INIT_I2C_DEFAULT) { - switch (iop13xx_dev_id()) { - /* enable all i2c units on iop341 and iop342 */ - case 0x3380: - case 0x3384: - case 0x3388: - case 0x338c: - case 0x3382: - case 0x3386: - case 0x338a: - case 0x338e: - init_i2c |= IOP13XX_INIT_I2C_0; - init_i2c |= IOP13XX_INIT_I2C_1; - init_i2c |= IOP13XX_INIT_I2C_2; - break; - /* only enable i2c 1 and 2 */ - default: - init_i2c |= IOP13XX_INIT_I2C_1; - init_i2c |= IOP13XX_INIT_I2C_2; - } - } - - if (init_adma == IOP13XX_INIT_ADMA_DEFAULT) { - init_adma |= IOP13XX_INIT_ADMA_0; - init_adma |= IOP13XX_INIT_ADMA_1; - init_adma |= IOP13XX_INIT_ADMA_2; - } - - plat_idx = 0; - uart_idx = 0; - i2c_idx = 0; - - /* uart 1 (if enabled) is ttyS0 */ - if (init_uart & IOP13XX_INIT_UART_1) { - PRINTK("Adding uart1 to platform device list\n"); - iop13xx_uart1.id = uart_idx++; - iop13xx_devices[plat_idx++] = &iop13xx_uart1; - } - if (init_uart & IOP13XX_INIT_UART_0) { - PRINTK("Adding uart0 to platform device list\n"); - iop13xx_uart0.id = uart_idx++; - iop13xx_devices[plat_idx++] = &iop13xx_uart0; - } - - for(i = 0; i < IQ81340_NUM_I2C; i++) { - if ((init_i2c & (1 << i)) && IOP13XX_SETUP_DEBUG) - printk("Adding i2c%d to platform device list\n", i); - switch(init_i2c & (1 << i)) { - case IOP13XX_INIT_I2C_0: - iop13xx_i2c_0_controller.id = i2c_idx++; - iop13xx_devices[plat_idx++] = - &iop13xx_i2c_0_controller; - break; - case IOP13XX_INIT_I2C_1: - iop13xx_i2c_1_controller.id = i2c_idx++; - iop13xx_devices[plat_idx++] = - &iop13xx_i2c_1_controller; - break; - case IOP13XX_INIT_I2C_2: - iop13xx_i2c_2_controller.id = i2c_idx++; - iop13xx_devices[plat_idx++] = - &iop13xx_i2c_2_controller; - break; - } - } - - /* initialize adma channel ids and capabilities */ - adma_idx = 0; - for (i = 0; i < IQ81340_NUM_ADMA; i++) { - struct iop_adma_platform_data *plat_data; - if ((init_adma & (1 << i)) && IOP13XX_SETUP_DEBUG) - printk(KERN_INFO - "Adding adma%d to platform device list\n", i); - switch (init_adma & (1 << i)) { - case IOP13XX_INIT_ADMA_0: - iop13xx_adma_0_channel.id = adma_idx++; - iop13xx_devices[plat_idx++] = &iop13xx_adma_0_channel; - plat_data = &iop13xx_adma_0_data; - dma_cap_set(DMA_MEMCPY, plat_data->cap_mask); - dma_cap_set(DMA_XOR, plat_data->cap_mask); - dma_cap_set(DMA_XOR_VAL, plat_data->cap_mask); - dma_cap_set(DMA_INTERRUPT, plat_data->cap_mask); - break; - case IOP13XX_INIT_ADMA_1: - iop13xx_adma_1_channel.id = adma_idx++; - iop13xx_devices[plat_idx++] = &iop13xx_adma_1_channel; - plat_data = &iop13xx_adma_1_data; - dma_cap_set(DMA_MEMCPY, plat_data->cap_mask); - dma_cap_set(DMA_XOR, plat_data->cap_mask); - dma_cap_set(DMA_XOR_VAL, plat_data->cap_mask); - dma_cap_set(DMA_INTERRUPT, plat_data->cap_mask); - break; - case IOP13XX_INIT_ADMA_2: - iop13xx_adma_2_channel.id = adma_idx++; - iop13xx_devices[plat_idx++] = &iop13xx_adma_2_channel; - plat_data = &iop13xx_adma_2_data; - dma_cap_set(DMA_MEMCPY, plat_data->cap_mask); - dma_cap_set(DMA_XOR, plat_data->cap_mask); - dma_cap_set(DMA_XOR_VAL, plat_data->cap_mask); - dma_cap_set(DMA_INTERRUPT, plat_data->cap_mask); - dma_cap_set(DMA_PQ, plat_data->cap_mask); - dma_cap_set(DMA_PQ_VAL, plat_data->cap_mask); - break; - } - } - -#ifdef CONFIG_MTD_PHYSMAP - iq8134x_flash_resource.end = iq8134x_flash_resource.start + - iq8134x_probe_flash_size() - 1; - if (iq8134x_flash_resource.end > iq8134x_flash_resource.start) - iop13xx_devices[plat_idx++] = &iq8134x_flash; - else - printk(KERN_ERR "%s: Failed to probe flash size\n", __func__); -#endif - - platform_add_devices(iop13xx_devices, plat_idx); -} - -static int __init iop13xx_init_uart_setup(char *str) -{ - if (str) { - while (*str != '\0') { - switch(*str) { - case '0': - init_uart |= IOP13XX_INIT_UART_0; - break; - case '1': - init_uart |= IOP13XX_INIT_UART_1; - break; - case ',': - case '=': - break; - default: - PRINTK("\"iop13xx_init_uart\" malformed" - " at character: \'%c\'", *str); - *(str + 1) = '\0'; - init_uart = IOP13XX_INIT_UART_DEFAULT; - } - str++; - } - } - return 1; -} - -static int __init iop13xx_init_i2c_setup(char *str) -{ - if (str) { - while (*str != '\0') { - switch(*str) { - case '0': - init_i2c |= IOP13XX_INIT_I2C_0; - break; - case '1': - init_i2c |= IOP13XX_INIT_I2C_1; - break; - case '2': - init_i2c |= IOP13XX_INIT_I2C_2; - break; - case ',': - case '=': - break; - default: - PRINTK("\"iop13xx_init_i2c\" malformed" - " at character: \'%c\'", *str); - *(str + 1) = '\0'; - init_i2c = IOP13XX_INIT_I2C_DEFAULT; - } - str++; - } - } - return 1; -} - -static int __init iop13xx_init_adma_setup(char *str) -{ - if (str) { - while (*str != '\0') { - switch (*str) { - case '0': - init_adma |= IOP13XX_INIT_ADMA_0; - break; - case '1': - init_adma |= IOP13XX_INIT_ADMA_1; - break; - case '2': - init_adma |= IOP13XX_INIT_ADMA_2; - break; - case ',': - case '=': - break; - default: - PRINTK("\"iop13xx_init_adma\" malformed" - " at character: \'%c\'", *str); - *(str + 1) = '\0'; - init_adma = IOP13XX_INIT_ADMA_DEFAULT; - } - str++; - } - } - return 1; -} - -__setup("iop13xx_init_adma", iop13xx_init_adma_setup); -__setup("iop13xx_init_uart", iop13xx_init_uart_setup); -__setup("iop13xx_init_i2c", iop13xx_init_i2c_setup); - -void iop13xx_restart(enum reboot_mode mode, const char *cmd) -{ - /* - * Reset the internal bus (warning both cores are reset) - */ - write_wdtcr(IOP_WDTCR_EN_ARM); - write_wdtcr(IOP_WDTCR_EN); - write_wdtsr(IOP13XX_WDTSR_WRITE_EN | IOP13XX_WDTCR_IB_RESET); - write_wdtcr(0x1000); -} diff --git a/arch/arm/mach-iop13xx/tpmi.c b/arch/arm/mach-iop13xx/tpmi.c deleted file mode 100644 index 4f916549e381..000000000000 --- a/arch/arm/mach-iop13xx/tpmi.c +++ /dev/null @@ -1,244 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * iop13xx tpmi device resources - * Copyright (c) 2005-2006, Intel Corporation. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/dma-mapping.h> -#include <linux/io.h> -#include <asm/irq.h> -#include <linux/sizes.h> -#include <mach/irqs.h> - -/* assumes CONTROLLER_ONLY# is never asserted in the ESSR register */ -#define IOP13XX_TPMI_MMR(dev) IOP13XX_REG_ADDR32_PHYS(0x48000 + (dev << 12)) -#define IOP13XX_TPMI_MEM(dev) IOP13XX_REG_ADDR32_PHYS(0x60000 + (dev << 13)) -#define IOP13XX_TPMI_CTRL(dev) IOP13XX_REG_ADDR32_PHYS(0x50000 + (dev << 10)) -#define IOP13XX_TPMI_IOP_CTRL(dev) (IOP13XX_TPMI_CTRL(dev) + 0x2000) -#define IOP13XX_TPMI_MMR_SIZE (SZ_4K - 1) -#define IOP13XX_TPMI_MEM_SIZE (255) -#define IOP13XX_TPMI_MEM_CTRL (SZ_1K - 1) -#define IOP13XX_TPMI_RESOURCE_MMR 0 -#define IOP13XX_TPMI_RESOURCE_MEM 1 -#define IOP13XX_TPMI_RESOURCE_CTRL 2 -#define IOP13XX_TPMI_RESOURCE_IOP_CTRL 3 -#define IOP13XX_TPMI_RESOURCE_IRQ 4 - -static struct resource iop13xx_tpmi_0_resources[] = { - [IOP13XX_TPMI_RESOURCE_MMR] = { - .start = IOP13XX_TPMI_MMR(4), /* tpmi0 starts at dev == 4 */ - .end = IOP13XX_TPMI_MMR(4) + IOP13XX_TPMI_MMR_SIZE, - .flags = IORESOURCE_MEM, - }, - [IOP13XX_TPMI_RESOURCE_MEM] = { - .start = IOP13XX_TPMI_MEM(0), - .end = IOP13XX_TPMI_MEM(0) + IOP13XX_TPMI_MEM_SIZE, - .flags = IORESOURCE_MEM, - }, - [IOP13XX_TPMI_RESOURCE_CTRL] = { - .start = IOP13XX_TPMI_CTRL(0), - .end = IOP13XX_TPMI_CTRL(0) + IOP13XX_TPMI_MEM_CTRL, - .flags = IORESOURCE_MEM, - }, - [IOP13XX_TPMI_RESOURCE_IOP_CTRL] = { - .start = IOP13XX_TPMI_IOP_CTRL(0), - .end = IOP13XX_TPMI_IOP_CTRL(0) + IOP13XX_TPMI_MEM_CTRL, - .flags = IORESOURCE_MEM, - }, - [IOP13XX_TPMI_RESOURCE_IRQ] = { - .start = IRQ_IOP13XX_TPMI0_OUT, - .end = IRQ_IOP13XX_TPMI0_OUT, - .flags = IORESOURCE_IRQ - } -}; - -static struct resource iop13xx_tpmi_1_resources[] = { - [IOP13XX_TPMI_RESOURCE_MMR] = { - .start = IOP13XX_TPMI_MMR(1), - .end = IOP13XX_TPMI_MMR(1) + IOP13XX_TPMI_MMR_SIZE, - .flags = IORESOURCE_MEM, - }, - [IOP13XX_TPMI_RESOURCE_MEM] = { - .start = IOP13XX_TPMI_MEM(1), - .end = IOP13XX_TPMI_MEM(1) + IOP13XX_TPMI_MEM_SIZE, - .flags = IORESOURCE_MEM, - }, - [IOP13XX_TPMI_RESOURCE_CTRL] = { - .start = IOP13XX_TPMI_CTRL(1), - .end = IOP13XX_TPMI_CTRL(1) + IOP13XX_TPMI_MEM_CTRL, - .flags = IORESOURCE_MEM, - }, - [IOP13XX_TPMI_RESOURCE_IOP_CTRL] = { - .start = IOP13XX_TPMI_IOP_CTRL(1), - .end = IOP13XX_TPMI_IOP_CTRL(1) + IOP13XX_TPMI_MEM_CTRL, - .flags = IORESOURCE_MEM, - }, - [IOP13XX_TPMI_RESOURCE_IRQ] = { - .start = IRQ_IOP13XX_TPMI1_OUT, - .end = IRQ_IOP13XX_TPMI1_OUT, - .flags = IORESOURCE_IRQ - } -}; - -static struct resource iop13xx_tpmi_2_resources[] = { - [IOP13XX_TPMI_RESOURCE_MMR] = { - .start = IOP13XX_TPMI_MMR(2), - .end = IOP13XX_TPMI_MMR(2) + IOP13XX_TPMI_MMR_SIZE, - .flags = IORESOURCE_MEM, - }, - [IOP13XX_TPMI_RESOURCE_MEM] = { - .start = IOP13XX_TPMI_MEM(2), - .end = IOP13XX_TPMI_MEM(2) + IOP13XX_TPMI_MEM_SIZE, - .flags = IORESOURCE_MEM, - }, - [IOP13XX_TPMI_RESOURCE_CTRL] = { - .start = IOP13XX_TPMI_CTRL(2), - .end = IOP13XX_TPMI_CTRL(2) + IOP13XX_TPMI_MEM_CTRL, - .flags = IORESOURCE_MEM, - }, - [IOP13XX_TPMI_RESOURCE_IOP_CTRL] = { - .start = IOP13XX_TPMI_IOP_CTRL(2), - .end = IOP13XX_TPMI_IOP_CTRL(2) + IOP13XX_TPMI_MEM_CTRL, - .flags = IORESOURCE_MEM, - }, - [IOP13XX_TPMI_RESOURCE_IRQ] = { - .start = IRQ_IOP13XX_TPMI2_OUT, - .end = IRQ_IOP13XX_TPMI2_OUT, - .flags = IORESOURCE_IRQ - } -}; - -static struct resource iop13xx_tpmi_3_resources[] = { - [IOP13XX_TPMI_RESOURCE_MMR] = { - .start = IOP13XX_TPMI_MMR(3), - .end = IOP13XX_TPMI_MMR(3) + IOP13XX_TPMI_MMR_SIZE, - .flags = IORESOURCE_MEM, - }, - [IOP13XX_TPMI_RESOURCE_MEM] = { - .start = IOP13XX_TPMI_MEM(3), - .end = IOP13XX_TPMI_MEM(3) + IOP13XX_TPMI_MEM_SIZE, - .flags = IORESOURCE_MEM, - }, - [IOP13XX_TPMI_RESOURCE_CTRL] = { - .start = IOP13XX_TPMI_CTRL(3), - .end = IOP13XX_TPMI_CTRL(3) + IOP13XX_TPMI_MEM_CTRL, - .flags = IORESOURCE_MEM, - }, - [IOP13XX_TPMI_RESOURCE_IOP_CTRL] = { - .start = IOP13XX_TPMI_IOP_CTRL(3), - .end = IOP13XX_TPMI_IOP_CTRL(3) + IOP13XX_TPMI_MEM_CTRL, - .flags = IORESOURCE_MEM, - }, - [IOP13XX_TPMI_RESOURCE_IRQ] = { - .start = IRQ_IOP13XX_TPMI3_OUT, - .end = IRQ_IOP13XX_TPMI3_OUT, - .flags = IORESOURCE_IRQ - } -}; - -u64 iop13xx_tpmi_mask = DMA_BIT_MASK(32); -static struct platform_device iop13xx_tpmi_0_device = { - .name = "iop-tpmi", - .id = 0, - .num_resources = ARRAY_SIZE(iop13xx_tpmi_0_resources), - .resource = iop13xx_tpmi_0_resources, - .dev = { - .dma_mask = &iop13xx_tpmi_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -static struct platform_device iop13xx_tpmi_1_device = { - .name = "iop-tpmi", - .id = 1, - .num_resources = ARRAY_SIZE(iop13xx_tpmi_1_resources), - .resource = iop13xx_tpmi_1_resources, - .dev = { - .dma_mask = &iop13xx_tpmi_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -static struct platform_device iop13xx_tpmi_2_device = { - .name = "iop-tpmi", - .id = 2, - .num_resources = ARRAY_SIZE(iop13xx_tpmi_2_resources), - .resource = iop13xx_tpmi_2_resources, - .dev = { - .dma_mask = &iop13xx_tpmi_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -static struct platform_device iop13xx_tpmi_3_device = { - .name = "iop-tpmi", - .id = 3, - .num_resources = ARRAY_SIZE(iop13xx_tpmi_3_resources), - .resource = iop13xx_tpmi_3_resources, - .dev = { - .dma_mask = &iop13xx_tpmi_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -__init void iop13xx_add_tpmi_devices(void) -{ - unsigned short device_id; - - /* tpmi's not present on iop341 or iop342 */ - if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX) - /* ATUE must be present */ - device_id = __raw_readw(IOP13XX_ATUE_DID); - else - /* ATUX must be present */ - device_id = __raw_readw(IOP13XX_ATUX_DID); - - switch (device_id) { - /* iop34[1|2] 0-tpmi */ - case 0x3380: - case 0x3384: - case 0x3388: - case 0x338c: - case 0x3382: - case 0x3386: - case 0x338a: - case 0x338e: - return; - /* iop348 1-tpmi */ - case 0x3310: - case 0x3312: - case 0x3314: - case 0x3318: - case 0x331a: - case 0x331c: - case 0x33c0: - case 0x33c2: - case 0x33c4: - case 0x33c8: - case 0x33ca: - case 0x33cc: - case 0x33b0: - case 0x33b2: - case 0x33b4: - case 0x33b8: - case 0x33ba: - case 0x33bc: - case 0x3320: - case 0x3322: - case 0x3324: - case 0x3328: - case 0x332a: - case 0x332c: - platform_device_register(&iop13xx_tpmi_0_device); - return; - default: - platform_device_register(&iop13xx_tpmi_0_device); - platform_device_register(&iop13xx_tpmi_1_device); - platform_device_register(&iop13xx_tpmi_2_device); - platform_device_register(&iop13xx_tpmi_3_device); - return; - } -} diff --git a/arch/arm/mach-iop32x/Makefile b/arch/arm/mach-iop32x/Makefile index 71d62447d4d5..c8018ef5c6a9 100644 --- a/arch/arm/mach-iop32x/Makefile +++ b/arch/arm/mach-iop32x/Makefile @@ -3,7 +3,15 @@ # Makefile for the linux kernel. # -obj-y := irq.o +obj-$(CONFIG_ARCH_IOP32X) += irq.o +obj-$(CONFIG_ARCH_IOP32X) += i2c.o +obj-$(CONFIG_ARCH_IOP32X) += pci.o +obj-$(CONFIG_ARCH_IOP32X) += setup.o +obj-$(CONFIG_ARCH_IOP32X) += time.o +obj-$(CONFIG_ARCH_IOP32X) += cp6.o +obj-$(CONFIG_ARCH_IOP32X) += adma.o +obj-$(CONFIG_ARCH_IOP32X) += pmu.o +obj-$(CONFIG_ARCH_IOP32X) += restart.o obj-$(CONFIG_MACH_GLANTANK) += glantank.o obj-$(CONFIG_ARCH_IQ80321) += iq80321.o diff --git a/arch/arm/plat-iop/adma.c b/arch/arm/mach-iop32x/adma.c index b8e360299293..764bcbff98df 100644 --- a/arch/arm/plat-iop/adma.c +++ b/arch/arm/mach-iop32x/adma.c @@ -4,12 +4,12 @@ * Copyright © 2006, Intel Corporation. */ #include <linux/platform_device.h> -#include <asm/hardware/iop3xx.h> #include <linux/dma-mapping.h> -#include <mach/adma.h> -#include <asm/hardware/iop_adma.h> +#include <linux/platform_data/dma-iop32x.h> + +#include "iop3xx.h" +#include "irqs.h" -#ifdef CONFIG_ARCH_IOP32X #define IRQ_DMA0_EOT IRQ_IOP32X_DMA0_EOT #define IRQ_DMA0_EOC IRQ_IOP32X_DMA0_EOC #define IRQ_DMA0_ERR IRQ_IOP32X_DMA0_ERR @@ -21,20 +21,7 @@ #define IRQ_AA_EOT IRQ_IOP32X_AA_EOT #define IRQ_AA_EOC IRQ_IOP32X_AA_EOC #define IRQ_AA_ERR IRQ_IOP32X_AA_ERR -#endif -#ifdef CONFIG_ARCH_IOP33X -#define IRQ_DMA0_EOT IRQ_IOP33X_DMA0_EOT -#define IRQ_DMA0_EOC IRQ_IOP33X_DMA0_EOC -#define IRQ_DMA0_ERR IRQ_IOP33X_DMA0_ERR - -#define IRQ_DMA1_EOT IRQ_IOP33X_DMA1_EOT -#define IRQ_DMA1_EOC IRQ_IOP33X_DMA1_EOC -#define IRQ_DMA1_ERR IRQ_IOP33X_DMA1_ERR - -#define IRQ_AA_EOT IRQ_IOP33X_AA_EOT -#define IRQ_AA_EOC IRQ_IOP33X_AA_EOC -#define IRQ_AA_ERR IRQ_IOP33X_AA_ERR -#endif + /* AAU and DMA Channels */ static struct resource iop3xx_dma_0_resources[] = { [0] = { @@ -161,30 +148,14 @@ struct platform_device iop3xx_aau_channel = { static int __init iop3xx_adma_cap_init(void) { - #ifdef CONFIG_ARCH_IOP32X /* the 32x DMA does not perform CRC32C */ - dma_cap_set(DMA_MEMCPY, iop3xx_dma_0_data.cap_mask); - dma_cap_set(DMA_INTERRUPT, iop3xx_dma_0_data.cap_mask); - #else dma_cap_set(DMA_MEMCPY, iop3xx_dma_0_data.cap_mask); dma_cap_set(DMA_INTERRUPT, iop3xx_dma_0_data.cap_mask); - #endif - #ifdef CONFIG_ARCH_IOP32X /* the 32x DMA does not perform CRC32C */ dma_cap_set(DMA_MEMCPY, iop3xx_dma_1_data.cap_mask); dma_cap_set(DMA_INTERRUPT, iop3xx_dma_1_data.cap_mask); - #else - dma_cap_set(DMA_MEMCPY, iop3xx_dma_1_data.cap_mask); - dma_cap_set(DMA_INTERRUPT, iop3xx_dma_1_data.cap_mask); - #endif - #ifdef CONFIG_ARCH_IOP32X /* the 32x AAU does not perform zero sum */ - dma_cap_set(DMA_XOR, iop3xx_aau_data.cap_mask); - dma_cap_set(DMA_INTERRUPT, iop3xx_aau_data.cap_mask); - #else dma_cap_set(DMA_XOR, iop3xx_aau_data.cap_mask); - dma_cap_set(DMA_XOR_VAL, iop3xx_aau_data.cap_mask); dma_cap_set(DMA_INTERRUPT, iop3xx_aau_data.cap_mask); - #endif return 0; } diff --git a/arch/arm/plat-iop/cp6.c b/arch/arm/mach-iop32x/cp6.c index ec74b07fb7e3..ec74b07fb7e3 100644 --- a/arch/arm/plat-iop/cp6.c +++ b/arch/arm/mach-iop32x/cp6.c diff --git a/arch/arm/mach-iop32x/em7210.c b/arch/arm/mach-iop32x/em7210.c index 61a1e593f9ec..d43ced3cd4e7 100644 --- a/arch/arm/mach-iop32x/em7210.c +++ b/arch/arm/mach-iop32x/em7210.c @@ -21,7 +21,6 @@ #include <linux/i2c.h> #include <linux/gpio.h> #include <linux/gpio/machine.h> -#include <mach/hardware.h> #include <linux/io.h> #include <linux/irq.h> #include <asm/mach/arch.h> @@ -29,8 +28,10 @@ #include <asm/mach/pci.h> #include <asm/mach/time.h> #include <asm/mach-types.h> -#include <mach/time.h> + +#include "hardware.h" #include "gpio-iop32x.h" +#include "irqs.h" static void __init em7210_timer_init(void) { diff --git a/arch/arm/mach-iop32x/glantank.c b/arch/arm/mach-iop32x/glantank.c index 5a45d616d9ac..2fe0f77d1f1d 100644 --- a/arch/arm/mach-iop32x/glantank.c +++ b/arch/arm/mach-iop32x/glantank.c @@ -22,7 +22,6 @@ #include <linux/platform_device.h> #include <linux/io.h> #include <linux/gpio/machine.h> -#include <mach/hardware.h> #include <asm/irq.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> @@ -30,8 +29,10 @@ #include <asm/mach/time.h> #include <asm/mach-types.h> #include <asm/page.h> -#include <mach/time.h> + +#include "hardware.h" #include "gpio-iop32x.h" +#include "irqs.h" /* * GLAN Tank timer tick configuration. diff --git a/arch/arm/mach-iop32x/include/mach/glantank.h b/arch/arm/mach-iop32x/glantank.h index b9df2e4614cf..f38e86b82c3d 100644 --- a/arch/arm/mach-iop32x/include/mach/glantank.h +++ b/arch/arm/mach-iop32x/glantank.h @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * arch/arm/mach-iop32x/include/mach/glantank.h - * * IO-Data GLAN Tank board registers */ diff --git a/arch/arm/mach-iop32x/include/mach/hardware.h b/arch/arm/mach-iop32x/hardware.h index 6e5303e60226..43ab4fb8f9b0 100644 --- a/arch/arm/mach-iop32x/include/mach/hardware.h +++ b/arch/arm/mach-iop32x/hardware.h @@ -1,8 +1,4 @@ /* SPDX-License-Identifier: GPL-2.0 */ -/* - * arch/arm/mach-iop32x/include/mach/hardware.h - */ - #ifndef __HARDWARE_H #define __HARDWARE_H @@ -28,7 +24,7 @@ void iop32x_init_irq(void); /* * Generic chipset bits */ -#include "iop32x.h" +#include "iop3xx.h" /* * Board specific bits diff --git a/arch/arm/plat-iop/i2c.c b/arch/arm/mach-iop32x/i2c.c index dfbd7c332866..dc9f6a14ab1b 100644 --- a/arch/arm/plat-iop/i2c.c +++ b/arch/arm/mach-iop32x/i2c.c @@ -22,18 +22,11 @@ #include <asm/mach/map.h> #include <asm/setup.h> #include <asm/memory.h> -#include <mach/hardware.h> -#include <asm/hardware/iop3xx.h> #include <asm/mach/arch.h> -#ifdef CONFIG_ARCH_IOP32X -#define IRQ_IOP3XX_I2C_0 IRQ_IOP32X_I2C_0 -#define IRQ_IOP3XX_I2C_1 IRQ_IOP32X_I2C_1 -#endif -#ifdef CONFIG_ARCH_IOP33X -#define IRQ_IOP3XX_I2C_0 IRQ_IOP33X_I2C_0 -#define IRQ_IOP3XX_I2C_1 IRQ_IOP33X_I2C_1 -#endif +#include "hardware.h" +#include "iop3xx.h" +#include "irqs.h" /* * Each of the I2C busses have corresponding GPIO lines, and the driver @@ -65,8 +58,8 @@ static struct resource iop3xx_i2c0_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = IRQ_IOP3XX_I2C_0, - .end = IRQ_IOP3XX_I2C_0, + .start = IRQ_IOP32X_I2C_0, + .end = IRQ_IOP32X_I2C_0, .flags = IORESOURCE_IRQ, }, }; @@ -86,8 +79,8 @@ static struct resource iop3xx_i2c1_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = IRQ_IOP3XX_I2C_1, - .end = IRQ_IOP3XX_I2C_1, + .start = IRQ_IOP32X_I2C_1, + .end = IRQ_IOP32X_I2C_1, .flags = IORESOURCE_IRQ, } }; diff --git a/arch/arm/mach-iop32x/include/mach/adma.h b/arch/arm/mach-iop32x/include/mach/adma.h deleted file mode 100644 index 2b20063123ad..000000000000 --- a/arch/arm/mach-iop32x/include/mach/adma.h +++ /dev/null @@ -1,6 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef IOP32X_ADMA_H -#define IOP32X_ADMA_H -#include <asm/hardware/iop3xx-adma.h> -#endif - diff --git a/arch/arm/mach-iop32x/include/mach/entry-macro.S b/arch/arm/mach-iop32x/include/mach/entry-macro.S index ea13ae02d9b1..8e6766d4621e 100644 --- a/arch/arm/mach-iop32x/include/mach/entry-macro.S +++ b/arch/arm/mach-iop32x/include/mach/entry-macro.S @@ -7,8 +7,6 @@ * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ -#include <mach/iop32x.h> - .macro get_irqnr_preamble, base, tmp mrc p15, 0, \tmp, c15, c1, 0 orr \tmp, \tmp, #(1 << 6) diff --git a/arch/arm/mach-iop32x/include/mach/iop32x.h b/arch/arm/mach-iop32x/include/mach/iop32x.h deleted file mode 100644 index 84223f86552f..000000000000 --- a/arch/arm/mach-iop32x/include/mach/iop32x.h +++ /dev/null @@ -1,31 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * arch/arm/mach-iop32x/include/mach/iop32x.h - * - * Intel IOP32X Chip definitions - * - * Author: Rory Bolt <rorybolt@pacbell.net> - * Copyright (C) 2002 Rory Bolt - * Copyright (C) 2004 Intel Corp. - */ - -#ifndef __IOP32X_H -#define __IOP32X_H - -/* - * Peripherals that are shared between the iop32x and iop33x but - * located at different addresses. - */ -#define IOP3XX_TIMER_REG(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07e0 + (reg)) - -#include <asm/hardware/iop3xx.h> - -/* ATU Parameters - * set up a 1:1 bus to physical ram relationship - * w/ physical ram on top of pci in the memory map - */ -#define IOP32X_MAX_RAM_SIZE 0x40000000UL -#define IOP3XX_MAX_RAM_SIZE IOP32X_MAX_RAM_SIZE -#define IOP3XX_PCI_LOWER_MEM_BA 0x80000000 - -#endif diff --git a/arch/arm/mach-iop32x/include/mach/irqs.h b/arch/arm/mach-iop32x/include/mach/irqs.h index 82b11743e91c..c4e78df428e8 100644 --- a/arch/arm/mach-iop32x/include/mach/irqs.h +++ b/arch/arm/mach-iop32x/include/mach/irqs.h @@ -9,39 +9,6 @@ #ifndef __IRQS_H #define __IRQS_H -/* - * IOP80321 chipset interrupts - */ -#define IRQ_IOP32X_DMA0_EOT 0 -#define IRQ_IOP32X_DMA0_EOC 1 -#define IRQ_IOP32X_DMA1_EOT 2 -#define IRQ_IOP32X_DMA1_EOC 3 -#define IRQ_IOP32X_AA_EOT 6 -#define IRQ_IOP32X_AA_EOC 7 -#define IRQ_IOP32X_CORE_PMON 8 -#define IRQ_IOP32X_TIMER0 9 -#define IRQ_IOP32X_TIMER1 10 -#define IRQ_IOP32X_I2C_0 11 -#define IRQ_IOP32X_I2C_1 12 -#define IRQ_IOP32X_MESSAGING 13 -#define IRQ_IOP32X_ATU_BIST 14 -#define IRQ_IOP32X_PERFMON 15 -#define IRQ_IOP32X_CORE_PMU 16 -#define IRQ_IOP32X_BIU_ERR 17 -#define IRQ_IOP32X_ATU_ERR 18 -#define IRQ_IOP32X_MCU_ERR 19 -#define IRQ_IOP32X_DMA0_ERR 20 -#define IRQ_IOP32X_DMA1_ERR 21 -#define IRQ_IOP32X_AA_ERR 23 -#define IRQ_IOP32X_MSG_ERR 24 -#define IRQ_IOP32X_SSP 25 -#define IRQ_IOP32X_XINT0 27 -#define IRQ_IOP32X_XINT1 28 -#define IRQ_IOP32X_XINT2 29 -#define IRQ_IOP32X_XINT3 30 -#define IRQ_IOP32X_HPI 31 - #define NR_IRQS 32 - #endif diff --git a/arch/arm/mach-iop32x/include/mach/time.h b/arch/arm/mach-iop32x/include/mach/time.h deleted file mode 100644 index d08950ccebc4..000000000000 --- a/arch/arm/mach-iop32x/include/mach/time.h +++ /dev/null @@ -1,5 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _IOP32X_TIME_H_ -#define _IOP32X_TIME_H_ -#define IRQ_IOP_TIMER0 IRQ_IOP32X_TIMER0 -#endif diff --git a/arch/arm/mach-iop32x/include/mach/uncompress.h b/arch/arm/mach-iop32x/include/mach/uncompress.h index ed4ac3e28fa1..c8548875d942 100644 --- a/arch/arm/mach-iop32x/include/mach/uncompress.h +++ b/arch/arm/mach-iop32x/include/mach/uncompress.h @@ -6,9 +6,8 @@ #include <asm/types.h> #include <asm/mach-types.h> #include <linux/serial_reg.h> -#include <mach/hardware.h> -volatile u8 *uart_base; +#define uart_base ((volatile u8 *)0xfe800000) #define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE) @@ -23,17 +22,4 @@ static inline void flush(void) { } -static __inline__ void __arch_decomp_setup(unsigned long arch_id) -{ - if (machine_is_iq80321()) - uart_base = (volatile u8 *)IQ80321_UART; - else if (machine_is_iq31244() || machine_is_em7210()) - uart_base = (volatile u8 *)IQ31244_UART; - else - uart_base = (volatile u8 *)0xfe800000; -} - -/* - * nothing to do - */ -#define arch_decomp_setup() __arch_decomp_setup(arch_id) +#define arch_decomp_setup() do { } while (0) diff --git a/arch/arm/include/asm/hardware/iop3xx.h b/arch/arm/mach-iop32x/iop3xx.h index 3cb6f22f510b..46b4b34a4ad2 100644 --- a/arch/arm/include/asm/hardware/iop3xx.h +++ b/arch/arm/mach-iop32x/iop3xx.h @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * arch/arm/include/asm/hardware/iop3xx.h - * * Intel IOP32X and IOP33X register definitions * * Author: Rory Bolt <rorybolt@pacbell.net> @@ -13,6 +11,22 @@ #define __IOP3XX_H /* + * Peripherals that are shared between the iop32x and iop33x but + * located at different addresses. + */ +#define IOP3XX_TIMER_REG(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07e0 + (reg)) + +#include "iop3xx.h" + +/* ATU Parameters + * set up a 1:1 bus to physical ram relationship + * w/ physical ram on top of pci in the memory map + */ +#define IOP32X_MAX_RAM_SIZE 0x40000000UL +#define IOP3XX_MAX_RAM_SIZE IOP32X_MAX_RAM_SIZE +#define IOP3XX_PCI_LOWER_MEM_BA 0x80000000 + +/* * IOP3XX GPIO handling */ #define IOP3XX_GPIO_LINE(x) (x) diff --git a/arch/arm/mach-iop32x/iq31244.c b/arch/arm/mach-iop32x/iq31244.c index 8755aa87e591..04a7d389d365 100644 --- a/arch/arm/mach-iop32x/iq31244.c +++ b/arch/arm/mach-iop32x/iq31244.c @@ -23,7 +23,6 @@ #include <linux/platform_device.h> #include <linux/io.h> #include <linux/gpio/machine.h> -#include <mach/hardware.h> #include <asm/cputype.h> #include <asm/irq.h> #include <asm/mach/arch.h> @@ -33,7 +32,9 @@ #include <asm/mach-types.h> #include <asm/page.h> #include <asm/pgtable.h> -#include <mach/time.h> + +#include "hardware.h" +#include "irqs.h" #include "gpio-iop32x.h" /* diff --git a/arch/arm/mach-iop32x/include/mach/iq31244.h b/arch/arm/mach-iop32x/iq31244.h index e62da5da6ed4..a7ac691e48d3 100644 --- a/arch/arm/mach-iop32x/include/mach/iq31244.h +++ b/arch/arm/mach-iop32x/iq31244.h @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * arch/arm/mach-iop32x/include/mach/iq31244.h - * * Intel IQ31244 evaluation board registers */ diff --git a/arch/arm/mach-iop32x/iq80321.c b/arch/arm/mach-iop32x/iq80321.c index e12699d1c540..4bd596d6c9c1 100644 --- a/arch/arm/mach-iop32x/iq80321.c +++ b/arch/arm/mach-iop32x/iq80321.c @@ -20,7 +20,6 @@ #include <linux/platform_device.h> #include <linux/io.h> #include <linux/gpio/machine.h> -#include <mach/hardware.h> #include <asm/irq.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> @@ -29,7 +28,9 @@ #include <asm/mach-types.h> #include <asm/page.h> #include <asm/pgtable.h> -#include <mach/time.h> + +#include "hardware.h" +#include "irqs.h" #include "gpio-iop32x.h" /* diff --git a/arch/arm/mach-iop32x/include/mach/iq80321.h b/arch/arm/mach-iop32x/iq80321.h index faf62c26f6f8..3a5d10626ea6 100644 --- a/arch/arm/mach-iop32x/include/mach/iq80321.h +++ b/arch/arm/mach-iop32x/iq80321.h @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * arch/arm/mach-iop32x/include/mach/iq80321.h - * * Intel IQ80321 evaluation board registers */ diff --git a/arch/arm/mach-iop32x/irq.c b/arch/arm/mach-iop32x/irq.c index 2f5d4ec94f9c..2d48bf1398c1 100644 --- a/arch/arm/mach-iop32x/irq.c +++ b/arch/arm/mach-iop32x/irq.c @@ -13,9 +13,10 @@ #include <linux/list.h> #include <asm/mach/irq.h> #include <asm/irq.h> -#include <mach/hardware.h> #include <asm/mach-types.h> +#include "hardware.h" + static u32 iop32x_mask; static void intctl_write(u32 val) diff --git a/arch/arm/mach-iop32x/irqs.h b/arch/arm/mach-iop32x/irqs.h new file mode 100644 index 000000000000..69858e4e905d --- /dev/null +++ b/arch/arm/mach-iop32x/irqs.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Author: Rory Bolt <rorybolt@pacbell.net> + * Copyright: (C) 2002 Rory Bolt + */ + +#ifndef __IOP32X_IRQS_H +#define __IOP32X_IRQS_H + +/* + * IOP80321 chipset interrupts + */ +#define IRQ_IOP32X_DMA0_EOT 0 +#define IRQ_IOP32X_DMA0_EOC 1 +#define IRQ_IOP32X_DMA1_EOT 2 +#define IRQ_IOP32X_DMA1_EOC 3 +#define IRQ_IOP32X_AA_EOT 6 +#define IRQ_IOP32X_AA_EOC 7 +#define IRQ_IOP32X_CORE_PMON 8 +#define IRQ_IOP32X_TIMER0 9 +#define IRQ_IOP32X_TIMER1 10 +#define IRQ_IOP32X_I2C_0 11 +#define IRQ_IOP32X_I2C_1 12 +#define IRQ_IOP32X_MESSAGING 13 +#define IRQ_IOP32X_ATU_BIST 14 +#define IRQ_IOP32X_PERFMON 15 +#define IRQ_IOP32X_CORE_PMU 16 +#define IRQ_IOP32X_BIU_ERR 17 +#define IRQ_IOP32X_ATU_ERR 18 +#define IRQ_IOP32X_MCU_ERR 19 +#define IRQ_IOP32X_DMA0_ERR 20 +#define IRQ_IOP32X_DMA1_ERR 21 +#define IRQ_IOP32X_AA_ERR 23 +#define IRQ_IOP32X_MSG_ERR 24 +#define IRQ_IOP32X_SSP 25 +#define IRQ_IOP32X_XINT0 27 +#define IRQ_IOP32X_XINT1 28 +#define IRQ_IOP32X_XINT2 29 +#define IRQ_IOP32X_XINT3 30 +#define IRQ_IOP32X_HPI 31 + +#endif diff --git a/arch/arm/mach-iop32x/n2100.c b/arch/arm/mach-iop32x/n2100.c index 26d76b377e79..5382a93ad0f8 100644 --- a/arch/arm/mach-iop32x/n2100.c +++ b/arch/arm/mach-iop32x/n2100.c @@ -28,7 +28,6 @@ #include <linux/io.h> #include <linux/gpio.h> #include <linux/gpio/machine.h> -#include <mach/hardware.h> #include <asm/irq.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> @@ -37,7 +36,9 @@ #include <asm/mach-types.h> #include <asm/page.h> #include <asm/pgtable.h> -#include <mach/time.h> + +#include "hardware.h" +#include "irqs.h" #include "gpio-iop32x.h" /* diff --git a/arch/arm/mach-iop32x/include/mach/n2100.h b/arch/arm/mach-iop32x/n2100.h index 70bb660b643a..0b97b940d3e7 100644 --- a/arch/arm/mach-iop32x/include/mach/n2100.h +++ b/arch/arm/mach-iop32x/n2100.h @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * arch/arm/mach-iop32x/include/mach/n2100.h - * * Thecus N2100 board registers */ diff --git a/arch/arm/plat-iop/pci.c b/arch/arm/mach-iop32x/pci.c index 4c42c95e4bf5..ab0010dc3145 100644 --- a/arch/arm/plat-iop/pci.c +++ b/arch/arm/mach-iop32x/pci.c @@ -17,9 +17,9 @@ #include <linux/io.h> #include <asm/irq.h> #include <asm/signal.h> -#include <mach/hardware.h> #include <asm/mach/pci.h> -#include <asm/hardware/iop3xx.h> +#include "hardware.h" +#include "iop3xx.h" // #define DEBUG diff --git a/arch/arm/plat-iop/pmu.c b/arch/arm/mach-iop32x/pmu.c index 04c44a809b32..bdbc7a3cb8a3 100644 --- a/arch/arm/plat-iop/pmu.c +++ b/arch/arm/mach-iop32x/pmu.c @@ -5,17 +5,11 @@ */ #include <linux/platform_device.h> -#include <mach/irqs.h> +#include "irqs.h" static struct resource pmu_resource = { -#ifdef CONFIG_ARCH_IOP32X .start = IRQ_IOP32X_CORE_PMU, .end = IRQ_IOP32X_CORE_PMU, -#endif -#ifdef CONFIG_ARCH_IOP33X - .start = IRQ_IOP33X_CORE_PMU, - .end = IRQ_IOP33X_CORE_PMU, -#endif .flags = IORESOURCE_IRQ, }; diff --git a/arch/arm/plat-iop/restart.c b/arch/arm/mach-iop32x/restart.c index cf6d3d9a2112..3dfa54d3a7a8 100644 --- a/arch/arm/plat-iop/restart.c +++ b/arch/arm/mach-iop32x/restart.c @@ -4,9 +4,9 @@ * * Copyright (C) 2001 MontaVista Software, Inc. */ -#include <asm/hardware/iop3xx.h> #include <asm/system_misc.h> -#include <mach/hardware.h> +#include "hardware.h" +#include "iop3xx.h" void iop3xx_restart(enum reboot_mode mode, const char *cmd) { diff --git a/arch/arm/plat-iop/setup.c b/arch/arm/mach-iop32x/setup.c index d10e0102d82c..a0a81c28a632 100644 --- a/arch/arm/plat-iop/setup.c +++ b/arch/arm/mach-iop32x/setup.c @@ -10,7 +10,7 @@ #include <linux/mm.h> #include <linux/init.h> #include <asm/mach/map.h> -#include <asm/hardware/iop3xx.h> +#include "iop3xx.h" /* * Standard IO mapping for all IOP3xx based systems. Note that diff --git a/arch/arm/plat-iop/time.c b/arch/arm/mach-iop32x/time.c index f9dd1f50cfe5..18a4df5c1baa 100644 --- a/arch/arm/plat-iop/time.c +++ b/arch/arm/mach-iop32x/time.c @@ -19,12 +19,13 @@ #include <linux/clockchips.h> #include <linux/export.h> #include <linux/sched_clock.h> -#include <mach/hardware.h> #include <asm/irq.h> #include <linux/uaccess.h> #include <asm/mach/irq.h> #include <asm/mach/time.h> -#include <mach/time.h> + +#include "hardware.h" +#include "irqs.h" /* * Minimum clocksource/clockevent timer range in seconds @@ -167,7 +168,7 @@ void __init iop_init_time(unsigned long tick_rate) */ write_tmr0(timer_ctl & ~IOP_TMR_EN); write_tisr(1); - setup_irq(IRQ_IOP_TIMER0, &iop_timer_irq); + setup_irq(IRQ_IOP32X_TIMER0, &iop_timer_irq); iop_clockevent.cpumask = cpumask_of(0); clockevents_config_and_register(&iop_clockevent, tick_rate, 0xf, 0xfffffffe); diff --git a/arch/arm/mach-iop33x/Kconfig b/arch/arm/mach-iop33x/Kconfig deleted file mode 100644 index cd6069c7c568..000000000000 --- a/arch/arm/mach-iop33x/Kconfig +++ /dev/null @@ -1,22 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -if ARCH_IOP33X - -menu "IOP33x Implementation Options" - -comment "IOP33x Platform Types" - -config ARCH_IQ80331 - bool "Enable support for IQ80331" - help - Say Y here if you want to run your kernel on the Intel IQ80331 - evaluation kit for the IOP331 chipset. - -config MACH_IQ80332 - bool "Enable support for IQ80332" - help - Say Y here if you want to run your kernel on the Intel IQ80332 - evaluation kit for the IOP332 chipset. - -endmenu - -endif diff --git a/arch/arm/mach-iop33x/Makefile b/arch/arm/mach-iop33x/Makefile deleted file mode 100644 index 320ecde1f907..000000000000 --- a/arch/arm/mach-iop33x/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -# -# Makefile for the linux kernel. -# - -obj-y := irq.o uart.o - -obj-$(CONFIG_ARCH_IQ80331) += iq80331.o -obj-$(CONFIG_MACH_IQ80332) += iq80332.o diff --git a/arch/arm/mach-iop33x/Makefile.boot b/arch/arm/mach-iop33x/Makefile.boot deleted file mode 100644 index e4dd1d26038f..000000000000 --- a/arch/arm/mach-iop33x/Makefile.boot +++ /dev/null @@ -1,4 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - zreladdr-y += 0x00008000 -params_phys-y := 0x00000100 -initrd_phys-y := 0x00800000 diff --git a/arch/arm/mach-iop33x/include/mach/adma.h b/arch/arm/mach-iop33x/include/mach/adma.h deleted file mode 100644 index 8aa7159ab6d8..000000000000 --- a/arch/arm/mach-iop33x/include/mach/adma.h +++ /dev/null @@ -1,6 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef IOP33X_ADMA_H -#define IOP33X_ADMA_H -#include <asm/hardware/iop3xx-adma.h> -#endif - diff --git a/arch/arm/mach-iop33x/include/mach/entry-macro.S b/arch/arm/mach-iop33x/include/mach/entry-macro.S deleted file mode 100644 index 0a398fe1fba4..000000000000 --- a/arch/arm/mach-iop33x/include/mach/entry-macro.S +++ /dev/null @@ -1,34 +0,0 @@ -/* - * arch/arm/mach-iop33x/include/mach/entry-macro.S - * - * Low-level IRQ helper macros for IOP33x-based platforms - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ -#include <mach/iop33x.h> - - .macro get_irqnr_preamble, base, tmp - mrc p15, 0, \tmp, c15, c1, 0 - orr \tmp, \tmp, #(1 << 6) - mcr p15, 0, \tmp, c15, c1, 0 @ Enable cp6 access - mrc p15, 0, \tmp, c15, c1, 0 - mov \tmp, \tmp - sub pc, pc, #4 @ cp_wait - .endm - - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - mrc p6, 0, \irqstat, c14, c0, 0 @ Read IINTVEC - cmp \irqstat, #0 - mrceq p6, 0, \irqstat, c14, c0, 0 @ erratum 63 workaround - adds \irqnr, \irqstat, #1 - movne \irqnr, \irqstat, lsr #2 - .endm - - .macro arch_ret_to_user, tmp1, tmp2 - mrc p15, 0, \tmp1, c15, c1, 0 - ands \tmp2, \tmp1, #(1 << 6) - bicne \tmp1, \tmp1, #(1 << 6) - mcrne p15, 0, \tmp1, c15, c1, 0 @ Disable cp6 access - .endm diff --git a/arch/arm/mach-iop33x/include/mach/hardware.h b/arch/arm/mach-iop33x/include/mach/hardware.h deleted file mode 100644 index 020bafbc36a5..000000000000 --- a/arch/arm/mach-iop33x/include/mach/hardware.h +++ /dev/null @@ -1,44 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * arch/arm/mach-iop33x/include/mach/hardware.h - */ - -#ifndef __HARDWARE_H -#define __HARDWARE_H - -#include <asm/types.h> - -/* - * Note about PCI IO space mappings - * - * To make IO space accesses efficient, we store virtual addresses in - * the IO resources. - * - * The PCI IO space is located at virtual 0xfe000000 from physical - * 0x90000000. The PCI BARs must be programmed with physical addresses, - * but when we read them, we convert them to virtual addresses. See - * arch/arm/mach-iop3xx/iop3xx-pci.c - */ - -#ifndef __ASSEMBLY__ -void iop33x_init_irq(void); - -extern struct platform_device iop33x_uart0_device; -extern struct platform_device iop33x_uart1_device; -#endif - - -/* - * Generic chipset bits - * - */ -#include "iop33x.h" - -/* - * Board specific bits - */ -#include "iq80331.h" -#include "iq80332.h" - - -#endif diff --git a/arch/arm/mach-iop33x/include/mach/iop33x.h b/arch/arm/mach-iop33x/include/mach/iop33x.h deleted file mode 100644 index 0c7041ed7a60..000000000000 --- a/arch/arm/mach-iop33x/include/mach/iop33x.h +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * arch/arm/mach-iop33x/include/mach/iop33x.h - * - * Intel IOP33X Chip definitions - * - * Author: Dave Jiang (dave.jiang@intel.com) - * Copyright (C) 2003, 2004 Intel Corp. - */ - -#ifndef __IOP33X_H -#define __IOP33X_H - -/* - * Peripherals that are shared between the iop32x and iop33x but - * located at different addresses. - */ -#define IOP3XX_TIMER_REG(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07d0 + (reg)) - -#include <asm/hardware/iop3xx.h> - -/* UARTs */ -#define IOP33X_UART0_PHYS (IOP3XX_PERIPHERAL_PHYS_BASE + 0x1700) -#define IOP33X_UART0_VIRT (IOP3XX_PERIPHERAL_VIRT_BASE + 0x1700) -#define IOP33X_UART1_PHYS (IOP3XX_PERIPHERAL_PHYS_BASE + 0x1740) -#define IOP33X_UART1_VIRT (IOP3XX_PERIPHERAL_VIRT_BASE + 0x1740) - -/* ATU Parameters - * set up a 1:1 bus to physical ram relationship - * w/ pci on top of physical ram in memory map - */ -#define IOP33X_MAX_RAM_SIZE 0x80000000UL -#define IOP3XX_MAX_RAM_SIZE IOP33X_MAX_RAM_SIZE -#define IOP3XX_PCI_LOWER_MEM_BA (PHYS_OFFSET + IOP33X_MAX_RAM_SIZE) - - -#endif diff --git a/arch/arm/mach-iop33x/include/mach/iq80331.h b/arch/arm/mach-iop33x/include/mach/iq80331.h deleted file mode 100644 index c7e68d863e44..000000000000 --- a/arch/arm/mach-iop33x/include/mach/iq80331.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * arch/arm/mach-iop33x/include/mach/iq80331.h - * - * Intel IQ80331 evaluation board registers - */ - -#ifndef __IQ80331_H -#define __IQ80331_H - -#define IQ80331_7SEG_1 0xce840000 /* 7-Segment MSB */ -#define IQ80331_7SEG_0 0xce850000 /* 7-Segment LSB (WO) */ -#define IQ80331_ROTARY_SW 0xce8d0000 /* Rotary Switch */ -#define IQ80331_BATT_STAT 0xce8f0000 /* Battery Status */ - - -#endif diff --git a/arch/arm/mach-iop33x/include/mach/iq80332.h b/arch/arm/mach-iop33x/include/mach/iq80332.h deleted file mode 100644 index 749b44bf7f62..000000000000 --- a/arch/arm/mach-iop33x/include/mach/iq80332.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * arch/arm/mach-iop33x/include/mach/iq80332.h - * - * Intel IQ80332 evaluation board registers - */ - -#ifndef __IQ80332_H -#define __IQ80332_H - -#define IQ80332_7SEG_1 0xce840000 /* 7-Segment MSB */ -#define IQ80332_7SEG_0 0xce850000 /* 7-Segment LSB (WO) */ -#define IQ80332_ROTARY_SW 0xce8d0000 /* Rotary Switch */ -#define IQ80332_BATT_STAT 0xce8f0000 /* Battery Status */ - - -#endif diff --git a/arch/arm/mach-iop33x/include/mach/irqs.h b/arch/arm/mach-iop33x/include/mach/irqs.h deleted file mode 100644 index cc3dce0ad4a1..000000000000 --- a/arch/arm/mach-iop33x/include/mach/irqs.h +++ /dev/null @@ -1,57 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * arch/arm/mach-iop33x/include/mach/irqs.h - * - * Author: Dave Jiang (dave.jiang@intel.com) - * Copyright: (C) 2003 Intel Corp. - */ - -#ifndef __IRQS_H -#define __IRQS_H - -/* - * IOP80331 chipset interrupts - */ -#define IRQ_IOP33X_DMA0_EOT 0 -#define IRQ_IOP33X_DMA0_EOC 1 -#define IRQ_IOP33X_DMA1_EOT 2 -#define IRQ_IOP33X_DMA1_EOC 3 -#define IRQ_IOP33X_AA_EOT 6 -#define IRQ_IOP33X_AA_EOC 7 -#define IRQ_IOP33X_TIMER0 8 -#define IRQ_IOP33X_TIMER1 9 -#define IRQ_IOP33X_I2C_0 10 -#define IRQ_IOP33X_I2C_1 11 -#define IRQ_IOP33X_MSG 12 -#define IRQ_IOP33X_MSGIBQ 13 -#define IRQ_IOP33X_ATU_BIST 14 -#define IRQ_IOP33X_PERFMON 15 -#define IRQ_IOP33X_CORE_PMU 16 -#define IRQ_IOP33X_XINT0 24 -#define IRQ_IOP33X_XINT1 25 -#define IRQ_IOP33X_XINT2 26 -#define IRQ_IOP33X_XINT3 27 -#define IRQ_IOP33X_XINT8 32 -#define IRQ_IOP33X_XINT9 33 -#define IRQ_IOP33X_XINT10 34 -#define IRQ_IOP33X_XINT11 35 -#define IRQ_IOP33X_XINT12 36 -#define IRQ_IOP33X_XINT13 37 -#define IRQ_IOP33X_XINT14 38 -#define IRQ_IOP33X_XINT15 39 -#define IRQ_IOP33X_UART0 51 -#define IRQ_IOP33X_UART1 52 -#define IRQ_IOP33X_PBIE 53 -#define IRQ_IOP33X_ATU_CRW 54 -#define IRQ_IOP33X_ATU_ERR 55 -#define IRQ_IOP33X_MCU_ERR 56 -#define IRQ_IOP33X_DMA0_ERR 57 -#define IRQ_IOP33X_DMA1_ERR 58 -#define IRQ_IOP33X_AA_ERR 60 -#define IRQ_IOP33X_MSG_ERR 62 -#define IRQ_IOP33X_HPI 63 - -#define NR_IRQS 64 - - -#endif diff --git a/arch/arm/mach-iop33x/include/mach/time.h b/arch/arm/mach-iop33x/include/mach/time.h deleted file mode 100644 index 801f8fd644ad..000000000000 --- a/arch/arm/mach-iop33x/include/mach/time.h +++ /dev/null @@ -1,5 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _IOP33X_TIME_H_ -#define _IOP33X_TIME_H_ -#define IRQ_IOP_TIMER0 IRQ_IOP33X_TIMER0 -#endif diff --git a/arch/arm/mach-iop33x/include/mach/uncompress.h b/arch/arm/mach-iop33x/include/mach/uncompress.h deleted file mode 100644 index 62b71cde1f79..000000000000 --- a/arch/arm/mach-iop33x/include/mach/uncompress.h +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * arch/arm/mach-iop33x/include/mach/uncompress.h - */ - -#include <asm/types.h> -#include <asm/mach-types.h> -#include <linux/serial_reg.h> -#include <mach/hardware.h> - -volatile u32 *uart_base; - -#define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE) - -static inline void putc(char c) -{ - while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE) - barrier(); - uart_base[UART_TX] = c; -} - -static inline void flush(void) -{ -} - -static __inline__ void __arch_decomp_setup(unsigned long arch_id) -{ - if (machine_is_iq80331() || machine_is_iq80332()) - uart_base = (volatile u32 *)IOP33X_UART0_PHYS; - else - uart_base = (volatile u32 *)0xfe800000; -} - -/* - * nothing to do - */ -#define arch_decomp_setup() __arch_decomp_setup(arch_id) diff --git a/arch/arm/mach-iop33x/iq80331.c b/arch/arm/mach-iop33x/iq80331.c deleted file mode 100644 index ab74fbabc749..000000000000 --- a/arch/arm/mach-iop33x/iq80331.c +++ /dev/null @@ -1,148 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * arch/arm/mach-iop33x/iq80331.c - * - * Board support code for the Intel IQ80331 platform. - * - * Author: Dave Jiang <dave.jiang@intel.com> - * Copyright (C) 2003 Intel Corp. - */ - -#include <linux/mm.h> -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/pci.h> -#include <linux/string.h> -#include <linux/serial_core.h> -#include <linux/serial_8250.h> -#include <linux/mtd/physmap.h> -#include <linux/platform_device.h> -#include <linux/io.h> -#include <mach/hardware.h> -#include <asm/irq.h> -#include <asm/mach/arch.h> -#include <asm/mach/map.h> -#include <asm/mach/pci.h> -#include <asm/mach/time.h> -#include <asm/mach-types.h> -#include <asm/page.h> -#include <asm/pgtable.h> -#include <mach/time.h> - -/* - * IQ80331 timer tick configuration. - */ -static void __init iq80331_timer_init(void) -{ - /* D-Step parts run at a higher internal bus frequency */ - if (*IOP3XX_ATURID >= 0xa) - iop_init_time(333000000); - else - iop_init_time(266000000); -} - - -/* - * IQ80331 PCI. - */ -static int __init -iq80331_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - int irq; - - if (slot == 1 && pin == 1) { - /* PCI-X Slot INTA */ - irq = IRQ_IOP33X_XINT1; - } else if (slot == 1 && pin == 2) { - /* PCI-X Slot INTB */ - irq = IRQ_IOP33X_XINT2; - } else if (slot == 1 && pin == 3) { - /* PCI-X Slot INTC */ - irq = IRQ_IOP33X_XINT3; - } else if (slot == 1 && pin == 4) { - /* PCI-X Slot INTD */ - irq = IRQ_IOP33X_XINT0; - } else if (slot == 2) { - /* GigE */ - irq = IRQ_IOP33X_XINT2; - } else { - printk(KERN_ERR "iq80331_pci_map_irq() called for unknown " - "device PCI:%d:%d:%d\n", dev->bus->number, - PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn)); - irq = -1; - } - - return irq; -} - -static struct hw_pci iq80331_pci __initdata = { - .nr_controllers = 1, - .ops = &iop3xx_ops, - .setup = iop3xx_pci_setup, - .preinit = iop3xx_pci_preinit_cond, - .map_irq = iq80331_pci_map_irq, -}; - -static int __init iq80331_pci_init(void) -{ - if ((iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) && - machine_is_iq80331()) - pci_common_init(&iq80331_pci); - - return 0; -} - -subsys_initcall(iq80331_pci_init); - - -/* - * IQ80331 machine initialisation. - */ -static struct physmap_flash_data iq80331_flash_data = { - .width = 1, -}; - -static struct resource iq80331_flash_resource = { - .start = 0xc0000000, - .end = 0xc07fffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device iq80331_flash_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &iq80331_flash_data, - }, - .num_resources = 1, - .resource = &iq80331_flash_resource, -}; - -static struct resource iq80331_gpio_res[] = { - DEFINE_RES_MEM((IOP3XX_PERIPHERAL_PHYS_BASE + 0x1780), 0x10), -}; - -static void __init iq80331_init_machine(void) -{ - platform_device_register_simple("gpio-iop", 0, - iq80331_gpio_res, - ARRAY_SIZE(iq80331_gpio_res)); - platform_device_register(&iop3xx_i2c0_device); - platform_device_register(&iop3xx_i2c1_device); - platform_device_register(&iop33x_uart0_device); - platform_device_register(&iop33x_uart1_device); - platform_device_register(&iq80331_flash_device); - platform_device_register(&iop3xx_dma_0_channel); - platform_device_register(&iop3xx_dma_1_channel); - platform_device_register(&iop3xx_aau_channel); -} - -MACHINE_START(IQ80331, "Intel IQ80331") - /* Maintainer: Intel Corp. */ - .atag_offset = 0x100, - .map_io = iop3xx_map_io, - .init_irq = iop33x_init_irq, - .init_time = iq80331_timer_init, - .init_machine = iq80331_init_machine, - .restart = iop3xx_restart, -MACHINE_END diff --git a/arch/arm/mach-iop33x/iq80332.c b/arch/arm/mach-iop33x/iq80332.c deleted file mode 100644 index 2e309b197aa4..000000000000 --- a/arch/arm/mach-iop33x/iq80332.c +++ /dev/null @@ -1,148 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * arch/arm/mach-iop33x/iq80332.c - * - * Board support code for the Intel IQ80332 platform. - * - * Author: Dave Jiang <dave.jiang@intel.com> - * Copyright (C) 2004 Intel Corp. - */ - -#include <linux/mm.h> -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/pci.h> -#include <linux/string.h> -#include <linux/serial_core.h> -#include <linux/serial_8250.h> -#include <linux/mtd/physmap.h> -#include <linux/platform_device.h> -#include <linux/io.h> -#include <mach/hardware.h> -#include <asm/irq.h> -#include <asm/mach/arch.h> -#include <asm/mach/map.h> -#include <asm/mach/pci.h> -#include <asm/mach/time.h> -#include <asm/mach-types.h> -#include <asm/page.h> -#include <asm/pgtable.h> -#include <mach/time.h> - -/* - * IQ80332 timer tick configuration. - */ -static void __init iq80332_timer_init(void) -{ - /* D-Step parts and the iop333 run at a higher internal bus frequency */ - if (*IOP3XX_ATURID >= 0xa || *IOP3XX_ATUDID == 0x374) - iop_init_time(333000000); - else - iop_init_time(266000000); -} - - -/* - * IQ80332 PCI. - */ -static int __init -iq80332_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - int irq; - - if (slot == 4 && pin == 1) { - /* PCI-X Slot INTA */ - irq = IRQ_IOP33X_XINT0; - } else if (slot == 4 && pin == 2) { - /* PCI-X Slot INTB */ - irq = IRQ_IOP33X_XINT1; - } else if (slot == 4 && pin == 3) { - /* PCI-X Slot INTC */ - irq = IRQ_IOP33X_XINT2; - } else if (slot == 4 && pin == 4) { - /* PCI-X Slot INTD */ - irq = IRQ_IOP33X_XINT3; - } else if (slot == 6) { - /* GigE */ - irq = IRQ_IOP33X_XINT2; - } else { - printk(KERN_ERR "iq80332_pci_map_irq() called for unknown " - "device PCI:%d:%d:%d\n", dev->bus->number, - PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn)); - irq = -1; - } - - return irq; -} - -static struct hw_pci iq80332_pci __initdata = { - .nr_controllers = 1, - .ops = &iop3xx_ops, - .setup = iop3xx_pci_setup, - .preinit = iop3xx_pci_preinit_cond, - .map_irq = iq80332_pci_map_irq, -}; - -static int __init iq80332_pci_init(void) -{ - if ((iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) && - machine_is_iq80332()) - pci_common_init(&iq80332_pci); - - return 0; -} - -subsys_initcall(iq80332_pci_init); - - -/* - * IQ80332 machine initialisation. - */ -static struct physmap_flash_data iq80332_flash_data = { - .width = 1, -}; - -static struct resource iq80332_flash_resource = { - .start = 0xc0000000, - .end = 0xc07fffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device iq80332_flash_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &iq80332_flash_data, - }, - .num_resources = 1, - .resource = &iq80332_flash_resource, -}; - -static struct resource iq80332_gpio_res[] = { - DEFINE_RES_MEM((IOP3XX_PERIPHERAL_PHYS_BASE + 0x1780), 0x10), -}; - -static void __init iq80332_init_machine(void) -{ - platform_device_register_simple("gpio-iop", 0, - iq80332_gpio_res, - ARRAY_SIZE(iq80332_gpio_res)); - platform_device_register(&iop3xx_i2c0_device); - platform_device_register(&iop3xx_i2c1_device); - platform_device_register(&iop33x_uart0_device); - platform_device_register(&iop33x_uart1_device); - platform_device_register(&iq80332_flash_device); - platform_device_register(&iop3xx_dma_0_channel); - platform_device_register(&iop3xx_dma_1_channel); - platform_device_register(&iop3xx_aau_channel); -} - -MACHINE_START(IQ80332, "Intel IQ80332") - /* Maintainer: Intel Corp. */ - .atag_offset = 0x100, - .map_io = iop3xx_map_io, - .init_irq = iop33x_init_irq, - .init_time = iq80332_timer_init, - .init_machine = iq80332_init_machine, - .restart = iop3xx_restart, -MACHINE_END diff --git a/arch/arm/mach-iop33x/irq.c b/arch/arm/mach-iop33x/irq.c deleted file mode 100644 index 03ad7d3a8f49..000000000000 --- a/arch/arm/mach-iop33x/irq.c +++ /dev/null @@ -1,115 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * arch/arm/mach-iop33x/irq.c - * - * Generic IOP331 IRQ handling functionality - * - * Author: Dave Jiang <dave.jiang@intel.com> - * Copyright (C) 2003 Intel Corp. - */ - -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/list.h> -#include <asm/mach/irq.h> -#include <asm/irq.h> -#include <mach/hardware.h> -#include <asm/mach-types.h> - -static u32 iop33x_mask0; -static u32 iop33x_mask1; - -static void intctl0_write(u32 val) -{ - asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val)); -} - -static void intctl1_write(u32 val) -{ - asm volatile("mcr p6, 0, %0, c1, c0, 0" : : "r" (val)); -} - -static void intstr0_write(u32 val) -{ - asm volatile("mcr p6, 0, %0, c2, c0, 0" : : "r" (val)); -} - -static void intstr1_write(u32 val) -{ - asm volatile("mcr p6, 0, %0, c3, c0, 0" : : "r" (val)); -} - -static void intbase_write(u32 val) -{ - asm volatile("mcr p6, 0, %0, c12, c0, 0" : : "r" (val)); -} - -static void intsize_write(u32 val) -{ - asm volatile("mcr p6, 0, %0, c13, c0, 0" : : "r" (val)); -} - -static void -iop33x_irq_mask1 (struct irq_data *d) -{ - iop33x_mask0 &= ~(1 << d->irq); - intctl0_write(iop33x_mask0); -} - -static void -iop33x_irq_mask2 (struct irq_data *d) -{ - iop33x_mask1 &= ~(1 << (d->irq - 32)); - intctl1_write(iop33x_mask1); -} - -static void -iop33x_irq_unmask1(struct irq_data *d) -{ - iop33x_mask0 |= 1 << d->irq; - intctl0_write(iop33x_mask0); -} - -static void -iop33x_irq_unmask2(struct irq_data *d) -{ - iop33x_mask1 |= (1 << (d->irq - 32)); - intctl1_write(iop33x_mask1); -} - -struct irq_chip iop33x_irqchip1 = { - .name = "IOP33x-1", - .irq_ack = iop33x_irq_mask1, - .irq_mask = iop33x_irq_mask1, - .irq_unmask = iop33x_irq_unmask1, -}; - -struct irq_chip iop33x_irqchip2 = { - .name = "IOP33x-2", - .irq_ack = iop33x_irq_mask2, - .irq_mask = iop33x_irq_mask2, - .irq_unmask = iop33x_irq_unmask2, -}; - -void __init iop33x_init_irq(void) -{ - int i; - - iop_init_cp6_handler(); - - intctl0_write(0); - intctl1_write(0); - intstr0_write(0); - intstr1_write(0); - intbase_write(0); - intsize_write(1); - if (machine_is_iq80331()) - *IOP3XX_PCIIRSR = 0x0f; - - for (i = 0; i < NR_IRQS; i++) { - irq_set_chip_and_handler(i, - (i < 32) ? &iop33x_irqchip1 : &iop33x_irqchip2, - handle_level_irq); - irq_clear_status_flags(i, IRQ_NOREQUEST | IRQ_NOPROBE); - } -} diff --git a/arch/arm/mach-iop33x/uart.c b/arch/arm/mach-iop33x/uart.c deleted file mode 100644 index 8fa079d2e3c3..000000000000 --- a/arch/arm/mach-iop33x/uart.c +++ /dev/null @@ -1,100 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * arch/arm/mach-iop33x/uart.c - * - * Author: Dave Jiang (dave.jiang@intel.com) - * Copyright (C) 2004 Intel Corporation. - */ - -#include <linux/mm.h> -#include <linux/init.h> -#include <linux/major.h> -#include <linux/fs.h> -#include <linux/platform_device.h> -#include <linux/serial.h> -#include <linux/tty.h> -#include <linux/serial_8250.h> -#include <linux/io.h> -#include <asm/pgtable.h> -#include <asm/page.h> -#include <asm/mach/map.h> -#include <asm/setup.h> -#include <asm/memory.h> -#include <mach/hardware.h> -#include <asm/hardware/iop3xx.h> -#include <asm/mach/arch.h> - -#define IOP33X_UART_XTAL 33334000 - -static struct plat_serial8250_port iop33x_uart0_data[] = { - { - .membase = (char *)IOP33X_UART0_VIRT, - .mapbase = IOP33X_UART0_PHYS, - .irq = IRQ_IOP33X_UART0, - .uartclk = IOP33X_UART_XTAL, - .regshift = 2, - .iotype = UPIO_MEM, - .flags = UPF_SKIP_TEST, - }, - { }, -}; - -static struct resource iop33x_uart0_resources[] = { - [0] = { - .start = IOP33X_UART0_PHYS, - .end = IOP33X_UART0_PHYS + 0x3f, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_IOP33X_UART0, - .end = IRQ_IOP33X_UART0, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device iop33x_uart0_device = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = iop33x_uart0_data, - }, - .num_resources = 2, - .resource = iop33x_uart0_resources, -}; - - -static struct resource iop33x_uart1_resources[] = { - [0] = { - .start = IOP33X_UART1_PHYS, - .end = IOP33X_UART1_PHYS + 0x3f, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_IOP33X_UART1, - .end = IRQ_IOP33X_UART1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct plat_serial8250_port iop33x_uart1_data[] = { - { - .membase = (char *)IOP33X_UART1_VIRT, - .mapbase = IOP33X_UART1_PHYS, - .irq = IRQ_IOP33X_UART1, - .uartclk = IOP33X_UART_XTAL, - .regshift = 2, - .iotype = UPIO_MEM, - .flags = UPF_SKIP_TEST, - }, - { }, -}; - -struct platform_device iop33x_uart1_device = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM1, - .dev = { - .platform_data = iop33x_uart1_data, - }, - .num_resources = 2, - .resource = iop33x_uart1_resources, -}; diff --git a/arch/arm/mach-ks8695/Kconfig b/arch/arm/mach-ks8695/Kconfig deleted file mode 100644 index 724d7d039f74..000000000000 --- a/arch/arm/mach-ks8695/Kconfig +++ /dev/null @@ -1,88 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -if ARCH_KS8695 - -menu "Kendin/Micrel KS8695 Implementations" - -config MACH_KS8695 - bool "KS8695 development board" - select HAVE_PCI - help - Say 'Y' here if you want your kernel to run on the original - Kendin-Micrel KS8695 development board. - -config MACH_DSM320 - bool "DSM-320 Wireless Media Player" - help - Say 'Y' here if you want your kernel to run on the D-Link - DSM-320 Wireless Media Player. - -config MACH_ACS5K - bool "Brivo Systems LLC, ACS-5000 Master board" - help - say 'Y' here if you want your kernel to run on the Brivo - Systems LLC, ACS-5000 Master board. - -config MACH_LITE300 - bool "SecureComputing SG300" - help - Say 'Y' here if you want your kernel to support the - SecureComputing / SnapGear SG300 VPN Internet Router. - See http://www.securecomputing.com for more details. - -config MACH_SG310 - bool "McAfee SG310" - help - Say 'Y' here if you want your kernel to support the - McAfee / SnapGear SG310 VPN Internet Router. - See http://www.mcafee.com for more details. - -config MACH_SE4200 - bool "SecureComputing SE4200" - help - Say 'Y' here if you want your kernel to support the - SecureComputing / SnapGear SE4200 Secure Wireless VPN - Internet Router. - See http://www.securecomputing.com for more details. - -config MACH_CM4002 - bool "OpenGear CM4002" - help - Say 'Y' here if you want your kernel to support the OpenGear - CM4002 Secure Access Server. See http://www.opengear.com for - more details. - -config MACH_CM4008 - bool "OpenGear CM4008" - select HAVE_PCI - help - Say 'Y' here if you want your kernel to support the OpenGear - CM4008 Console Server. See http://www.opengear.com for more - details. - -config MACH_CM41xx - bool "OpenGear CM41xx" - select HAVE_PCI - help - Say 'Y' here if you want your kernel to support the OpenGear - CM4016 or CM4048 Console Servers. See http://www.opengear.com for - more details. - -config MACH_IM4004 - bool "OpenGear IM4004" - select HAVE_PCI - help - Say 'Y' here if you want your kernel to support the OpenGear - IM4004 Secure Access Server. See http://www.opengear.com for - more details. - -config MACH_IM42xx - bool "OpenGear IM42xx" - select HAVE_PCI - help - Say 'Y' here if you want your kernel to support the OpenGear - IM4216 or IM4248 Console Servers. See http://www.opengear.com for - more details. - -endmenu - -endif diff --git a/arch/arm/mach-ks8695/Makefile b/arch/arm/mach-ks8695/Makefile deleted file mode 100644 index 439b22255a32..000000000000 --- a/arch/arm/mach-ks8695/Makefile +++ /dev/null @@ -1,23 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# arch/arm/mach-ks8695/Makefile -# -# Makefile for KS8695 architecture support -# - -obj-y := cpu.o irq.o time.o devices.o - -# PCI support is optional -obj-$(CONFIG_PCI) += pci.o - -# Board-specific support -obj-$(CONFIG_MACH_KS8695) += board-micrel.o -obj-$(CONFIG_MACH_DSM320) += board-dsm320.o -obj-$(CONFIG_MACH_ACS5K) += board-acs5k.o -obj-$(CONFIG_MACH_LITE300) += board-sg.o -obj-$(CONFIG_MACH_SG310) += board-sg.o -obj-$(CONFIG_MACH_SE4200) += board-sg.o -obj-$(CONFIG_MACH_CM4002) += board-og.o -obj-$(CONFIG_MACH_CM4008) += board-og.o -obj-$(CONFIG_MACH_CM41xx) += board-og.o -obj-$(CONFIG_MACH_IM4004) += board-og.o -obj-$(CONFIG_MACH_IM42xx) += board-og.o diff --git a/arch/arm/mach-ks8695/Makefile.boot b/arch/arm/mach-ks8695/Makefile.boot deleted file mode 100644 index cf32eb605bd8..000000000000 --- a/arch/arm/mach-ks8695/Makefile.boot +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -# Note: the following conditions must always be true: -# ZRELADDR == virt_to_phys(TEXTADDR) -# PARAMS_PHYS must be within 4MB of ZRELADDR -# INITRD_PHYS must be in RAM - - zreladdr-y += 0x00008000 -params_phys-y := 0x00000100 -initrd_phys-y := 0x00800000 diff --git a/arch/arm/mach-ks8695/board-acs5k.c b/arch/arm/mach-ks8695/board-acs5k.c deleted file mode 100644 index f319258d1226..000000000000 --- a/arch/arm/mach-ks8695/board-acs5k.c +++ /dev/null @@ -1,238 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * arch/arm/mach-ks8695/board-acs5k.c - * - * Brivo Systems LLC, ACS-5000 Master Board - * - * Copyright 2008 Simtec Electronics - * Daniel Silverstone <dsilvers@simtec.co.uk> - */ -#include <linux/gpio.h> -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/interrupt.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/gpio/machine.h> -#include <linux/i2c.h> -#include <linux/i2c-algo-bit.h> -#include <linux/platform_data/i2c-gpio.h> -#include <linux/platform_data/pca953x.h> - -#include <linux/mtd/mtd.h> -#include <linux/mtd/map.h> -#include <linux/mtd/physmap.h> -#include <linux/mtd/partitions.h> - -#include <asm/mach-types.h> - -#include <asm/mach/arch.h> -#include <asm/mach/map.h> -#include <asm/mach/irq.h> - -#include "devices.h" -#include <mach/gpio-ks8695.h> - -#include "generic.h" - -static struct gpiod_lookup_table acs5k_i2c_gpiod_table = { - .dev_id = "i2c-gpio", - .table = { - GPIO_LOOKUP_IDX("KS8695", 4, NULL, 0, - GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN), - GPIO_LOOKUP_IDX("KS8695", 5, NULL, 1, - GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN), - }, -}; - -static struct i2c_gpio_platform_data acs5k_i2c_device_platdata = { - .udelay = 10, -}; - -static struct platform_device acs5k_i2c_device = { - .name = "i2c-gpio", - .id = -1, - .num_resources = 0, - .resource = NULL, - .dev = { - .platform_data = &acs5k_i2c_device_platdata, - }, -}; - -static int acs5k_pca9555_setup(struct i2c_client *client, - unsigned gpio_base, unsigned ngpio, - void *context) -{ - static int acs5k_gpio_value[] = { - -1, -1, -1, -1, -1, -1, -1, 0, 1, 1, -1, 0, 1, 0, -1, -1 - }; - int n; - - for (n = 0; n < ARRAY_SIZE(acs5k_gpio_value); ++n) { - gpio_request(gpio_base + n, "ACS-5000 GPIO Expander"); - if (acs5k_gpio_value[n] < 0) - gpio_direction_input(gpio_base + n); - else - gpio_direction_output(gpio_base + n, - acs5k_gpio_value[n]); - gpio_export(gpio_base + n, 0); /* Export, direction locked down */ - } - - return 0; -} - -static struct pca953x_platform_data acs5k_i2c_pca9555_platdata = { - .gpio_base = 16, /* Start directly after the CPU's GPIO */ - .invert = 0, /* Do not invert */ - .setup = acs5k_pca9555_setup, -}; - -static struct i2c_board_info acs5k_i2c_devs[] __initdata = { - { - I2C_BOARD_INFO("pcf8563", 0x51), - }, - { - I2C_BOARD_INFO("pca9555", 0x20), - .platform_data = &acs5k_i2c_pca9555_platdata, - }, -}; - -static void __init acs5k_i2c_init(void) -{ - /* The gpio interface */ - gpiod_add_lookup_table(&acs5k_i2c_gpiod_table); - platform_device_register(&acs5k_i2c_device); - /* I2C devices */ - i2c_register_board_info(0, acs5k_i2c_devs, - ARRAY_SIZE(acs5k_i2c_devs)); -} - -static struct mtd_partition acs5k_nor_partitions[] = { - [0] = { - .name = "Boot Agent and config", - .size = SZ_256K, - .offset = 0, - .mask_flags = MTD_WRITEABLE, - }, - [1] = { - .name = "Kernel", - .size = SZ_1M, - .offset = SZ_256K, - }, - [2] = { - .name = "SquashFS1", - .size = SZ_2M, - .offset = SZ_256K + SZ_1M, - }, - [3] = { - .name = "SquashFS2", - .size = SZ_4M + SZ_2M, - .offset = SZ_256K + SZ_1M + SZ_2M, - }, - [4] = { - .name = "Data", - .size = SZ_16M + SZ_4M + SZ_2M + SZ_512K, /* 22.5 MB */ - .offset = SZ_256K + SZ_8M + SZ_1M, - } -}; - -static struct physmap_flash_data acs5k_nor_pdata = { - .width = 4, - .nr_parts = ARRAY_SIZE(acs5k_nor_partitions), - .parts = acs5k_nor_partitions, -}; - -static struct resource acs5k_nor_resource[] = { - [0] = { - .start = SZ_32M, /* We expect the bootloader to map - * the flash here. - */ - .end = SZ_32M + SZ_16M - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = SZ_32M + SZ_16M, - .end = SZ_32M + SZ_32M - SZ_256K - 1, - .flags = IORESOURCE_MEM, - } -}; - -static struct platform_device acs5k_device_nor = { - .name = "physmap-flash", - .id = -1, - .num_resources = ARRAY_SIZE(acs5k_nor_resource), - .resource = acs5k_nor_resource, - .dev = { - .platform_data = &acs5k_nor_pdata, - }, -}; - -static void __init acs5k_register_nor(void) -{ - int ret; - - if (acs5k_nor_partitions[0].mask_flags == 0) - printk(KERN_WARNING "Warning: Unprotecting bootloader and configuration partition\n"); - - ret = platform_device_register(&acs5k_device_nor); - if (ret < 0) - printk(KERN_ERR "failed to register physmap-flash device\n"); -} - -static int __init acs5k_protection_setup(char *s) -{ - /* We can't allocate anything here but we should be able - * to trivially parse s and decide if we can protect the - * bootloader partition or not - */ - if (strcmp(s, "no") == 0) - acs5k_nor_partitions[0].mask_flags = 0; - - return 1; -} - -__setup("protect_bootloader=", acs5k_protection_setup); - -static void __init acs5k_init_gpio(void) -{ - int i; - - ks8695_register_gpios(); - for (i = 0; i < 4; ++i) - gpio_request(i, "ACS5K IRQ"); - gpio_request(7, "ACS5K KS_FRDY"); - for (i = 8; i < 16; ++i) - gpio_request(i, "ACS5K Unused"); - - gpio_request(3, "ACS5K CAN Control"); - gpio_request(6, "ACS5K Heartbeat"); - gpio_direction_output(3, 1); /* Default CAN_RESET high */ - gpio_direction_output(6, 0); /* Default KS8695_ACTIVE low */ - gpio_export(3, 0); /* export CAN_RESET as output only */ - gpio_export(6, 0); /* export KS8695_ACTIVE as output only */ -} - -static void __init acs5k_init(void) -{ - acs5k_init_gpio(); - - /* Network device */ - ks8695_add_device_lan(); /* eth0 = LAN */ - ks8695_add_device_wan(); /* ethX = WAN */ - - /* NOR devices */ - acs5k_register_nor(); - - /* I2C bus */ - acs5k_i2c_init(); -} - -MACHINE_START(ACS5K, "Brivo Systems LLC ACS-5000 Master board") - /* Maintainer: Simtec Electronics. */ - .atag_offset = 0x100, - .map_io = ks8695_map_io, - .init_irq = ks8695_init_irq, - .init_machine = acs5k_init, - .init_time = ks8695_timer_init, - .restart = ks8695_restart, -MACHINE_END diff --git a/arch/arm/mach-ks8695/board-dsm320.c b/arch/arm/mach-ks8695/board-dsm320.c deleted file mode 100644 index d5f435cae6e0..000000000000 --- a/arch/arm/mach-ks8695/board-dsm320.c +++ /dev/null @@ -1,127 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * arch/arm/mach-ks8695/board-dsm320.c - * - * DSM-320 D-Link Wireless Media Player, board support. - * - * Copyright 2008 Simtec Electronics - * Daniel Silverstone <dsilvers@simtec.co.uk> - */ -#include <linux/gpio.h> -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/interrupt.h> -#include <linux/init.h> -#include <linux/platform_device.h> - -#include <linux/mtd/mtd.h> -#include <linux/mtd/map.h> -#include <linux/mtd/physmap.h> -#include <linux/mtd/partitions.h> - -#include <asm/mach-types.h> - -#include <asm/mach/arch.h> -#include <asm/mach/map.h> -#include <asm/mach/irq.h> - -#include "devices.h" -#include <mach/gpio-ks8695.h> - -#include "generic.h" - -#ifdef CONFIG_PCI -static int dsm320_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - switch (slot) { - case 0: - /* PCI-AHB bridge? */ - return KS8695_IRQ_EXTERN0; - case 18: - /* Mini PCI slot */ - return KS8695_IRQ_EXTERN2; - case 20: - /* RealMAGIC chip */ - return KS8695_IRQ_EXTERN0; - } - BUG(); -} - -static struct ks8695_pci_cfg __initdata dsm320_pci = { - .mode = KS8695_MODE_MINIPCI, - .map_irq = dsm320_pci_map_irq, -}; - -static void __init dsm320_register_pci(void) -{ - /* Initialise the GPIO lines for interrupt mode */ - /* RealMAGIC */ - ks8695_gpio_interrupt(KS8695_GPIO_0, IRQ_TYPE_LEVEL_LOW); - /* MiniPCI Slot */ - ks8695_gpio_interrupt(KS8695_GPIO_2, IRQ_TYPE_LEVEL_LOW); - - ks8695_init_pci(&dsm320_pci); -} - -#else -static inline void __init dsm320_register_pci(void) { } -#endif - -static struct physmap_flash_data dsm320_nor_pdata = { - .width = 4, - .nr_parts = 0, -}; - -static struct resource dsm320_nor_resource[] = { - [0] = { - .start = SZ_32M, /* We expect the bootloader to map - * the flash here. - */ - .end = SZ_32M + SZ_4M - 1, - .flags = IORESOURCE_MEM, - } -}; - -static struct platform_device dsm320_device_nor = { - .name = "physmap-flash", - .id = -1, - .num_resources = ARRAY_SIZE(dsm320_nor_resource), - .resource = dsm320_nor_resource, - .dev = { - .platform_data = &dsm320_nor_pdata, - }, -}; - -void __init dsm320_register_nor(void) -{ - int ret; - - ret = platform_device_register(&dsm320_device_nor); - if (ret < 0) - printk(KERN_ERR "failed to register physmap-flash device\n"); -} - -static void __init dsm320_init(void) -{ - /* GPIO registration */ - ks8695_register_gpios(); - - /* PCI registration */ - dsm320_register_pci(); - - /* Network device */ - ks8695_add_device_lan(); /* eth0 = LAN */ - - /* NOR devices */ - dsm320_register_nor(); -} - -MACHINE_START(DSM320, "D-Link DSM-320 Wireless Media Player") - /* Maintainer: Simtec Electronics. */ - .atag_offset = 0x100, - .map_io = ks8695_map_io, - .init_irq = ks8695_init_irq, - .init_machine = dsm320_init, - .init_time = ks8695_timer_init, - .restart = ks8695_restart, -MACHINE_END diff --git a/arch/arm/mach-ks8695/board-micrel.c b/arch/arm/mach-ks8695/board-micrel.c deleted file mode 100644 index bf8856ce3fbb..000000000000 --- a/arch/arm/mach-ks8695/board-micrel.c +++ /dev/null @@ -1,59 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * arch/arm/mach-ks8695/board-micrel.c - */ -#include <linux/gpio.h> -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/interrupt.h> -#include <linux/init.h> -#include <linux/platform_device.h> - -#include <asm/mach-types.h> - -#include <asm/mach/arch.h> -#include <asm/mach/map.h> -#include <asm/mach/irq.h> - -#include <mach/gpio-ks8695.h> -#include "devices.h" - -#include "generic.h" - -#ifdef CONFIG_PCI -static int micrel_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - return KS8695_IRQ_EXTERN0; -} - -static struct ks8695_pci_cfg __initdata micrel_pci = { - .mode = KS8695_MODE_MINIPCI, - .map_irq = micrel_pci_map_irq, -}; -#endif - - -static void __init micrel_init(void) -{ - printk(KERN_INFO "Micrel KS8695 Development Board initializing\n"); - - ks8695_register_gpios(); - -#ifdef CONFIG_PCI - ks8695_init_pci(&micrel_pci); -#endif - - /* Add devices */ - ks8695_add_device_wan(); /* eth0 = WAN */ - ks8695_add_device_lan(); /* eth1 = LAN */ -} - -MACHINE_START(KS8695, "KS8695 Centaur Development Board") - /* Maintainer: Micrel Semiconductor Inc. */ - .atag_offset = 0x100, - .map_io = ks8695_map_io, - .init_irq = ks8695_init_irq, - .init_machine = micrel_init, - .init_time = ks8695_timer_init, - .restart = ks8695_restart, -MACHINE_END diff --git a/arch/arm/mach-ks8695/board-og.c b/arch/arm/mach-ks8695/board-og.c deleted file mode 100644 index 12ffe9227f9c..000000000000 --- a/arch/arm/mach-ks8695/board-og.c +++ /dev/null @@ -1,197 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * board-og.c -- support for the OpenGear KS8695 based boards. - */ - -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/interrupt.h> -#include <linux/init.h> -#include <linux/delay.h> -#include <linux/platform_device.h> -#include <linux/serial_8250.h> -#include <linux/gpio.h> -#include <linux/irq.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/map.h> -#include "devices.h" -#include <mach/regs-gpio.h> -#include <mach/gpio-ks8695.h> -#include "generic.h" - -static int og_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - if (machine_is_im4004() && (slot == 8)) - return KS8695_IRQ_EXTERN1; - return KS8695_IRQ_EXTERN0; -} - -static struct ks8695_pci_cfg __initdata og_pci = { - .mode = KS8695_MODE_PCI, - .map_irq = og_pci_map_irq, -}; - -static void __init og_register_pci(void) -{ - /* Initialize the GPIO lines for interrupt mode */ - ks8695_gpio_interrupt(KS8695_GPIO_0, IRQ_TYPE_LEVEL_LOW); - - /* Cardbus Slot */ - if (machine_is_im4004()) - ks8695_gpio_interrupt(KS8695_GPIO_1, IRQ_TYPE_LEVEL_LOW); - - if (IS_ENABLED(CONFIG_PCI)) - ks8695_init_pci(&og_pci); -} - -/* - * The PCI bus reset is driven by a dedicated GPIO line. Toggle it here - * and bring the PCI bus out of reset. - */ -static void __init og_pci_bus_reset(void) -{ - unsigned int rstline = 1; - - /* Some boards use a different GPIO as the PCI reset line */ - if (machine_is_im4004()) - rstline = 2; - else if (machine_is_im42xx()) - rstline = 0; - - gpio_request(rstline, "PCI reset"); - gpio_direction_output(rstline, 0); - - /* Drive a reset on the PCI reset line */ - gpio_set_value(rstline, 1); - gpio_set_value(rstline, 0); - mdelay(100); - gpio_set_value(rstline, 1); - mdelay(100); -} - -/* - * Direct connect serial ports (non-PCI that is). - */ -#define S8250_PHYS 0x03800000 -#define S8250_VIRT 0xf4000000 -#define S8250_SIZE 0x00100000 - -static struct map_desc og_io_desc[] __initdata = { - { - .virtual = S8250_VIRT, - .pfn = __phys_to_pfn(S8250_PHYS), - .length = S8250_SIZE, - .type = MT_DEVICE, - } -}; - -static struct resource og_uart_resources[] = { - { - .start = S8250_VIRT, - .end = S8250_VIRT + S8250_SIZE, - .flags = IORESOURCE_MEM - }, -}; - -static struct plat_serial8250_port og_uart_data[] = { - { - .mapbase = S8250_VIRT, - .membase = (char *) S8250_VIRT, - .irq = 3, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, - .iotype = UPIO_MEM, - .regshift = 2, - .uartclk = 115200 * 16, - }, - { }, -}; - -static struct platform_device og_uart = { - .name = "serial8250", - .id = 0, - .dev.platform_data = og_uart_data, - .num_resources = 1, - .resource = og_uart_resources -}; - -static struct platform_device *og_devices[] __initdata = { - &og_uart -}; - -static void __init og_init(void) -{ - ks8695_register_gpios(); - - if (machine_is_cm4002()) { - ks8695_gpio_interrupt(KS8695_GPIO_1, IRQ_TYPE_LEVEL_HIGH); - iotable_init(og_io_desc, ARRAY_SIZE(og_io_desc)); - platform_add_devices(og_devices, ARRAY_SIZE(og_devices)); - } else { - og_pci_bus_reset(); - og_register_pci(); - } - - ks8695_add_device_lan(); - ks8695_add_device_wan(); -} - -#ifdef CONFIG_MACH_CM4002 -MACHINE_START(CM4002, "OpenGear/CM4002") - /* OpenGear Inc. */ - .atag_offset = 0x100, - .map_io = ks8695_map_io, - .init_irq = ks8695_init_irq, - .init_machine = og_init, - .init_time = ks8695_timer_init, - .restart = ks8695_restart, -MACHINE_END -#endif - -#ifdef CONFIG_MACH_CM4008 -MACHINE_START(CM4008, "OpenGear/CM4008") - /* OpenGear Inc. */ - .atag_offset = 0x100, - .map_io = ks8695_map_io, - .init_irq = ks8695_init_irq, - .init_machine = og_init, - .init_time = ks8695_timer_init, - .restart = ks8695_restart, -MACHINE_END -#endif - -#ifdef CONFIG_MACH_CM41xx -MACHINE_START(CM41XX, "OpenGear/CM41xx") - /* OpenGear Inc. */ - .atag_offset = 0x100, - .map_io = ks8695_map_io, - .init_irq = ks8695_init_irq, - .init_machine = og_init, - .init_time = ks8695_timer_init, - .restart = ks8695_restart, -MACHINE_END -#endif - -#ifdef CONFIG_MACH_IM4004 -MACHINE_START(IM4004, "OpenGear/IM4004") - /* OpenGear Inc. */ - .atag_offset = 0x100, - .map_io = ks8695_map_io, - .init_irq = ks8695_init_irq, - .init_machine = og_init, - .init_time = ks8695_timer_init, - .restart = ks8695_restart, -MACHINE_END -#endif - -#ifdef CONFIG_MACH_IM42xx -MACHINE_START(IM42XX, "OpenGear/IM42xx") - /* OpenGear Inc. */ - .atag_offset = 0x100, - .map_io = ks8695_map_io, - .init_irq = ks8695_init_irq, - .init_machine = og_init, - .init_time = ks8695_timer_init, - .restart = ks8695_restart, -MACHINE_END -#endif diff --git a/arch/arm/mach-ks8695/board-sg.c b/arch/arm/mach-ks8695/board-sg.c deleted file mode 100644 index d5ec85a56375..000000000000 --- a/arch/arm/mach-ks8695/board-sg.c +++ /dev/null @@ -1,118 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * board-sg.c -- support for the SnapGear KS8695 based boards - */ - -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/map.h> -#include <linux/mtd/physmap.h> -#include <linux/mtd/partitions.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include "devices.h" -#include "generic.h" - -/* - * The SG310 machine type is fitted with a conventional 8MB Strataflash - * device. Define its partitioning. - */ -#define FL_BASE 0x02000000 -#define FL_SIZE SZ_8M - -static struct mtd_partition sg_mtd_partitions[] = { - [0] = { - .name = "SnapGear Boot Loader", - .size = SZ_128K, - }, - [1] = { - .name = "SnapGear non-volatile configuration", - .size = SZ_512K, - .offset = SZ_256K, - }, - [2] = { - .name = "SnapGear image", - .offset = SZ_512K + SZ_256K, - }, - [3] = { - .name = "SnapGear StrataFlash", - }, - [4] = { - .name = "SnapGear Boot Tags", - .size = SZ_128K, - .offset = SZ_128K, - }, -}; - -static struct physmap_flash_data sg_mtd_pdata = { - .width = 1, - .nr_parts = ARRAY_SIZE(sg_mtd_partitions), - .parts = sg_mtd_partitions, -}; - - -static struct resource sg_mtd_resource[] = { - [0] = { - .start = FL_BASE, - .end = FL_BASE + FL_SIZE - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device sg_mtd_device = { - .name = "physmap-flash", - .id = 0, - .num_resources = ARRAY_SIZE(sg_mtd_resource), - .resource = sg_mtd_resource, - .dev = { - .platform_data = &sg_mtd_pdata, - }, -}; - -static void __init sg_init(void) -{ - ks8695_add_device_lan(); - ks8695_add_device_wan(); - - if (machine_is_sg310()) - platform_device_register(&sg_mtd_device); -} - -#ifdef CONFIG_MACH_LITE300 -MACHINE_START(LITE300, "SecureComputing/SG300") - /* SnapGear */ - .atag_offset = 0x100, - .map_io = ks8695_map_io, - .init_irq = ks8695_init_irq, - .init_machine = sg_init, - .init_time = ks8695_timer_init, - .restart = ks8695_restart, -MACHINE_END -#endif - -#ifdef CONFIG_MACH_SG310 -MACHINE_START(SG310, "McAfee/SG310") - /* SnapGear */ - .atag_offset = 0x100, - .map_io = ks8695_map_io, - .init_irq = ks8695_init_irq, - .init_machine = sg_init, - .init_time = ks8695_timer_init, - .restart = ks8695_restart, -MACHINE_END -#endif - -#ifdef CONFIG_MACH_SE4200 -MACHINE_START(SE4200, "SecureComputing/SE4200") - /* SnapGear */ - .atag_offset = 0x100, - .map_io = ks8695_map_io, - .init_irq = ks8695_init_irq, - .init_machine = sg_init, - .init_time = ks8695_timer_init, - .restart = ks8695_restart, -MACHINE_END -#endif diff --git a/arch/arm/mach-ks8695/cpu.c b/arch/arm/mach-ks8695/cpu.c deleted file mode 100644 index aa6bb0c93aa8..000000000000 --- a/arch/arm/mach-ks8695/cpu.c +++ /dev/null @@ -1,60 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * arch/arm/mach-ks8695/cpu.c - * - * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> - * Copyright (C) 2006 Simtec Electronics - * - * KS8695 CPU support - */ - -#include <linux/kernel.h> -#include <linux/module.h> -#include <linux/init.h> -#include <linux/io.h> - -#include <mach/hardware.h> -#include <asm/mach/arch.h> -#include <asm/mach/map.h> - -#include "regs-sys.h" -#include <mach/regs-misc.h> - - -static struct map_desc ks8695_io_desc[] __initdata = { - { - .virtual = (unsigned long)KS8695_IO_VA, - .pfn = __phys_to_pfn(KS8695_IO_PA), - .length = KS8695_IO_SIZE, - .type = MT_DEVICE, - } -}; - -static void __init ks8695_processor_info(void) -{ - unsigned long id, rev; - - id = __raw_readl(KS8695_MISC_VA + KS8695_DID); - rev = __raw_readl(KS8695_MISC_VA + KS8695_RID); - - printk("KS8695 ID=%04lx SubID=%02lx Revision=%02lx\n", (id & DID_ID), (rev & RID_SUBID), (rev & RID_REVISION)); -} - -static unsigned int sysclk[8] = { 125000000, 100000000, 62500000, 50000000, 41700000, 33300000, 31300000, 25000000 }; -static unsigned int cpuclk[8] = { 166000000, 166000000, 83000000, 83000000, 55300000, 55300000, 41500000, 41500000 }; - -static void __init ks8695_clock_info(void) -{ - unsigned int scdc = __raw_readl(KS8695_SYS_VA + KS8695_CLKCON) & CLKCON_SCDC; - - printk("Clocks: System %u MHz, CPU %u MHz\n", - sysclk[scdc] / 1000000, cpuclk[scdc] / 1000000); -} - -void __init ks8695_map_io(void) -{ - iotable_init(ks8695_io_desc, ARRAY_SIZE(ks8695_io_desc)); - - ks8695_processor_info(); - ks8695_clock_info(); -} diff --git a/arch/arm/mach-ks8695/devices.c b/arch/arm/mach-ks8695/devices.c deleted file mode 100644 index 61cf20beb45f..000000000000 --- a/arch/arm/mach-ks8695/devices.c +++ /dev/null @@ -1,197 +0,0 @@ -/* - * arch/arm/mach-ks8695/devices.c - * - * Copyright (C) 2006 Andrew Victor - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#include <asm/mach/arch.h> -#include <asm/mach/map.h> - -#include <linux/gpio.h> -#include <linux/platform_device.h> - -#include <mach/irqs.h> -#include "regs-wan.h" -#include "regs-lan.h" -#include "regs-hpna.h" -#include <mach/regs-switch.h> -#include <mach/regs-misc.h> - - -/* -------------------------------------------------------------------- - * Ethernet - * -------------------------------------------------------------------- */ - -static u64 eth_dmamask = 0xffffffffUL; - -static struct resource ks8695_wan_resources[] = { - [0] = { - .start = KS8695_WAN_PA, - .end = KS8695_WAN_PA + 0x00ff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .name = "WAN RX", - .start = KS8695_IRQ_WAN_RX_STATUS, - .end = KS8695_IRQ_WAN_RX_STATUS, - .flags = IORESOURCE_IRQ, - }, - [2] = { - .name = "WAN TX", - .start = KS8695_IRQ_WAN_TX_STATUS, - .end = KS8695_IRQ_WAN_TX_STATUS, - .flags = IORESOURCE_IRQ, - }, - [3] = { - .name = "WAN Link", - .start = KS8695_IRQ_WAN_LINK, - .end = KS8695_IRQ_WAN_LINK, - .flags = IORESOURCE_IRQ, - }, - [4] = { - .name = "WAN PHY", - .start = KS8695_MISC_PA, - .end = KS8695_MISC_PA + 0x1f, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device ks8695_wan_device = { - .name = "ks8695_ether", - .id = 0, - .dev = { - .dma_mask = ð_dmamask, - .coherent_dma_mask = 0xffffffff, - }, - .resource = ks8695_wan_resources, - .num_resources = ARRAY_SIZE(ks8695_wan_resources), -}; - - -static struct resource ks8695_lan_resources[] = { - [0] = { - .start = KS8695_LAN_PA, - .end = KS8695_LAN_PA + 0x00ff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .name = "LAN RX", - .start = KS8695_IRQ_LAN_RX_STATUS, - .end = KS8695_IRQ_LAN_RX_STATUS, - .flags = IORESOURCE_IRQ, - }, - [2] = { - .name = "LAN TX", - .start = KS8695_IRQ_LAN_TX_STATUS, - .end = KS8695_IRQ_LAN_TX_STATUS, - .flags = IORESOURCE_IRQ, - }, - [3] = { - .name = "LAN SWITCH", - .start = KS8695_SWITCH_PA, - .end = KS8695_SWITCH_PA + 0x4f, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device ks8695_lan_device = { - .name = "ks8695_ether", - .id = 1, - .dev = { - .dma_mask = ð_dmamask, - .coherent_dma_mask = 0xffffffff, - }, - .resource = ks8695_lan_resources, - .num_resources = ARRAY_SIZE(ks8695_lan_resources), -}; - - -static struct resource ks8695_hpna_resources[] = { - [0] = { - .start = KS8695_HPNA_PA, - .end = KS8695_HPNA_PA + 0x00ff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .name = "HPNA RX", - .start = KS8695_IRQ_HPNA_RX_STATUS, - .end = KS8695_IRQ_HPNA_RX_STATUS, - .flags = IORESOURCE_IRQ, - }, - [2] = { - .name = "HPNA TX", - .start = KS8695_IRQ_HPNA_TX_STATUS, - .end = KS8695_IRQ_HPNA_TX_STATUS, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device ks8695_hpna_device = { - .name = "ks8695_ether", - .id = 2, - .dev = { - .dma_mask = ð_dmamask, - .coherent_dma_mask = 0xffffffff, - }, - .resource = ks8695_hpna_resources, - .num_resources = ARRAY_SIZE(ks8695_hpna_resources), -}; - -void __init ks8695_add_device_wan(void) -{ - platform_device_register(&ks8695_wan_device); -} - -void __init ks8695_add_device_lan(void) -{ - platform_device_register(&ks8695_lan_device); -} - -void __init ks8696_add_device_hpna(void) -{ - platform_device_register(&ks8695_hpna_device); -} - - -/* -------------------------------------------------------------------- - * Watchdog - * -------------------------------------------------------------------- */ - -static struct platform_device ks8695_wdt_device = { - .name = "ks8695_wdt", - .id = -1, - .num_resources = 0, -}; - -static void __init ks8695_add_device_watchdog(void) -{ - platform_device_register(&ks8695_wdt_device); -} - - -/* -------------------------------------------------------------------- */ - -/* - * These devices are always present and don't need any board-specific - * setup. - */ -static int __init ks8695_add_standard_devices(void) -{ - ks8695_add_device_watchdog(); - return 0; -} - -arch_initcall(ks8695_add_standard_devices); diff --git a/arch/arm/mach-ks8695/devices.h b/arch/arm/mach-ks8695/devices.h deleted file mode 100644 index cc23ee3820ea..000000000000 --- a/arch/arm/mach-ks8695/devices.h +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * arch/arm/mach-ks8695/include/mach/devices.h - * - * Copyright (C) 2006 Andrew Victor - */ - -#ifndef __ASM_ARCH_DEVICES_H -#define __ASM_ARCH_DEVICES_H - -#include <linux/pci.h> - - /* Ethernet */ -extern void __init ks8695_add_device_wan(void); -extern void __init ks8695_add_device_lan(void); -extern void __init ks8695_add_device_hpna(void); - - /* PCI */ -#define KS8695_MODE_PCI 0 -#define KS8695_MODE_MINIPCI 1 -#define KS8695_MODE_CARDBUS 2 - -struct ks8695_pci_cfg { - short mode; - int (*map_irq)(const struct pci_dev *, u8, u8); -}; -extern __init void ks8695_init_pci(struct ks8695_pci_cfg *); - -#endif diff --git a/arch/arm/mach-ks8695/generic.h b/arch/arm/mach-ks8695/generic.h deleted file mode 100644 index 9e9cbdd436a9..000000000000 --- a/arch/arm/mach-ks8695/generic.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * arch/arm/mach-ks8695/generic.h - * - * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> - * Copyright (C) 2006 Simtec Electronics -*/ - -extern __init void ks8695_map_io(void); -extern __init void ks8695_init_irq(void); -extern void ks8695_restart(enum reboot_mode, const char *); -extern void ks8695_timer_init(void); diff --git a/arch/arm/mach-ks8695/include/mach/entry-macro.S b/arch/arm/mach-ks8695/include/mach/entry-macro.S deleted file mode 100644 index 7ff812cb010b..000000000000 --- a/arch/arm/mach-ks8695/include/mach/entry-macro.S +++ /dev/null @@ -1,47 +0,0 @@ -/* - * arch/arm/mach-ks8695/include/mach/entry-macro.S - * - * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> - * Copyright (C) 2006 Simtec Electronics - * - * Low-level IRQ helper macros for KS8695 - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. -*/ - -#include <mach/hardware.h> -#include <mach/regs-irq.h> - - .macro get_irqnr_preamble, base, tmp - ldr \base, =KS8695_IRQ_VA @ Base address of interrupt controller - .endm - - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - ldr \irqstat, [\base, #KS8695_INTMS] @ Mask Status register - - teq \irqstat, #0 - beq 1001f - - mov \irqnr, #0 - - tst \irqstat, #0xff - moveq \irqstat, \irqstat, lsr #8 - addeq \irqnr, \irqnr, #8 - tsteq \irqstat, #0xff - moveq \irqstat, \irqstat, lsr #8 - addeq \irqnr, \irqnr, #8 - tsteq \irqstat, #0xff - moveq \irqstat, \irqstat, lsr #8 - addeq \irqnr, \irqnr, #8 - tst \irqstat, #0x0f - moveq \irqstat, \irqstat, lsr #4 - addeq \irqnr, \irqnr, #4 - tst \irqstat, #0x03 - moveq \irqstat, \irqstat, lsr #2 - addeq \irqnr, \irqnr, #2 - tst \irqstat, #0x01 - addseq \irqnr, \irqnr, #1 -1001: - .endm diff --git a/arch/arm/mach-ks8695/include/mach/gpio-ks8695.h b/arch/arm/mach-ks8695/include/mach/gpio-ks8695.h deleted file mode 100644 index 600115f48fb3..000000000000 --- a/arch/arm/mach-ks8695/include/mach/gpio-ks8695.h +++ /dev/null @@ -1,36 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2006 Andrew Victor - */ - -#ifndef __MACH_KS8659_GPIO_H -#define __MACH_KS8659_GPIO_H - -#include <linux/kernel.h> - -#define KS8695_GPIO_0 0 -#define KS8695_GPIO_1 1 -#define KS8695_GPIO_2 2 -#define KS8695_GPIO_3 3 -#define KS8695_GPIO_4 4 -#define KS8695_GPIO_5 5 -#define KS8695_GPIO_6 6 -#define KS8695_GPIO_7 7 -#define KS8695_GPIO_8 8 -#define KS8695_GPIO_9 9 -#define KS8695_GPIO_10 10 -#define KS8695_GPIO_11 11 -#define KS8695_GPIO_12 12 -#define KS8695_GPIO_13 13 -#define KS8695_GPIO_14 14 -#define KS8695_GPIO_15 15 - -/* - * Configure GPIO pin as external interrupt source. - */ -extern int ks8695_gpio_interrupt(unsigned int pin, unsigned int type); - -/* Register the GPIOs */ -extern void ks8695_register_gpios(void); - -#endif /* __MACH_KS8659_GPIO_H */ diff --git a/arch/arm/mach-ks8695/include/mach/hardware.h b/arch/arm/mach-ks8695/include/mach/hardware.h deleted file mode 100644 index 0fb889be8112..000000000000 --- a/arch/arm/mach-ks8695/include/mach/hardware.h +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * arch/arm/mach-ks8695/include/mach/hardware.h - * - * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> - * Copyright (C) 2006 Simtec Electronics - * - * KS8695 - Memory Map definitions -*/ - -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -#include <linux/sizes.h> - -/* - * Clocks are derived from MCLK, which is 25MHz - */ -#define KS8695_CLOCK_RATE 25000000 - -/* - * Physical RAM address. - */ -#define KS8695_SDRAM_PA 0x00000000 - - -/* - * We map an entire MiB with the System Configuration Registers in even - * though only 64KiB is needed. This makes it easier for use with the - * head debug code as the initial MMU setup only deals in L1 sections. - */ -#define KS8695_IO_PA 0x03F00000 -#define KS8695_IO_VA IOMEM(0xF0000000) -#define KS8695_IO_SIZE SZ_1M - -#define KS8695_PCIMEM_PA 0x60000000 -#define KS8695_PCIMEM_SIZE SZ_512M - -#define KS8695_PCIIO_PA 0x80000000 -#define KS8695_PCIIO_SIZE SZ_64K - -#endif diff --git a/arch/arm/mach-ks8695/include/mach/irqs.h b/arch/arm/mach-ks8695/include/mach/irqs.h deleted file mode 100644 index 0cbb30672427..000000000000 --- a/arch/arm/mach-ks8695/include/mach/irqs.h +++ /dev/null @@ -1,51 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * arch/arm/mach-ks8695/include/mach/irqs.h - * - * Copyright (C) 2006 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - */ - -#ifndef __ASM_ARCH_IRQS_H -#define __ASM_ARCH_IRQS_H - - -#define NR_IRQS 32 - -/* - * IRQ definitions - */ -#define KS8695_IRQ_COMM_RX 0 -#define KS8695_IRQ_COMM_TX 1 -#define KS8695_IRQ_EXTERN0 2 -#define KS8695_IRQ_EXTERN1 3 -#define KS8695_IRQ_EXTERN2 4 -#define KS8695_IRQ_EXTERN3 5 -#define KS8695_IRQ_TIMER0 6 -#define KS8695_IRQ_TIMER1 7 -#define KS8695_IRQ_UART_TX 8 -#define KS8695_IRQ_UART_RX 9 -#define KS8695_IRQ_UART_LINE_STATUS 10 -#define KS8695_IRQ_UART_MODEM_STATUS 11 -#define KS8695_IRQ_LAN_RX_STOP 12 -#define KS8695_IRQ_LAN_TX_STOP 13 -#define KS8695_IRQ_LAN_RX_BUF 14 -#define KS8695_IRQ_LAN_TX_BUF 15 -#define KS8695_IRQ_LAN_RX_STATUS 16 -#define KS8695_IRQ_LAN_TX_STATUS 17 -#define KS8695_IRQ_HPNA_RX_STOP 18 -#define KS8695_IRQ_HPNA_TX_STOP 19 -#define KS8695_IRQ_HPNA_RX_BUF 20 -#define KS8695_IRQ_HPNA_TX_BUF 21 -#define KS8695_IRQ_HPNA_RX_STATUS 22 -#define KS8695_IRQ_HPNA_TX_STATUS 23 -#define KS8695_IRQ_BUS_ERROR 24 -#define KS8695_IRQ_WAN_RX_STOP 25 -#define KS8695_IRQ_WAN_TX_STOP 26 -#define KS8695_IRQ_WAN_RX_BUF 27 -#define KS8695_IRQ_WAN_TX_BUF 28 -#define KS8695_IRQ_WAN_RX_STATUS 29 -#define KS8695_IRQ_WAN_TX_STATUS 30 -#define KS8695_IRQ_WAN_LINK 31 - -#endif diff --git a/arch/arm/mach-ks8695/include/mach/memory.h b/arch/arm/mach-ks8695/include/mach/memory.h deleted file mode 100644 index ab0d27fa8969..000000000000 --- a/arch/arm/mach-ks8695/include/mach/memory.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * arch/arm/mach-ks8695/include/mach/memory.h - * - * Copyright (C) 2006 Andrew Victor - * - * KS8695 Memory definitions - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASM_ARCH_MEMORY_H -#define __ASM_ARCH_MEMORY_H - -#include <mach/hardware.h> - -#ifndef __ASSEMBLY__ - -#ifdef CONFIG_PCI - -/* PCI mappings */ -#define __virt_to_bus(x) ((x) - PAGE_OFFSET + KS8695_PCIMEM_PA) -#define __bus_to_virt(x) ((x) - KS8695_PCIMEM_PA + PAGE_OFFSET) - -/* Platform-bus mapping */ -extern struct bus_type platform_bus_type; -#define is_lbus_device(dev) (dev && dev->bus == &platform_bus_type) -#define __arch_dma_to_virt(dev, x) ({ (void *) (is_lbus_device(dev) ? \ - __phys_to_virt(x) : __bus_to_virt(x)); }) -#define __arch_virt_to_dma(dev, x) ({ is_lbus_device(dev) ? \ - (dma_addr_t)__virt_to_phys((unsigned long)x) \ - : (dma_addr_t)__virt_to_bus(x); }) -#define __arch_pfn_to_dma(dev, pfn) \ - ({ dma_addr_t __dma = __pfn_to_phys(pfn); \ - if (!is_lbus_device(dev)) \ - __dma = __dma - PHYS_OFFSET + KS8695_PCIMEM_PA; \ - __dma; }) - -#define __arch_dma_to_pfn(dev, x) \ - ({ dma_addr_t __dma = x; \ - if (!is_lbus_device(dev)) \ - __dma += PHYS_OFFSET - KS8695_PCIMEM_PA; \ - __phys_to_pfn(__dma); \ - }) - -#endif - -#endif - -#endif diff --git a/arch/arm/mach-ks8695/include/mach/regs-gpio.h b/arch/arm/mach-ks8695/include/mach/regs-gpio.h deleted file mode 100644 index 90614a7d0548..000000000000 --- a/arch/arm/mach-ks8695/include/mach/regs-gpio.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * arch/arm/mach-ks8695/include/mach/regs-gpio.h - * - * Copyright (C) 2007 Andrew Victor - * - * KS8695 - GPIO control registers and bit definitions. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef KS8695_GPIO_H -#define KS8695_GPIO_H - -#define KS8695_GPIO_OFFSET (0xF0000 + 0xE600) -#define KS8695_GPIO_VA (KS8695_IO_VA + KS8695_GPIO_OFFSET) -#define KS8695_GPIO_PA (KS8695_IO_PA + KS8695_GPIO_OFFSET) - - -#define KS8695_IOPM (0x00) /* I/O Port Mode Register */ -#define KS8695_IOPC (0x04) /* I/O Port Control Register */ -#define KS8695_IOPD (0x08) /* I/O Port Data Register */ - - -/* Port Mode Register */ -#define IOPM(x) (1 << (x)) /* Mode for GPIO Pin x */ - -/* Port Control Register */ -#define IOPC_IOTIM1EN (1 << 17) /* GPIO Pin for Timer1 Enable */ -#define IOPC_IOTIM0EN (1 << 16) /* GPIO Pin for Timer0 Enable */ -#define IOPC_IOEINT3EN (1 << 15) /* GPIO Pin for External/Soft Interrupt 3 Enable */ -#define IOPC_IOEINT3TM (7 << 12) /* GPIO Pin for External/Soft Interrupt 3 Trigger Mode */ -#define IOPC_IOEINT3_MODE(x) ((x) << 12) -#define IOPC_IOEINT2EN (1 << 11) /* GPIO Pin for External/Soft Interrupt 2 Enable */ -#define IOPC_IOEINT2TM (7 << 8) /* GPIO Pin for External/Soft Interrupt 2 Trigger Mode */ -#define IOPC_IOEINT2_MODE(x) ((x) << 8) -#define IOPC_IOEINT1EN (1 << 7) /* GPIO Pin for External/Soft Interrupt 1 Enable */ -#define IOPC_IOEINT1TM (7 << 4) /* GPIO Pin for External/Soft Interrupt 1 Trigger Mode */ -#define IOPC_IOEINT1_MODE(x) ((x) << 4) -#define IOPC_IOEINT0EN (1 << 3) /* GPIO Pin for External/Soft Interrupt 0 Enable */ -#define IOPC_IOEINT0TM (7 << 0) /* GPIO Pin for External/Soft Interrupt 0 Trigger Mode */ -#define IOPC_IOEINT0_MODE(x) ((x) << 0) - - /* Trigger Modes */ -#define IOPC_TM_LOW (0) /* Level Detection (Active Low) */ -#define IOPC_TM_HIGH (1) /* Level Detection (Active High) */ -#define IOPC_TM_RISING (2) /* Rising Edge Detection */ -#define IOPC_TM_FALLING (4) /* Falling Edge Detection */ -#define IOPC_TM_EDGE (6) /* Both Edge Detection */ - -/* Port Data Register */ -#define IOPD(x) (1 << (x)) /* Signal Level of GPIO Pin x */ - -#endif diff --git a/arch/arm/mach-ks8695/include/mach/regs-irq.h b/arch/arm/mach-ks8695/include/mach/regs-irq.h deleted file mode 100644 index 352b7e8704d5..000000000000 --- a/arch/arm/mach-ks8695/include/mach/regs-irq.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * arch/arm/mach-ks8695/include/mach/regs-irq.h - * - * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> - * Copyright (C) 2006 Simtec Electronics - * - * KS8695 - IRQ registers and bit definitions - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef KS8695_IRQ_H -#define KS8695_IRQ_H - -#define KS8695_IRQ_OFFSET (0xF0000 + 0xE200) -#define KS8695_IRQ_VA (KS8695_IO_VA + KS8695_IRQ_OFFSET) -#define KS8695_IRQ_PA (KS8695_IO_PA + KS8695_IRQ_OFFSET) - - -/* - * Interrupt Controller registers - */ -#define KS8695_INTMC (0x00) /* Mode Control Register */ -#define KS8695_INTEN (0x04) /* Interrupt Enable Register */ -#define KS8695_INTST (0x08) /* Interrupt Status Register */ -#define KS8695_INTPW (0x0c) /* Interrupt Priority (WAN MAC) */ -#define KS8695_INTPH (0x10) /* Interrupt Priority (HPNA) [KS8695 only] */ -#define KS8695_INTPL (0x14) /* Interrupt Priority (LAN MAC) */ -#define KS8695_INTPT (0x18) /* Interrupt Priority (Timer) */ -#define KS8695_INTPU (0x1c) /* Interrupt Priority (UART) */ -#define KS8695_INTPE (0x20) /* Interrupt Priority (External Interrupt) */ -#define KS8695_INTPC (0x24) /* Interrupt Priority (Communications Channel) */ -#define KS8695_INTPBE (0x28) /* Interrupt Priority (Bus Error Response) */ -#define KS8695_INTMS (0x2c) /* Interrupt Mask Status Register */ -#define KS8695_INTHPF (0x30) /* Interrupt Pending Highest Priority (FIQ) */ -#define KS8695_INTHPI (0x34) /* Interrupt Pending Highest Priority (IRQ) */ - - -#endif diff --git a/arch/arm/mach-ks8695/include/mach/regs-misc.h b/arch/arm/mach-ks8695/include/mach/regs-misc.h deleted file mode 100644 index 2740c52494a0..000000000000 --- a/arch/arm/mach-ks8695/include/mach/regs-misc.h +++ /dev/null @@ -1,97 +0,0 @@ -/* - * arch/arm/mach-ks8695/include/mach/regs-misc.h - * - * Copyright (C) 2006 Andrew Victor - * - * KS8695 - Miscellaneous Registers - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef KS8695_MISC_H -#define KS8695_MISC_H - -#define KS8695_MISC_OFFSET (0xF0000 + 0xEA00) -#define KS8695_MISC_VA (KS8695_IO_VA + KS8695_MISC_OFFSET) -#define KS8695_MISC_PA (KS8695_IO_PA + KS8695_MISC_OFFSET) - - -/* - * Miscellaneous registers - */ -#define KS8695_DID (0x00) /* Device ID */ -#define KS8695_RID (0x04) /* Revision ID */ -#define KS8695_HMC (0x08) /* HPNA Miscellaneous Control [KS8695 only] */ -#define KS8695_WMC (0x0c) /* WAN Miscellaneous Control */ -#define KS8695_WPPM (0x10) /* WAN PHY Power Management */ -#define KS8695_PPS (0x1c) /* PHY PowerSave */ - -/* Device ID Register */ -#define DID_ID (0xffff << 0) /* Device ID */ - -/* Revision ID Register */ -#define RID_SUBID (0xf << 4) /* Sub-Device ID */ -#define RID_REVISION (0xf << 0) /* Revision ID */ - -/* HPNA Miscellaneous Control Register */ -#define HMC_HSS (1 << 1) /* Speed */ -#define HMC_HDS (1 << 0) /* Duplex */ - -/* WAN Miscellaneous Control Register */ -#define WMC_WANC (1 << 30) /* Auto-negotiation complete */ -#define WMC_WANR (1 << 29) /* Auto-negotiation restart */ -#define WMC_WANAP (1 << 28) /* Advertise Pause */ -#define WMC_WANA100F (1 << 27) /* Advertise 100 FDX */ -#define WMC_WANA100H (1 << 26) /* Advertise 100 HDX */ -#define WMC_WANA10F (1 << 25) /* Advertise 10 FDX */ -#define WMC_WANA10H (1 << 24) /* Advertise 10 HDX */ -#define WMC_WLS (1 << 23) /* Link status */ -#define WMC_WDS (1 << 22) /* Duplex status */ -#define WMC_WSS (1 << 21) /* Speed status */ -#define WMC_WLPP (1 << 20) /* Link Partner Pause */ -#define WMC_WLP100F (1 << 19) /* Link Partner 100 FDX */ -#define WMC_WLP100H (1 << 18) /* Link Partner 100 HDX */ -#define WMC_WLP10F (1 << 17) /* Link Partner 10 FDX */ -#define WMC_WLP10H (1 << 16) /* Link Partner 10 HDX */ -#define WMC_WAND (1 << 15) /* Auto-negotiation disable */ -#define WMC_WANF100 (1 << 14) /* Force 100 */ -#define WMC_WANFF (1 << 13) /* Force FDX */ -#define WMC_WLED1S (7 << 4) /* LED1 Select */ -#define WLED1S_SPEED (0 << 4) -#define WLED1S_LINK (1 << 4) -#define WLED1S_DUPLEX (2 << 4) -#define WLED1S_COLLISION (3 << 4) -#define WLED1S_ACTIVITY (4 << 4) -#define WLED1S_FDX_COLLISION (5 << 4) -#define WLED1S_LINK_ACTIVITY (6 << 4) -#define WMC_WLED0S (7 << 0) /* LED0 Select */ -#define WLED0S_SPEED (0 << 0) -#define WLED0S_LINK (1 << 0) -#define WLED0S_DUPLEX (2 << 0) -#define WLED0S_COLLISION (3 << 0) -#define WLED0S_ACTIVITY (4 << 0) -#define WLED0S_FDX_COLLISION (5 << 0) -#define WLED0S_LINK_ACTIVITY (6 << 0) - -/* WAN PHY Power Management Register */ -#define WPPM_WLPBK (1 << 14) /* Local Loopback */ -#define WPPM_WRLPKB (1 << 13) /* Remove Loopback */ -#define WPPM_WPI (1 << 12) /* PHY isolate */ -#define WPPM_WFL (1 << 10) /* Force link */ -#define WPPM_MDIXS (1 << 9) /* MDIX Status */ -#define WPPM_FEF (1 << 8) /* Far End Fault */ -#define WPPM_AMDIXP (1 << 7) /* Auto MDIX Parameter */ -#define WPPM_TXDIS (1 << 6) /* Disable transmitter */ -#define WPPM_DFEF (1 << 5) /* Disable Far End Fault */ -#define WPPM_PD (1 << 4) /* Power Down */ -#define WPPM_DMDX (1 << 3) /* Disable Auto MDI/MDIX */ -#define WPPM_FMDX (1 << 2) /* Force MDIX */ -#define WPPM_LPBK (1 << 1) /* MAX Loopback */ - -/* PHY Power Save Register */ -#define PPS_PPSM (1 << 0) /* PHY Power Save Mode */ - - -#endif diff --git a/arch/arm/mach-ks8695/include/mach/regs-switch.h b/arch/arm/mach-ks8695/include/mach/regs-switch.h deleted file mode 100644 index 97e8acb1cf6c..000000000000 --- a/arch/arm/mach-ks8695/include/mach/regs-switch.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * arch/arm/mach-ks8695/include/mach/regs-switch.h - * - * Copyright (C) 2006 Andrew Victor - * - * KS8695 - Switch Registers and bit definitions. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef KS8695_SWITCH_H -#define KS8695_SWITCH_H - -#define KS8695_SWITCH_OFFSET (0xF0000 + 0xe800) -#define KS8695_SWITCH_VA (KS8695_IO_VA + KS8695_SWITCH_OFFSET) -#define KS8695_SWITCH_PA (KS8695_IO_PA + KS8695_SWITCH_OFFSET) - - -/* - * Switch registers - */ -#define KS8695_SEC0 (0x00) /* Switch Engine Control 0 */ -#define KS8695_SEC1 (0x04) /* Switch Engine Control 1 */ -#define KS8695_SEC2 (0x08) /* Switch Engine Control 2 */ - -#define KS8695_SEPXCZ(x,z) (0x0c + (((x)-1)*3 + ((z)-1))*4) /* Port Configuration Registers */ - -#define KS8695_SEP12AN (0x48) /* Port 1 & 2 Auto-Negotiation */ -#define KS8695_SEP34AN (0x4c) /* Port 3 & 4 Auto-Negotiation */ -#define KS8695_SEIAC (0x50) /* Indirect Access Control */ -#define KS8695_SEIADH2 (0x54) /* Indirect Access Data High 2 */ -#define KS8695_SEIADH1 (0x58) /* Indirect Access Data High 1 */ -#define KS8695_SEIADL (0x5c) /* Indirect Access Data Low */ -#define KS8695_SEAFC (0x60) /* Advance Feature Control */ -#define KS8695_SEDSCPH (0x64) /* TOS Priority High */ -#define KS8695_SEDSCPL (0x68) /* TOS Priority Low */ -#define KS8695_SEMAH (0x6c) /* Switch Engine MAC Address High */ -#define KS8695_SEMAL (0x70) /* Switch Engine MAC Address Low */ -#define KS8695_LPPM12 (0x74) /* Port 1 & 2 PHY Power Management */ -#define KS8695_LPPM34 (0x78) /* Port 3 & 4 PHY Power Management */ - - -/* Switch Engine Control 0 */ -#define SEC0_LLED1S (7 << 25) /* LED1 Select */ -#define LLED1S_SPEED (0 << 25) -#define LLED1S_LINK (1 << 25) -#define LLED1S_DUPLEX (2 << 25) -#define LLED1S_COLLISION (3 << 25) -#define LLED1S_ACTIVITY (4 << 25) -#define LLED1S_FDX_COLLISION (5 << 25) -#define LLED1S_LINK_ACTIVITY (6 << 25) -#define SEC0_LLED0S (7 << 22) /* LED0 Select */ -#define LLED0S_SPEED (0 << 22) -#define LLED0S_LINK (1 << 22) -#define LLED0S_DUPLEX (2 << 22) -#define LLED0S_COLLISION (3 << 22) -#define LLED0S_ACTIVITY (4 << 22) -#define LLED0S_FDX_COLLISION (5 << 22) -#define LLED0S_LINK_ACTIVITY (6 << 22) -#define SEC0_ENABLE (1 << 0) /* Enable Switch */ - - - -#endif diff --git a/arch/arm/mach-ks8695/include/mach/regs-uart.h b/arch/arm/mach-ks8695/include/mach/regs-uart.h deleted file mode 100644 index 941a542c5f23..000000000000 --- a/arch/arm/mach-ks8695/include/mach/regs-uart.h +++ /dev/null @@ -1,89 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * arch/arm/mach-ks8695/include/mach/regs-uart.h - * - * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> - * Copyright (C) 2006 Simtec Electronics - * - * KS8695 - UART register and bit definitions. - */ - -#ifndef KS8695_UART_H -#define KS8695_UART_H - -#define KS8695_UART_OFFSET (0xF0000 + 0xE000) -#define KS8695_UART_VA (KS8695_IO_VA + KS8695_UART_OFFSET) -#define KS8695_UART_PA (KS8695_IO_PA + KS8695_UART_OFFSET) - - -/* - * UART registers - */ -#define KS8695_URRB (0x00) /* Receive Buffer Register */ -#define KS8695_URTH (0x04) /* Transmit Holding Register */ -#define KS8695_URFC (0x08) /* FIFO Control Register */ -#define KS8695_URLC (0x0C) /* Line Control Register */ -#define KS8695_URMC (0x10) /* Modem Control Register */ -#define KS8695_URLS (0x14) /* Line Status Register */ -#define KS8695_URMS (0x18) /* Modem Status Register */ -#define KS8695_URBD (0x1C) /* Baud Rate Divisor Register */ -#define KS8695_USR (0x20) /* Status Register */ - - -/* FIFO Control Register */ -#define URFC_URFRT (3 << 6) /* Receive FIFO Trigger Level */ -#define URFC_URFRT_1 (0 << 6) -#define URFC_URFRT_4 (1 << 6) -#define URFC_URFRT_8 (2 << 6) -#define URFC_URFRT_14 (3 << 6) -#define URFC_URTFR (1 << 2) /* Transmit FIFO Reset */ -#define URFC_URRFR (1 << 1) /* Receive FIFO Reset */ -#define URFC_URFE (1 << 0) /* FIFO Enable */ - -/* Line Control Register */ -#define URLC_URSBC (1 << 6) /* Set Break Condition */ -#define URLC_PARITY (7 << 3) /* Parity */ -#define URPE_NONE (0 << 3) -#define URPE_ODD (1 << 3) -#define URPE_EVEN (3 << 3) -#define URPE_MARK (5 << 3) -#define URPE_SPACE (7 << 3) -#define URLC_URSB (1 << 2) /* Stop Bits */ -#define URLC_URCL (3 << 0) /* Character Length */ -#define URCL_5 (0 << 0) -#define URCL_6 (1 << 0) -#define URCL_7 (2 << 0) -#define URCL_8 (3 << 0) - -/* Modem Control Register */ -#define URMC_URLB (1 << 4) /* Loop-back mode */ -#define URMC_UROUT2 (1 << 3) /* OUT2 signal */ -#define URMC_UROUT1 (1 << 2) /* OUT1 signal */ -#define URMC_URRTS (1 << 1) /* Request to Send */ -#define URMC_URDTR (1 << 0) /* Data Terminal Ready */ - -/* Line Status Register */ -#define URLS_URRFE (1 << 7) /* Receive FIFO Error */ -#define URLS_URTE (1 << 6) /* Transmit Empty */ -#define URLS_URTHRE (1 << 5) /* Transmit Holding Register Empty */ -#define URLS_URBI (1 << 4) /* Break Interrupt */ -#define URLS_URFE (1 << 3) /* Framing Error */ -#define URLS_URPE (1 << 2) /* Parity Error */ -#define URLS_URROE (1 << 1) /* Receive Overrun Error */ -#define URLS_URDR (1 << 0) /* Receive Data Ready */ - -/* Modem Status Register */ -#define URMS_URDCD (1 << 7) /* Data Carrier Detect */ -#define URMS_URRI (1 << 6) /* Ring Indicator */ -#define URMS_URDSR (1 << 5) /* Data Set Ready */ -#define URMS_URCTS (1 << 4) /* Clear to Send */ -#define URMS_URDDCD (1 << 3) /* Delta Data Carrier Detect */ -#define URMS_URTERI (1 << 2) /* Trailing Edge Ring Indicator */ -#define URMS_URDDST (1 << 1) /* Delta Data Set Ready */ -#define URMS_URDCTS (1 << 0) /* Delta Clear to Send */ - -/* Status Register */ -#define USR_UTI (1 << 0) /* Timeout Indication */ - - -#endif diff --git a/arch/arm/mach-ks8695/include/mach/uncompress.h b/arch/arm/mach-ks8695/include/mach/uncompress.h deleted file mode 100644 index dc78a29759b5..000000000000 --- a/arch/arm/mach-ks8695/include/mach/uncompress.h +++ /dev/null @@ -1,33 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * arch/arm/mach-ks8695/include/mach/uncompress.h - * - * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> - * Copyright (C) 2006 Simtec Electronics - * - * KS8695 - Kernel uncompressor - */ - -#ifndef __ASM_ARCH_UNCOMPRESS_H -#define __ASM_ARCH_UNCOMPRESS_H - -#include <linux/io.h> -#include <mach/regs-uart.h> - -static inline void putc(char c) -{ - while (!(__raw_readl((void __iomem*)KS8695_UART_PA + KS8695_URLS) & URLS_URTHRE)) - barrier(); - - __raw_writel(c, (void __iomem*)KS8695_UART_PA + KS8695_URTH); -} - -static inline void flush(void) -{ - while (!(__raw_readl((void __iomem*)KS8695_UART_PA + KS8695_URLS) & URLS_URTE)) - barrier(); -} - -#define arch_decomp_setup() - -#endif diff --git a/arch/arm/mach-ks8695/irq.c b/arch/arm/mach-ks8695/irq.c deleted file mode 100644 index 4b7ec8d9300c..000000000000 --- a/arch/arm/mach-ks8695/irq.c +++ /dev/null @@ -1,164 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * arch/arm/mach-ks8695/irq.c - * - * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> - * Copyright (C) 2006 Simtec Electronics - */ - -#include <linux/init.h> -#include <linux/module.h> -#include <linux/interrupt.h> -#include <linux/ioport.h> -#include <linux/device.h> -#include <linux/io.h> - -#include <mach/hardware.h> -#include <asm/irq.h> - -#include <asm/mach/irq.h> - -#include <mach/regs-irq.h> -#include <mach/regs-gpio.h> - -static void ks8695_irq_mask(struct irq_data *d) -{ - unsigned long inten; - - inten = __raw_readl(KS8695_IRQ_VA + KS8695_INTEN); - inten &= ~(1 << d->irq); - - __raw_writel(inten, KS8695_IRQ_VA + KS8695_INTEN); -} - -static void ks8695_irq_unmask(struct irq_data *d) -{ - unsigned long inten; - - inten = __raw_readl(KS8695_IRQ_VA + KS8695_INTEN); - inten |= (1 << d->irq); - - __raw_writel(inten, KS8695_IRQ_VA + KS8695_INTEN); -} - -static void ks8695_irq_ack(struct irq_data *d) -{ - __raw_writel((1 << d->irq), KS8695_IRQ_VA + KS8695_INTST); -} - - -static struct irq_chip ks8695_irq_level_chip; -static struct irq_chip ks8695_irq_edge_chip; - - -static int ks8695_irq_set_type(struct irq_data *d, unsigned int type) -{ - unsigned long ctrl, mode; - unsigned short level_triggered = 0; - - ctrl = __raw_readl(KS8695_GPIO_VA + KS8695_IOPC); - - switch (type) { - case IRQ_TYPE_LEVEL_HIGH: - mode = IOPC_TM_HIGH; - level_triggered = 1; - break; - case IRQ_TYPE_LEVEL_LOW: - mode = IOPC_TM_LOW; - level_triggered = 1; - break; - case IRQ_TYPE_EDGE_RISING: - mode = IOPC_TM_RISING; - break; - case IRQ_TYPE_EDGE_FALLING: - mode = IOPC_TM_FALLING; - break; - case IRQ_TYPE_EDGE_BOTH: - mode = IOPC_TM_EDGE; - break; - default: - return -EINVAL; - } - - switch (d->irq) { - case KS8695_IRQ_EXTERN0: - ctrl &= ~IOPC_IOEINT0TM; - ctrl |= IOPC_IOEINT0_MODE(mode); - break; - case KS8695_IRQ_EXTERN1: - ctrl &= ~IOPC_IOEINT1TM; - ctrl |= IOPC_IOEINT1_MODE(mode); - break; - case KS8695_IRQ_EXTERN2: - ctrl &= ~IOPC_IOEINT2TM; - ctrl |= IOPC_IOEINT2_MODE(mode); - break; - case KS8695_IRQ_EXTERN3: - ctrl &= ~IOPC_IOEINT3TM; - ctrl |= IOPC_IOEINT3_MODE(mode); - break; - default: - return -EINVAL; - } - - if (level_triggered) { - irq_set_chip_and_handler(d->irq, &ks8695_irq_level_chip, - handle_level_irq); - } - else { - irq_set_chip_and_handler(d->irq, &ks8695_irq_edge_chip, - handle_edge_irq); - } - - __raw_writel(ctrl, KS8695_GPIO_VA + KS8695_IOPC); - return 0; -} - -static struct irq_chip ks8695_irq_level_chip = { - .irq_ack = ks8695_irq_mask, - .irq_mask = ks8695_irq_mask, - .irq_unmask = ks8695_irq_unmask, - .irq_set_type = ks8695_irq_set_type, -}; - -static struct irq_chip ks8695_irq_edge_chip = { - .irq_ack = ks8695_irq_ack, - .irq_mask = ks8695_irq_mask, - .irq_unmask = ks8695_irq_unmask, - .irq_set_type = ks8695_irq_set_type, -}; - -void __init ks8695_init_irq(void) -{ - unsigned int irq; - - /* Disable all interrupts initially */ - __raw_writel(0, KS8695_IRQ_VA + KS8695_INTMC); - __raw_writel(0, KS8695_IRQ_VA + KS8695_INTEN); - - for (irq = 0; irq < NR_IRQS; irq++) { - switch (irq) { - /* Level-triggered interrupts */ - case KS8695_IRQ_BUS_ERROR: - case KS8695_IRQ_UART_MODEM_STATUS: - case KS8695_IRQ_UART_LINE_STATUS: - case KS8695_IRQ_UART_RX: - case KS8695_IRQ_COMM_TX: - case KS8695_IRQ_COMM_RX: - irq_set_chip_and_handler(irq, - &ks8695_irq_level_chip, - handle_level_irq); - break; - - /* Edge-triggered interrupts */ - default: - /* clear pending bit */ - ks8695_irq_ack(irq_get_irq_data(irq)); - irq_set_chip_and_handler(irq, - &ks8695_irq_edge_chip, - handle_edge_irq); - } - - irq_clear_status_flags(irq, IRQ_NOREQUEST); - } -} diff --git a/arch/arm/mach-ks8695/pci.c b/arch/arm/mach-ks8695/pci.c deleted file mode 100644 index 83f330bf07dd..000000000000 --- a/arch/arm/mach-ks8695/pci.c +++ /dev/null @@ -1,247 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * arch/arm/mach-ks8695/pci.c - * - * Copyright (C) 2003, Micrel Semiconductors - * Copyright (C) 2006, Greg Ungerer <gerg@snapgear.com> - * Copyright (C) 2006, Ben Dooks - * Copyright (C) 2007, Andrew Victor - */ - -#include <linux/kernel.h> -#include <linux/pci.h> -#include <linux/mm.h> -#include <linux/init.h> -#include <linux/irq.h> -#include <linux/delay.h> -#include <linux/io.h> - -#include <asm/signal.h> -#include <asm/mach/pci.h> -#include <mach/hardware.h> - -#include "devices.h" -#include "regs-pci.h" - - -static int pci_dbg; - -static void ks8695_pci_setupconfig(unsigned int bus_nr, unsigned int devfn, unsigned int where) -{ - unsigned long pbca; - - pbca = PBCA_ENABLE | (where & ~3); - pbca |= PCI_SLOT(devfn) << 11 ; - pbca |= PCI_FUNC(devfn) << 8; - pbca |= bus_nr << 16; - - if (bus_nr == 0) { - /* use Type-0 transaction */ - __raw_writel(pbca, KS8695_PCI_VA + KS8695_PBCA); - } else { - /* use Type-1 transaction */ - __raw_writel(pbca | PBCA_TYPE1, KS8695_PCI_VA + KS8695_PBCA); - } -} - -static void __iomem *ks8695_pci_map_bus(struct pci_bus *bus, unsigned int devfn, - int where) -{ - ks8695_pci_setupconfig(bus->number, devfn, where); - return KS8695_PCI_VA + KS8695_PBCD; -} - -static void ks8695_local_writeconfig(int where, u32 value) -{ - ks8695_pci_setupconfig(0, 0, where); - __raw_writel(value, KS8695_PCI_VA + KS8695_PBCD); -} - -static struct pci_ops ks8695_pci_ops = { - .map_bus = ks8695_pci_map_bus, - .read = pci_generic_config_read32, - .write = pci_generic_config_write32, -}; - -static struct resource pci_mem = { - .name = "PCI Memory space", - .start = KS8695_PCIMEM_PA, - .end = KS8695_PCIMEM_PA + (KS8695_PCIMEM_SIZE - 1), - .flags = IORESOURCE_MEM, -}; - -static struct resource pci_io = { - .name = "PCI IO space", - .start = KS8695_PCIIO_PA, - .end = KS8695_PCIIO_PA + (KS8695_PCIIO_SIZE - 1), - .flags = IORESOURCE_IO, -}; - -static int __init ks8695_pci_setup(int nr, struct pci_sys_data *sys) -{ - if (nr > 0) - return 0; - - request_resource(&iomem_resource, &pci_mem); - request_resource(&ioport_resource, &pci_io); - - pci_add_resource_offset(&sys->resources, &pci_io, sys->io_offset); - pci_add_resource_offset(&sys->resources, &pci_mem, sys->mem_offset); - - /* Assign and enable processor bridge */ - ks8695_local_writeconfig(PCI_BASE_ADDRESS_0, KS8695_PCIMEM_PA); - - /* Enable bus-master & Memory Space access */ - ks8695_local_writeconfig(PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); - - /* Set cache-line size & latency. */ - ks8695_local_writeconfig(PCI_CACHE_LINE_SIZE, (32 << 8) | (L1_CACHE_BYTES / sizeof(u32))); - - /* Reserve PCI memory space for PCI-AHB resources */ - if (!request_mem_region(KS8695_PCIMEM_PA, SZ_64M, "PCI-AHB Bridge")) { - printk(KERN_ERR "Cannot allocate PCI-AHB Bridge memory.\n"); - return -EBUSY; - } - - return 1; -} - -static inline unsigned int size_mask(unsigned long size) -{ - return (~size) + 1; -} - -static int ks8695_pci_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs) -{ - unsigned long pc = instruction_pointer(regs); - unsigned long instr = *(unsigned long *)pc; - unsigned long cmdstat; - - cmdstat = __raw_readl(KS8695_PCI_VA + KS8695_CRCFCS); - - printk(KERN_ERR "PCI abort: address = 0x%08lx fsr = 0x%03x PC = 0x%08lx LR = 0x%08lx [%s%s%s%s%s]\n", - addr, fsr, regs->ARM_pc, regs->ARM_lr, - cmdstat & (PCI_STATUS_SIG_TARGET_ABORT << 16) ? "GenTarget" : " ", - cmdstat & (PCI_STATUS_REC_TARGET_ABORT << 16) ? "RecvTarget" : " ", - cmdstat & (PCI_STATUS_REC_MASTER_ABORT << 16) ? "MasterAbort" : " ", - cmdstat & (PCI_STATUS_SIG_SYSTEM_ERROR << 16) ? "SysError" : " ", - cmdstat & (PCI_STATUS_DETECTED_PARITY << 16) ? "Parity" : " " - ); - - __raw_writel(cmdstat, KS8695_PCI_VA + KS8695_CRCFCS); - - /* - * If the instruction being executed was a read, - * make it look like it read all-ones. - */ - if ((instr & 0x0c100000) == 0x04100000) { - int reg = (instr >> 12) & 15; - unsigned long val; - - if (instr & 0x00400000) - val = 255; - else - val = -1; - - regs->uregs[reg] = val; - regs->ARM_pc += 4; - return 0; - } - - if ((instr & 0x0e100090) == 0x00100090) { - int reg = (instr >> 12) & 15; - - regs->uregs[reg] = -1; - regs->ARM_pc += 4; - return 0; - } - - return 1; -} - -static void __init ks8695_pci_preinit(void) -{ - /* make software reset to avoid freeze if PCI bus was messed up */ - __raw_writel(0x80000000, KS8695_PCI_VA + KS8695_PBCS); - - /* stage 1 initialization, subid, subdevice = 0x0001 */ - __raw_writel(0x00010001, KS8695_PCI_VA + KS8695_CRCSID); - - /* stage 2 initialization */ - /* prefetch limits with 16 words, retry enable */ - __raw_writel(0x40000000, KS8695_PCI_VA + KS8695_PBCS); - - /* configure memory mapping */ - __raw_writel(KS8695_PCIMEM_PA, KS8695_PCI_VA + KS8695_PMBA); - __raw_writel(size_mask(KS8695_PCIMEM_SIZE), KS8695_PCI_VA + KS8695_PMBAM); - __raw_writel(KS8695_PCIMEM_PA, KS8695_PCI_VA + KS8695_PMBAT); - __raw_writel(0, KS8695_PCI_VA + KS8695_PMBAC); - - /* configure IO mapping */ - __raw_writel(KS8695_PCIIO_PA, KS8695_PCI_VA + KS8695_PIOBA); - __raw_writel(size_mask(KS8695_PCIIO_SIZE), KS8695_PCI_VA + KS8695_PIOBAM); - __raw_writel(KS8695_PCIIO_PA, KS8695_PCI_VA + KS8695_PIOBAT); - __raw_writel(0, KS8695_PCI_VA + KS8695_PIOBAC); - - /* hook in fault handlers */ - hook_fault_code(8, ks8695_pci_fault, SIGBUS, 0, "external abort on non-linefetch"); - hook_fault_code(10, ks8695_pci_fault, SIGBUS, 0, "external abort on non-linefetch"); -} - -static void ks8695_show_pciregs(void) -{ - if (!pci_dbg) - return; - - printk(KERN_INFO "PCI: CRCFID = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_CRCFID)); - printk(KERN_INFO "PCI: CRCFCS = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_CRCFCS)); - printk(KERN_INFO "PCI: CRCFRV = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_CRCFRV)); - printk(KERN_INFO "PCI: CRCFLT = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_CRCFLT)); - printk(KERN_INFO "PCI: CRCBMA = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_CRCBMA)); - printk(KERN_INFO "PCI: CRCSID = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_CRCSID)); - printk(KERN_INFO "PCI: CRCFIT = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_CRCFIT)); - - printk(KERN_INFO "PCI: PBM = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_PBM)); - printk(KERN_INFO "PCI: PBCS = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_PBCS)); - - printk(KERN_INFO "PCI: PMBA = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_PMBA)); - printk(KERN_INFO "PCI: PMBAC = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_PMBAC)); - printk(KERN_INFO "PCI: PMBAM = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_PMBAM)); - printk(KERN_INFO "PCI: PMBAT = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_PMBAT)); - - printk(KERN_INFO "PCI: PIOBA = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_PIOBA)); - printk(KERN_INFO "PCI: PIOBAC = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_PIOBAC)); - printk(KERN_INFO "PCI: PIOBAM = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_PIOBAM)); - printk(KERN_INFO "PCI: PIOBAT = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_PIOBAT)); -} - - -static struct hw_pci ks8695_pci __initdata = { - .nr_controllers = 1, - .ops = &ks8695_pci_ops, - .preinit = ks8695_pci_preinit, - .setup = ks8695_pci_setup, - .postinit = NULL, - .map_irq = NULL, -}; - -void __init ks8695_init_pci(struct ks8695_pci_cfg *cfg) -{ - if (__raw_readl(KS8695_PCI_VA + KS8695_CRCFRV) & CFRV_GUEST) { - printk("PCI: KS8695 in guest mode, not initialising\n"); - return; - } - - pcibios_min_io = 0; - pcibios_min_mem = 0; - - printk(KERN_INFO "PCI: Initialising\n"); - ks8695_show_pciregs(); - - /* set Mode */ - __raw_writel(cfg->mode << 29, KS8695_PCI_VA + KS8695_PBM); - - ks8695_pci.map_irq = cfg->map_irq; /* board-specific map_irq method */ - - pci_common_init(&ks8695_pci); -} diff --git a/arch/arm/mach-ks8695/regs-hpna.h b/arch/arm/mach-ks8695/regs-hpna.h deleted file mode 100644 index 815ce5c2e3b9..000000000000 --- a/arch/arm/mach-ks8695/regs-hpna.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * arch/arm/mach-ks8695/include/mach/regs-wan.h - * - * Copyright (C) 2006 Andrew Victor - * - * KS8695 - HPNA Registers and bit definitions. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef KS8695_HPNA_H -#define KS8695_HPNA_H - -#define KS8695_HPNA_OFFSET (0xF0000 + 0xA000) -#define KS8695_HPNA_VA (KS8695_IO_VA + KS8695_HPNA_OFFSET) -#define KS8695_HPNA_PA (KS8695_IO_PA + KS8695_HPNA_OFFSET) - - -/* - * HPNA registers - */ - -#endif diff --git a/arch/arm/mach-ks8695/regs-lan.h b/arch/arm/mach-ks8695/regs-lan.h deleted file mode 100644 index 82c5f3791afb..000000000000 --- a/arch/arm/mach-ks8695/regs-lan.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - * arch/arm/mach-ks8695/include/mach/regs-lan.h - * - * Copyright (C) 2006 Andrew Victor - * - * KS8695 - LAN Registers and bit definitions. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef KS8695_LAN_H -#define KS8695_LAN_H - -#define KS8695_LAN_OFFSET (0xF0000 + 0x8000) -#define KS8695_LAN_VA (KS8695_IO_VA + KS8695_LAN_OFFSET) -#define KS8695_LAN_PA (KS8695_IO_PA + KS8695_LAN_OFFSET) - - -/* - * LAN registers - */ -#define KS8695_LMDTXC (0x00) /* DMA Transmit Control */ -#define KS8695_LMDRXC (0x04) /* DMA Receive Control */ -#define KS8695_LMDTSC (0x08) /* DMA Transmit Start Command */ -#define KS8695_LMDRSC (0x0c) /* DMA Receive Start Command */ -#define KS8695_LTDLB (0x10) /* Transmit Descriptor List Base Address */ -#define KS8695_LRDLB (0x14) /* Receive Descriptor List Base Address */ -#define KS8695_LMAL (0x18) /* MAC Station Address Low */ -#define KS8695_LMAH (0x1c) /* MAC Station Address High */ -#define KS8695_LMAAL(n) (0x80 + ((n)*8)) /* MAC Additional Station Address (0..15) Low */ -#define KS8695_LMAAH(n) (0x84 + ((n)*8)) /* MAC Additional Station Address (0..15) High */ - - -/* DMA Transmit Control Register */ -#define LMDTXC_LMTRST (1 << 31) /* Soft Reset */ -#define LMDTXC_LMTBS (0x3f << 24) /* Transmit Burst Size */ -#define LMDTXC_LMTUCG (1 << 18) /* Transmit UDP Checksum Generate */ -#define LMDTXC_LMTTCG (1 << 17) /* Transmit TCP Checksum Generate */ -#define LMDTXC_LMTICG (1 << 16) /* Transmit IP Checksum Generate */ -#define LMDTXC_LMTFCE (1 << 9) /* Transmit Flow Control Enable */ -#define LMDTXC_LMTLB (1 << 8) /* Loopback mode */ -#define LMDTXC_LMTEP (1 << 2) /* Transmit Enable Padding */ -#define LMDTXC_LMTAC (1 << 1) /* Transmit Add CRC */ -#define LMDTXC_LMTE (1 << 0) /* TX Enable */ - -/* DMA Receive Control Register */ -#define LMDRXC_LMRBS (0x3f << 24) /* Receive Burst Size */ -#define LMDRXC_LMRUCC (1 << 18) /* Receive UDP Checksum check */ -#define LMDRXC_LMRTCG (1 << 17) /* Receive TCP Checksum check */ -#define LMDRXC_LMRICG (1 << 16) /* Receive IP Checksum check */ -#define LMDRXC_LMRFCE (1 << 9) /* Receive Flow Control Enable */ -#define LMDRXC_LMRB (1 << 6) /* Receive Broadcast */ -#define LMDRXC_LMRM (1 << 5) /* Receive Multicast */ -#define LMDRXC_LMRU (1 << 4) /* Receive Unicast */ -#define LMDRXC_LMRERR (1 << 3) /* Receive Error Frame */ -#define LMDRXC_LMRA (1 << 2) /* Receive All */ -#define LMDRXC_LMRE (1 << 1) /* RX Enable */ - -/* Additional Station Address High */ -#define LMAAH_E (1 << 31) /* Address Enabled */ - - -#endif diff --git a/arch/arm/mach-ks8695/regs-mem.h b/arch/arm/mach-ks8695/regs-mem.h deleted file mode 100644 index 55806bc68ce3..000000000000 --- a/arch/arm/mach-ks8695/regs-mem.h +++ /dev/null @@ -1,89 +0,0 @@ -/* - * arch/arm/mach-ks8695/include/mach/regs-mem.h - * - * Copyright (C) 2006 Andrew Victor - * - * KS8695 - Memory Controller registers and bit definitions - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef KS8695_MEM_H -#define KS8695_MEM_H - -#define KS8695_MEM_OFFSET (0xF0000 + 0x4000) -#define KS8695_MEM_VA (KS8695_IO_VA + KS8695_MEM_OFFSET) -#define KS8695_MEM_PA (KS8695_IO_PA + KS8695_MEM_OFFSET) - - -/* - * Memory Controller Registers - */ -#define KS8695_EXTACON0 (0x00) /* External I/O 0 Access Control */ -#define KS8695_EXTACON1 (0x04) /* External I/O 1 Access Control */ -#define KS8695_EXTACON2 (0x08) /* External I/O 2 Access Control */ -#define KS8695_ROMCON0 (0x10) /* ROM/SRAM/Flash 1 Control Register */ -#define KS8695_ROMCON1 (0x14) /* ROM/SRAM/Flash 2 Control Register */ -#define KS8695_ERGCON (0x20) /* External I/O and ROM/SRAM/Flash General Register */ -#define KS8695_SDCON0 (0x30) /* SDRAM Control Register 0 */ -#define KS8695_SDCON1 (0x34) /* SDRAM Control Register 1 */ -#define KS8695_SDGCON (0x38) /* SDRAM General Control */ -#define KS8695_SDBCON (0x3c) /* SDRAM Buffer Control */ -#define KS8695_REFTIM (0x40) /* SDRAM Refresh Timer */ - - -/* External I/O Access Control Registers */ -#define EXTACON_EBNPTR (0x3ff << 22) /* Last Address Pointer */ -#define EXTACON_EBBPTR (0x3ff << 12) /* Base Pointer */ -#define EXTACON_EBTACT (7 << 9) /* Write Enable/Output Enable Active Time */ -#define EXTACON_EBTCOH (7 << 6) /* Chip Select Hold Time */ -#define EXTACON_EBTACS (7 << 3) /* Address Setup Time before ECSN */ -#define EXTACON_EBTCOS (7 << 0) /* Chip Select Time before OEN */ - -/* ROM/SRAM/Flash Control Register */ -#define ROMCON_RBNPTR (0x3ff << 22) /* Next Pointer */ -#define ROMCON_RBBPTR (0x3ff << 12) /* Base Pointer */ -#define ROMCON_RBTACC (7 << 4) /* Access Cycle Time */ -#define ROMCON_RBTPA (3 << 2) /* Page Address Access Time */ -#define ROMCON_PMC (3 << 0) /* Page Mode Configuration */ -#define PMC_NORMAL (0 << 0) -#define PMC_4WORD (1 << 0) -#define PMC_8WORD (2 << 0) -#define PMC_16WORD (3 << 0) - -/* External I/O and ROM/SRAM/Flash General Register */ -#define ERGCON_TMULT (3 << 28) /* Time Multiplier */ -#define ERGCON_DSX2 (3 << 20) /* Data Width (External I/O Bank 2) */ -#define ERGCON_DSX1 (3 << 18) /* Data Width (External I/O Bank 1) */ -#define ERGCON_DSX0 (3 << 16) /* Data Width (External I/O Bank 0) */ -#define ERGCON_DSR1 (3 << 2) /* Data Width (ROM/SRAM/Flash Bank 1) */ -#define ERGCON_DSR0 (3 << 0) /* Data Width (ROM/SRAM/Flash Bank 0) */ - -/* SDRAM Control Register */ -#define SDCON_DBNPTR (0x3ff << 22) /* Last Address Pointer */ -#define SDCON_DBBPTR (0x3ff << 12) /* Base Pointer */ -#define SDCON_DBCAB (3 << 8) /* Column Address Bits */ -#define SDCON_DBBNUM (1 << 3) /* Number of Banks */ -#define SDCON_DBDBW (3 << 1) /* Data Bus Width */ - -/* SDRAM General Control Register */ -#define SDGCON_SDTRC (3 << 2) /* RAS to CAS latency */ -#define SDGCON_SDCAS (3 << 0) /* CAS latency */ - -/* SDRAM Buffer Control Register */ -#define SDBCON_SDESTA (1 << 31) /* SDRAM Engine Status */ -#define SDBCON_RBUFBDIS (1 << 24) /* Read Buffer Burst Enable */ -#define SDBCON_WFIFOEN (1 << 23) /* Write FIFO Enable */ -#define SDBCON_RBUFEN (1 << 22) /* Read Buffer Enable */ -#define SDBCON_FLUSHWFIFO (1 << 21) /* Flush Write FIFO */ -#define SDBCON_RBUFINV (1 << 20) /* Read Buffer Invalidate */ -#define SDBCON_SDINI (3 << 16) /* SDRAM Initialization Control */ -#define SDBCON_SDMODE (0x3fff << 0) /* SDRAM Mode Register Value Program */ - -/* SDRAM Refresh Timer Register */ -#define REFTIM_REFTIM (0xffff << 0) /* Refresh Timer Value */ - - -#endif diff --git a/arch/arm/mach-ks8695/regs-pci.h b/arch/arm/mach-ks8695/regs-pci.h deleted file mode 100644 index 75a9db6edbd9..000000000000 --- a/arch/arm/mach-ks8695/regs-pci.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * arch/arm/mach-ks8695/include/mach/regs-pci.h - * - * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> - * Copyright (C) 2006 Simtec Electronics - * - * KS8695 - PCI bridge registers and bit definitions. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#define KS8695_PCI_OFFSET (0xF0000 + 0x2000) -#define KS8695_PCI_VA (KS8695_IO_VA + KS8695_PCI_OFFSET) -#define KS8695_PCI_PA (KS8695_IO_PA + KS8695_PCI_OFFSET) - - -#define KS8695_CRCFID (0x000) /* Configuration: Identification */ -#define KS8695_CRCFCS (0x004) /* Configuration: Command and Status */ -#define KS8695_CRCFRV (0x008) /* Configuration: Revision */ -#define KS8695_CRCFLT (0x00C) /* Configuration: Latency Timer */ -#define KS8695_CRCBMA (0x010) /* Configuration: Base Memory Address */ -#define KS8695_CRCSID (0x02C) /* Configuration: Subsystem ID */ -#define KS8695_CRCFIT (0x03C) /* Configuration: Interrupt */ -#define KS8695_PBCA (0x100) /* Bridge Configuration Address */ -#define KS8695_PBCD (0x104) /* Bridge Configuration Data */ -#define KS8695_PBM (0x200) /* Bridge Mode */ -#define KS8695_PBCS (0x204) /* Bridge Control and Status */ -#define KS8695_PMBA (0x208) /* Bridge Memory Base Address */ -#define KS8695_PMBAC (0x20C) /* Bridge Memory Base Address Control */ -#define KS8695_PMBAM (0x210) /* Bridge Memory Base Address Mask */ -#define KS8695_PMBAT (0x214) /* Bridge Memory Base Address Translation */ -#define KS8695_PIOBA (0x218) /* Bridge I/O Base Address */ -#define KS8695_PIOBAC (0x21C) /* Bridge I/O Base Address Control */ -#define KS8695_PIOBAM (0x220) /* Bridge I/O Base Address Mask */ -#define KS8695_PIOBAT (0x224) /* Bridge I/O Base Address Translation */ - - -/* Configuration: Identification */ - -/* Configuration: Command and Status */ - -/* Configuration: Revision */ - - - -#define CFRV_GUEST (1 << 23) - -#define PBCA_TYPE1 (1) -#define PBCA_ENABLE (1 << 31) - - diff --git a/arch/arm/mach-ks8695/regs-sys.h b/arch/arm/mach-ks8695/regs-sys.h deleted file mode 100644 index 57c20be0c129..000000000000 --- a/arch/arm/mach-ks8695/regs-sys.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * arch/arm/mach-ks8695/include/mach/regs-sys.h - * - * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> - * Copyright (C) 2006 Simtec Electronics - * - * KS8695 - System control registers and bit definitions - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef KS8695_SYS_H -#define KS8695_SYS_H - -#define KS8695_SYS_OFFSET (0xF0000 + 0x0000) -#define KS8695_SYS_VA (KS8695_IO_VA + KS8695_SYS_OFFSET) -#define KS8695_SYS_PA (KS8695_IO_PA + KS8695_SYS_OFFSET) - - -#define KS8695_SYSCFG (0x00) /* System Configuration Register */ -#define KS8695_CLKCON (0x04) /* System Clock and Bus Control Register */ - - -/* System Configuration Register */ -#define SYSCFG_SPRBP (0x3ff << 16) /* Register Bank Base Pointer */ - -/* System Clock and Bus Control Register */ -#define CLKCON_SFMODE (1 << 8) /* System Fast Mode for Simulation */ -#define CLKCON_SCDC (7 << 0) /* System Clock Divider Select */ - - -#endif diff --git a/arch/arm/mach-ks8695/regs-wan.h b/arch/arm/mach-ks8695/regs-wan.h deleted file mode 100644 index c475bed22b8e..000000000000 --- a/arch/arm/mach-ks8695/regs-wan.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - * arch/arm/mach-ks8695/include/mach/regs-wan.h - * - * Copyright (C) 2006 Andrew Victor - * - * KS8695 - WAN Registers and bit definitions. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef KS8695_WAN_H -#define KS8695_WAN_H - -#define KS8695_WAN_OFFSET (0xF0000 + 0x6000) -#define KS8695_WAN_VA (KS8695_IO_VA + KS8695_WAN_OFFSET) -#define KS8695_WAN_PA (KS8695_IO_PA + KS8695_WAN_OFFSET) - - -/* - * WAN registers - */ -#define KS8695_WMDTXC (0x00) /* DMA Transmit Control */ -#define KS8695_WMDRXC (0x04) /* DMA Receive Control */ -#define KS8695_WMDTSC (0x08) /* DMA Transmit Start Command */ -#define KS8695_WMDRSC (0x0c) /* DMA Receive Start Command */ -#define KS8695_WTDLB (0x10) /* Transmit Descriptor List Base Address */ -#define KS8695_WRDLB (0x14) /* Receive Descriptor List Base Address */ -#define KS8695_WMAL (0x18) /* MAC Station Address Low */ -#define KS8695_WMAH (0x1c) /* MAC Station Address High */ -#define KS8695_WMAAL(n) (0x80 + ((n)*8)) /* MAC Additional Station Address (0..15) Low */ -#define KS8695_WMAAH(n) (0x84 + ((n)*8)) /* MAC Additional Station Address (0..15) High */ - - -/* DMA Transmit Control Register */ -#define WMDTXC_WMTRST (1 << 31) /* Soft Reset */ -#define WMDTXC_WMTBS (0x3f << 24) /* Transmit Burst Size */ -#define WMDTXC_WMTUCG (1 << 18) /* Transmit UDP Checksum Generate */ -#define WMDTXC_WMTTCG (1 << 17) /* Transmit TCP Checksum Generate */ -#define WMDTXC_WMTICG (1 << 16) /* Transmit IP Checksum Generate */ -#define WMDTXC_WMTFCE (1 << 9) /* Transmit Flow Control Enable */ -#define WMDTXC_WMTLB (1 << 8) /* Loopback mode */ -#define WMDTXC_WMTEP (1 << 2) /* Transmit Enable Padding */ -#define WMDTXC_WMTAC (1 << 1) /* Transmit Add CRC */ -#define WMDTXC_WMTE (1 << 0) /* TX Enable */ - -/* DMA Receive Control Register */ -#define WMDRXC_WMRBS (0x3f << 24) /* Receive Burst Size */ -#define WMDRXC_WMRUCC (1 << 18) /* Receive UDP Checksum check */ -#define WMDRXC_WMRTCG (1 << 17) /* Receive TCP Checksum check */ -#define WMDRXC_WMRICG (1 << 16) /* Receive IP Checksum check */ -#define WMDRXC_WMRFCE (1 << 9) /* Receive Flow Control Enable */ -#define WMDRXC_WMRB (1 << 6) /* Receive Broadcast */ -#define WMDRXC_WMRM (1 << 5) /* Receive Multicast */ -#define WMDRXC_WMRU (1 << 4) /* Receive Unicast */ -#define WMDRXC_WMRERR (1 << 3) /* Receive Error Frame */ -#define WMDRXC_WMRA (1 << 2) /* Receive All */ -#define WMDRXC_WMRE (1 << 0) /* RX Enable */ - -/* Additional Station Address High */ -#define WMAAH_E (1 << 31) /* Address Enabled */ - - -#endif diff --git a/arch/arm/mach-ks8695/time.c b/arch/arm/mach-ks8695/time.c deleted file mode 100644 index 50561eec0c32..000000000000 --- a/arch/arm/mach-ks8695/time.c +++ /dev/null @@ -1,159 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * arch/arm/mach-ks8695/time.c - * - * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> - * Copyright (C) 2006 Simtec Electronics - */ - -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/irq.h> -#include <linux/kernel.h> -#include <linux/sched.h> -#include <linux/io.h> -#include <linux/clockchips.h> - -#include <asm/mach/time.h> -#include <asm/system_misc.h> - -#include <mach/regs-irq.h> - -#include "generic.h" - -#define KS8695_TMR_OFFSET (0xF0000 + 0xE400) -#define KS8695_TMR_VA (KS8695_IO_VA + KS8695_TMR_OFFSET) -#define KS8695_TMR_PA (KS8695_IO_PA + KS8695_TMR_OFFSET) - -/* - * Timer registers - */ -#define KS8695_TMCON (0x00) /* Timer Control Register */ -#define KS8695_T1TC (0x04) /* Timer 1 Timeout Count Register */ -#define KS8695_T0TC (0x08) /* Timer 0 Timeout Count Register */ -#define KS8695_T1PD (0x0C) /* Timer 1 Pulse Count Register */ -#define KS8695_T0PD (0x10) /* Timer 0 Pulse Count Register */ - -/* Timer Control Register */ -#define TMCON_T1EN (1 << 1) /* Timer 1 Enable */ -#define TMCON_T0EN (1 << 0) /* Timer 0 Enable */ - -/* Timer0 Timeout Counter Register */ -#define T0TC_WATCHDOG (0xff) /* Enable watchdog mode */ - -static int ks8695_set_periodic(struct clock_event_device *evt) -{ - u32 rate = DIV_ROUND_CLOSEST(KS8695_CLOCK_RATE, HZ); - u32 half = DIV_ROUND_CLOSEST(rate, 2); - u32 tmcon; - - /* Disable timer 1 */ - tmcon = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON); - tmcon &= ~TMCON_T1EN; - writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON); - - /* Both registers need to count down */ - writel_relaxed(half, KS8695_TMR_VA + KS8695_T1TC); - writel_relaxed(half, KS8695_TMR_VA + KS8695_T1PD); - - /* Re-enable timer1 */ - tmcon |= TMCON_T1EN; - writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON); - return 0; -} - -static int ks8695_set_next_event(unsigned long cycles, - struct clock_event_device *evt) - -{ - u32 half = DIV_ROUND_CLOSEST(cycles, 2); - u32 tmcon; - - /* Disable timer 1 */ - tmcon = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON); - tmcon &= ~TMCON_T1EN; - writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON); - - /* Both registers need to count down */ - writel_relaxed(half, KS8695_TMR_VA + KS8695_T1TC); - writel_relaxed(half, KS8695_TMR_VA + KS8695_T1PD); - - /* Re-enable timer1 */ - tmcon |= TMCON_T1EN; - writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON); - - return 0; -} - -static struct clock_event_device clockevent_ks8695 = { - .name = "ks8695_t1tc", - /* Reasonably fast and accurate clock event */ - .rating = 300, - .features = CLOCK_EVT_FEAT_ONESHOT | - CLOCK_EVT_FEAT_PERIODIC, - .set_next_event = ks8695_set_next_event, - .set_state_periodic = ks8695_set_periodic, -}; - -/* - * IRQ handler for the timer. - */ -static irqreturn_t ks8695_timer_interrupt(int irq, void *dev_id) -{ - struct clock_event_device *evt = &clockevent_ks8695; - - evt->event_handler(evt); - return IRQ_HANDLED; -} - -static struct irqaction ks8695_timer_irq = { - .name = "ks8695_tick", - .flags = IRQF_TIMER, - .handler = ks8695_timer_interrupt, -}; - -static void ks8695_timer_setup(void) -{ - unsigned long tmcon; - - /* Disable timer 0 and 1 */ - tmcon = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON); - tmcon &= ~TMCON_T0EN; - tmcon &= ~TMCON_T1EN; - writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON); - - /* - * Use timer 1 to fire IRQs on the timeline, minimum 2 cycles - * (one on each counter) maximum 2*2^32, but the API will only - * accept up to a 32bit full word (0xFFFFFFFFU). - */ - clockevents_config_and_register(&clockevent_ks8695, - KS8695_CLOCK_RATE, 2, - 0xFFFFFFFFU); -} - -void __init ks8695_timer_init(void) -{ - ks8695_timer_setup(); - - /* Enable timer interrupts */ - setup_irq(KS8695_IRQ_TIMER1, &ks8695_timer_irq); -} - -void ks8695_restart(enum reboot_mode reboot_mode, const char *cmd) -{ - unsigned int reg; - - if (reboot_mode == REBOOT_SOFT) - soft_restart(0); - - /* disable timer0 */ - reg = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON); - writel_relaxed(reg & ~TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON); - - /* enable watchdog mode */ - writel_relaxed((10 << 8) | T0TC_WATCHDOG, KS8695_TMR_VA + KS8695_T0TC); - - /* re-enable timer0 */ - writel_relaxed(reg | TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON); -} diff --git a/arch/arm/mach-lpc32xx/Kconfig b/arch/arm/mach-lpc32xx/Kconfig new file mode 100644 index 000000000000..ec87c65f4536 --- /dev/null +++ b/arch/arm/mach-lpc32xx/Kconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config ARCH_LPC32XX + bool "NXP LPC32XX" + depends on ARCH_MULTI_V5 + select ARM_AMBA + select CLKSRC_LPC32XX + select CPU_ARM926T + select GPIOLIB + help + Support for the NXP LPC32XX family of processors diff --git a/arch/arm/mach-lpc32xx/common.c b/arch/arm/mach-lpc32xx/common.c index 5b71b4fab2cd..304ea61a0716 100644 --- a/arch/arm/mach-lpc32xx/common.c +++ b/arch/arm/mach-lpc32xx/common.c @@ -8,12 +8,12 @@ */ #include <linux/init.h> +#include <linux/soc/nxp/lpc32xx-misc.h> #include <asm/mach/map.h> #include <asm/system_info.h> -#include <mach/hardware.h> -#include <mach/platform.h> +#include "lpc32xx.h" #include "common.h" /* @@ -32,7 +32,7 @@ void lpc32xx_get_uid(u32 devid[4]) */ #define LPC32XX_IRAM_BANK_SIZE SZ_128K static u32 iram_size; -u32 lpc32xx_return_iram_size(void) +u32 lpc32xx_return_iram(void __iomem **mapbase, dma_addr_t *dmaaddr) { if (iram_size == 0) { u32 savedval1, savedval2; @@ -53,10 +53,26 @@ u32 lpc32xx_return_iram_size(void) } else iram_size = LPC32XX_IRAM_BANK_SIZE * 2; } + if (dmaaddr) + *dmaaddr = LPC32XX_IRAM_BASE; + if (mapbase) + *mapbase = io_p2v(LPC32XX_IRAM_BASE); return iram_size; } -EXPORT_SYMBOL_GPL(lpc32xx_return_iram_size); +EXPORT_SYMBOL_GPL(lpc32xx_return_iram); + +void lpc32xx_set_phy_interface_mode(phy_interface_t mode) +{ + u32 tmp = __raw_readl(LPC32XX_CLKPWR_MACCLK_CTRL); + tmp &= ~LPC32XX_CLKPWR_MACCTRL_PINS_MSK; + if (mode == PHY_INTERFACE_MODE_MII) + tmp |= LPC32XX_CLKPWR_MACCTRL_USE_MII_PINS; + else + tmp |= LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS; + __raw_writel(tmp, LPC32XX_CLKPWR_MACCLK_CTRL); +} +EXPORT_SYMBOL_GPL(lpc32xx_set_phy_interface_mode); static struct map_desc lpc32xx_io_desc[] __initdata = { { diff --git a/arch/arm/mach-lpc32xx/common.h b/arch/arm/mach-lpc32xx/common.h index 8e597ce48a73..32f0ad217807 100644 --- a/arch/arm/mach-lpc32xx/common.h +++ b/arch/arm/mach-lpc32xx/common.h @@ -23,7 +23,6 @@ extern void __init lpc32xx_serial_init(void); */ extern void lpc32xx_get_uid(u32 devid[4]); -extern u32 lpc32xx_return_iram_size(void); /* * Pointers used for sizing and copying suspend function data */ diff --git a/arch/arm/mach-lpc32xx/include/mach/board.h b/arch/arm/mach-lpc32xx/include/mach/board.h deleted file mode 100644 index 476513d970a4..000000000000 --- a/arch/arm/mach-lpc32xx/include/mach/board.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * arm/arch/mach-lpc32xx/include/mach/board.h - * - * Author: Kevin Wells <kevin.wells@nxp.com> - * - * Copyright (C) 2010 NXP Semiconductors - */ - -#ifndef __ASM_ARCH_BOARD_H -#define __ASM_ARCH_BOARD_H - -extern u32 lpc32xx_return_iram_size(void); - -#endif /* __ASM_ARCH_BOARD_H */ diff --git a/arch/arm/mach-lpc32xx/include/mach/entry-macro.S b/arch/arm/mach-lpc32xx/include/mach/entry-macro.S deleted file mode 100644 index eec0f5f7e722..000000000000 --- a/arch/arm/mach-lpc32xx/include/mach/entry-macro.S +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * arch/arm/mach-lpc32xx/include/mach/entry-macro.S - * - * Author: Kevin Wells <kevin.wells@nxp.com> - * - * Copyright (C) 2010 NXP Semiconductors - */ - -#include <mach/hardware.h> -#include <mach/platform.h> - -#define LPC32XX_INTC_MASKED_STATUS_OFS 0x8 - - .macro get_irqnr_preamble, base, tmp - ldr \base, =IO_ADDRESS(LPC32XX_MIC_BASE) - .endm - -/* - * Return IRQ number in irqnr. Also return processor Z flag status in CPSR - * as set if an interrupt is pending. - */ - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - ldr \irqstat, [\base, #LPC32XX_INTC_MASKED_STATUS_OFS] - clz \irqnr, \irqstat - rsb \irqnr, \irqnr, #31 - teq \irqstat, #0 - .endm diff --git a/arch/arm/mach-lpc32xx/include/mach/hardware.h b/arch/arm/mach-lpc32xx/include/mach/hardware.h deleted file mode 100644 index 4866f096ffce..000000000000 --- a/arch/arm/mach-lpc32xx/include/mach/hardware.h +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * arch/arm/mach-lpc32xx/include/mach/hardware.h - * - * Copyright (c) 2005 MontaVista Software, Inc. <source@mvista.com> - */ - -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -/* - * Start of virtual addresses for IO devices - */ -#define IO_BASE 0xF0000000 - -/* - * This macro relies on fact that for all HW i/o addresses bits 20-23 are 0 - */ -#define IO_ADDRESS(x) IOMEM(((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) |\ - IO_BASE) - -#define io_p2v(x) ((void __iomem *) (unsigned long) IO_ADDRESS(x)) -#define io_v2p(x) ((((x) & 0x0ff00000) << 4) | ((x) & 0x000fffff)) - -#endif diff --git a/arch/arm/mach-lpc32xx/include/mach/uncompress.h b/arch/arm/mach-lpc32xx/include/mach/uncompress.h deleted file mode 100644 index a568812a0b91..000000000000 --- a/arch/arm/mach-lpc32xx/include/mach/uncompress.h +++ /dev/null @@ -1,50 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * arch/arm/mach-lpc32xx/include/mach/uncompress.h - * - * Author: Kevin Wells <kevin.wells@nxp.com> - * - * Copyright (C) 2010 NXP Semiconductors - */ - -#ifndef __ASM_ARM_ARCH_UNCOMPRESS_H -#define __ASM_ARM_ARCH_UNCOMPRESS_H - -#include <linux/io.h> - -#include <mach/hardware.h> -#include <mach/platform.h> - -/* - * Uncompress output is hardcoded to standard UART 5 - */ - -#define UART_FIFO_CTL_TX_RESET (1 << 2) -#define UART_STATUS_TX_MT (1 << 6) - -#define _UARTREG(x) (void __iomem *)(LPC32XX_UART5_BASE + (x)) - -#define LPC32XX_UART_DLLFIFO_O 0x00 -#define LPC32XX_UART_IIRFCR_O 0x08 -#define LPC32XX_UART_LSR_O 0x14 - -static inline void putc(int ch) -{ - /* Wait for transmit FIFO to empty */ - while ((__raw_readl(_UARTREG(LPC32XX_UART_LSR_O)) & - UART_STATUS_TX_MT) == 0) - ; - - __raw_writel((u32) ch, _UARTREG(LPC32XX_UART_DLLFIFO_O)); -} - -static inline void flush(void) -{ - __raw_writel(__raw_readl(_UARTREG(LPC32XX_UART_IIRFCR_O)) | - UART_FIFO_CTL_TX_RESET, _UARTREG(LPC32XX_UART_IIRFCR_O)); -} - -/* NULL functions; we don't presently need them */ -#define arch_decomp_setup() - -#endif diff --git a/arch/arm/mach-lpc32xx/include/mach/platform.h b/arch/arm/mach-lpc32xx/lpc32xx.h index 1c53790444fc..5eeb884a1993 100644 --- a/arch/arm/mach-lpc32xx/include/mach/platform.h +++ b/arch/arm/mach-lpc32xx/lpc32xx.h @@ -7,8 +7,8 @@ * Copyright (C) 2010 NXP Semiconductors */ -#ifndef __ASM_ARCH_PLATFORM_H -#define __ASM_ARCH_PLATFORM_H +#ifndef __ARM_LPC32XX_H +#define __ARM_LPC32XX_H #define _SBF(f, v) ((v) << (f)) #define _BIT(n) _SBF(n, 1) @@ -700,4 +700,18 @@ #define LPC32XX_USB_OTG_DEV_CLOCK_ON _BIT(1) #define LPC32XX_USB_OTG_HOST_CLOCK_ON _BIT(0) +/* + * Start of virtual addresses for IO devices + */ +#define IO_BASE 0xF0000000 + +/* + * This macro relies on fact that for all HW i/o addresses bits 20-23 are 0 + */ +#define IO_ADDRESS(x) IOMEM(((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) |\ + IO_BASE) + +#define io_p2v(x) ((void __iomem *) (unsigned long) IO_ADDRESS(x)) +#define io_v2p(x) ((((x) & 0x0ff00000) << 4) | ((x) & 0x000fffff)) + #endif diff --git a/arch/arm/mach-lpc32xx/pm.c b/arch/arm/mach-lpc32xx/pm.c index 32bca351a73b..b27fa1b9f56c 100644 --- a/arch/arm/mach-lpc32xx/pm.c +++ b/arch/arm/mach-lpc32xx/pm.c @@ -70,8 +70,7 @@ #include <asm/cacheflush.h> -#include <mach/hardware.h> -#include <mach/platform.h> +#include "lpc32xx.h" #include "common.h" #define TEMP_IRAM_AREA IO_ADDRESS(LPC32XX_IRAM_BASE) diff --git a/arch/arm/mach-lpc32xx/serial.c b/arch/arm/mach-lpc32xx/serial.c index 3f9b30df9f0e..3e765c4bf986 100644 --- a/arch/arm/mach-lpc32xx/serial.c +++ b/arch/arm/mach-lpc32xx/serial.c @@ -16,8 +16,7 @@ #include <linux/clk.h> #include <linux/io.h> -#include <mach/hardware.h> -#include <mach/platform.h> +#include "lpc32xx.h" #include "common.h" #define LPC32XX_SUART_FIFO_SIZE 64 @@ -60,6 +59,36 @@ static struct uartinit uartinit_data[] __initdata = { }, }; +/* LPC3250 Errata HSUART.1: Hang workaround via loopback mode on inactivity */ +void lpc32xx_loopback_set(resource_size_t mapbase, int state) +{ + int bit; + u32 tmp; + + switch (mapbase) { + case LPC32XX_HS_UART1_BASE: + bit = 0; + break; + case LPC32XX_HS_UART2_BASE: + bit = 1; + break; + case LPC32XX_HS_UART7_BASE: + bit = 6; + break; + default: + WARN(1, "lpc32xx_hs: Warning: Unknown port at %08x\n", mapbase); + return; + } + + tmp = readl(LPC32XX_UARTCTL_CLOOP); + if (state) + tmp |= (1 << bit); + else + tmp &= ~(1 << bit); + writel(tmp, LPC32XX_UARTCTL_CLOOP); +} +EXPORT_SYMBOL_GPL(lpc32xx_loopback_set); + void __init lpc32xx_serial_init(void) { u32 tmp, clkmodes = 0; diff --git a/arch/arm/mach-lpc32xx/suspend.S b/arch/arm/mach-lpc32xx/suspend.S index 374f9f07fe48..3f0a8282ef6f 100644 --- a/arch/arm/mach-lpc32xx/suspend.S +++ b/arch/arm/mach-lpc32xx/suspend.S @@ -11,8 +11,7 @@ */ #include <linux/linkage.h> #include <asm/assembler.h> -#include <mach/platform.h> -#include <mach/hardware.h> +#include "lpc32xx.h" /* Using named register defines makes the code easier to follow */ #define WORK1_REG r0 diff --git a/arch/arm/mach-mv78xx0/mv78xx0.h b/arch/arm/mach-mv78xx0/mv78xx0.h index 2db1265ec121..c1a9a1d1b295 100644 --- a/arch/arm/mach-mv78xx0/mv78xx0.h +++ b/arch/arm/mach-mv78xx0/mv78xx0.h @@ -37,7 +37,7 @@ * fee50000 f0d00000 64K PCIe #5 I/O space * fee60000 f0e00000 64K PCIe #6 I/O space * fee70000 f0f00000 64K PCIe #7 I/O space - * fd000000 f1000000 1M on-chip peripheral registers + * fec00000 f1000000 1M on-chip peripheral registers */ #define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000 #define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000 @@ -49,7 +49,7 @@ #define MV78XX0_PCIE_IO_SIZE SZ_1M #define MV78XX0_REGS_PHYS_BASE 0xf1000000 -#define MV78XX0_REGS_VIRT_BASE IOMEM(0xfd000000) +#define MV78XX0_REGS_VIRT_BASE IOMEM(0xfec00000) #define MV78XX0_REGS_SIZE SZ_1M #define MV78XX0_PCIE_MEM_PHYS_BASE 0xc0000000 diff --git a/arch/arm/mach-nspire/Makefile b/arch/arm/mach-nspire/Makefile index 1d568c600452..4716b9b9aa7b 100644 --- a/arch/arm/mach-nspire/Makefile +++ b/arch/arm/mach-nspire/Makefile @@ -1,3 +1,2 @@ # SPDX-License-Identifier: GPL-2.0-only obj-y += nspire.o -obj-y += clcd.o diff --git a/arch/arm/mach-nspire/clcd.c b/arch/arm/mach-nspire/clcd.c deleted file mode 100644 index 44738dcb391d..000000000000 --- a/arch/arm/mach-nspire/clcd.c +++ /dev/null @@ -1,114 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/mach-nspire/clcd.c - * - * Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au> - */ - -#include <linux/init.h> -#include <linux/of.h> -#include <linux/amba/bus.h> -#include <linux/amba/clcd.h> -#include <linux/dma-mapping.h> - -static struct clcd_panel nspire_cx_lcd_panel = { - .mode = { - .name = "Color LCD", - .refresh = 60, - .xres = 320, - .yres = 240, - .sync = 0, - .vmode = FB_VMODE_NONINTERLACED, - .pixclock = 1, - .hsync_len = 6, - .vsync_len = 1, - .right_margin = 50, - .left_margin = 38, - .lower_margin = 3, - .upper_margin = 17, - }, - .width = 65, /* ~6.50 cm */ - .height = 49, /* ~4.87 cm */ - .tim2 = TIM2_IPC, - .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1), - .bpp = 16, - .caps = CLCD_CAP_565, -}; - -static struct clcd_panel nspire_classic_lcd_panel = { - .mode = { - .name = "Grayscale LCD", - .refresh = 60, - .xres = 320, - .yres = 240, - .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, - .vmode = FB_VMODE_NONINTERLACED, - .pixclock = 1, - .hsync_len = 6, - .vsync_len = 1, - .right_margin = 6, - .left_margin = 6, - }, - .width = 71, /* 7.11cm */ - .height = 53, /* 5.33cm */ - .tim2 = 0x80007d0, - .cntl = CNTL_LCDMONO8, - .bpp = 8, - .grayscale = 1, - .caps = CLCD_CAP_5551, -}; - -int nspire_clcd_setup(struct clcd_fb *fb) -{ - struct clcd_panel *panel; - size_t panel_size; - const char *type; - dma_addr_t dma; - int err; - - BUG_ON(!fb->dev->dev.of_node); - - err = of_property_read_string(fb->dev->dev.of_node, "lcd-type", &type); - if (err) { - pr_err("CLCD: Could not find lcd-type property\n"); - return err; - } - - if (!strcmp(type, "cx")) { - panel = &nspire_cx_lcd_panel; - } else if (!strcmp(type, "classic")) { - panel = &nspire_classic_lcd_panel; - } else { - pr_err("CLCD: Unknown lcd-type %s\n", type); - return -EINVAL; - } - - panel_size = ((panel->mode.xres * panel->mode.yres) * panel->bpp) / 8; - panel_size = ALIGN(panel_size, PAGE_SIZE); - - fb->fb.screen_base = dma_alloc_wc(&fb->dev->dev, panel_size, &dma, - GFP_KERNEL); - - if (!fb->fb.screen_base) { - pr_err("CLCD: unable to map framebuffer\n"); - return -ENOMEM; - } - - fb->fb.fix.smem_start = dma; - fb->fb.fix.smem_len = panel_size; - fb->panel = panel; - - return 0; -} - -int nspire_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma) -{ - return dma_mmap_wc(&fb->dev->dev, vma, fb->fb.screen_base, - fb->fb.fix.smem_start, fb->fb.fix.smem_len); -} - -void nspire_clcd_remove(struct clcd_fb *fb) -{ - dma_free_wc(&fb->dev->dev, fb->fb.fix.smem_len, fb->fb.screen_base, - fb->fb.fix.smem_start); -} diff --git a/arch/arm/mach-nspire/clcd.h b/arch/arm/mach-nspire/clcd.h deleted file mode 100644 index 7f36bd8511c5..000000000000 --- a/arch/arm/mach-nspire/clcd.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * linux/arch/arm/mach-nspire/clcd.h - * - * Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au> - */ - -int nspire_clcd_setup(struct clcd_fb *fb); -int nspire_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma); -void nspire_clcd_remove(struct clcd_fb *fb); diff --git a/arch/arm/mach-nspire/nspire.c b/arch/arm/mach-nspire/nspire.c index 957bd0c0fbd5..2d4abb0288b9 100644 --- a/arch/arm/mach-nspire/nspire.c +++ b/arch/arm/mach-nspire/nspire.c @@ -12,14 +12,12 @@ #include <linux/irqchip/arm-vic.h> #include <linux/clkdev.h> #include <linux/amba/bus.h> -#include <linux/amba/clcd.h> #include <asm/mach/arch.h> #include <asm/mach-types.h> #include <asm/mach/map.h> #include "mmio.h" -#include "clcd.h" static const char *const nspire_dt_match[] __initconst = { "ti,nspire", @@ -29,28 +27,6 @@ static const char *const nspire_dt_match[] __initconst = { NULL, }; -static struct clcd_board nspire_clcd_data = { - .name = "LCD", - .caps = CLCD_CAP_5551 | CLCD_CAP_565, - .check = clcdfb_check, - .decode = clcdfb_decode, - .setup = nspire_clcd_setup, - .mmap = nspire_clcd_mmap, - .remove = nspire_clcd_remove, -}; - - -static struct of_dev_auxdata nspire_auxdata[] __initdata = { - OF_DEV_AUXDATA("arm,pl111", NSPIRE_LCD_PHYS_BASE, - NULL, &nspire_clcd_data), - { } -}; - -static void __init nspire_init(void) -{ - of_platform_default_populate(NULL, nspire_auxdata, NULL); -} - static void nspire_restart(enum reboot_mode mode, const char *cmd) { void __iomem *base = ioremap(NSPIRE_MISC_PHYS_BASE, SZ_4K); @@ -62,6 +38,5 @@ static void nspire_restart(enum reboot_mode mode, const char *cmd) DT_MACHINE_START(NSPIRE, "TI-NSPIRE") .dt_compat = nspire_dt_match, - .init_machine = nspire_init, .restart = nspire_restart, MACHINE_END diff --git a/arch/arm/mach-omap2/.gitignore b/arch/arm/mach-omap2/.gitignore new file mode 100644 index 000000000000..79a8d6ea7152 --- /dev/null +++ b/arch/arm/mach-omap2/.gitignore @@ -0,0 +1 @@ +pm-asm-offsets.h diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index d4f11c5070ae..8f208197988f 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -223,11 +223,12 @@ obj-y += omap_phy_internal.o obj-$(CONFIG_MACH_OMAP2_TUSB6010) += usb-tusb6010.o -include/generated/ti-pm-asm-offsets.h: arch/arm/mach-omap2/pm-asm-offsets.s FORCE +$(obj)/pm-asm-offsets.h: $(obj)/pm-asm-offsets.s FORCE $(call filechk,offsets,__TI_PM_ASM_OFFSETS_H__) -$(obj)/sleep33xx.o $(obj)/sleep43xx.o: include/generated/ti-pm-asm-offsets.h +$(obj)/sleep33xx.o $(obj)/sleep43xx.o: $(obj)/pm-asm-offsets.h targets += pm-asm-offsets.s +clean-files += pm-asm-offsets.h obj-$(CONFIG_OMAP_IOMMU) += omap-iommu.o diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c index 14b9c13c1fa0..63423ea6a240 100644 --- a/arch/arm/mach-omap2/hsmmc.c +++ b/arch/arm/mach-omap2/hsmmc.c @@ -32,10 +32,8 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c, char *hc_name; hc_name = kzalloc(HSMMC_NAME_LEN + 1, GFP_KERNEL); - if (!hc_name) { - kfree(hc_name); + if (!hc_name) return -ENOMEM; - } snprintf(hc_name, (HSMMC_NAME_LEN + 1), "mmc%islot%i", c->mmc, 1); mmc->name = hc_name; diff --git a/arch/arm/mach-omap2/sleep33xx.S b/arch/arm/mach-omap2/sleep33xx.S index 68fee339d3f1..dc221249bc22 100644 --- a/arch/arm/mach-omap2/sleep33xx.S +++ b/arch/arm/mach-omap2/sleep33xx.S @@ -6,7 +6,6 @@ * Dave Gerlach, Vaibhav Bedia */ -#include <generated/ti-pm-asm-offsets.h> #include <linux/linkage.h> #include <linux/platform_data/pm33xx.h> #include <linux/ti-emif-sram.h> @@ -15,6 +14,7 @@ #include "iomap.h" #include "cm33xx.h" +#include "pm-asm-offsets.h" #define AM33XX_CM_CLKCTRL_MODULESTATE_DISABLED 0x00030000 #define AM33XX_CM_CLKCTRL_MODULEMODE_DISABLE 0x0003 diff --git a/arch/arm/mach-omap2/sleep43xx.S b/arch/arm/mach-omap2/sleep43xx.S index c1f4e4852644..90d2907a2eb2 100644 --- a/arch/arm/mach-omap2/sleep43xx.S +++ b/arch/arm/mach-omap2/sleep43xx.S @@ -6,7 +6,6 @@ * Dave Gerlach, Vaibhav Bedia */ -#include <generated/ti-pm-asm-offsets.h> #include <linux/linkage.h> #include <linux/ti-emif-sram.h> #include <linux/platform_data/pm33xx.h> @@ -19,6 +18,7 @@ #include "iomap.h" #include "omap-secure.h" #include "omap44xx.h" +#include "pm-asm-offsets.h" #include "prm33xx.h" #include "prcm43xx.h" diff --git a/arch/arm/mach-orion5x/orion5x.h b/arch/arm/mach-orion5x/orion5x.h index 3364df331f01..2b66120fba86 100644 --- a/arch/arm/mach-orion5x/orion5x.h +++ b/arch/arm/mach-orion5x/orion5x.h @@ -31,13 +31,13 @@ * fc000000 device bus mappings (cs0/cs1) * * virt phys size - * fe000000 f1000000 1M on-chip peripheral registers + * fec00000 f1000000 1M on-chip peripheral registers * fee00000 f2000000 64K PCIe I/O space * fee10000 f2100000 64K PCI I/O space * fd000000 f0000000 16M PCIe WA space (Orion-1/Orion-NAS only) ****************************************************************************/ #define ORION5X_REGS_PHYS_BASE 0xf1000000 -#define ORION5X_REGS_VIRT_BASE IOMEM(0xfe000000) +#define ORION5X_REGS_VIRT_BASE IOMEM(0xfec00000) #define ORION5X_REGS_SIZE SZ_1M #define ORION5X_PCIE_IO_PHYS_BASE 0xf2000000 diff --git a/arch/arm/mach-s3c64xx/setup-usb-phy.c b/arch/arm/mach-s3c64xx/setup-usb-phy.c index 46a9e955607f..6aaaa1d8e8b9 100644 --- a/arch/arm/mach-s3c64xx/setup-usb-phy.c +++ b/arch/arm/mach-s3c64xx/setup-usb-phy.c @@ -15,6 +15,11 @@ #include "regs-sys.h" #include "regs-usb-hsotg-phy.h" +enum samsung_usb_phy_type { + USB_PHY_TYPE_DEVICE, + USB_PHY_TYPE_HOST, +}; + static int s3c_usb_otgphy_init(struct platform_device *pdev) { struct clk *xusbxti; diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c index 9580525102da..3875027ef8fc 100644 --- a/arch/arm/mach-ux500/cpu-db8500.c +++ b/arch/arm/mach-ux500/cpu-db8500.c @@ -110,7 +110,6 @@ static void ux500_restart(enum reboot_mode mode, const char *cmd) static const struct of_device_id u8500_local_bus_nodes[] = { /* only create devices below soc node */ { .compatible = "stericsson,db8500", }, - { .compatible = "stericsson,db8500-prcmu", }, { .compatible = "simple-bus"}, { }, }; diff --git a/arch/arm/mach-vexpress/spc.c b/arch/arm/mach-vexpress/spc.c index 0f5381d13494..354e0e7025ae 100644 --- a/arch/arm/mach-vexpress/spc.c +++ b/arch/arm/mach-vexpress/spc.c @@ -69,7 +69,7 @@ #define A7_PERFVAL_BASE 0xC30 /* Config interface control bits */ -#define SYSCFG_START (1 << 31) +#define SYSCFG_START BIT(31) #define SYSCFG_SCC (6 << 20) #define SYSCFG_STAT (14 << 20) @@ -162,7 +162,7 @@ void ve_spc_cpu_wakeup_irq(u32 cluster, u32 cpu, bool set) if (cluster >= MAX_CLUSTERS) return; - mask = 1 << cpu; + mask = BIT(cpu); if (!cluster_is_a15(cluster)) mask <<= 4; diff --git a/arch/arm/mach-w90x900/Kconfig b/arch/arm/mach-w90x900/Kconfig deleted file mode 100644 index b16ffc03bbe5..000000000000 --- a/arch/arm/mach-w90x900/Kconfig +++ /dev/null @@ -1,50 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -if ARCH_W90X900 - -config CPU_W90P910 - bool - help - Support for W90P910 of Nuvoton W90X900 CPUs. - -config CPU_NUC950 - bool - help - Support for NUCP950 of Nuvoton NUC900 CPUs. - -config CPU_NUC960 - bool - help - Support for NUCP960 of Nuvoton NUC900 CPUs. - -menu "W90P910 Machines" - -config MACH_W90P910EVB - bool "Nuvoton W90P910 Evaluation Board" - default y - select CPU_W90P910 - help - Say Y here if you are using the Nuvoton W90P910EVB - -endmenu - -menu "NUC950 Machines" - -config MACH_W90P950EVB - bool "Nuvoton NUC950 Evaluation Board" - select CPU_NUC950 - help - Say Y here if you are using the Nuvoton NUC950EVB - -endmenu - -menu "NUC960 Machines" - -config MACH_W90N960EVB - bool "Nuvoton NUC960 Evaluation Board" - select CPU_NUC960 - help - Say Y here if you are using the Nuvoton NUC960EVB - -endmenu - -endif diff --git a/arch/arm/mach-w90x900/Makefile b/arch/arm/mach-w90x900/Makefile deleted file mode 100644 index 33b5bf53990f..000000000000 --- a/arch/arm/mach-w90x900/Makefile +++ /dev/null @@ -1,20 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# -# Makefile for the linux kernel. -# - -# Object file lists. - -obj-y := irq.o time.o mfp.o gpio.o clock.o -obj-y += clksel.o dev.o cpu.o -# W90X900 CPU support files - -obj-$(CONFIG_CPU_W90P910) += nuc910.o -obj-$(CONFIG_CPU_NUC950) += nuc950.o -obj-$(CONFIG_CPU_NUC960) += nuc960.o - -# machine support - -obj-$(CONFIG_MACH_W90P910EVB) += mach-nuc910evb.o -obj-$(CONFIG_MACH_W90P950EVB) += mach-nuc950evb.o -obj-$(CONFIG_MACH_W90N960EVB) += mach-nuc960evb.o diff --git a/arch/arm/mach-w90x900/Makefile.boot b/arch/arm/mach-w90x900/Makefile.boot deleted file mode 100644 index 07d1b3b23ac0..000000000000 --- a/arch/arm/mach-w90x900/Makefile.boot +++ /dev/null @@ -1,4 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -zreladdr-y += 0x00008000 -params_phys-y := 0x00000100 - diff --git a/arch/arm/mach-w90x900/clksel.c b/arch/arm/mach-w90x900/clksel.c deleted file mode 100644 index b50577a5a840..000000000000 --- a/arch/arm/mach-w90x900/clksel.c +++ /dev/null @@ -1,88 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/mach-w90x900/clksel.c - * - * Copyright (c) 2008 Nuvoton technology corporation - * - * Wan ZongShun <mcuos.com@gmail.com> - */ - -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/device.h> -#include <linux/list.h> -#include <linux/errno.h> -#include <linux/err.h> -#include <linux/string.h> -#include <linux/clk.h> -#include <linux/mutex.h> -#include <linux/io.h> - -#include <mach/hardware.h> -#include <mach/regs-clock.h> - -#define PLL0 0x00 -#define PLL1 0x01 -#define OTHER 0x02 -#define EXT 0x03 -#define MSOFFSET 0x0C -#define ATAOFFSET 0x0a -#define LCDOFFSET 0x06 -#define AUDOFFSET 0x04 -#define CPUOFFSET 0x00 - -static DEFINE_MUTEX(clksel_sem); - -static void clock_source_select(const char *dev_id, unsigned int clkval) -{ - unsigned int clksel, offset; - - clksel = __raw_readl(REG_CLKSEL); - - if (strcmp(dev_id, "nuc900-ms") == 0) - offset = MSOFFSET; - else if (strcmp(dev_id, "nuc900-atapi") == 0) - offset = ATAOFFSET; - else if (strcmp(dev_id, "nuc900-lcd") == 0) - offset = LCDOFFSET; - else if (strcmp(dev_id, "nuc900-ac97") == 0) - offset = AUDOFFSET; - else - offset = CPUOFFSET; - - clksel &= ~(0x03 << offset); - clksel |= (clkval << offset); - - __raw_writel(clksel, REG_CLKSEL); -} - -void nuc900_clock_source(struct device *dev, unsigned char *src) -{ - unsigned int clkval; - const char *dev_id; - - BUG_ON(!src); - clkval = 0; - - mutex_lock(&clksel_sem); - - if (dev) - dev_id = dev_name(dev); - else - dev_id = "cpufreq"; - - if (strcmp(src, "pll0") == 0) - clkval = PLL0; - else if (strcmp(src, "pll1") == 0) - clkval = PLL1; - else if (strcmp(src, "ext") == 0) - clkval = EXT; - else if (strcmp(src, "oth") == 0) - clkval = OTHER; - - clock_source_select(dev_id, clkval); - - mutex_unlock(&clksel_sem); -} -EXPORT_SYMBOL(nuc900_clock_source); - diff --git a/arch/arm/mach-w90x900/clock.c b/arch/arm/mach-w90x900/clock.c deleted file mode 100644 index df55aa8ce5ff..000000000000 --- a/arch/arm/mach-w90x900/clock.c +++ /dev/null @@ -1,121 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/mach-w90x900/clock.c - * - * Copyright (c) 2008 Nuvoton technology corporation - * - * Wan ZongShun <mcuos.com@gmail.com> - */ - -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/list.h> -#include <linux/errno.h> -#include <linux/err.h> -#include <linux/string.h> -#include <linux/clk.h> -#include <linux/spinlock.h> -#include <linux/platform_device.h> -#include <linux/io.h> - -#include <mach/hardware.h> - -#include "clock.h" - -#define SUBCLK 0x24 - -static DEFINE_SPINLOCK(clocks_lock); - -int clk_enable(struct clk *clk) -{ - unsigned long flags; - - spin_lock_irqsave(&clocks_lock, flags); - if (clk->enabled++ == 0) - (clk->enable)(clk, 1); - spin_unlock_irqrestore(&clocks_lock, flags); - - return 0; -} -EXPORT_SYMBOL(clk_enable); - -void clk_disable(struct clk *clk) -{ - unsigned long flags; - - if (!clk) - return; - - WARN_ON(clk->enabled == 0); - - spin_lock_irqsave(&clocks_lock, flags); - if (--clk->enabled == 0) - (clk->enable)(clk, 0); - spin_unlock_irqrestore(&clocks_lock, flags); -} -EXPORT_SYMBOL(clk_disable); - -unsigned long clk_get_rate(struct clk *clk) -{ - return 15000000; -} -EXPORT_SYMBOL(clk_get_rate); - -void nuc900_clk_enable(struct clk *clk, int enable) -{ - unsigned int clocks = clk->cken; - unsigned long clken; - - clken = __raw_readl(W90X900_VA_CLKPWR); - - if (enable) - clken |= clocks; - else - clken &= ~clocks; - - __raw_writel(clken, W90X900_VA_CLKPWR); -} - -void nuc900_subclk_enable(struct clk *clk, int enable) -{ - unsigned int clocks = clk->cken; - unsigned long clken; - - clken = __raw_readl(W90X900_VA_CLKPWR + SUBCLK); - - if (enable) - clken |= clocks; - else - clken &= ~clocks; - - __raw_writel(clken, W90X900_VA_CLKPWR + SUBCLK); -} - -/* dummy functions, should not be called */ -long clk_round_rate(struct clk *clk, unsigned long rate) -{ - WARN_ON(clk); - return 0; -} -EXPORT_SYMBOL(clk_round_rate); - -int clk_set_rate(struct clk *clk, unsigned long rate) -{ - WARN_ON(clk); - return 0; -} -EXPORT_SYMBOL(clk_set_rate); - -int clk_set_parent(struct clk *clk, struct clk *parent) -{ - WARN_ON(clk); - return 0; -} -EXPORT_SYMBOL(clk_set_parent); - -struct clk *clk_get_parent(struct clk *clk) -{ - WARN_ON(clk); - return NULL; -} -EXPORT_SYMBOL(clk_get_parent); diff --git a/arch/arm/mach-w90x900/clock.h b/arch/arm/mach-w90x900/clock.h deleted file mode 100644 index e81c369430b3..000000000000 --- a/arch/arm/mach-w90x900/clock.h +++ /dev/null @@ -1,40 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * linux/arch/arm/mach-w90x900/clock.h - * - * Copyright (c) 2008 Nuvoton technology corporation - * - * Wan ZongShun <mcuos.com@gmail.com> - */ - -#include <linux/clkdev.h> - -void nuc900_clk_enable(struct clk *clk, int enable); -void nuc900_subclk_enable(struct clk *clk, int enable); - -struct clk { - unsigned long cken; - unsigned int enabled; - void (*enable)(struct clk *, int enable); -}; - -#define DEFINE_CLK(_name, _ctrlbit) \ -struct clk clk_##_name = { \ - .enable = nuc900_clk_enable, \ - .cken = (1 << _ctrlbit), \ - } - -#define DEFINE_SUBCLK(_name, _ctrlbit) \ -struct clk clk_##_name = { \ - .enable = nuc900_subclk_enable, \ - .cken = (1 << _ctrlbit), \ - } - - -#define DEF_CLKLOOK(_clk, _devname, _conname) \ - { \ - .clk = _clk, \ - .dev_id = _devname, \ - .con_id = _conname, \ - } - diff --git a/arch/arm/mach-w90x900/cpu.c b/arch/arm/mach-w90x900/cpu.c deleted file mode 100644 index aeaafc2ebb01..000000000000 --- a/arch/arm/mach-w90x900/cpu.c +++ /dev/null @@ -1,238 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/mach-w90x900/cpu.c - * - * Copyright (c) 2009 Nuvoton corporation. - * - * Wan ZongShun <mcuos.com@gmail.com> - * - * NUC900 series cpu common support - */ - -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/interrupt.h> -#include <linux/list.h> -#include <linux/timer.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/io.h> -#include <linux/serial_8250.h> -#include <linux/delay.h> - -#include <asm/mach/arch.h> -#include <asm/mach/map.h> -#include <asm/mach/irq.h> -#include <asm/irq.h> -#include <asm/system_misc.h> - -#include <mach/hardware.h> -#include <mach/regs-serial.h> -#include <mach/regs-clock.h> -#include "regs-ebi.h" -#include "regs-timer.h" - -#include "cpu.h" -#include "clock.h" -#include "nuc9xx.h" - -/* Initial IO mappings */ - -static struct map_desc nuc900_iodesc[] __initdata = { - IODESC_ENT(IRQ), - IODESC_ENT(GCR), - IODESC_ENT(UART), - IODESC_ENT(TIMER), - IODESC_ENT(EBI), - IODESC_ENT(GPIO), -}; - -/* Initial clock declarations. */ -static DEFINE_CLK(lcd, 0); -static DEFINE_CLK(audio, 1); -static DEFINE_CLK(fmi, 4); -static DEFINE_SUBCLK(ms, 0); -static DEFINE_SUBCLK(sd, 1); -static DEFINE_CLK(dmac, 5); -static DEFINE_CLK(atapi, 6); -static DEFINE_CLK(emc, 7); -static DEFINE_SUBCLK(rmii, 2); -static DEFINE_CLK(usbd, 8); -static DEFINE_CLK(usbh, 9); -static DEFINE_CLK(g2d, 10); -static DEFINE_CLK(pwm, 18); -static DEFINE_CLK(ps2, 24); -static DEFINE_CLK(kpi, 25); -static DEFINE_CLK(wdt, 26); -static DEFINE_CLK(gdma, 27); -static DEFINE_CLK(adc, 28); -static DEFINE_CLK(usi, 29); -static DEFINE_CLK(ext, 0); -static DEFINE_CLK(timer0, 19); -static DEFINE_CLK(timer1, 20); -static DEFINE_CLK(timer2, 21); -static DEFINE_CLK(timer3, 22); -static DEFINE_CLK(timer4, 23); - -static struct clk_lookup nuc900_clkregs[] = { - DEF_CLKLOOK(&clk_lcd, "nuc900-lcd", NULL), - DEF_CLKLOOK(&clk_audio, "nuc900-ac97", NULL), - DEF_CLKLOOK(&clk_fmi, "nuc900-fmi", NULL), - DEF_CLKLOOK(&clk_ms, "nuc900-fmi", "MS"), - DEF_CLKLOOK(&clk_sd, "nuc900-fmi", "SD"), - DEF_CLKLOOK(&clk_dmac, "nuc900-dmac", NULL), - DEF_CLKLOOK(&clk_atapi, "nuc900-atapi", NULL), - DEF_CLKLOOK(&clk_emc, "nuc900-emc", NULL), - DEF_CLKLOOK(&clk_rmii, "nuc900-emc", "RMII"), - DEF_CLKLOOK(&clk_usbd, "nuc900-usbd", NULL), - DEF_CLKLOOK(&clk_usbh, "nuc900-usbh", NULL), - DEF_CLKLOOK(&clk_g2d, "nuc900-g2d", NULL), - DEF_CLKLOOK(&clk_pwm, "nuc900-pwm", NULL), - DEF_CLKLOOK(&clk_ps2, "nuc900-ps2", NULL), - DEF_CLKLOOK(&clk_kpi, "nuc900-kpi", NULL), - DEF_CLKLOOK(&clk_wdt, "nuc900-wdt", NULL), - DEF_CLKLOOK(&clk_gdma, "nuc900-gdma", NULL), - DEF_CLKLOOK(&clk_adc, "nuc900-ts", NULL), - DEF_CLKLOOK(&clk_usi, "nuc900-spi", NULL), - DEF_CLKLOOK(&clk_ext, NULL, "ext"), - DEF_CLKLOOK(&clk_timer0, NULL, "timer0"), - DEF_CLKLOOK(&clk_timer1, NULL, "timer1"), - DEF_CLKLOOK(&clk_timer2, NULL, "timer2"), - DEF_CLKLOOK(&clk_timer3, NULL, "timer3"), - DEF_CLKLOOK(&clk_timer4, NULL, "timer4"), -}; - -/* Initial serial platform data */ - -struct plat_serial8250_port nuc900_uart_data[] = { - NUC900_8250PORT(UART0), - {}, -}; - -struct platform_device nuc900_serial_device = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = nuc900_uart_data, - }, -}; - -/*Set NUC900 series cpu frequence*/ -static int __init nuc900_set_clkval(unsigned int cpufreq) -{ - unsigned int pllclk, ahbclk, apbclk, val; - - pllclk = 0; - ahbclk = 0; - apbclk = 0; - - switch (cpufreq) { - case 66: - pllclk = PLL_66MHZ; - ahbclk = AHB_CPUCLK_1_1; - apbclk = APB_AHB_1_2; - break; - - case 100: - pllclk = PLL_100MHZ; - ahbclk = AHB_CPUCLK_1_1; - apbclk = APB_AHB_1_2; - break; - - case 120: - pllclk = PLL_120MHZ; - ahbclk = AHB_CPUCLK_1_2; - apbclk = APB_AHB_1_2; - break; - - case 166: - pllclk = PLL_166MHZ; - ahbclk = AHB_CPUCLK_1_2; - apbclk = APB_AHB_1_2; - break; - - case 200: - pllclk = PLL_200MHZ; - ahbclk = AHB_CPUCLK_1_2; - apbclk = APB_AHB_1_2; - break; - } - - __raw_writel(pllclk, REG_PLLCON0); - - val = __raw_readl(REG_CLKDIV); - val &= ~(0x03 << 24 | 0x03 << 26); - val |= (ahbclk << 24 | apbclk << 26); - __raw_writel(val, REG_CLKDIV); - - return 0; -} -static int __init nuc900_set_cpufreq(char *str) -{ - unsigned long cpufreq, val; - - if (!*str) - return 0; - - if (kstrtoul(str, 0, &cpufreq)) - return 0; - - nuc900_clock_source(NULL, "ext"); - - nuc900_set_clkval(cpufreq); - - mdelay(1); - - val = __raw_readl(REG_CKSKEW); - val &= ~0xff; - val |= DEFAULTSKEW; - __raw_writel(val, REG_CKSKEW); - - nuc900_clock_source(NULL, "pll0"); - - return 1; -} - -__setup("cpufreq=", nuc900_set_cpufreq); - -/*Init NUC900 evb io*/ - -void __init nuc900_map_io(struct map_desc *mach_desc, int mach_size) -{ - unsigned long idcode = 0x0; - - iotable_init(mach_desc, mach_size); - iotable_init(nuc900_iodesc, ARRAY_SIZE(nuc900_iodesc)); - - idcode = __raw_readl(NUC900PDID); - if (idcode == NUC910_CPUID) - printk(KERN_INFO "CPU type 0x%08lx is NUC910\n", idcode); - else if (idcode == NUC920_CPUID) - printk(KERN_INFO "CPU type 0x%08lx is NUC920\n", idcode); - else if (idcode == NUC950_CPUID) - printk(KERN_INFO "CPU type 0x%08lx is NUC950\n", idcode); - else if (idcode == NUC960_CPUID) - printk(KERN_INFO "CPU type 0x%08lx is NUC960\n", idcode); -} - -/*Init NUC900 clock*/ - -void __init nuc900_init_clocks(void) -{ - clkdev_add_table(nuc900_clkregs, ARRAY_SIZE(nuc900_clkregs)); -} - -#define WTCR (TMR_BA + 0x1C) -#define WTCLK (1 << 10) -#define WTE (1 << 7) -#define WTRE (1 << 1) - -void nuc9xx_restart(enum reboot_mode mode, const char *cmd) -{ - if (mode == REBOOT_SOFT) { - /* Jump into ROM at address 0 */ - soft_restart(0); - } else { - __raw_writel(WTE | WTRE | WTCLK, WTCR); - } -} diff --git a/arch/arm/mach-w90x900/cpu.h b/arch/arm/mach-w90x900/cpu.h deleted file mode 100644 index a56f36d04bac..000000000000 --- a/arch/arm/mach-w90x900/cpu.h +++ /dev/null @@ -1,56 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * arch/arm/mach-w90x900/cpu.h - * - * Based on linux/include/asm-arm/plat-s3c24xx/cpu.h by Ben Dooks - * - * Copyright (c) 2008 Nuvoton technology corporation - * All rights reserved. - * - * Header file for NUC900 CPU support - * - * Wan ZongShun <mcuos.com@gmail.com> - */ - -#define IODESC_ENT(y) \ -{ \ - .virtual = (unsigned long)W90X900_VA_##y, \ - .pfn = __phys_to_pfn(W90X900_PA_##y), \ - .length = W90X900_SZ_##y, \ - .type = MT_DEVICE, \ -} - -#define NUC900_8250PORT(name) \ -{ \ - .membase = name##_BA, \ - .mapbase = name##_PA, \ - .irq = IRQ_##name, \ - .uartclk = 11313600, \ - .regshift = 2, \ - .iotype = UPIO_MEM, \ - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, \ -} - -/*Cpu identifier register*/ - -#define NUC900PDID W90X900_VA_GCR -#define NUC910_CPUID 0x02900910 -#define NUC920_CPUID 0x02900920 -#define NUC950_CPUID 0x02900950 -#define NUC960_CPUID 0x02900960 - -/* extern file from cpu.c */ - -extern void nuc900_clock_source(struct device *dev, unsigned char *src); -extern void nuc900_init_clocks(void); -extern void nuc900_map_io(struct map_desc *mach_desc, int mach_size); -extern void nuc900_board_init(struct platform_device **device, int size); - -/* for either public between 910 and 920, or between 920 and 950 */ - -extern struct platform_device nuc900_serial_device; -extern struct platform_device nuc900_device_fmi; -extern struct platform_device nuc900_device_kpi; -extern struct platform_device nuc900_device_rtc; -extern struct platform_device nuc900_device_ts; -extern struct platform_device nuc900_device_lcd; diff --git a/arch/arm/mach-w90x900/dev.c b/arch/arm/mach-w90x900/dev.c deleted file mode 100644 index ce5fe400cb99..000000000000 --- a/arch/arm/mach-w90x900/dev.c +++ /dev/null @@ -1,537 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/mach-w90x900/dev.c - * - * Copyright (C) 2009 Nuvoton corporation. - * - * Wan ZongShun <mcuos.com@gmail.com> - */ - -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/interrupt.h> -#include <linux/list.h> -#include <linux/timer.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/slab.h> -#include <linux/cpu.h> - -#include <linux/mtd/physmap.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/partitions.h> - -#include <linux/spi/spi.h> -#include <linux/spi/flash.h> - -#include <asm/system_misc.h> -#include <asm/mach/arch.h> -#include <asm/mach/map.h> -#include <asm/mach/irq.h> -#include <asm/mach-types.h> - -#include <mach/regs-serial.h> -#include <linux/platform_data/spi-nuc900.h> -#include <mach/map.h> -#include <linux/platform_data/video-nuc900fb.h> -#include <mach/regs-ldm.h> -#include <linux/platform_data/keypad-w90p910.h> - -#include "cpu.h" - -/*NUC900 evb norflash driver data */ - -#define NUC900_FLASH_BASE 0xA0000000 -#define NUC900_FLASH_SIZE 0x400000 -#define SPIOFFSET 0x200 -#define SPIOREG_SIZE 0x100 - -static struct mtd_partition nuc900_flash_partitions[] = { - { - .name = "NOR Partition 1 for kernel (960K)", - .size = 0xF0000, - .offset = 0x10000, - }, - { - .name = "NOR Partition 2 for image (1M)", - .size = 0x100000, - .offset = 0x100000, - }, - { - .name = "NOR Partition 3 for user (2M)", - .size = 0x200000, - .offset = 0x00200000, - } -}; - -static struct physmap_flash_data nuc900_flash_data = { - .width = 2, - .parts = nuc900_flash_partitions, - .nr_parts = ARRAY_SIZE(nuc900_flash_partitions), -}; - -static struct resource nuc900_flash_resources[] = { - { - .start = NUC900_FLASH_BASE, - .end = NUC900_FLASH_BASE + NUC900_FLASH_SIZE - 1, - .flags = IORESOURCE_MEM, - } -}; - -static struct platform_device nuc900_flash_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &nuc900_flash_data, - }, - .resource = nuc900_flash_resources, - .num_resources = ARRAY_SIZE(nuc900_flash_resources), -}; - -/* USB EHCI Host Controller */ - -static struct resource nuc900_usb_ehci_resource[] = { - [0] = { - .start = W90X900_PA_USBEHCIHOST, - .end = W90X900_PA_USBEHCIHOST + W90X900_SZ_USBEHCIHOST - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_USBH, - .end = IRQ_USBH, - .flags = IORESOURCE_IRQ, - } -}; - -static u64 nuc900_device_usb_ehci_dmamask = 0xffffffffUL; - -static struct platform_device nuc900_device_usb_ehci = { - .name = "nuc900-ehci", - .id = -1, - .num_resources = ARRAY_SIZE(nuc900_usb_ehci_resource), - .resource = nuc900_usb_ehci_resource, - .dev = { - .dma_mask = &nuc900_device_usb_ehci_dmamask, - .coherent_dma_mask = 0xffffffffUL - } -}; - -/* USB OHCI Host Controller */ - -static struct resource nuc900_usb_ohci_resource[] = { - [0] = { - .start = W90X900_PA_USBOHCIHOST, - .end = W90X900_PA_USBOHCIHOST + W90X900_SZ_USBOHCIHOST - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_USBH, - .end = IRQ_USBH, - .flags = IORESOURCE_IRQ, - } -}; - -static u64 nuc900_device_usb_ohci_dmamask = 0xffffffffUL; -static struct platform_device nuc900_device_usb_ohci = { - .name = "nuc900-ohci", - .id = -1, - .num_resources = ARRAY_SIZE(nuc900_usb_ohci_resource), - .resource = nuc900_usb_ohci_resource, - .dev = { - .dma_mask = &nuc900_device_usb_ohci_dmamask, - .coherent_dma_mask = 0xffffffffUL - } -}; - -/* USB Device (Gadget)*/ - -static struct resource nuc900_usbgadget_resource[] = { - [0] = { - .start = W90X900_PA_USBDEV, - .end = W90X900_PA_USBDEV + W90X900_SZ_USBDEV - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_USBD, - .end = IRQ_USBD, - .flags = IORESOURCE_IRQ, - } -}; - -static struct platform_device nuc900_device_usbgadget = { - .name = "nuc900-usbgadget", - .id = -1, - .num_resources = ARRAY_SIZE(nuc900_usbgadget_resource), - .resource = nuc900_usbgadget_resource, -}; - -/* MAC device */ - -static struct resource nuc900_emc_resource[] = { - [0] = { - .start = W90X900_PA_EMC, - .end = W90X900_PA_EMC + W90X900_SZ_EMC - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_EMCTX, - .end = IRQ_EMCTX, - .flags = IORESOURCE_IRQ, - }, - [2] = { - .start = IRQ_EMCRX, - .end = IRQ_EMCRX, - .flags = IORESOURCE_IRQ, - } -}; - -static u64 nuc900_device_emc_dmamask = 0xffffffffUL; -static struct platform_device nuc900_device_emc = { - .name = "nuc900-emc", - .id = -1, - .num_resources = ARRAY_SIZE(nuc900_emc_resource), - .resource = nuc900_emc_resource, - .dev = { - .dma_mask = &nuc900_device_emc_dmamask, - .coherent_dma_mask = 0xffffffffUL - } -}; - -/* SPI device */ - -static struct nuc900_spi_info nuc900_spiflash_data = { - .num_cs = 1, - .lsb = 0, - .txneg = 1, - .rxneg = 0, - .divider = 24, - .sleep = 0, - .txnum = 0, - .txbitlen = 8, - .bus_num = 0, -}; - -static struct resource nuc900_spi_resource[] = { - [0] = { - .start = W90X900_PA_I2C + SPIOFFSET, - .end = W90X900_PA_I2C + SPIOFFSET + SPIOREG_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_SSP, - .end = IRQ_SSP, - .flags = IORESOURCE_IRQ, - } -}; - -static struct platform_device nuc900_device_spi = { - .name = "nuc900-spi", - .id = -1, - .num_resources = ARRAY_SIZE(nuc900_spi_resource), - .resource = nuc900_spi_resource, - .dev = { - .platform_data = &nuc900_spiflash_data, - } -}; - -/* spi device, spi flash info */ - -static struct mtd_partition nuc900_spi_flash_partitions[] = { - { - .name = "bootloader(spi)", - .size = 0x0100000, - .offset = 0, - }, -}; - -static struct flash_platform_data nuc900_spi_flash_data = { - .name = "m25p80", - .parts = nuc900_spi_flash_partitions, - .nr_parts = ARRAY_SIZE(nuc900_spi_flash_partitions), - .type = "w25x16", -}; - -static struct spi_board_info nuc900_spi_board_info[] __initdata = { - { - .modalias = "m25p80", - .max_speed_hz = 20000000, - .bus_num = 0, - .chip_select = 0, - .platform_data = &nuc900_spi_flash_data, - .mode = SPI_MODE_0, - }, -}; - -/* WDT Device */ - -static struct resource nuc900_wdt_resource[] = { - [0] = { - .start = W90X900_PA_TIMER, - .end = W90X900_PA_TIMER + W90X900_SZ_TIMER - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_WDT, - .end = IRQ_WDT, - .flags = IORESOURCE_IRQ, - } -}; - -static struct platform_device nuc900_device_wdt = { - .name = "nuc900-wdt", - .id = -1, - .num_resources = ARRAY_SIZE(nuc900_wdt_resource), - .resource = nuc900_wdt_resource, -}; - -/* - * public device definition between 910 and 920, or 910 - * and 950 or 950 and 960...,their dev platform register - * should be in specific file such as nuc950, nuc960 c - * files rather than the public dev.c file here. so the - * corresponding platform_device definition should not be - * static. -*/ - -/* RTC controller*/ - -static struct resource nuc900_rtc_resource[] = { - [0] = { - .start = W90X900_PA_RTC, - .end = W90X900_PA_RTC + 0xff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_RTC, - .end = IRQ_RTC, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device nuc900_device_rtc = { - .name = "nuc900-rtc", - .id = -1, - .num_resources = ARRAY_SIZE(nuc900_rtc_resource), - .resource = nuc900_rtc_resource, -}; - -/*TouchScreen controller*/ - -static struct resource nuc900_ts_resource[] = { - [0] = { - .start = W90X900_PA_ADC, - .end = W90X900_PA_ADC + W90X900_SZ_ADC-1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_ADC, - .end = IRQ_ADC, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device nuc900_device_ts = { - .name = "nuc900-ts", - .id = -1, - .resource = nuc900_ts_resource, - .num_resources = ARRAY_SIZE(nuc900_ts_resource), -}; - -/* FMI Device */ - -static struct resource nuc900_fmi_resource[] = { - [0] = { - .start = W90X900_PA_FMI, - .end = W90X900_PA_FMI + W90X900_SZ_FMI - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_FMI, - .end = IRQ_FMI, - .flags = IORESOURCE_IRQ, - } -}; - -struct platform_device nuc900_device_fmi = { - .name = "nuc900-fmi", - .id = -1, - .num_resources = ARRAY_SIZE(nuc900_fmi_resource), - .resource = nuc900_fmi_resource, -}; - -/* KPI controller*/ - -static int nuc900_keymap[] = { - KEY(0, 0, KEY_A), - KEY(0, 1, KEY_B), - KEY(0, 2, KEY_C), - KEY(0, 3, KEY_D), - - KEY(1, 0, KEY_E), - KEY(1, 1, KEY_F), - KEY(1, 2, KEY_G), - KEY(1, 3, KEY_H), - - KEY(2, 0, KEY_I), - KEY(2, 1, KEY_J), - KEY(2, 2, KEY_K), - KEY(2, 3, KEY_L), - - KEY(3, 0, KEY_M), - KEY(3, 1, KEY_N), - KEY(3, 2, KEY_O), - KEY(3, 3, KEY_P), -}; - -static struct matrix_keymap_data nuc900_map_data = { - .keymap = nuc900_keymap, - .keymap_size = ARRAY_SIZE(nuc900_keymap), -}; - -struct w90p910_keypad_platform_data nuc900_keypad_info = { - .keymap_data = &nuc900_map_data, - .prescale = 0xfa, - .debounce = 0x50, -}; - -static struct resource nuc900_kpi_resource[] = { - [0] = { - .start = W90X900_PA_KPI, - .end = W90X900_PA_KPI + W90X900_SZ_KPI - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_KPI, - .end = IRQ_KPI, - .flags = IORESOURCE_IRQ, - } - -}; - -struct platform_device nuc900_device_kpi = { - .name = "nuc900-kpi", - .id = -1, - .num_resources = ARRAY_SIZE(nuc900_kpi_resource), - .resource = nuc900_kpi_resource, - .dev = { - .platform_data = &nuc900_keypad_info, - } -}; - -/* LCD controller*/ - -static struct nuc900fb_display nuc900_lcd_info[] = { - /* Giantplus Technology GPM1040A0 320x240 Color TFT LCD */ - [0] = { - .type = LCM_DCCS_VA_SRC_RGB565, - .width = 320, - .height = 240, - .xres = 320, - .yres = 240, - .bpp = 16, - .pixclock = 200000, - .left_margin = 34, - .right_margin = 54, - .hsync_len = 10, - .upper_margin = 18, - .lower_margin = 4, - .vsync_len = 1, - .dccs = 0x8e00041a, - .devctl = 0x060800c0, - .fbctrl = 0x00a000a0, - .scale = 0x04000400, - }, -}; - -static struct nuc900fb_mach_info nuc900_fb_info = { -#if defined(CONFIG_GPM1040A0_320X240) - .displays = &nuc900_lcd_info[0], -#else - .displays = nuc900_lcd_info, -#endif - .num_displays = ARRAY_SIZE(nuc900_lcd_info), - .default_display = 0, - .gpio_dir = 0x00000004, - .gpio_dir_mask = 0xFFFFFFFD, - .gpio_data = 0x00000004, - .gpio_data_mask = 0xFFFFFFFD, -}; - -static struct resource nuc900_lcd_resource[] = { - [0] = { - .start = W90X900_PA_LCD, - .end = W90X900_PA_LCD + W90X900_SZ_LCD - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_LCD, - .end = IRQ_LCD, - .flags = IORESOURCE_IRQ, - } -}; - -static u64 nuc900_device_lcd_dmamask = -1; -struct platform_device nuc900_device_lcd = { - .name = "nuc900-lcd", - .id = -1, - .num_resources = ARRAY_SIZE(nuc900_lcd_resource), - .resource = nuc900_lcd_resource, - .dev = { - .dma_mask = &nuc900_device_lcd_dmamask, - .coherent_dma_mask = -1, - .platform_data = &nuc900_fb_info, - } -}; - -/* AUDIO controller*/ -static u64 nuc900_device_audio_dmamask = -1; -static struct resource nuc900_ac97_resource[] = { - [0] = { - .start = W90X900_PA_ACTL, - .end = W90X900_PA_ACTL + W90X900_SZ_ACTL - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_ACTL, - .end = IRQ_ACTL, - .flags = IORESOURCE_IRQ, - } - -}; - -struct platform_device nuc900_device_ac97 = { - .name = "nuc900-ac97", - .id = -1, - .num_resources = ARRAY_SIZE(nuc900_ac97_resource), - .resource = nuc900_ac97_resource, - .dev = { - .dma_mask = &nuc900_device_audio_dmamask, - .coherent_dma_mask = -1, - } -}; - -/*Here should be your evb resourse,such as LCD*/ - -static struct platform_device *nuc900_public_dev[] __initdata = { - &nuc900_serial_device, - &nuc900_flash_device, - &nuc900_device_usb_ehci, - &nuc900_device_usb_ohci, - &nuc900_device_usbgadget, - &nuc900_device_emc, - &nuc900_device_spi, - &nuc900_device_wdt, - &nuc900_device_ac97, -}; - -/* Provide adding specific CPU platform devices API */ - -void __init nuc900_board_init(struct platform_device **device, int size) -{ - cpu_idle_poll_ctrl(true); - platform_add_devices(device, size); - platform_add_devices(nuc900_public_dev, ARRAY_SIZE(nuc900_public_dev)); - spi_register_board_info(nuc900_spi_board_info, - ARRAY_SIZE(nuc900_spi_board_info)); -} - diff --git a/arch/arm/mach-w90x900/gpio.c b/arch/arm/mach-w90x900/gpio.c deleted file mode 100644 index cb5df211f1ed..000000000000 --- a/arch/arm/mach-w90x900/gpio.c +++ /dev/null @@ -1,150 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/mach-w90x900/gpio.c - * - * Generic nuc900 GPIO handling - * - * Wan ZongShun <mcuos.com@gmail.com> - */ - -#include <linux/clk.h> -#include <linux/errno.h> -#include <linux/interrupt.h> -#include <linux/irq.h> -#include <linux/debugfs.h> -#include <linux/seq_file.h> -#include <linux/kernel.h> -#include <linux/list.h> -#include <linux/module.h> -#include <linux/io.h> -#include <linux/gpio/driver.h> - -#include <mach/hardware.h> - -#define GPIO_BASE (W90X900_VA_GPIO) -#define GPIO_DIR (0x04) -#define GPIO_OUT (0x08) -#define GPIO_IN (0x0C) -#define GROUPINERV (0x10) -#define GPIO_GPIO(Nb) (0x00000001 << (Nb)) - -#define NUC900_GPIO_CHIP(name, base_gpio, nr_gpio) \ - { \ - .chip = { \ - .label = name, \ - .direction_input = nuc900_dir_input, \ - .direction_output = nuc900_dir_output, \ - .get = nuc900_gpio_get, \ - .set = nuc900_gpio_set, \ - .base = base_gpio, \ - .ngpio = nr_gpio, \ - } \ - } - -struct nuc900_gpio_chip { - struct gpio_chip chip; - void __iomem *regbase; /* Base of group register*/ - spinlock_t gpio_lock; -}; - -static int nuc900_gpio_get(struct gpio_chip *chip, unsigned offset) -{ - struct nuc900_gpio_chip *nuc900_gpio = gpiochip_get_data(chip); - void __iomem *pio = nuc900_gpio->regbase + GPIO_IN; - unsigned int regval; - - regval = __raw_readl(pio); - regval &= GPIO_GPIO(offset); - - return (regval != 0); -} - -static void nuc900_gpio_set(struct gpio_chip *chip, unsigned offset, int val) -{ - struct nuc900_gpio_chip *nuc900_gpio = gpiochip_get_data(chip); - void __iomem *pio = nuc900_gpio->regbase + GPIO_OUT; - unsigned int regval; - unsigned long flags; - - spin_lock_irqsave(&nuc900_gpio->gpio_lock, flags); - - regval = __raw_readl(pio); - - if (val) - regval |= GPIO_GPIO(offset); - else - regval &= ~GPIO_GPIO(offset); - - __raw_writel(regval, pio); - - spin_unlock_irqrestore(&nuc900_gpio->gpio_lock, flags); -} - -static int nuc900_dir_input(struct gpio_chip *chip, unsigned offset) -{ - struct nuc900_gpio_chip *nuc900_gpio = gpiochip_get_data(chip); - void __iomem *pio = nuc900_gpio->regbase + GPIO_DIR; - unsigned int regval; - unsigned long flags; - - spin_lock_irqsave(&nuc900_gpio->gpio_lock, flags); - - regval = __raw_readl(pio); - regval &= ~GPIO_GPIO(offset); - __raw_writel(regval, pio); - - spin_unlock_irqrestore(&nuc900_gpio->gpio_lock, flags); - - return 0; -} - -static int nuc900_dir_output(struct gpio_chip *chip, unsigned offset, int val) -{ - struct nuc900_gpio_chip *nuc900_gpio = gpiochip_get_data(chip); - void __iomem *outreg = nuc900_gpio->regbase + GPIO_OUT; - void __iomem *pio = nuc900_gpio->regbase + GPIO_DIR; - unsigned int regval; - unsigned long flags; - - spin_lock_irqsave(&nuc900_gpio->gpio_lock, flags); - - regval = __raw_readl(pio); - regval |= GPIO_GPIO(offset); - __raw_writel(regval, pio); - - regval = __raw_readl(outreg); - - if (val) - regval |= GPIO_GPIO(offset); - else - regval &= ~GPIO_GPIO(offset); - - __raw_writel(regval, outreg); - - spin_unlock_irqrestore(&nuc900_gpio->gpio_lock, flags); - - return 0; -} - -static struct nuc900_gpio_chip nuc900_gpio[] = { - NUC900_GPIO_CHIP("GROUPC", 0, 16), - NUC900_GPIO_CHIP("GROUPD", 16, 10), - NUC900_GPIO_CHIP("GROUPE", 26, 14), - NUC900_GPIO_CHIP("GROUPF", 40, 10), - NUC900_GPIO_CHIP("GROUPG", 50, 17), - NUC900_GPIO_CHIP("GROUPH", 67, 8), - NUC900_GPIO_CHIP("GROUPI", 75, 17), -}; - -void __init nuc900_init_gpio(int nr_group) -{ - unsigned i; - struct nuc900_gpio_chip *gpio_chip; - - for (i = 0; i < nr_group; i++) { - gpio_chip = &nuc900_gpio[i]; - spin_lock_init(&gpio_chip->gpio_lock); - gpio_chip->regbase = GPIO_BASE + i * GROUPINERV; - gpiochip_add_data(&gpio_chip->chip, gpio_chip); - } -} diff --git a/arch/arm/mach-w90x900/include/mach/entry-macro.S b/arch/arm/mach-w90x900/include/mach/entry-macro.S deleted file mode 100644 index 0ff612ac95ba..000000000000 --- a/arch/arm/mach-w90x900/include/mach/entry-macro.S +++ /dev/null @@ -1,26 +0,0 @@ -/* - * arch/arm/mach-w90x900/include/mach/entry-macro.S - * - * Low-level IRQ helper macros for W90P910-based platforms - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - * - */ - -#include <mach/hardware.h> -#include <mach/regs-irq.h> - - .macro get_irqnr_preamble, base, tmp - .endm - - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - - mov \base, #AIC_BA - - ldr \irqnr, [\base, #AIC_IPER] - ldr \irqnr, [\base, #AIC_ISNR] - cmp \irqnr, #0 - - .endm diff --git a/arch/arm/mach-w90x900/include/mach/hardware.h b/arch/arm/mach-w90x900/include/mach/hardware.h deleted file mode 100644 index 137403960483..000000000000 --- a/arch/arm/mach-w90x900/include/mach/hardware.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * arch/arm/mach-w90x900/include/mach/hardware.h - * - * Copyright (c) 2008 Nuvoton technology corporation - * All rights reserved. - * - * Wan ZongShun <mcuos.com@gmail.com> - * - * Based on arch/arm/mach-s3c2410/include/mach/hardware.h - */ - -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -#include <linux/sizes.h> -#include <mach/map.h> - -#endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/mach-w90x900/include/mach/irqs.h b/arch/arm/mach-w90x900/include/mach/irqs.h deleted file mode 100644 index 23ea01d97a02..000000000000 --- a/arch/arm/mach-w90x900/include/mach/irqs.h +++ /dev/null @@ -1,82 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * arch/arm/mach-w90x900/include/mach/irqs.h - * - * Copyright (c) 2008 Nuvoton technology corporation. - * - * Wan ZongShun <mcuos.com@gmail.com> - * - * Based on arch/arm/mach-s3c2410/include/mach/irqs.h - */ - -#ifndef __ASM_ARCH_IRQS_H -#define __ASM_ARCH_IRQS_H - -/* - * we keep the first set of CPU IRQs out of the range of - * the ISA space, so that the PC104 has them to itself - * and we don't end up having to do horrible things to the - * standard ISA drivers.... - * - */ - -#define W90X900_IRQ(x) (x) - -/* Main cpu interrupts */ - -#define IRQ_WDT W90X900_IRQ(1) -#define IRQ_GROUP0 W90X900_IRQ(2) -#define IRQ_GROUP1 W90X900_IRQ(3) -#define IRQ_ACTL W90X900_IRQ(4) -#define IRQ_LCD W90X900_IRQ(5) -#define IRQ_RTC W90X900_IRQ(6) -#define IRQ_UART0 W90X900_IRQ(7) -#define IRQ_UART1 W90X900_IRQ(8) -#define IRQ_UART2 W90X900_IRQ(9) -#define IRQ_UART3 W90X900_IRQ(10) -#define IRQ_UART4 W90X900_IRQ(11) -#define IRQ_TIMER0 W90X900_IRQ(12) -#define IRQ_TIMER1 W90X900_IRQ(13) -#define IRQ_T_INT_GROUP W90X900_IRQ(14) -#define IRQ_USBH W90X900_IRQ(15) -#define IRQ_EMCTX W90X900_IRQ(16) -#define IRQ_EMCRX W90X900_IRQ(17) -#define IRQ_GDMAGROUP W90X900_IRQ(18) -#define IRQ_DMAC W90X900_IRQ(19) -#define IRQ_FMI W90X900_IRQ(20) -#define IRQ_USBD W90X900_IRQ(21) -#define IRQ_ATAPI W90X900_IRQ(22) -#define IRQ_G2D W90X900_IRQ(23) -#define IRQ_PCI W90X900_IRQ(24) -#define IRQ_SCGROUP W90X900_IRQ(25) -#define IRQ_I2CGROUP W90X900_IRQ(26) -#define IRQ_SSP W90X900_IRQ(27) -#define IRQ_PWM W90X900_IRQ(28) -#define IRQ_KPI W90X900_IRQ(29) -#define IRQ_P2SGROUP W90X900_IRQ(30) -#define IRQ_ADC W90X900_IRQ(31) -#define NR_IRQS (IRQ_ADC+1) - -/*for irq group*/ - -#define IRQ_PS2_PORT0 0x10000000 -#define IRQ_PS2_PORT1 0x20000000 -#define IRQ_I2C_LINE0 0x04000000 -#define IRQ_I2C_LINE1 0x08000000 -#define IRQ_SC_CARD0 0x01000000 -#define IRQ_SC_CARD1 0x02000000 -#define IRQ_GDMA_CH0 0x00100000 -#define IRQ_GDMA_CH1 0x00200000 -#define IRQ_TIMER2 0x00010000 -#define IRQ_TIMER3 0x00020000 -#define IRQ_TIMER4 0x00040000 -#define IRQ_GROUP0_IRQ0 0x00000001 -#define IRQ_GROUP0_IRQ1 0x00000002 -#define IRQ_GROUP0_IRQ2 0x00000004 -#define IRQ_GROUP0_IRQ3 0x00000008 -#define IRQ_GROUP1_IRQ4 0x00000010 -#define IRQ_GROUP1_IRQ5 0x00000020 -#define IRQ_GROUP1_IRQ6 0x00000040 -#define IRQ_GROUP1_IRQ7 0x00000080 - -#endif /* __ASM_ARCH_IRQ_H */ diff --git a/arch/arm/mach-w90x900/include/mach/map.h b/arch/arm/mach-w90x900/include/mach/map.h deleted file mode 100644 index 570a74e04b1c..000000000000 --- a/arch/arm/mach-w90x900/include/mach/map.h +++ /dev/null @@ -1,153 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * arch/arm/mach-w90x900/include/mach/map.h - * - * Copyright (c) 2008 Nuvoton technology corporation. - * - * Wan ZongShun <mcuos.com@gmail.com> - * - * Based on arch/arm/mach-s3c2410/include/mach/map.h - */ - -#ifndef __ASM_ARCH_MAP_H -#define __ASM_ARCH_MAP_H - -#ifndef __ASSEMBLY__ -#define W90X900_ADDR(x) ((void __iomem *)(0xF0000000 + (x))) -#else -#define W90X900_ADDR(x) (0xF0000000 + (x)) -#endif - -#define AHB_IO_BASE 0xB0000000 -#define APB_IO_BASE 0xB8000000 -#define CLOCKPW_BASE (APB_IO_BASE+0x200) -#define AIC_IO_BASE (APB_IO_BASE+0x2000) -#define TIMER_IO_BASE (APB_IO_BASE+0x1000) - -/* - * interrupt controller is the first thing we put in, to make - * the assembly code for the irq detection easier - */ -#define W90X900_VA_IRQ W90X900_ADDR(0x00000000) -#define W90X900_PA_IRQ (0xB8002000) -#define W90X900_SZ_IRQ SZ_4K - -#define W90X900_VA_GCR W90X900_ADDR(0x08002000) -#define W90X900_PA_GCR (0xB0000000) -#define W90X900_SZ_GCR SZ_4K - -/* Clock and Power management */ -#define W90X900_VA_CLKPWR (W90X900_VA_GCR+0x200) -#define W90X900_PA_CLKPWR (0xB0000200) -#define W90X900_SZ_CLKPWR SZ_4K - -/* EBI management */ -#define W90X900_VA_EBI W90X900_ADDR(0x00001000) -#define W90X900_PA_EBI (0xB0001000) -#define W90X900_SZ_EBI SZ_4K - -/* UARTs */ -#define W90X900_VA_UART W90X900_ADDR(0x08000000) -#define W90X900_PA_UART (0xB8000000) -#define W90X900_SZ_UART SZ_4K - -/* Timers */ -#define W90X900_VA_TIMER W90X900_ADDR(0x08001000) -#define W90X900_PA_TIMER (0xB8001000) -#define W90X900_SZ_TIMER SZ_4K - -/* GPIO ports */ -#define W90X900_VA_GPIO W90X900_ADDR(0x08003000) -#define W90X900_PA_GPIO (0xB8003000) -#define W90X900_SZ_GPIO SZ_4K - -/* GDMA control */ -#define W90X900_VA_GDMA W90X900_ADDR(0x00004000) -#define W90X900_PA_GDMA (0xB0004000) -#define W90X900_SZ_GDMA SZ_4K - -/* USB host controller*/ -#define W90X900_VA_USBEHCIHOST W90X900_ADDR(0x00005000) -#define W90X900_PA_USBEHCIHOST (0xB0005000) -#define W90X900_SZ_USBEHCIHOST SZ_4K - -#define W90X900_VA_USBOHCIHOST W90X900_ADDR(0x00007000) -#define W90X900_PA_USBOHCIHOST (0xB0007000) -#define W90X900_SZ_USBOHCIHOST SZ_4K - -/* I2C hardware controller */ -#define W90X900_VA_I2C W90X900_ADDR(0x08006000) -#define W90X900_PA_I2C (0xB8006000) -#define W90X900_SZ_I2C SZ_4K - -/* Keypad Interface*/ -#define W90X900_VA_KPI W90X900_ADDR(0x08008000) -#define W90X900_PA_KPI (0xB8008000) -#define W90X900_SZ_KPI SZ_4K - -/* Smart card host*/ -#define W90X900_VA_SC W90X900_ADDR(0x08005000) -#define W90X900_PA_SC (0xB8005000) -#define W90X900_SZ_SC SZ_4K - -/* LCD controller*/ -#define W90X900_VA_LCD W90X900_ADDR(0x00008000) -#define W90X900_PA_LCD (0xB0008000) -#define W90X900_SZ_LCD SZ_4K - -/* 2D controller*/ -#define W90X900_VA_GE W90X900_ADDR(0x0000B000) -#define W90X900_PA_GE (0xB000B000) -#define W90X900_SZ_GE SZ_4K - -/* ATAPI */ -#define W90X900_VA_ATAPI W90X900_ADDR(0x0000A000) -#define W90X900_PA_ATAPI (0xB000A000) -#define W90X900_SZ_ATAPI SZ_4K - -/* ADC */ -#define W90X900_VA_ADC W90X900_ADDR(0x0800A000) -#define W90X900_PA_ADC (0xB800A000) -#define W90X900_SZ_ADC SZ_4K - -/* PS2 Interface*/ -#define W90X900_VA_PS2 W90X900_ADDR(0x08009000) -#define W90X900_PA_PS2 (0xB8009000) -#define W90X900_SZ_PS2 SZ_4K - -/* RTC */ -#define W90X900_VA_RTC W90X900_ADDR(0x08004000) -#define W90X900_PA_RTC (0xB8004000) -#define W90X900_SZ_RTC SZ_4K - -/* Pulse Width Modulation(PWM) Registers */ -#define W90X900_VA_PWM W90X900_ADDR(0x08007000) -#define W90X900_PA_PWM (0xB8007000) -#define W90X900_SZ_PWM SZ_4K - -/* Audio Controller controller */ -#define W90X900_VA_ACTL W90X900_ADDR(0x00009000) -#define W90X900_PA_ACTL (0xB0009000) -#define W90X900_SZ_ACTL SZ_4K - -/* DMA controller */ -#define W90X900_VA_DMA W90X900_ADDR(0x0000c000) -#define W90X900_PA_DMA (0xB000c000) -#define W90X900_SZ_DMA SZ_4K - -/* FMI controller */ -#define W90X900_VA_FMI W90X900_ADDR(0x0000d000) -#define W90X900_PA_FMI (0xB000d000) -#define W90X900_SZ_FMI SZ_4K - -/* USB Device port */ -#define W90X900_VA_USBDEV W90X900_ADDR(0x00006000) -#define W90X900_PA_USBDEV (0xB0006000) -#define W90X900_SZ_USBDEV SZ_4K - -/* External MAC control*/ -#define W90X900_VA_EMC W90X900_ADDR(0x00003000) -#define W90X900_PA_EMC (0xB0003000) -#define W90X900_SZ_EMC SZ_4K - -#endif /* __ASM_ARCH_MAP_H */ diff --git a/arch/arm/mach-w90x900/include/mach/mfp.h b/arch/arm/mach-w90x900/include/mach/mfp.h deleted file mode 100644 index be5485efab0a..000000000000 --- a/arch/arm/mach-w90x900/include/mach/mfp.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * arch/arm/mach-w90x900/include/mach/mfp.h - * - * Copyright (c) 2010 Nuvoton technology corporation. - * - * Wan ZongShun <mcuos.com@gmail.com> - * - * Based on arch/arm/mach-s3c2410/include/mach/map.h - */ - -#ifndef __ASM_ARCH_MFP_H -#define __ASM_ARCH_MFP_H - -extern void mfp_set_groupf(struct device *dev); -extern void mfp_set_groupc(struct device *dev); -extern void mfp_set_groupi(struct device *dev); -extern void mfp_set_groupg(struct device *dev, const char *subname); -extern void mfp_set_groupd(struct device *dev, const char *subname); - -#endif /* __ASM_ARCH_MFP_H */ diff --git a/arch/arm/mach-w90x900/include/mach/regs-clock.h b/arch/arm/mach-w90x900/include/mach/regs-clock.h deleted file mode 100644 index f06245d26bd7..000000000000 --- a/arch/arm/mach-w90x900/include/mach/regs-clock.h +++ /dev/null @@ -1,49 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * arch/arm/mach-w90x900/include/mach/regs-clock.h - * - * Copyright (c) 2008 Nuvoton technology corporation. - * - * Wan ZongShun <mcuos.com@gmail.com> - */ - -#ifndef __ASM_ARCH_REGS_CLOCK_H -#define __ASM_ARCH_REGS_CLOCK_H - -/* Clock Control Registers */ -#define CLK_BA W90X900_VA_CLKPWR -#define REG_CLKEN (CLK_BA + 0x00) -#define REG_CLKSEL (CLK_BA + 0x04) -#define REG_CLKDIV (CLK_BA + 0x08) -#define REG_PLLCON0 (CLK_BA + 0x0C) -#define REG_PLLCON1 (CLK_BA + 0x10) -#define REG_PMCON (CLK_BA + 0x14) -#define REG_IRQWAKECON (CLK_BA + 0x18) -#define REG_IRQWAKEFLAG (CLK_BA + 0x1C) -#define REG_IPSRST (CLK_BA + 0x20) -#define REG_CLKEN1 (CLK_BA + 0x24) -#define REG_CLKDIV1 (CLK_BA + 0x28) - -/* Define PLL freq setting */ -#define PLL_DISABLE 0x12B63 -#define PLL_66MHZ 0x2B63 -#define PLL_100MHZ 0x4F64 -#define PLL_120MHZ 0x4F63 -#define PLL_166MHZ 0x4124 -#define PLL_200MHZ 0x4F24 - -/* Define AHB:CPUFREQ ratio */ -#define AHB_CPUCLK_1_1 0x00 -#define AHB_CPUCLK_1_2 0x01 -#define AHB_CPUCLK_1_4 0x02 -#define AHB_CPUCLK_1_8 0x03 - -/* Define APB:AHB ratio */ -#define APB_AHB_1_2 0x01 -#define APB_AHB_1_4 0x02 -#define APB_AHB_1_8 0x03 - -/* Define clock skew */ -#define DEFAULTSKEW 0x48 - -#endif /* __ASM_ARCH_REGS_CLOCK_H */ diff --git a/arch/arm/mach-w90x900/include/mach/regs-irq.h b/arch/arm/mach-w90x900/include/mach/regs-irq.h deleted file mode 100644 index 89fcbc60b60a..000000000000 --- a/arch/arm/mach-w90x900/include/mach/regs-irq.h +++ /dev/null @@ -1,46 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * arch/arm/mach-w90x900/include/mach/regs-irq.h - * - * Copyright (c) 2008 Nuvoton technology corporation - * All rights reserved. - * - * Wan ZongShun <mcuos.com@gmail.com> - * - * Based on arch/arm/mach-s3c2410/include/mach/regs-irq.h - */ - -#ifndef ___ASM_ARCH_REGS_IRQ_H -#define ___ASM_ARCH_REGS_IRQ_H - -/* Advance Interrupt Controller (AIC) Registers */ - -#define AIC_BA W90X900_VA_IRQ - -#define REG_AIC_IRQSC (AIC_BA+0x80) -#define REG_AIC_GEN (AIC_BA+0x84) -#define REG_AIC_GASR (AIC_BA+0x88) -#define REG_AIC_GSCR (AIC_BA+0x8C) -#define REG_AIC_IRSR (AIC_BA+0x100) -#define REG_AIC_IASR (AIC_BA+0x104) -#define REG_AIC_ISR (AIC_BA+0x108) -#define REG_AIC_IPER (AIC_BA+0x10C) -#define REG_AIC_ISNR (AIC_BA+0x110) -#define REG_AIC_IMR (AIC_BA+0x114) -#define REG_AIC_OISR (AIC_BA+0x118) -#define REG_AIC_MECR (AIC_BA+0x120) -#define REG_AIC_MDCR (AIC_BA+0x124) -#define REG_AIC_SSCR (AIC_BA+0x128) -#define REG_AIC_SCCR (AIC_BA+0x12C) -#define REG_AIC_EOSCR (AIC_BA+0x130) -#define AIC_IPER (0x10C) -#define AIC_ISNR (0x110) - -/*16-18 bits of REG_AIC_GEN define irq(2-4) group*/ - -#define TIMER2_IRQ (1 << 16) -#define TIMER3_IRQ (1 << 17) -#define TIMER4_IRQ (1 << 18) -#define TIME_GROUP_IRQ (TIMER2_IRQ|TIMER3_IRQ|TIMER4_IRQ) - -#endif /* ___ASM_ARCH_REGS_IRQ_H */ diff --git a/arch/arm/mach-w90x900/include/mach/regs-ldm.h b/arch/arm/mach-w90x900/include/mach/regs-ldm.h deleted file mode 100644 index ffe7e67c99de..000000000000 --- a/arch/arm/mach-w90x900/include/mach/regs-ldm.h +++ /dev/null @@ -1,248 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * arch/arm/mach-w90x900/include/mach/regs-serial.h - * - * Copyright (c) 2009 Nuvoton technology corporation - * All rights reserved. - * - * Description: - * Nuvoton Display, LCM Register list - * Author: Wang Qiang (rurality.linux@gmail.com) 2009/12/11 - */ - - -#ifndef __ASM_ARM_W90X900_REGS_LDM_H -#define __ASM_ARM_W90X900_REGS_LDM_H - -#include <mach/map.h> - -/* Display Controller Control/Status Register */ -#define REG_LCM_DCCS (0x00) - -#define LCM_DCCS_ENG_RST (1 << 0) -#define LCM_DCCS_VA_EN (1 << 1) -#define LCM_DCCS_OSD_EN (1 << 2) -#define LCM_DCCS_DISP_OUT_EN (1 << 3) -#define LCM_DCCS_DISP_INT_EN (1 << 4) -#define LCM_DCCS_CMD_ON (1 << 5) -#define LCM_DCCS_FIELD_INTR (1 << 6) -#define LCM_DCCS_SINGLE (1 << 7) - -enum LCM_DCCS_VA_SRC { - LCM_DCCS_VA_SRC_YUV422 = (0 << 8), - LCM_DCCS_VA_SRC_YCBCR422 = (1 << 8), - LCM_DCCS_VA_SRC_RGB888 = (2 << 8), - LCM_DCCS_VA_SRC_RGB666 = (3 << 8), - LCM_DCCS_VA_SRC_RGB565 = (4 << 8), - LCM_DCCS_VA_SRC_RGB444LOW = (5 << 8), - LCM_DCCS_VA_SRC_RGB444HIGH = (7 << 8) -}; - - -/* Display Device Control Register */ -#define REG_LCM_DEV_CTRL (0x04) - -enum LCM_DEV_CTRL_SWAP_YCbCr { - LCM_DEV_CTRL_SWAP_UYVY = (0 << 1), - LCM_DEV_CTRL_SWAP_YUYV = (1 << 1), - LCM_DEV_CTRL_SWAP_VYUY = (2 << 1), - LCM_DEV_CTRL_SWAP_YVYU = (3 << 1) -}; - -enum LCM_DEV_CTRL_RGB_SHIFT { - LCM_DEV_CTRL_RGB_SHIFT_NOT = (0 << 3), - LCM_DEV_CTRL_RGB_SHIFT_ONECYCLE = (1 << 3), - LCM_DEV_CTRL_RGB_SHIFT_TWOCYCLE = (2 << 3), - LCM_DEV_CTRL_RGB_SHIFT_NOT_DEF = (3 << 3) -}; - -enum LCM_DEV_CTRL_DEVICE { - LCM_DEV_CTRL_DEVICE_YUV422 = (0 << 5), - LCM_DEV_CTRL_DEVICE_YUV444 = (1 << 5), - LCM_DEV_CTRL_DEVICE_UNIPAC = (4 << 5), - LCM_DEV_CTRL_DEVICE_SEIKO_EPSON = (5 << 5), - LCM_DEV_CTRL_DEVICE_HIGH_COLOR = (6 << 5), - LCM_DEV_CTRL_DEVICE_MPU = (7 << 5) -}; - -#define LCM_DEV_CTRL_LCD_DDA (8) -#define LCM_DEV_CTRL_YUV2CCIR (16) - -enum LCM_DEV_CTRL_LCD_SEL { - LCM_DEV_CTRL_LCD_SEL_RGB_GBR = (0 << 17), - LCM_DEV_CTRL_LCD_SEL_BGR_RBG = (1 << 17), - LCM_DEV_CTRL_LCD_SEL_GBR_RGB = (2 << 17), - LCM_DEV_CTRL_LCD_SEL_RBG_BGR = (3 << 17) -}; - -enum LCM_DEV_CTRL_FAL_D { - LCM_DEV_CTRL_FAL_D_FALLING = (0 << 19), - LCM_DEV_CTRL_FAL_D_RISING = (1 << 19), -}; - -enum LCM_DEV_CTRL_H_POL { - LCM_DEV_CTRL_H_POL_LOW = (0 << 20), - LCM_DEV_CTRL_H_POL_HIGH = (1 << 20), -}; - -enum LCM_DEV_CTRL_V_POL { - LCM_DEV_CTRL_V_POL_LOW = (0 << 21), - LCM_DEV_CTRL_V_POL_HIGH = (1 << 21), -}; - -enum LCM_DEV_CTRL_VR_LACE { - LCM_DEV_CTRL_VR_LACE_NINTERLACE = (0 << 22), - LCM_DEV_CTRL_VR_LACE_INTERLACE = (1 << 22), -}; - -enum LCM_DEV_CTRL_LACE { - LCM_DEV_CTRL_LACE_NINTERLACE = (0 << 23), - LCM_DEV_CTRL_LACE_INTERLACE = (1 << 23), -}; - -enum LCM_DEV_CTRL_RGB_SCALE { - LCM_DEV_CTRL_RGB_SCALE_4096 = (0 << 24), - LCM_DEV_CTRL_RGB_SCALE_65536 = (1 << 24), - LCM_DEV_CTRL_RGB_SCALE_262144 = (2 << 24), - LCM_DEV_CTRL_RGB_SCALE_16777216 = (3 << 24), -}; - -enum LCM_DEV_CTRL_DBWORD { - LCM_DEV_CTRL_DBWORD_HALFWORD = (0 << 26), - LCM_DEV_CTRL_DBWORD_FULLWORD = (1 << 26), -}; - -enum LCM_DEV_CTRL_MPU68 { - LCM_DEV_CTRL_MPU68_80_SERIES = (0 << 27), - LCM_DEV_CTRL_MPU68_68_SERIES = (1 << 27), -}; - -enum LCM_DEV_CTRL_DE_POL { - LCM_DEV_CTRL_DE_POL_HIGH = (0 << 28), - LCM_DEV_CTRL_DE_POL_LOW = (1 << 28), -}; - -#define LCM_DEV_CTRL_CMD16 (29) -#define LCM_DEV_CTRL_CM16t18 (30) -#define LCM_DEV_CTRL_CMD_LOW (31) - -/* MPU-Interface LCD Write Command */ -#define REG_LCM_MPU_CMD (0x08) - -/* Interrupt Control/Status Register */ -#define REG_LCM_INT_CS (0x0c) -#define LCM_INT_CS_DISP_F_EN (1 << 0) -#define LCM_INT_CS_UNDERRUN_EN (1 << 1) -#define LCM_INT_CS_BUS_ERROR_INT (1 << 28) -#define LCM_INT_CS_UNDERRUN_INT (1 << 29) -#define LCM_INT_CS_DISP_F_STATUS (1 << 30) -#define LCM_INT_CS_DISP_F_INT (1 << 31) - -/* CRTC Display Size Control Register */ -#define REG_LCM_CRTC_SIZE (0x10) -#define LCM_CRTC_SIZE_VTTVAL(x) ((x) << 16) -#define LCM_CRTC_SIZE_HTTVAL(x) ((x) << 0) - -/* CRTC Display Enable End */ -#define REG_LCM_CRTC_DEND (0x14) -#define LCM_CRTC_DEND_VDENDVAL(x) ((x) << 16) -#define LCM_CRTC_DEND_HDENDVAL(x) ((x) << 0) - -/* CRTC Internal Horizontal Retrace Control Register */ -#define REG_LCM_CRTC_HR (0x18) -#define LCM_CRTC_HR_EVAL(x) ((x) << 16) -#define LCM_CRTC_HR_SVAL(x) ((x) << 0) - -/* CRTC Horizontal Sync Control Register */ -#define REG_LCM_CRTC_HSYNC (0x1C) -#define LCM_CRTC_HSYNC_SHIFTVAL(x) ((x) << 30) -#define LCM_CRTC_HSYNC_EVAL(x) ((x) << 16) -#define LCM_CRTC_HSYNC_SVAL(x) ((x) << 0) - -/* CRTC Internal Vertical Retrace Control Register */ -#define REG_LCM_CRTC_VR (0x20) -#define LCM_CRTC_VR_EVAL(x) ((x) << 16) -#define LCM_CRTC_VR_SVAL(x) ((x) << 0) - -/* Video Stream Frame Buffer-0 Starting Address */ -#define REG_LCM_VA_BADDR0 (0x24) - -/* Video Stream Frame Buffer-1 Starting Address */ -#define REG_LCM_VA_BADDR1 (0x28) - -/* Video Stream Frame Buffer Control Register */ -#define REG_LCM_VA_FBCTRL (0x2C) -#define LCM_VA_FBCTRL_IO_REGION_HALF (1 << 28) -#define LCM_VA_FBCTRL_FIELD_DUAL (1 << 29) -#define LCM_VA_FBCTRL_START_BUF (1 << 30) -#define LCM_VA_FBCTRL_DB_EN (1 << 31) - -/* Video Stream Scaling Control Register */ -#define REG_LCM_VA_SCALE (0x30) -#define LCM_VA_SCALE_XCOPY_INTERPOLATION (0 << 15) -#define LCM_VA_SCALE_XCOPY_DUPLICATION (1 << 15) - -/* Image Stream Active Window Coordinates */ -#define REG_LCM_VA_WIN (0x38) - -/* Image Stream Stuff Pixel */ -#define REG_LCM_VA_STUFF (0x3C) - -/* OSD Window Starting Coordinates */ -#define REG_LCM_OSD_WINS (0x40) - -/* OSD Window Ending Coordinates */ -#define REG_LCM_OSD_WINE (0x44) - -/* OSD Stream Frame Buffer Starting Address */ -#define REG_LCM_OSD_BADDR (0x48) - -/* OSD Stream Frame Buffer Control Register */ -#define REG_LCM_OSD_FBCTRL (0x4c) - -/* OSD Overlay Control Register */ -#define REG_LCM_OSD_OVERLAY (0x50) - -/* OSD Overlay Color-Key Pattern Register */ -#define REG_LCM_OSD_CKEY (0x54) - -/* OSD Overlay Color-Key Mask Register */ -#define REG_LCM_OSD_CMASK (0x58) - -/* OSD Window Skip1 Register */ -#define REG_LCM_OSD_SKIP1 (0x5C) - -/* OSD Window Skip2 Register */ -#define REG_LCM_OSD_SKIP2 (0x60) - -/* OSD horizontal up scaling control register */ -#define REG_LCM_OSD_SCALE (0x64) - -/* MPU Vsync control register */ -#define REG_LCM_MPU_VSYNC (0x68) - -/* Hardware cursor control Register */ -#define REG_LCM_HC_CTRL (0x6C) - -/* Hardware cursot tip point potison on va picture */ -#define REG_LCM_HC_POS (0x70) - -/* Hardware Cursor Window Buffer Control Register */ -#define REG_LCM_HC_WBCTRL (0x74) - -/* Hardware cursor memory base address register */ -#define REG_LCM_HC_BADDR (0x78) - -/* Hardware cursor color ram register mapped to bpp = 0 */ -#define REG_LCM_HC_COLOR0 (0x7C) - -/* Hardware cursor color ram register mapped to bpp = 1 */ -#define REG_LCM_HC_COLOR1 (0x80) - -/* Hardware cursor color ram register mapped to bpp = 2 */ -#define REG_LCM_HC_COLOR2 (0x84) - -/* Hardware cursor color ram register mapped to bpp = 3 */ -#define REG_LCM_HC_COLOR3 (0x88) - -#endif /* __ASM_ARM_W90X900_REGS_LDM_H */ diff --git a/arch/arm/mach-w90x900/include/mach/regs-serial.h b/arch/arm/mach-w90x900/include/mach/regs-serial.h deleted file mode 100644 index 797c9727a157..000000000000 --- a/arch/arm/mach-w90x900/include/mach/regs-serial.h +++ /dev/null @@ -1,54 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * arch/arm/mach-w90x900/include/mach/regs-serial.h - * - * Copyright (c) 2008 Nuvoton technology corporation - * All rights reserved. - * - * Wan ZongShun <mcuos.com@gmail.com> - * - * Based on arch/arm/mach-s3c2410/include/mach/regs-serial.h - */ - -#ifndef __ASM_ARM_REGS_SERIAL_H -#define __ASM_ARM_REGS_SERIAL_H - -#define UART0_BA W90X900_VA_UART -#define UART1_BA (W90X900_VA_UART+0x100) -#define UART2_BA (W90X900_VA_UART+0x200) -#define UART3_BA (W90X900_VA_UART+0x300) -#define UART4_BA (W90X900_VA_UART+0x400) - -#define UART0_PA W90X900_PA_UART -#define UART1_PA (W90X900_PA_UART+0x100) -#define UART2_PA (W90X900_PA_UART+0x200) -#define UART3_PA (W90X900_PA_UART+0x300) -#define UART4_PA (W90X900_PA_UART+0x400) - -#ifndef __ASSEMBLY__ - -struct w90x900_uart_clksrc { - const char *name; - unsigned int divisor; - unsigned int min_baud; - unsigned int max_baud; -}; - -struct w90x900_uartcfg { - unsigned char hwport; - unsigned char unused; - unsigned short flags; - unsigned long uart_flags; - - unsigned long ucon; - unsigned long ulcon; - unsigned long ufcon; - - struct w90x900_uart_clksrc *clocks; - unsigned int clocks_size; -}; - -#endif /* __ASSEMBLY__ */ - -#endif /* __ASM_ARM_REGS_SERIAL_H */ - diff --git a/arch/arm/mach-w90x900/include/mach/uncompress.h b/arch/arm/mach-w90x900/include/mach/uncompress.h deleted file mode 100644 index 32e92a77ccae..000000000000 --- a/arch/arm/mach-w90x900/include/mach/uncompress.h +++ /dev/null @@ -1,43 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * arch/arm/mach-w90x900/include/mach/uncompress.h - * - * Copyright (c) 2008 Nuvoton technology corporation - * All rights reserved. - * - * Wan ZongShun <mcuos.com@gmail.com> - * - * Based on arch/arm/mach-s3c2410/include/mach/uncompress.h - */ - -#ifndef __ASM_ARCH_UNCOMPRESS_H -#define __ASM_ARCH_UNCOMPRESS_H - -/* Defines for UART registers */ - -#include <mach/regs-serial.h> -#include <mach/map.h> -#include <linux/serial_reg.h> - -#define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE) -static volatile u32 * const uart_base = (u32 *)UART0_PA; - -static inline void putc(int ch) -{ - /* Check THRE and TEMT bits before we transmit the character. - */ - while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE) - barrier(); - - *uart_base = ch; -} - -static inline void flush(void) -{ -} - -static void arch_decomp_setup(void) -{ -} - -#endif/* __ASM_W90X900_UNCOMPRESS_H */ diff --git a/arch/arm/mach-w90x900/irq.c b/arch/arm/mach-w90x900/irq.c deleted file mode 100644 index 081b0f65477a..000000000000 --- a/arch/arm/mach-w90x900/irq.c +++ /dev/null @@ -1,212 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/mach-w90x900/irq.c - * - * based on linux/arch/arm/plat-s3c24xx/irq.c by Ben Dooks - * - * Copyright (c) 2008 Nuvoton technology corporation - * All rights reserved. - * - * Wan ZongShun <mcuos.com@gmail.com> - */ - -#include <linux/init.h> -#include <linux/module.h> -#include <linux/interrupt.h> -#include <linux/ioport.h> -#include <linux/ptrace.h> -#include <linux/device.h> -#include <linux/io.h> - -#include <asm/irq.h> -#include <asm/mach/irq.h> - -#include <mach/hardware.h> -#include <mach/regs-irq.h> - -#include "nuc9xx.h" - -struct group_irq { - unsigned long gpen; - unsigned int enabled; - void (*enable)(struct group_irq *, int enable); -}; - -static DEFINE_SPINLOCK(groupirq_lock); - -#define DEFINE_GROUP(_name, _ctrlbit, _num) \ -struct group_irq group_##_name = { \ - .enable = nuc900_group_enable, \ - .gpen = ((1 << _num) - 1) << _ctrlbit, \ - } - -static void nuc900_group_enable(struct group_irq *gpirq, int enable); - -static DEFINE_GROUP(nirq0, 0, 4); -static DEFINE_GROUP(nirq1, 4, 4); -static DEFINE_GROUP(usbh, 8, 2); -static DEFINE_GROUP(ottimer, 16, 3); -static DEFINE_GROUP(gdma, 20, 2); -static DEFINE_GROUP(sc, 24, 2); -static DEFINE_GROUP(i2c, 26, 2); -static DEFINE_GROUP(ps2, 28, 2); - -static int group_irq_enable(struct group_irq *group_irq) -{ - unsigned long flags; - - spin_lock_irqsave(&groupirq_lock, flags); - if (group_irq->enabled++ == 0) - (group_irq->enable)(group_irq, 1); - spin_unlock_irqrestore(&groupirq_lock, flags); - - return 0; -} - -static void group_irq_disable(struct group_irq *group_irq) -{ - unsigned long flags; - - WARN_ON(group_irq->enabled == 0); - - spin_lock_irqsave(&groupirq_lock, flags); - if (--group_irq->enabled == 0) - (group_irq->enable)(group_irq, 0); - spin_unlock_irqrestore(&groupirq_lock, flags); -} - -static void nuc900_group_enable(struct group_irq *gpirq, int enable) -{ - unsigned int groupen = gpirq->gpen; - unsigned long regval; - - regval = __raw_readl(REG_AIC_GEN); - - if (enable) - regval |= groupen; - else - regval &= ~groupen; - - __raw_writel(regval, REG_AIC_GEN); -} - -static void nuc900_irq_mask(struct irq_data *d) -{ - struct group_irq *group_irq; - - group_irq = NULL; - - __raw_writel(1 << d->irq, REG_AIC_MDCR); - - switch (d->irq) { - case IRQ_GROUP0: - group_irq = &group_nirq0; - break; - - case IRQ_GROUP1: - group_irq = &group_nirq1; - break; - - case IRQ_USBH: - group_irq = &group_usbh; - break; - - case IRQ_T_INT_GROUP: - group_irq = &group_ottimer; - break; - - case IRQ_GDMAGROUP: - group_irq = &group_gdma; - break; - - case IRQ_SCGROUP: - group_irq = &group_sc; - break; - - case IRQ_I2CGROUP: - group_irq = &group_i2c; - break; - - case IRQ_P2SGROUP: - group_irq = &group_ps2; - break; - } - - if (group_irq) - group_irq_disable(group_irq); -} - -/* - * By the w90p910 spec,any irq,only write 1 - * to REG_AIC_EOSCR for ACK - */ - -static void nuc900_irq_ack(struct irq_data *d) -{ - __raw_writel(0x01, REG_AIC_EOSCR); -} - -static void nuc900_irq_unmask(struct irq_data *d) -{ - struct group_irq *group_irq; - - group_irq = NULL; - - __raw_writel(1 << d->irq, REG_AIC_MECR); - - switch (d->irq) { - case IRQ_GROUP0: - group_irq = &group_nirq0; - break; - - case IRQ_GROUP1: - group_irq = &group_nirq1; - break; - - case IRQ_USBH: - group_irq = &group_usbh; - break; - - case IRQ_T_INT_GROUP: - group_irq = &group_ottimer; - break; - - case IRQ_GDMAGROUP: - group_irq = &group_gdma; - break; - - case IRQ_SCGROUP: - group_irq = &group_sc; - break; - - case IRQ_I2CGROUP: - group_irq = &group_i2c; - break; - - case IRQ_P2SGROUP: - group_irq = &group_ps2; - break; - } - - if (group_irq) - group_irq_enable(group_irq); -} - -static struct irq_chip nuc900_irq_chip = { - .irq_ack = nuc900_irq_ack, - .irq_mask = nuc900_irq_mask, - .irq_unmask = nuc900_irq_unmask, -}; - -void __init nuc900_init_irq(void) -{ - int irqno; - - __raw_writel(0xFFFFFFFE, REG_AIC_MDCR); - - for (irqno = IRQ_WDT; irqno <= IRQ_ADC; irqno++) { - irq_set_chip_and_handler(irqno, &nuc900_irq_chip, - handle_level_irq); - irq_clear_status_flags(irqno, IRQ_NOREQUEST); - } -} diff --git a/arch/arm/mach-w90x900/mach-nuc910evb.c b/arch/arm/mach-w90x900/mach-nuc910evb.c deleted file mode 100644 index e6d30af3e35a..000000000000 --- a/arch/arm/mach-w90x900/mach-nuc910evb.c +++ /dev/null @@ -1,38 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/mach-w90x900/mach-nuc910evb.c - * - * Based on mach-s3c2410/mach-smdk2410.c by Jonas Dietsche - * - * Copyright (C) 2008 Nuvoton technology corporation. - * - * Wan ZongShun <mcuos.com@gmail.com> - */ - -#include <linux/platform_device.h> -#include <asm/mach/arch.h> -#include <asm/mach/map.h> -#include <asm/mach-types.h> -#include <mach/map.h> - -#include "nuc910.h" - -static void __init nuc910evb_map_io(void) -{ - nuc910_map_io(); - nuc910_init_clocks(); -} - -static void __init nuc910evb_init(void) -{ - nuc910_board_init(); -} - -MACHINE_START(W90P910EVB, "W90P910EVB") - /* Maintainer: Wan ZongShun */ - .map_io = nuc910evb_map_io, - .init_irq = nuc900_init_irq, - .init_machine = nuc910evb_init, - .init_time = nuc900_timer_init, - .restart = nuc9xx_restart, -MACHINE_END diff --git a/arch/arm/mach-w90x900/mach-nuc950evb.c b/arch/arm/mach-w90x900/mach-nuc950evb.c deleted file mode 100644 index 62547308c344..000000000000 --- a/arch/arm/mach-w90x900/mach-nuc950evb.c +++ /dev/null @@ -1,42 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/mach-w90x900/mach-nuc950evb.c - * - * Based on mach-s3c2410/mach-smdk2410.c by Jonas Dietsche - * - * Copyright (C) 2008 Nuvoton technology corporation. - * - * Wan ZongShun <mcuos.com@gmail.com> - * - * history: - * Wang Qiang (rurality.linux@gmail.com) add LCD support - */ - -#include <linux/platform_device.h> -#include <asm/mach/arch.h> -#include <asm/mach/map.h> -#include <asm/mach-types.h> -#include <mach/map.h> -#include <linux/platform_data/video-nuc900fb.h> - -#include "nuc950.h" - -static void __init nuc950evb_map_io(void) -{ - nuc950_map_io(); - nuc950_init_clocks(); -} - -static void __init nuc950evb_init(void) -{ - nuc950_board_init(); -} - -MACHINE_START(W90P950EVB, "W90P950EVB") - /* Maintainer: Wan ZongShun */ - .map_io = nuc950evb_map_io, - .init_irq = nuc900_init_irq, - .init_machine = nuc950evb_init, - .init_time = nuc900_timer_init, - .restart = nuc9xx_restart, -MACHINE_END diff --git a/arch/arm/mach-w90x900/mach-nuc960evb.c b/arch/arm/mach-w90x900/mach-nuc960evb.c deleted file mode 100644 index 35a53459d0d2..000000000000 --- a/arch/arm/mach-w90x900/mach-nuc960evb.c +++ /dev/null @@ -1,38 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/mach-w90x900/mach-nuc960evb.c - * - * Based on mach-s3c2410/mach-smdk2410.c by Jonas Dietsche - * - * Copyright (C) 2008 Nuvoton technology corporation. - * - * Wan ZongShun <mcuos.com@gmail.com> - */ - -#include <linux/platform_device.h> -#include <asm/mach/arch.h> -#include <asm/mach/map.h> -#include <asm/mach-types.h> -#include <mach/map.h> - -#include "nuc960.h" - -static void __init nuc960evb_map_io(void) -{ - nuc960_map_io(); - nuc960_init_clocks(); -} - -static void __init nuc960evb_init(void) -{ - nuc960_board_init(); -} - -MACHINE_START(W90N960EVB, "W90N960EVB") - /* Maintainer: Wan ZongShun */ - .map_io = nuc960evb_map_io, - .init_irq = nuc900_init_irq, - .init_machine = nuc960evb_init, - .init_time = nuc900_timer_init, - .restart = nuc9xx_restart, -MACHINE_END diff --git a/arch/arm/mach-w90x900/mfp.c b/arch/arm/mach-w90x900/mfp.c deleted file mode 100644 index 05f3779a3618..000000000000 --- a/arch/arm/mach-w90x900/mfp.c +++ /dev/null @@ -1,197 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/mach-w90x900/mfp.c - * - * Copyright (c) 2008 Nuvoton technology corporation - * - * Wan ZongShun <mcuos.com@gmail.com> - */ - -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/device.h> -#include <linux/list.h> -#include <linux/errno.h> -#include <linux/err.h> -#include <linux/string.h> -#include <linux/clk.h> -#include <linux/mutex.h> -#include <linux/io.h> - -#include <mach/hardware.h> - -#define REG_MFSEL (W90X900_VA_GCR + 0xC) - -#define GPSELF (0x01 << 1) -#define GPSELC (0x03 << 2) -#define GPSELD (0x0f << 4) - -#define GPSELEI0 (0x01 << 26) -#define GPSELEI1 (0x01 << 27) - -#define GPIOG0TO1 (0x03 << 14) -#define GPIOG2TO3 (0x03 << 16) -#define GPIOG22TO23 (0x03 << 22) -#define GPIOG18TO20 (0x07 << 18) - -#define ENSPI (0x0a << 14) -#define ENI2C0 (0x01 << 14) -#define ENI2C1 (0x01 << 16) -#define ENAC97 (0x02 << 22) -#define ENSD1 (0x02 << 18) -#define ENSD0 (0x0a << 4) -#define ENKPI (0x02 << 2) -#define ENNAND (0x01 << 2) - -static DEFINE_MUTEX(mfp_mutex); - -void mfp_set_groupf(struct device *dev) -{ - unsigned long mfpen; - const char *dev_id; - - BUG_ON(!dev); - - mutex_lock(&mfp_mutex); - - dev_id = dev_name(dev); - - mfpen = __raw_readl(REG_MFSEL); - - if (strcmp(dev_id, "nuc900-emc") == 0) - mfpen |= GPSELF;/*enable mac*/ - else - mfpen &= ~GPSELF;/*GPIOF[9:0]*/ - - __raw_writel(mfpen, REG_MFSEL); - - mutex_unlock(&mfp_mutex); -} -EXPORT_SYMBOL(mfp_set_groupf); - -void mfp_set_groupc(struct device *dev) -{ - unsigned long mfpen; - const char *dev_id; - - BUG_ON(!dev); - - mutex_lock(&mfp_mutex); - - dev_id = dev_name(dev); - - mfpen = __raw_readl(REG_MFSEL); - - if (strcmp(dev_id, "nuc900-lcd") == 0) - mfpen |= GPSELC;/*enable lcd*/ - else if (strcmp(dev_id, "nuc900-kpi") == 0) { - mfpen &= (~GPSELC);/*enable kpi*/ - mfpen |= ENKPI; - } else if (strcmp(dev_id, "nuc900-nand") == 0) { - mfpen &= (~GPSELC);/*enable nand*/ - mfpen |= ENNAND; - } else - mfpen &= (~GPSELC);/*GPIOC[14:0]*/ - - __raw_writel(mfpen, REG_MFSEL); - - mutex_unlock(&mfp_mutex); -} -EXPORT_SYMBOL(mfp_set_groupc); - -void mfp_set_groupi(struct device *dev) -{ - unsigned long mfpen; - const char *dev_id; - - BUG_ON(!dev); - - mutex_lock(&mfp_mutex); - - dev_id = dev_name(dev); - - mfpen = __raw_readl(REG_MFSEL); - - mfpen &= ~GPSELEI1;/*default gpio16*/ - - if (strcmp(dev_id, "nuc900-wdog") == 0) - mfpen |= GPSELEI1;/*enable wdog*/ - else if (strcmp(dev_id, "nuc900-atapi") == 0) - mfpen |= GPSELEI0;/*enable atapi*/ - else if (strcmp(dev_id, "nuc900-keypad") == 0) - mfpen &= ~GPSELEI0;/*enable keypad*/ - - __raw_writel(mfpen, REG_MFSEL); - - mutex_unlock(&mfp_mutex); -} -EXPORT_SYMBOL(mfp_set_groupi); - -void mfp_set_groupg(struct device *dev, const char *subname) -{ - unsigned long mfpen; - const char *dev_id; - - BUG_ON((!dev) && (!subname)); - - mutex_lock(&mfp_mutex); - - if (subname != NULL) - dev_id = subname; - else - dev_id = dev_name(dev); - - mfpen = __raw_readl(REG_MFSEL); - - if (strcmp(dev_id, "nuc900-spi") == 0) { - mfpen &= ~(GPIOG0TO1 | GPIOG2TO3); - mfpen |= ENSPI;/*enable spi*/ - } else if (strcmp(dev_id, "nuc900-i2c0") == 0) { - mfpen &= ~(GPIOG0TO1); - mfpen |= ENI2C0;/*enable i2c0*/ - } else if (strcmp(dev_id, "nuc900-i2c1") == 0) { - mfpen &= ~(GPIOG2TO3); - mfpen |= ENI2C1;/*enable i2c1*/ - } else if (strcmp(dev_id, "nuc900-ac97") == 0) { - mfpen &= ~(GPIOG22TO23); - mfpen |= ENAC97;/*enable AC97*/ - } else if (strcmp(dev_id, "nuc900-mmc-port1") == 0) { - mfpen &= ~(GPIOG18TO20); - mfpen |= (ENSD1 | 0x01);/*enable sd1*/ - } else { - mfpen &= ~(GPIOG0TO1 | GPIOG2TO3);/*GPIOG[3:0]*/ - } - - __raw_writel(mfpen, REG_MFSEL); - - mutex_unlock(&mfp_mutex); -} -EXPORT_SYMBOL(mfp_set_groupg); - -void mfp_set_groupd(struct device *dev, const char *subname) -{ - unsigned long mfpen; - const char *dev_id; - - BUG_ON((!dev) && (!subname)); - - mutex_lock(&mfp_mutex); - - if (subname != NULL) - dev_id = subname; - else - dev_id = dev_name(dev); - - mfpen = __raw_readl(REG_MFSEL); - - if (strcmp(dev_id, "nuc900-mmc-port0") == 0) { - mfpen &= ~GPSELD;/*enable sd0*/ - mfpen |= ENSD0; - } else - mfpen &= (~GPSELD); - - __raw_writel(mfpen, REG_MFSEL); - - mutex_unlock(&mfp_mutex); -} -EXPORT_SYMBOL(mfp_set_groupd); diff --git a/arch/arm/mach-w90x900/nuc910.c b/arch/arm/mach-w90x900/nuc910.c deleted file mode 100644 index 45ae8285bfc9..000000000000 --- a/arch/arm/mach-w90x900/nuc910.c +++ /dev/null @@ -1,58 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/mach-w90x900/nuc910.c - * - * Based on linux/arch/arm/plat-s3c24xx/s3c244x.c by Ben Dooks - * - * Copyright (c) 2009 Nuvoton corporation. - * - * Wan ZongShun <mcuos.com@gmail.com> - * - * NUC910 cpu support - */ - -#include <linux/platform_device.h> -#include <asm/mach/map.h> -#include <mach/hardware.h> -#include "cpu.h" -#include "clock.h" - -/* define specific CPU platform device */ - -static struct platform_device *nuc910_dev[] __initdata = { - &nuc900_device_ts, - &nuc900_device_rtc, - &nuc900_device_lcd, - &nuc900_device_kpi, -}; - -/* define specific CPU platform io map */ - -static struct map_desc nuc910evb_iodesc[] __initdata = { - IODESC_ENT(USBEHCIHOST), - IODESC_ENT(USBOHCIHOST), - IODESC_ENT(KPI), - IODESC_ENT(USBDEV), - IODESC_ENT(ADC), -}; - -/*Init NUC910 evb io*/ - -void __init nuc910_map_io(void) -{ - nuc900_map_io(nuc910evb_iodesc, ARRAY_SIZE(nuc910evb_iodesc)); -} - -/*Init NUC910 clock*/ - -void __init nuc910_init_clocks(void) -{ - nuc900_init_clocks(); -} - -/*Init NUC910 board info*/ - -void __init nuc910_board_init(void) -{ - nuc900_board_init(nuc910_dev, ARRAY_SIZE(nuc910_dev)); -} diff --git a/arch/arm/mach-w90x900/nuc910.h b/arch/arm/mach-w90x900/nuc910.h deleted file mode 100644 index 53be3323736f..000000000000 --- a/arch/arm/mach-w90x900/nuc910.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * arch/arm/mach-w90x900/nuc910.h - * - * Copyright (c) 2008 Nuvoton corporation - * - * Header file for NUC900 CPU support - * - * Wan ZongShun <mcuos.com@gmail.com> - */ -#include "nuc9xx.h" - -/* extern file from nuc910.c */ - -extern void nuc910_board_init(void); -extern void nuc910_init_clocks(void); -extern void nuc910_map_io(void); diff --git a/arch/arm/mach-w90x900/nuc950.c b/arch/arm/mach-w90x900/nuc950.c deleted file mode 100644 index 3be114249cd8..000000000000 --- a/arch/arm/mach-w90x900/nuc950.c +++ /dev/null @@ -1,52 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/mach-w90x900/nuc950.c - * - * Based on linux/arch/arm/plat-s3c24xx/s3c244x.c by Ben Dooks - * - * Copyright (c) 2008 Nuvoton technology corporation. - * - * Wan ZongShun <mcuos.com@gmail.com> - * - * NUC950 cpu support - */ - -#include <linux/platform_device.h> -#include <asm/mach/map.h> -#include <mach/hardware.h> - -#include "cpu.h" - -/* define specific CPU platform device */ - -static struct platform_device *nuc950_dev[] __initdata = { - &nuc900_device_kpi, - &nuc900_device_fmi, - &nuc900_device_lcd, -}; - -/* define specific CPU platform io map */ - -static struct map_desc nuc950evb_iodesc[] __initdata = { -}; - -/*Init NUC950 evb io*/ - -void __init nuc950_map_io(void) -{ - nuc900_map_io(nuc950evb_iodesc, ARRAY_SIZE(nuc950evb_iodesc)); -} - -/*Init NUC950 clock*/ - -void __init nuc950_init_clocks(void) -{ - nuc900_init_clocks(); -} - -/*Init NUC950 board info*/ - -void __init nuc950_board_init(void) -{ - nuc900_board_init(nuc950_dev, ARRAY_SIZE(nuc950_dev)); -} diff --git a/arch/arm/mach-w90x900/nuc950.h b/arch/arm/mach-w90x900/nuc950.h deleted file mode 100644 index 23cff81ea630..000000000000 --- a/arch/arm/mach-w90x900/nuc950.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * arch/arm/mach-w90x900/nuc950.h - * - * Copyright (c) 2008 Nuvoton corporation - * - * Header file for NUC900 CPU support - * - * Wan ZongShun <mcuos.com@gmail.com> - */ -#include "nuc9xx.h" - -/* extern file from nuc950.c */ - -extern void nuc950_board_init(void); -extern void nuc950_init_clocks(void); -extern void nuc950_map_io(void); diff --git a/arch/arm/mach-w90x900/nuc960.c b/arch/arm/mach-w90x900/nuc960.c deleted file mode 100644 index 8a27d74b975e..000000000000 --- a/arch/arm/mach-w90x900/nuc960.c +++ /dev/null @@ -1,50 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/mach-w90x900/nuc960.c - * - * Based on linux/arch/arm/plat-s3c24xx/s3c244x.c by Ben Dooks - * - * Copyright (c) 2008 Nuvoton technology corporation. - * - * Wan ZongShun <mcuos.com@gmail.com> - * - * NUC960 cpu support - */ - -#include <linux/platform_device.h> -#include <asm/mach/map.h> -#include <mach/hardware.h> -#include "cpu.h" - -/* define specific CPU platform device */ - -static struct platform_device *nuc960_dev[] __initdata = { - &nuc900_device_kpi, - &nuc900_device_fmi, -}; - -/* define specific CPU platform io map */ - -static struct map_desc nuc960evb_iodesc[] __initdata = { -}; - -/*Init NUC960 evb io*/ - -void __init nuc960_map_io(void) -{ - nuc900_map_io(nuc960evb_iodesc, ARRAY_SIZE(nuc960evb_iodesc)); -} - -/*Init NUC960 clock*/ - -void __init nuc960_init_clocks(void) -{ - nuc900_init_clocks(); -} - -/*Init NUC960 board info*/ - -void __init nuc960_board_init(void) -{ - nuc900_board_init(nuc960_dev, ARRAY_SIZE(nuc960_dev)); -} diff --git a/arch/arm/mach-w90x900/nuc960.h b/arch/arm/mach-w90x900/nuc960.h deleted file mode 100644 index 88bb13c971dc..000000000000 --- a/arch/arm/mach-w90x900/nuc960.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * arch/arm/mach-w90x900/nuc960.h - * - * Copyright (c) 2008 Nuvoton corporation - * - * Header file for NUC900 CPU support - * - * Wan ZongShun <mcuos.com@gmail.com> - */ -#include "nuc9xx.h" - -/* extern file from nuc960.c */ - -extern void nuc960_board_init(void); -extern void nuc960_init_clocks(void); -extern void nuc960_map_io(void); diff --git a/arch/arm/mach-w90x900/nuc9xx.h b/arch/arm/mach-w90x900/nuc9xx.h deleted file mode 100644 index 21f6f9c304e8..000000000000 --- a/arch/arm/mach-w90x900/nuc9xx.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * arch/arm/mach-w90x900/nuc9xx.h - * - * Copied from nuc910.h, which had: - * - * Copyright (c) 2008 Nuvoton corporation - * - * Header file for NUC900 CPU support - * - * Wan ZongShun <mcuos.com@gmail.com> - */ - -#include <linux/reboot.h> - -struct map_desc; - -/* core initialisation functions */ - -extern void nuc900_init_irq(void); -extern void nuc900_timer_init(void); -extern void nuc9xx_restart(enum reboot_mode, const char *); diff --git a/arch/arm/mach-w90x900/regs-ebi.h b/arch/arm/mach-w90x900/regs-ebi.h deleted file mode 100644 index 3fb22702cfc0..000000000000 --- a/arch/arm/mach-w90x900/regs-ebi.h +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * arch/arm/mach-w90x900/include/mach/regs-ebi.h - * - * Copyright (c) 2009 Nuvoton technology corporation. - * - * Wan ZongShun <mcuos.com@gmail.com> - */ - -#ifndef __ASM_ARCH_REGS_EBI_H -#define __ASM_ARCH_REGS_EBI_H - -/* EBI Control Registers */ - -#define EBI_BA W90X900_VA_EBI -#define REG_EBICON (EBI_BA + 0x00) -#define REG_ROMCON (EBI_BA + 0x04) -#define REG_SDCONF0 (EBI_BA + 0x08) -#define REG_SDCONF1 (EBI_BA + 0x0C) -#define REG_SDTIME0 (EBI_BA + 0x10) -#define REG_SDTIME1 (EBI_BA + 0x14) -#define REG_EXT0CON (EBI_BA + 0x18) -#define REG_EXT1CON (EBI_BA + 0x1C) -#define REG_EXT2CON (EBI_BA + 0x20) -#define REG_EXT3CON (EBI_BA + 0x24) -#define REG_EXT4CON (EBI_BA + 0x28) -#define REG_CKSKEW (EBI_BA + 0x2C) - -#endif /* __ASM_ARCH_REGS_EBI_H */ diff --git a/arch/arm/mach-w90x900/regs-gcr.h b/arch/arm/mach-w90x900/regs-gcr.h deleted file mode 100644 index caf1090ecad8..000000000000 --- a/arch/arm/mach-w90x900/regs-gcr.h +++ /dev/null @@ -1,34 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * arch/arm/mach-w90x900/include/mach/regs-gcr.h - * - * Copyright (c) 2010 Nuvoton technology corporation - * All rights reserved. - * - * Wan ZongShun <mcuos.com@gmail.com> - */ - -#ifndef __ASM_ARCH_REGS_GCR_H -#define __ASM_ARCH_REGS_GCR_H - -/* Global control registers */ - -#define GCR_BA W90X900_VA_GCR -#define REG_PDID (GCR_BA+0x000) -#define REG_PWRON (GCR_BA+0x004) -#define REG_ARBCON (GCR_BA+0x008) -#define REG_MFSEL (GCR_BA+0x00C) -#define REG_EBIDPE (GCR_BA+0x010) -#define REG_LCDDPE (GCR_BA+0x014) -#define REG_GPIOCPE (GCR_BA+0x018) -#define REG_GPIODPE (GCR_BA+0x01C) -#define REG_GPIOEPE (GCR_BA+0x020) -#define REG_GPIOFPE (GCR_BA+0x024) -#define REG_GPIOGPE (GCR_BA+0x028) -#define REG_GPIOHPE (GCR_BA+0x02C) -#define REG_GPIOIPE (GCR_BA+0x030) -#define REG_GTMP1 (GCR_BA+0x034) -#define REG_GTMP2 (GCR_BA+0x038) -#define REG_GTMP3 (GCR_BA+0x03C) - -#endif /* __ASM_ARCH_REGS_GCR_H */ diff --git a/arch/arm/mach-w90x900/regs-timer.h b/arch/arm/mach-w90x900/regs-timer.h deleted file mode 100644 index d12807fd1e3e..000000000000 --- a/arch/arm/mach-w90x900/regs-timer.h +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * arch/arm/mach-w90x900/include/mach/regs-timer.h - * - * Copyright (c) 2008 Nuvoton technology corporation - * All rights reserved. - * - * Wan ZongShun <mcuos.com@gmail.com> - * - * Based on arch/arm/mach-s3c2410/include/mach/regs-timer.h - */ - -#ifndef __ASM_ARCH_REGS_TIMER_H -#define __ASM_ARCH_REGS_TIMER_H - -/* Timer Registers */ - -#define TMR_BA W90X900_VA_TIMER -#define REG_TCSR0 (TMR_BA+0x00) -#define REG_TCSR1 (TMR_BA+0x04) -#define REG_TICR0 (TMR_BA+0x08) -#define REG_TICR1 (TMR_BA+0x0C) -#define REG_TDR0 (TMR_BA+0x10) -#define REG_TDR1 (TMR_BA+0x14) -#define REG_TISR (TMR_BA+0x18) -#define REG_WTCR (TMR_BA+0x1C) -#define REG_TCSR2 (TMR_BA+0x20) -#define REG_TCSR3 (TMR_BA+0x24) -#define REG_TICR2 (TMR_BA+0x28) -#define REG_TICR3 (TMR_BA+0x2C) -#define REG_TDR2 (TMR_BA+0x30) -#define REG_TDR3 (TMR_BA+0x34) -#define REG_TCSR4 (TMR_BA+0x40) -#define REG_TICR4 (TMR_BA+0x48) -#define REG_TDR4 (TMR_BA+0x50) - -#endif /* __ASM_ARCH_REGS_TIMER_H */ diff --git a/arch/arm/mach-w90x900/regs-usb.h b/arch/arm/mach-w90x900/regs-usb.h deleted file mode 100644 index 98046c811bf7..000000000000 --- a/arch/arm/mach-w90x900/regs-usb.h +++ /dev/null @@ -1,31 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * arch/arm/mach-w90x900/include/mach/regs-usb.h - * - * Copyright (c) 2008 Nuvoton technology corporation. - * - * Wan ZongShun <mcuos.com@gmail.com> - */ - -#ifndef __ASM_ARCH_REGS_USB_H -#define __ASM_ARCH_REGS_USB_H - -/* usb Control Registers */ -#define USBH_BA W90X900_VA_USBEHCIHOST -#define USBD_BA W90X900_VA_USBDEV -#define USBO_BA W90X900_VA_USBOHCIHOST - -/* USB Host Control Registers */ -#define REG_UPSCR0 (USBH_BA+0x064) -#define REG_UPSCR1 (USBH_BA+0x068) -#define REG_USBPCR0 (USBH_BA+0x0C4) -#define REG_USBPCR1 (USBH_BA+0x0C8) - -/* USBH OHCI Control Registers */ -#define REG_OpModEn (USBO_BA+0x204) -/*This bit controls the polarity of over -*current flag from external power IC. -*/ -#define OCALow 0x08 - -#endif /* __ASM_ARCH_REGS_USB_H */ diff --git a/arch/arm/mach-w90x900/time.c b/arch/arm/mach-w90x900/time.c deleted file mode 100644 index dd20fab9a960..000000000000 --- a/arch/arm/mach-w90x900/time.c +++ /dev/null @@ -1,168 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * linux/arch/arm/mach-w90x900/time.c - * - * Based on linux/arch/arm/plat-s3c24xx/time.c by Ben Dooks - * - * Copyright (c) 2009 Nuvoton technology corporation - * All rights reserved. - * - * Wan ZongShun <mcuos.com@gmail.com> - */ - -#include <linux/kernel.h> -#include <linux/sched.h> -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/err.h> -#include <linux/clk.h> -#include <linux/io.h> -#include <linux/leds.h> -#include <linux/clocksource.h> -#include <linux/clockchips.h> - -#include <asm/mach-types.h> -#include <asm/mach/irq.h> -#include <asm/mach/time.h> - -#include <mach/map.h> -#include "regs-timer.h" - -#include "nuc9xx.h" - -#define RESETINT 0x1f -#define PERIOD (0x01 << 27) -#define ONESHOT (0x00 << 27) -#define COUNTEN (0x01 << 30) -#define INTEN (0x01 << 29) - -#define TICKS_PER_SEC 100 -#define PRESCALE 0x63 /* Divider = prescale + 1 */ - -#define TDR_SHIFT 24 - -static unsigned int timer0_load; - -static int nuc900_clockevent_shutdown(struct clock_event_device *evt) -{ - unsigned int val = __raw_readl(REG_TCSR0) & ~(0x03 << 27); - - __raw_writel(val, REG_TCSR0); - return 0; -} - -static int nuc900_clockevent_set_oneshot(struct clock_event_device *evt) -{ - unsigned int val = __raw_readl(REG_TCSR0) & ~(0x03 << 27); - - val |= (ONESHOT | COUNTEN | INTEN | PRESCALE); - - __raw_writel(val, REG_TCSR0); - return 0; -} - -static int nuc900_clockevent_set_periodic(struct clock_event_device *evt) -{ - unsigned int val = __raw_readl(REG_TCSR0) & ~(0x03 << 27); - - __raw_writel(timer0_load, REG_TICR0); - val |= (PERIOD | COUNTEN | INTEN | PRESCALE); - __raw_writel(val, REG_TCSR0); - return 0; -} - -static int nuc900_clockevent_setnextevent(unsigned long evt, - struct clock_event_device *clk) -{ - unsigned int val; - - __raw_writel(evt, REG_TICR0); - - val = __raw_readl(REG_TCSR0); - val |= (COUNTEN | INTEN | PRESCALE); - __raw_writel(val, REG_TCSR0); - - return 0; -} - -static struct clock_event_device nuc900_clockevent_device = { - .name = "nuc900-timer0", - .features = CLOCK_EVT_FEAT_PERIODIC | - CLOCK_EVT_FEAT_ONESHOT, - .set_state_shutdown = nuc900_clockevent_shutdown, - .set_state_periodic = nuc900_clockevent_set_periodic, - .set_state_oneshot = nuc900_clockevent_set_oneshot, - .tick_resume = nuc900_clockevent_shutdown, - .set_next_event = nuc900_clockevent_setnextevent, - .rating = 300, -}; - -/*IRQ handler for the timer*/ - -static irqreturn_t nuc900_timer0_interrupt(int irq, void *dev_id) -{ - struct clock_event_device *evt = &nuc900_clockevent_device; - - __raw_writel(0x01, REG_TISR); /* clear TIF0 */ - - evt->event_handler(evt); - return IRQ_HANDLED; -} - -static struct irqaction nuc900_timer0_irq = { - .name = "nuc900-timer0", - .flags = IRQF_TIMER | IRQF_IRQPOLL, - .handler = nuc900_timer0_interrupt, -}; - -static void __init nuc900_clockevents_init(void) -{ - unsigned int rate; - struct clk *clk = clk_get(NULL, "timer0"); - - BUG_ON(IS_ERR(clk)); - - __raw_writel(0x00, REG_TCSR0); - - clk_enable(clk); - rate = clk_get_rate(clk) / (PRESCALE + 1); - - timer0_load = (rate / TICKS_PER_SEC); - - __raw_writel(RESETINT, REG_TISR); - setup_irq(IRQ_TIMER0, &nuc900_timer0_irq); - - nuc900_clockevent_device.cpumask = cpumask_of(0); - - clockevents_config_and_register(&nuc900_clockevent_device, rate, - 0xf, 0xffffffff); -} - -static void __init nuc900_clocksource_init(void) -{ - unsigned int val; - unsigned int rate; - struct clk *clk = clk_get(NULL, "timer1"); - - BUG_ON(IS_ERR(clk)); - - __raw_writel(0x00, REG_TCSR1); - - clk_enable(clk); - rate = clk_get_rate(clk) / (PRESCALE + 1); - - __raw_writel(0xffffffff, REG_TICR1); - - val = __raw_readl(REG_TCSR1); - val |= (COUNTEN | PERIOD | PRESCALE); - __raw_writel(val, REG_TCSR1); - - clocksource_mmio_init(REG_TDR1, "nuc900-timer1", rate, 200, - TDR_SHIFT, clocksource_mmio_readl_down); -} - -void __init nuc900_timer_init(void) -{ - nuc900_clocksource_init(); - nuc900_clockevents_init(); -} diff --git a/arch/arm/mach-zynq/headsmp.S b/arch/arm/mach-zynq/headsmp.S index ab85003cf9ad..3449e0d1f990 100644 --- a/arch/arm/mach-zynq/headsmp.S +++ b/arch/arm/mach-zynq/headsmp.S @@ -7,6 +7,8 @@ #include <linux/init.h> #include <asm/assembler.h> + .arm + ENTRY(zynq_secondary_trampoline) ARM_BE8(setend be) @ ensure we are in BE8 mode ldr r0, zynq_secondary_trampoline_jump diff --git a/arch/arm/mach-zynq/platsmp.c b/arch/arm/mach-zynq/platsmp.c index a7cfe07156f4..a10085be9073 100644 --- a/arch/arm/mach-zynq/platsmp.c +++ b/arch/arm/mach-zynq/platsmp.c @@ -57,7 +57,7 @@ int zynq_cpun_start(u32 address, int cpu) * 0x4: Jump by mov instruction * 0x8: Jumping address */ - memcpy((__force void *)zero, &zynq_secondary_trampoline, + memcpy_toio(zero, &zynq_secondary_trampoline, trampoline_size); writel(address, zero + trampoline_size); @@ -81,7 +81,7 @@ EXPORT_SYMBOL(zynq_cpun_start); static int zynq_boot_secondary(unsigned int cpu, struct task_struct *idle) { - return zynq_cpun_start(__pa_symbol(secondary_startup), cpu); + return zynq_cpun_start(__pa_symbol(secondary_startup_arm), cpu); } /* diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index c1222c0e9fd3..0ab3a86b1f52 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -106,7 +106,7 @@ config CPU_ARM922T help The ARM922T is a version of the ARM920T, but with smaller instruction and data caches. It is used in Altera's - Excalibur XA device family and Micrel's KS8695 Centaur. + Excalibur XA device family and the ARM Integrator. Say Y if you want support for the ARM922T processor. Otherwise, say N. diff --git a/arch/arm/mm/copypage-xscale.c b/arch/arm/mm/copypage-xscale.c index 61d834157bc0..382e1c2855e8 100644 --- a/arch/arm/mm/copypage-xscale.c +++ b/arch/arm/mm/copypage-xscale.c @@ -42,6 +42,7 @@ static void mc_copy_user_page(void *from, void *to) * when prefetching destination as well. (NP) */ asm volatile ("\ +.arch xscale \n\ pld [%0, #0] \n\ pld [%0, #32] \n\ pld [%1, #0] \n\ @@ -106,8 +107,9 @@ void xscale_mc_clear_user_highpage(struct page *page, unsigned long vaddr) { void *ptr, *kaddr = kmap_atomic(page); - asm volatile( - "mov r1, %2 \n\ + asm volatile("\ +.arch xscale \n\ + mov r1, %2 \n\ mov r2, #0 \n\ mov r3, #0 \n\ 1: mov ip, %0 \n\ diff --git a/arch/arm/plat-iop/Makefile b/arch/arm/plat-iop/Makefile deleted file mode 100644 index 4d839a3cf284..000000000000 --- a/arch/arm/plat-iop/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# -# Makefile for the linux kernel. -# - -# IOP32X -obj-$(CONFIG_ARCH_IOP32X) += i2c.o -obj-$(CONFIG_ARCH_IOP32X) += pci.o -obj-$(CONFIG_ARCH_IOP32X) += setup.o -obj-$(CONFIG_ARCH_IOP32X) += time.o -obj-$(CONFIG_ARCH_IOP32X) += cp6.o -obj-$(CONFIG_ARCH_IOP32X) += adma.o -obj-$(CONFIG_ARCH_IOP32X) += pmu.o -obj-$(CONFIG_ARCH_IOP32X) += restart.o - -# IOP33X -obj-$(CONFIG_ARCH_IOP33X) += i2c.o -obj-$(CONFIG_ARCH_IOP33X) += pci.o -obj-$(CONFIG_ARCH_IOP33X) += setup.o -obj-$(CONFIG_ARCH_IOP33X) += time.o -obj-$(CONFIG_ARCH_IOP33X) += cp6.o -obj-$(CONFIG_ARCH_IOP33X) += adma.o -obj-$(CONFIG_ARCH_IOP33X) += pmu.o -obj-$(CONFIG_ARCH_IOP33X) += restart.o - -# IOP13XX -obj-$(CONFIG_ARCH_IOP13XX) += cp6.o -obj-$(CONFIG_ARCH_IOP13XX) += time.o diff --git a/arch/arm/plat-samsung/include/plat/gpio-core.h b/arch/arm/plat-samsung/include/plat/gpio-core.h index 51e721f5e491..c0bfceb88340 100644 --- a/arch/arm/plat-samsung/include/plat/gpio-core.h +++ b/arch/arm/plat-samsung/include/plat/gpio-core.h @@ -12,6 +12,7 @@ /* Bring in machine-local definitions, especially S3C_GPIO_END */ #include <mach/gpio-samsung.h> +#include <linux/gpio/driver.h> #define GPIOCON_OFF (0x00) #define GPIODAT_OFF (0x04) diff --git a/arch/arm/plat-samsung/include/plat/usb-phy.h b/arch/arm/plat-samsung/include/plat/usb-phy.h index 6d0c788beb9d..94da89ecbd3b 100644 --- a/arch/arm/plat-samsung/include/plat/usb-phy.h +++ b/arch/arm/plat-samsung/include/plat/usb-phy.h @@ -7,8 +7,6 @@ #ifndef __PLAT_SAMSUNG_USB_PHY_H #define __PLAT_SAMSUNG_USB_PHY_H __FILE__ -#include <linux/usb/samsung_usb_phy.h> - extern int s5p_usb_phy_init(struct platform_device *pdev, int type); extern int s5p_usb_phy_exit(struct platform_device *pdev, int type); diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 4778c775de1b..16d761475a86 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -77,6 +77,7 @@ config ARCH_BRCMSTB config ARCH_EXYNOS bool "ARMv8 based Samsung Exynos SoC family" select COMMON_CLK_SAMSUNG + select EXYNOS_CHIPID select EXYNOS_PM_DOMAINS if PM_GENERIC_DOMAINS select EXYNOS_PMU select HAVE_S3C2410_WATCHDOG if WATCHDOG @@ -173,6 +174,7 @@ config ARCH_MXC select PM select PM_GENERIC_DOMAINS select SOC_BUS + select TIMER_IMX_SYS_CTR help This enables support for the ARMv8 based SoCs in the NXP i.MX family. diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index 03fa0c58cef3..413efef5fbb6 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -294,8 +294,8 @@ config INTEL_IOATDMA If unsure, say N. config INTEL_IOP_ADMA - tristate "Intel IOP ADMA support" - depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_IOP13XX + tristate "Intel IOP32x ADMA support" + depends on ARCH_IOP32X select DMA_ENGINE select ASYNC_TX_ENABLE_CHANNEL_SWITCH help diff --git a/drivers/dma/iop-adma.c b/drivers/dma/iop-adma.c index c6c0143670d9..03f4a588cf7f 100644 --- a/drivers/dma/iop-adma.c +++ b/drivers/dma/iop-adma.c @@ -16,13 +16,13 @@ #include <linux/spinlock.h> #include <linux/interrupt.h> #include <linux/platform_device.h> +#include <linux/prefetch.h> #include <linux/memory.h> #include <linux/ioport.h> #include <linux/raid/pq.h> #include <linux/slab.h> -#include <mach/adma.h> - +#include "iop-adma.h" #include "dmaengine.h" #define to_iop_adma_chan(chan) container_of(chan, struct iop_adma_chan, common) @@ -116,9 +116,9 @@ static void __iop_adma_slot_cleanup(struct iop_adma_chan *iop_chan) list_for_each_entry_safe(iter, _iter, &iop_chan->chain, chain_node) { pr_debug("\tcookie: %d slot: %d busy: %d " - "this_desc: %#x next_desc: %#x ack: %d\n", + "this_desc: %#x next_desc: %#llx ack: %d\n", iter->async_tx.cookie, iter->idx, busy, - iter->async_tx.phys, iop_desc_get_next_desc(iter), + iter->async_tx.phys, (u64)iop_desc_get_next_desc(iter), async_tx_test_ack(&iter->async_tx)); prefetch(_iter); prefetch(&_iter->async_tx); @@ -306,9 +306,9 @@ retry: int i; dev_dbg(iop_chan->device->common.dev, "allocated slot: %d " - "(desc %p phys: %#x) slots_per_op %d\n", + "(desc %p phys: %#llx) slots_per_op %d\n", iter->idx, iter->hw_desc, - iter->async_tx.phys, slots_per_op); + (u64)iter->async_tx.phys, slots_per_op); /* pre-ack all but the last descriptor */ if (num_slots != slots_per_op) @@ -516,7 +516,7 @@ iop_adma_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dma_dest, return NULL; BUG_ON(len > IOP_ADMA_MAX_BYTE_COUNT); - dev_dbg(iop_chan->device->common.dev, "%s len: %u\n", + dev_dbg(iop_chan->device->common.dev, "%s len: %zu\n", __func__, len); spin_lock_bh(&iop_chan->lock); @@ -549,7 +549,7 @@ iop_adma_prep_dma_xor(struct dma_chan *chan, dma_addr_t dma_dest, BUG_ON(len > IOP_ADMA_XOR_MAX_BYTE_COUNT); dev_dbg(iop_chan->device->common.dev, - "%s src_cnt: %d len: %u flags: %lx\n", + "%s src_cnt: %d len: %zu flags: %lx\n", __func__, src_cnt, len, flags); spin_lock_bh(&iop_chan->lock); @@ -582,7 +582,7 @@ iop_adma_prep_dma_xor_val(struct dma_chan *chan, dma_addr_t *dma_src, if (unlikely(!len)) return NULL; - dev_dbg(iop_chan->device->common.dev, "%s src_cnt: %d len: %u\n", + dev_dbg(iop_chan->device->common.dev, "%s src_cnt: %d len: %zu\n", __func__, src_cnt, len); spin_lock_bh(&iop_chan->lock); @@ -620,7 +620,7 @@ iop_adma_prep_dma_pq(struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src, BUG_ON(len > IOP_ADMA_XOR_MAX_BYTE_COUNT); dev_dbg(iop_chan->device->common.dev, - "%s src_cnt: %d len: %u flags: %lx\n", + "%s src_cnt: %d len: %zu flags: %lx\n", __func__, src_cnt, len, flags); if (dmaf_p_disabled_continue(flags)) @@ -683,7 +683,7 @@ iop_adma_prep_dma_pq_val(struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src, return NULL; BUG_ON(len > IOP_ADMA_XOR_MAX_BYTE_COUNT); - dev_dbg(iop_chan->device->common.dev, "%s src_cnt: %d len: %u\n", + dev_dbg(iop_chan->device->common.dev, "%s src_cnt: %d len: %zu\n", __func__, src_cnt, len); spin_lock_bh(&iop_chan->lock); diff --git a/arch/arm/include/asm/hardware/iop3xx-adma.h b/drivers/dma/iop-adma.h index 6d998df17efd..c499c9578f00 100644 --- a/arch/arm/include/asm/hardware/iop3xx-adma.h +++ b/drivers/dma/iop-adma.h @@ -6,8 +6,7 @@ #define _ADMA_H #include <linux/types.h> #include <linux/io.h> -#include <mach/hardware.h> -#include <asm/hardware/iop_adma.h> +#include <linux/platform_data/dma-iop32x.h> /* Memory copy units */ #define DMA_CCR(chan) (chan->mmr_base + 0x0) @@ -34,10 +33,6 @@ #define AAU_EDCR1_IDX 17 #define AAU_EDCR2_IDX 26 -#define DMA0_ID 0 -#define DMA1_ID 1 -#define AAU_ID 2 - struct iop3xx_aau_desc_ctrl { unsigned int int_en:1; unsigned int blk1_cmd_ctrl:3; diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index e193c76948c4..305b47ed4532 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -275,7 +275,7 @@ config GPIO_ICH config GPIO_IOP tristate "Intel IOP GPIO" - depends on ARCH_IOP32X || ARCH_IOP33X || COMPILE_TEST + depends on ARCH_IOP32X || COMPILE_TEST select GPIO_GENERIC help Say yes here to support the GPIO functionality of a number of Intel diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index 09367fc014c3..f8c77edf70d0 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -684,7 +684,7 @@ config I2C_IMX_LPI2C config I2C_IOP3XX tristate "Intel IOPx3xx and IXP4xx on-chip I2C interface" - depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_IXP4XX || ARCH_IOP13XX + depends on ARCH_IOP32X || ARCH_IXP4XX help Say Y here if you want to use the IIC bus controller on the Intel IOPx3xx I/O Processors or IXP4xx Network Processors. diff --git a/drivers/net/ethernet/nxp/Kconfig b/drivers/net/ethernet/nxp/Kconfig index 261f107e2be0..418afb84c84b 100644 --- a/drivers/net/ethernet/nxp/Kconfig +++ b/drivers/net/ethernet/nxp/Kconfig @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only config LPC_ENET tristate "NXP ethernet MAC on LPC devices" - depends on ARCH_LPC32XX + depends on ARCH_LPC32XX || COMPILE_TEST select PHYLIB help Say Y or M here if you want to use the NXP ethernet MAC included on diff --git a/drivers/net/ethernet/nxp/lpc_eth.c b/drivers/net/ethernet/nxp/lpc_eth.c index f7e11f1b0426..141571e2ec11 100644 --- a/drivers/net/ethernet/nxp/lpc_eth.c +++ b/drivers/net/ethernet/nxp/lpc_eth.c @@ -14,14 +14,12 @@ #include <linux/crc32.h> #include <linux/etherdevice.h> #include <linux/module.h> +#include <linux/of.h> #include <linux/of_net.h> #include <linux/phy.h> #include <linux/platform_device.h> #include <linux/spinlock.h> - -#include <mach/board.h> -#include <mach/hardware.h> -#include <mach/platform.h> +#include <linux/soc/nxp/lpc32xx-misc.h> #define MODNAME "lpc-eth" #define DRV_VERSION "1.00" @@ -1237,16 +1235,9 @@ static int lpc_eth_drv_probe(struct platform_device *pdev) dma_addr_t dma_handle; struct resource *res; int irq, ret; - u32 tmp; /* Setup network interface for RMII or MII mode */ - tmp = __raw_readl(LPC32XX_CLKPWR_MACCLK_CTRL); - tmp &= ~LPC32XX_CLKPWR_MACCTRL_PINS_MSK; - if (lpc_phy_interface_mode(dev) == PHY_INTERFACE_MODE_MII) - tmp |= LPC32XX_CLKPWR_MACCTRL_USE_MII_PINS; - else - tmp |= LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS; - __raw_writel(tmp, LPC32XX_CLKPWR_MACCLK_CTRL); + lpc32xx_set_phy_interface_mode(lpc_phy_interface_mode(dev)); /* Get platform resources */ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); @@ -1311,19 +1302,18 @@ static int lpc_eth_drv_probe(struct platform_device *pdev) /* Get size of DMA buffers/descriptors region */ pldat->dma_buff_size = (ENET_TX_DESC + ENET_RX_DESC) * (ENET_MAXF_SIZE + sizeof(struct txrx_desc_t) + sizeof(struct rx_status_t)); - pldat->dma_buff_base_v = 0; if (use_iram_for_net(dev)) { - dma_handle = LPC32XX_IRAM_BASE; - if (pldat->dma_buff_size <= lpc32xx_return_iram_size()) - pldat->dma_buff_base_v = - io_p2v(LPC32XX_IRAM_BASE); - else + if (pldat->dma_buff_size > + lpc32xx_return_iram(&pldat->dma_buff_base_v, &dma_handle)) { + pldat->dma_buff_base_v = NULL; + pldat->dma_buff_size = 0; netdev_err(ndev, "IRAM not big enough for net buffers, using SDRAM instead.\n"); + } } - if (pldat->dma_buff_base_v == 0) { + if (pldat->dma_buff_base_v == NULL) { ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(32)); if (ret) goto err_out_free_irq; @@ -1344,13 +1334,14 @@ static int lpc_eth_drv_probe(struct platform_device *pdev) pldat->dma_buff_base_p = dma_handle; netdev_dbg(ndev, "IO address space :%pR\n", res); - netdev_dbg(ndev, "IO address size :%d\n", resource_size(res)); + netdev_dbg(ndev, "IO address size :%zd\n", + (size_t)resource_size(res)); netdev_dbg(ndev, "IO address (mapped) :0x%p\n", pldat->net_base); netdev_dbg(ndev, "IRQ number :%d\n", ndev->irq); - netdev_dbg(ndev, "DMA buffer size :%d\n", pldat->dma_buff_size); - netdev_dbg(ndev, "DMA buffer P address :0x%08x\n", - pldat->dma_buff_base_p); + netdev_dbg(ndev, "DMA buffer size :%zd\n", pldat->dma_buff_size); + netdev_dbg(ndev, "DMA buffer P address :%pad\n", + &pldat->dma_buff_base_p); netdev_dbg(ndev, "DMA buffer V address :0x%p\n", pldat->dma_buff_base_v); @@ -1397,8 +1388,8 @@ static int lpc_eth_drv_probe(struct platform_device *pdev) if (ret) goto err_out_unregister_netdev; - netdev_info(ndev, "LPC mac at 0x%08x irq %d\n", - res->start, ndev->irq); + netdev_info(ndev, "LPC mac at 0x%08lx irq %d\n", + (unsigned long)res->start, ndev->irq); device_init_wakeup(dev, 1); device_set_wakeup_enable(dev, 0); @@ -1409,7 +1400,7 @@ err_out_unregister_netdev: unregister_netdev(ndev); err_out_dma_unmap: if (!use_iram_for_net(dev) || - pldat->dma_buff_size > lpc32xx_return_iram_size()) + pldat->dma_buff_size > lpc32xx_return_iram(NULL, NULL)) dma_free_coherent(dev, pldat->dma_buff_size, pldat->dma_buff_base_v, pldat->dma_buff_base_p); @@ -1436,7 +1427,7 @@ static int lpc_eth_drv_remove(struct platform_device *pdev) unregister_netdev(ndev); if (!use_iram_for_net(&pldat->pdev->dev) || - pldat->dma_buff_size > lpc32xx_return_iram_size()) + pldat->dma_buff_size > lpc32xx_return_iram(NULL, NULL)) dma_free_coherent(&pldat->pdev->dev, pldat->dma_buff_size, pldat->dma_buff_base_v, pldat->dma_buff_base_p); diff --git a/drivers/soc/ux500/ux500-soc-id.c b/drivers/soc/ux500/ux500-soc-id.c index ea5fd2e5e340..d64feeb51a40 100644 --- a/drivers/soc/ux500/ux500-soc-id.c +++ b/drivers/soc/ux500/ux500-soc-id.c @@ -203,10 +203,13 @@ static int __init ux500_soc_device_init(void) ux500_setup_id(); soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); - if (!soc_dev_attr) + if (!soc_dev_attr) { + of_node_put(backupram); return -ENOMEM; + } soc_info_populate(soc_dev_attr, backupram); + of_node_put(backupram); soc_dev = soc_device_register(soc_dev_attr); if (IS_ERR(soc_dev)) { diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index 2f631501c75f..514169eb1859 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -739,7 +739,8 @@ config SERIAL_PNX8XXX_CONSOLE config SERIAL_HS_LPC32XX tristate "LPC32XX high speed serial port support" - depends on ARCH_LPC32XX && OF + depends on ARCH_LPC32XX || COMPILE_TEST + depends on OF select SERIAL_CORE help Support for the LPC32XX high speed serial ports (up to 900kbps). diff --git a/drivers/tty/serial/lpc32xx_hs.c b/drivers/tty/serial/lpc32xx_hs.c index f4e27d0ad947..d3843f722182 100644 --- a/drivers/tty/serial/lpc32xx_hs.c +++ b/drivers/tty/serial/lpc32xx_hs.c @@ -25,8 +25,8 @@ #include <linux/irq.h> #include <linux/gpio.h> #include <linux/of.h> -#include <mach/platform.h> -#include <mach/hardware.h> +#include <linux/sizes.h> +#include <linux/soc/nxp/lpc32xx-misc.h> /* * High Speed UART register offsets @@ -81,6 +81,8 @@ #define LPC32XX_HSU_TX_TL8B (0x2 << 0) #define LPC32XX_HSU_TX_TL16B (0x3 << 0) +#define LPC32XX_MAIN_OSC_FREQ 13000000 + #define MODNAME "lpc32xx_hsuart" struct lpc32xx_hsuart_port { @@ -151,8 +153,6 @@ static void lpc32xx_hsuart_console_write(struct console *co, const char *s, local_irq_restore(flags); } -static void lpc32xx_loopback_set(resource_size_t mapbase, int state); - static int __init lpc32xx_hsuart_console_setup(struct console *co, char *options) { @@ -439,35 +439,6 @@ static void serial_lpc32xx_break_ctl(struct uart_port *port, spin_unlock_irqrestore(&port->lock, flags); } -/* LPC3250 Errata HSUART.1: Hang workaround via loopback mode on inactivity */ -static void lpc32xx_loopback_set(resource_size_t mapbase, int state) -{ - int bit; - u32 tmp; - - switch (mapbase) { - case LPC32XX_HS_UART1_BASE: - bit = 0; - break; - case LPC32XX_HS_UART2_BASE: - bit = 1; - break; - case LPC32XX_HS_UART7_BASE: - bit = 6; - break; - default: - WARN(1, "lpc32xx_hs: Warning: Unknown port at %08x\n", mapbase); - return; - } - - tmp = readl(LPC32XX_UARTCTL_CLOOP); - if (state) - tmp |= (1 << bit); - else - tmp &= ~(1 << bit); - writel(tmp, LPC32XX_UARTCTL_CLOOP); -} - /* port->lock is not held. */ static int serial_lpc32xx_startup(struct uart_port *port) { diff --git a/drivers/usb/gadget/udc/Kconfig b/drivers/usb/gadget/udc/Kconfig index ef0259a950ba..d7e611645533 100644 --- a/drivers/usb/gadget/udc/Kconfig +++ b/drivers/usb/gadget/udc/Kconfig @@ -45,7 +45,8 @@ config USB_AT91 config USB_LPC32XX tristate "LPC32XX USB Peripheral Controller" - depends on ARCH_LPC32XX && I2C + depends on ARCH_LPC32XX + depends on I2C select USB_ISP1301 help This option selects the USB device controller in the LPC32xx SoC. diff --git a/drivers/usb/gadget/udc/lpc32xx_udc.c b/drivers/usb/gadget/udc/lpc32xx_udc.c index bb6af6b5ac97..c65aed3e84c7 100644 --- a/drivers/usb/gadget/udc/lpc32xx_udc.c +++ b/drivers/usb/gadget/udc/lpc32xx_udc.c @@ -24,6 +24,7 @@ #include <linux/module.h> #include <linux/of.h> #include <linux/platform_device.h> +#include <linux/prefetch.h> #include <linux/proc_fs.h> #include <linux/slab.h> #include <linux/usb/ch9.h> @@ -35,8 +36,6 @@ #include <linux/seq_file.h> #endif -#include <mach/hardware.h> - /* * USB device configuration structure */ diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 40b5de597112..73d233d3bf4d 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -441,7 +441,8 @@ config USB_OHCI_HCD_S3C2410 config USB_OHCI_HCD_LPC32XX tristate "Support for LPC on-chip OHCI USB controller" - depends on USB_OHCI_HCD && ARCH_LPC32XX + depends on USB_OHCI_HCD + depends on ARCH_LPC32XX || COMPILE_TEST depends on USB_ISP1301 default y ---help--- diff --git a/drivers/usb/host/ohci-nxp.c b/drivers/usb/host/ohci-nxp.c index f5f532601092..c561881d0e79 100644 --- a/drivers/usb/host/ohci-nxp.c +++ b/drivers/usb/host/ohci-nxp.c @@ -29,10 +29,7 @@ #include "ohci.h" -#include <mach/hardware.h> - #define USB_CONFIG_BASE 0x31020000 -#define USB_OTG_STAT_CONTROL IO_ADDRESS(USB_CONFIG_BASE + 0x110) /* USB_OTG_STAT_CONTROL bit defines */ #define TRANSPARENT_I2C_EN (1 << 7) @@ -122,19 +119,33 @@ static inline void isp1301_vbus_off(void) static void ohci_nxp_start_hc(void) { - unsigned long tmp = __raw_readl(USB_OTG_STAT_CONTROL) | HOST_EN; + void __iomem *usb_otg_stat_control = ioremap(USB_CONFIG_BASE + 0x110, 4); + unsigned long tmp; + + if (WARN_ON(!usb_otg_stat_control)) + return; + + tmp = __raw_readl(usb_otg_stat_control) | HOST_EN; - __raw_writel(tmp, USB_OTG_STAT_CONTROL); + __raw_writel(tmp, usb_otg_stat_control); isp1301_vbus_on(); + + iounmap(usb_otg_stat_control); } static void ohci_nxp_stop_hc(void) { + void __iomem *usb_otg_stat_control = ioremap(USB_CONFIG_BASE + 0x110, 4); unsigned long tmp; + if (WARN_ON(!usb_otg_stat_control)) + return; + isp1301_vbus_off(); - tmp = __raw_readl(USB_OTG_STAT_CONTROL) & ~HOST_EN; - __raw_writel(tmp, USB_OTG_STAT_CONTROL); + tmp = __raw_readl(usb_otg_stat_control) & ~HOST_EN; + __raw_writel(tmp, usb_otg_stat_control); + + iounmap(usb_otg_stat_control); } static int ohci_hcd_nxp_probe(struct platform_device *pdev) diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 8188963a405b..a45f9e3e442b 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -551,7 +551,7 @@ config OMAP_WATCHDOG config PNX4008_WATCHDOG tristate "LPC32XX Watchdog" - depends on ARCH_LPC32XX + depends on ARCH_LPC32XX || COMPILE_TEST select WATCHDOG_CORE help Say Y here if to include support for the watchdog timer diff --git a/drivers/watchdog/pnx4008_wdt.c b/drivers/watchdog/pnx4008_wdt.c index 7b446b696f2b..e0ea133c1690 100644 --- a/drivers/watchdog/pnx4008_wdt.c +++ b/drivers/watchdog/pnx4008_wdt.c @@ -30,7 +30,6 @@ #include <linux/of.h> #include <linux/delay.h> #include <linux/reboot.h> -#include <mach/hardware.h> /* WatchDog Timer - Chapter 23 Page 207 */ diff --git a/arch/arm/include/asm/hardware/iop_adma.h b/include/linux/platform_data/dma-iop32x.h index bcedbab90ac0..ac83cff89549 100644 --- a/arch/arm/include/asm/hardware/iop_adma.h +++ b/include/linux/platform_data/dma-iop32x.h @@ -17,6 +17,10 @@ #endif #define iop_paranoia(x) BUG_ON(IOP_PARANOIA && (x)) +#define DMA0_ID 0 +#define DMA1_ID 1 +#define AAU_ID 2 + /** * struct iop_adma_device - internal representation of an ADMA device * @pdev: Platform device diff --git a/include/linux/soc/nxp/lpc32xx-misc.h b/include/linux/soc/nxp/lpc32xx-misc.h new file mode 100644 index 000000000000..699c6f1e3aab --- /dev/null +++ b/include/linux/soc/nxp/lpc32xx-misc.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Author: Kevin Wells <kevin.wells@nxp.com> + * + * Copyright (C) 2010 NXP Semiconductors + */ + +#ifndef __SOC_LPC32XX_MISC_H +#define __SOC_LPC32XX_MISC_H + +#include <linux/types.h> +#include <linux/phy.h> + +#ifdef CONFIG_ARCH_LPC32XX +extern u32 lpc32xx_return_iram(void __iomem **mapbase, dma_addr_t *dmaaddr); +extern void lpc32xx_set_phy_interface_mode(phy_interface_t mode); +extern void lpc32xx_loopback_set(resource_size_t mapbase, int state); +#else +static inline u32 lpc32xx_return_iram(void __iomem **mapbase, dma_addr_t *dmaaddr) +{ + *mapbase = NULL; + *dmaaddr = 0; + return 0; +} +static inline void lpc32xx_set_phy_interface_mode(phy_interface_t mode) +{ +} +static inline void lpc32xx_loopback_set(resource_size_t mapbase, int state) +{ +} +#endif + +#endif /* __SOC_LPC32XX_MISC_H */ diff --git a/include/linux/usb/samsung_usb_phy.h b/include/linux/usb/samsung_usb_phy.h deleted file mode 100644 index dc0071741695..000000000000 --- a/include/linux/usb/samsung_usb_phy.h +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2012 Samsung Electronics Co.Ltd - * http://www.samsung.com/ - * - * Defines phy types for samsung usb phy controllers - HOST or DEIVCE. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -enum samsung_usb_phy_type { - USB_PHY_TYPE_DEVICE, - USB_PHY_TYPE_HOST, -}; |