diff options
| -rw-r--r-- | arch/arm/boot/dts/r7s72100-rskrza1.dts | 8 | ||||
| -rw-r--r-- | arch/arm/boot/dts/r7s72100.dtsi | 28 | ||||
| -rw-r--r-- | arch/arm/boot/dts/r8a7743.dtsi | 3 | ||||
| -rw-r--r-- | arch/arm/boot/dts/r8a7745.dtsi | 3 | ||||
| -rw-r--r-- | arch/arm/boot/dts/r8a7779-marzen.dts | 4 | ||||
| -rw-r--r-- | arch/arm/boot/dts/r8a7779.dtsi | 1 | ||||
| -rw-r--r-- | include/dt-bindings/clock/r7s72100-clock.h | 4 |
7 files changed, 51 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r7s72100-rskrza1.dts b/arch/arm/boot/dts/r7s72100-rskrza1.dts index dd4418195ca6..02b59c5b3c53 100644 --- a/arch/arm/boot/dts/r7s72100-rskrza1.dts +++ b/arch/arm/boot/dts/r7s72100-rskrza1.dts @@ -61,6 +61,14 @@ status = "okay"; }; +&ostm0 { + status = "okay"; +}; + +&ostm1 { + status = "okay"; +}; + &scif2 { status = "okay"; }; diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi index 3dd427d68c83..b8aa256bd515 100644 --- a/arch/arm/boot/dts/r7s72100.dtsi +++ b/arch/arm/boot/dts/r7s72100.dtsi @@ -108,6 +108,15 @@ clock-output-names = "scif0", "scif1", "scif2", "scif3", "scif4", "scif5", "scif6", "scif7"; }; + mstp5_clks: mstp5_clks@fcfe0428 { + #clock-cells = <1>; + compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xfcfe0428 4>; + clocks = <&p0_clk>, <&p0_clk>; + clock-indices = <R7S72100_CLK_OSTM0 R7S72100_CLK_OSTM1>; + clock-output-names = "ostm0", "ostm1"; + }; + mstp7_clks: mstp7_clks@fcfe0430 { #clock-cells = <1>; compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; @@ -466,6 +475,7 @@ GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp8_clks R7S72100_CLK_MMCIF>; + power-domains = <&cpg_clocks>; reg-io-width = <4>; bus-width = <8>; status = "disabled"; @@ -496,4 +506,22 @@ cap-sdio-irq; status = "disabled"; }; + + ostm0: timer@fcfec000 { + compatible = "renesas,r7s72100-ostm", "renesas,ostm"; + reg = <0xfcfec000 0x30>; + interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>; + clocks = <&mstp5_clks R7S72100_CLK_OSTM0>; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + ostm1: timer@fcfec400 { + compatible = "renesas,r7s72100-ostm", "renesas,ostm"; + reg = <0xfcfec400 0x30>; + interrupts = <GIC_SPI 103 IRQ_TYPE_EDGE_RISING>; + clocks = <&mstp5_clks R7S72100_CLK_OSTM1>; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; }; diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi index 0956125597fd..40d2cdede702 100644 --- a/arch/arm/boot/dts/r8a7743.dtsi +++ b/arch/arm/boot/dts/r8a7743.dtsi @@ -60,6 +60,9 @@ <0 0xf1006000 0 0x2000>; interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; }; irqc: interrupt-controller@e61c0000 { diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi index 2f60c3cb9117..a81dcc82e2ea 100644 --- a/arch/arm/boot/dts/r8a7745.dtsi +++ b/arch/arm/boot/dts/r8a7745.dtsi @@ -60,6 +60,9 @@ <0 0xf1006000 0 0x2000>; interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; }; irqc: interrupt-controller@e61c0000 { diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts index 676151b70185..89c5b24a3d03 100644 --- a/arch/arm/boot/dts/r8a7779-marzen.dts +++ b/arch/arm/boot/dts/r8a7779-marzen.dts @@ -216,6 +216,10 @@ }; }; +&sata { + status = "okay"; +}; + &scif2 { pinctrl-0 = <&scif2_pins>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi index f47a0edc26d4..ae2d9a9c65af 100644 --- a/arch/arm/boot/dts/r8a7779.dtsi +++ b/arch/arm/boot/dts/r8a7779.dtsi @@ -347,6 +347,7 @@ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp1_clks R8A7779_CLK_SATA>; power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; + status = "disabled"; }; sdhi0: sd@ffe4c000 { diff --git a/include/dt-bindings/clock/r7s72100-clock.h b/include/dt-bindings/clock/r7s72100-clock.h index 29e01ed10e74..ce09915c298f 100644 --- a/include/dt-bindings/clock/r7s72100-clock.h +++ b/include/dt-bindings/clock/r7s72100-clock.h @@ -25,6 +25,10 @@ #define R7S72100_CLK_SCIF6 1 #define R7S72100_CLK_SCIF7 0 +/* MSTP5 */ +#define R7S72100_CLK_OSTM0 1 +#define R7S72100_CLK_OSTM1 0 + /* MSTP7 */ #define R7S72100_CLK_ETHER 4 |