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| author | Marc Zyngier <marc.zyngier@arm.com> | 2018-02-06 20:56:14 +0300 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2018-02-07 01:54:05 +0300 |
| commit | 6167ec5c9145cdf493722dfd80a5d48bafc4a18a (patch) | |
| tree | cdabac4f0a97488800cf46264d53b3cbbefbd65c /virt | |
| parent | a4097b351118e821841941a79ec77d3ce3f1c5d9 (diff) | |
| download | linux-6167ec5c9145cdf493722dfd80a5d48bafc4a18a.tar.xz | |
arm64: KVM: Report SMCCC_ARCH_WORKAROUND_1 BP hardening support
A new feature of SMCCC 1.1 is that it offers firmware-based CPU
workarounds. In particular, SMCCC_ARCH_WORKAROUND_1 provides
BP hardening for CVE-2017-5715.
If the host has some mitigation for this issue, report that
we deal with it using SMCCC_ARCH_WORKAROUND_1, as we apply the
host workaround on every guest exit.
Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'virt')
| -rw-r--r-- | virt/kvm/arm/psci.c | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/virt/kvm/arm/psci.c b/virt/kvm/arm/psci.c index e105c1153794..6919352cbf15 100644 --- a/virt/kvm/arm/psci.c +++ b/virt/kvm/arm/psci.c @@ -405,13 +405,20 @@ int kvm_hvc_call_handler(struct kvm_vcpu *vcpu) { u32 func_id = smccc_get_function(vcpu); u32 val = PSCI_RET_NOT_SUPPORTED; + u32 feature; switch (func_id) { case ARM_SMCCC_VERSION_FUNC_ID: val = ARM_SMCCC_VERSION_1_1; break; case ARM_SMCCC_ARCH_FEATURES_FUNC_ID: - /* Nothing supported yet */ + feature = smccc_get_arg1(vcpu); + switch(feature) { + case ARM_SMCCC_ARCH_WORKAROUND_1: + if (kvm_arm_harden_branch_predictor()) + val = 0; + break; + } break; default: return kvm_psci_call(vcpu); |