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authorTakeshi Kihara <takeshi.kihara.df@renesas.com>2017-07-28 14:41:14 +0300
committerGeert Uytterhoeven <geert+renesas@glider.be>2017-08-16 15:26:25 +0300
commit712f36fbb7738a60df0622e950726b6977dd41f3 (patch)
treee8a00d8ac351331e46e48b2ad217fd4ba443786e /usr
parent50d83156e84ee5112fa07a0033eef4e58110709d (diff)
downloadlinux-712f36fbb7738a60df0622e950726b6977dd41f3.tar.xz
pinctrl: sh-pfc: r8a7795: Fix MOD_SEL2 bit26 to 0x0 when using SCK5_A
This patch fixes the implementation incorrect of MOD_SEL2 bit26 value when SCK5_A pin function is selected for IPSR16 bit[31:28]. This is a correction to the incorrect implementation of MOD_SEL register pin assignment for R8A7795 ES2.0 SoC specification of R-Car Gen3 Hardware User's Manual Rev.0.51E or later. Fixes: b205914c8f822ef2 ("pinctrl: sh-pfc: r8a7795: Add support for R-Car H3 ES2.0") Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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