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author | Vincent Chen <vincent.chen@sifive.com> | 2022-03-08 11:32:53 +0300 |
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committer | Palmer Dabbelt <palmer@rivosinc.com> | 2022-03-23 00:45:19 +0300 |
commit | 6d1a6f464efd596779d1b272b3dc8170c5fa189f (patch) | |
tree | 35f6444e6bae8e031bcefcb457bd0de3ebbfe16a /tools/testing/selftests/rseq/rseq.h | |
parent | 93917ad50972e6298885d81b37b6a8602eb0b188 (diff) | |
download | linux-6d1a6f464efd596779d1b272b3dc8170c5fa189f.tar.xz |
rseq/selftests: Add support for RISC-V
Add support for RISC-V in the rseq selftests, which covers both
64-bit and 32-bit ISA with little endian mode.
Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
Tested-by: Eric Lin <eric.lin@sifive.com>
Reviewed-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'tools/testing/selftests/rseq/rseq.h')
-rw-r--r-- | tools/testing/selftests/rseq/rseq.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/tools/testing/selftests/rseq/rseq.h b/tools/testing/selftests/rseq/rseq.h index 3f63eb362b92..72efb6d3d84e 100644 --- a/tools/testing/selftests/rseq/rseq.h +++ b/tools/testing/selftests/rseq/rseq.h @@ -79,6 +79,8 @@ extern int __rseq_handled; #include <rseq-mips.h> #elif defined(__s390__) #include <rseq-s390.h> +#elif defined(__riscv) +#include <rseq-riscv.h> #else #error unsupported target #endif |