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| author | Imre Deak <imre.deak@intel.com> | 2018-11-01 17:04:24 +0300 |
|---|---|---|
| committer | Imre Deak <imre.deak@intel.com> | 2018-11-02 02:24:02 +0300 |
| commit | bdaa29b6bea7cd89dd866be2038fa66e2a3ab40d (patch) | |
| tree | 46b82c92b427e87d7e74ceaf99d46086084e9388 /tools/perf/scripts/python/syscall-counts-by-pid.py | |
| parent | 337837ac3a75f126b53a522bebf2d8b3e82b105b (diff) | |
| download | linux-bdaa29b6bea7cd89dd866be2038fa66e2a3ab40d.tar.xz | |
drm/i915: Enable AUX power earlier
For DDI/TypeC ports the AUX power domain needs to be enabled before the
port's PLL is enabled, so move the enabling earlier accordingly.
v2:
- Preserve the pre_pll hook for GEN9_LP. (Ville)
v3:
- Add related BSpec entries to commit log. (Jose)
v4:
- Rebase on the upstream ICL pre_pll_enable change.
BSpec: 21750, 22243
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181101140427.31026-6-imre.deak@intel.com
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts-by-pid.py')
0 files changed, 0 insertions, 0 deletions