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| author | Maxime Chevallier <maxime.chevallier@bootlin.com> | 2022-09-02 11:32:05 +0300 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2022-09-05 12:16:53 +0300 |
| commit | 565f02fc1e5dc18a577545aaef3c1191cd011849 (patch) | |
| tree | 566380cce9c6fe7c68afcab001fe77482e028f7a /tools/perf/scripts/python/stackcollapse.py | |
| parent | fef2998203e17e4298843afb2056fbed44611734 (diff) | |
| download | linux-565f02fc1e5dc18a577545aaef3c1191cd011849.tar.xz | |
dt-bindings: net: altera: tse: add an optional pcs register range
Some implementations of the TSE have their PCS as an external bloc,
exposed at its own register range. Document this, and add a new example
showing a case using the pcs and the new phylink conversion to connect
an sfp port to a TSE mac.
Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions