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authorFabrice Gasnier <fabrice.gasnier@foss.st.com>2025-02-24 20:06:57 +0300
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2025-04-07 11:08:35 +0300
commit181a2ab650f77996c03ba0f5f208f6019ea1f15a (patch)
treee2f1b0e906e58b738e9b60b440d16c08df57fbf7 /tools/perf/scripts/python/parallel-perf.py
parent3ed38d0297fa448d130dc99e20eba8ff047cc229 (diff)
downloadlinux-181a2ab650f77996c03ba0f5f208f6019ea1f15a.tar.xz
counter: stm32-lptimer-cnt: fix error handling when enabling
commit 8744dcd4fc7800de2eb9369410470bb2930d4c14 upstream. In case the stm32_lptim_set_enable_state() fails to update CMP and ARR, a timeout error is raised, by regmap_read_poll_timeout. It may happen, when the lptimer runs on a slow clock, and the clock is gated only few times during the polling. Badly, when this happen, STM32_LPTIM_ENABLE in CR register has been set. So the 'enable' state in sysfs wrongly lies on the counter being correctly enabled, due to CR is read as one in stm32_lptim_is_enabled(). To fix both issues: - enable the clock before writing CMP, ARR and polling ISR bits. It will avoid the possible timeout error. - clear the ENABLE bit in CR and disable the clock in the error path. Fixes: d8958824cf07 ("iio: counter: Add support for STM32 LPTimer") Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Link: https://lore.kernel.org/r/20250224170657.3368236-1-fabrice.gasnier@foss.st.com Signed-off-by: William Breathitt Gray <wbg@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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