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| author | Rajendra Nayak <quic_rjendra@quicinc.com> | 2024-09-03 13:15:10 +0300 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2024-10-06 06:17:08 +0300 |
| commit | 0a97195d2181caced187acd7454464b8e37021d7 (patch) | |
| tree | 6c4b2f1b65c1cd8317704f3f0af10f218ae472bb /tools/perf/scripts/python/mem-phys-addr.py | |
| parent | ca61d6836e6f4442a77762e1074d2706a2a6e578 (diff) | |
| download | linux-0a97195d2181caced187acd7454464b8e37021d7.tar.xz | |
EDAC/qcom: Make irq configuration optional
On most modern qualcomm SoCs, the configuration necessary to enable the
Tag/Data RAM related irqs being propagated to the SoC irq controller is
already done in firmware (in DSF or 'DDR System Firmware')
On some like the x1e80100, these registers aren't even accesible to the
kernel causing a crash when edac device is probed.
Hence, make the irq configuration optional in the driver and mark x1e80100
as the SoC on which this should be avoided.
Fixes: af16b00578a7 ("arm64: dts: qcom: Add base X1E80100 dtsi and the QCP dts")
Reported-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20240903101510.3452734-1-quic_rjendra@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions