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| author | Komal Bajaj <quic_kbajaj@quicinc.com> | 2024-11-19 09:46:08 +0300 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2025-02-27 15:34:21 +0300 |
| commit | 8c4f36e3828906083d43d25dae5e79fbf5ba6bbc (patch) | |
| tree | 7dc956dd18cc0b13ebddc95c1d3cf1a8206906f7 /tools/perf/scripts/python/mem-phys-addr.py | |
| parent | 554736b583f529ee159aa95af9a0cbc12b5ffc96 (diff) | |
| download | linux-8c4f36e3828906083d43d25dae5e79fbf5ba6bbc.tar.xz | |
EDAC/qcom: Correct interrupt enable register configuration
commit c158647c107358bf1be579f98e4bb705c1953292 upstream.
The previous implementation incorrectly configured the cmn_interrupt_2_enable
register for interrupt handling. Using cmn_interrupt_2_enable to configure
Tag, Data RAM ECC interrupts would lead to issues like double handling of the
interrupts (EL1 and EL3) as cmn_interrupt_2_enable is meant to be configured
for interrupts which needs to be handled by EL3.
EL1 LLCC EDAC driver needs to use cmn_interrupt_0_enable register to configure
Tag, Data RAM ECC interrupts instead of cmn_interrupt_2_enable.
Fixes: 27450653f1db ("drivers: edac: Add EDAC driver support for QCOM SoCs")
Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: <stable@kernel.org>
Link: https://lore.kernel.org/r/20241119064608.12326-1-quic_kbajaj@quicinc.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions