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authormonk.liu <monk.liu@amd.com>2015-09-23 08:49:58 +0300
committerAlex Deucher <alexander.deucher@amd.com>2015-09-24 00:23:45 +0300
commit5c3422b0b135b46c8dca9c1d909c1ae84f3561bd (patch)
tree98bb55830306ee8e9869dc5a474de3732ed6a86c /tools/perf/scripts/python/export-to-postgresql.py
parent54ef0b5461c071050c61e501af5544842d61f40a (diff)
downloadlinux-5c3422b0b135b46c8dca9c1d909c1ae84f3561bd.tar.xz
drm/amdgpu: sync ce and me with SWITCH_BUFFER(2)
we used to adopt wait_reg_mem to let CE wait before DE finish page updating, but from Tonga+, CE doesn't support wait_reg_mem package so this logic no longer works. so here is another approach to do same thing: Insert two of SWITCH_BUFFER at both front and end of vm_flush can guarantee that CE not go further to process IB_const before vm_flush done. Insert two of SWITCH_BUFFER also works on CI, so remove legency method to sync CE and ME v2: Insert double SWITCH_BUFFER at front of vm flush as well. Signed-off-by: monk.liu <monk.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
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