diff options
author | Andi Kleen <ak@linux.intel.com> | 2018-01-18 15:49:26 +0300 |
---|---|---|
committer | Arnaldo Carvalho de Melo <acme@redhat.com> | 2018-01-25 12:36:50 +0300 |
commit | 032c16b296d512d151a3276ab3c53d4a4d65e2ed (patch) | |
tree | e4101f68ef9771483821cdcd214fc3f7036f34cd /tools/perf/pmu-events/arch/x86/haswellx/other.json | |
parent | ca3a2d055d86e6a731c783f2081deb9b03e36d2e (diff) | |
download | linux-032c16b296d512d151a3276ab3c53d4a4d65e2ed.tar.xz |
perf vendor events intel: Update HaswellX events to V19
Signed-off-by: Andi Kleen <ak@linux.intel.com>
Link: https://lkml.kernel.org/r/20180118234518.GA27753@tassilo.jf.intel.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Diffstat (limited to 'tools/perf/pmu-events/arch/x86/haswellx/other.json')
-rw-r--r-- | tools/perf/pmu-events/arch/x86/haswellx/other.json | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/tools/perf/pmu-events/arch/x86/haswellx/other.json b/tools/perf/pmu-events/arch/x86/haswellx/other.json index 4e1b6ce96ca3..800e65df31bc 100644 --- a/tools/perf/pmu-events/arch/x86/haswellx/other.json +++ b/tools/perf/pmu-events/arch/x86/haswellx/other.json @@ -10,16 +10,6 @@ "CounterHTOff": "0,1,2,3,4,5,6,7" }, { - "EventCode": "0x5C", - "UMask": "0x2", - "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3", - "Counter": "0,1,2,3", - "EventName": "CPL_CYCLES.RING123", - "PublicDescription": "Unhalted core cycles when the thread is not in ring 0.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { "EdgeDetect": "1", "EventCode": "0x5C", "UMask": "0x1", @@ -31,6 +21,16 @@ "CounterHTOff": "0,1,2,3,4,5,6,7" }, { + "EventCode": "0x5C", + "UMask": "0x2", + "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3", + "Counter": "0,1,2,3", + "EventName": "CPL_CYCLES.RING123", + "PublicDescription": "Unhalted core cycles when the thread is not in ring 0.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { "EventCode": "0x63", "UMask": "0x1", "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock", |