diff options
| author | Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com> | 2017-11-09 02:42:03 +0300 |
|---|---|---|
| committer | Arnaldo Carvalho de Melo <acme@redhat.com> | 2017-11-16 20:49:54 +0300 |
| commit | e795dd42b716ff36ebaa5384fd1be8458d6c9c34 (patch) | |
| tree | 04ff7ef962f5a8ad7ca6fd5cb143ea7d68691109 /tools/perf/pmu-events/arch/powerpc/power9/frontend.json | |
| parent | fa48c892645dfd3159e5aa6eb9cefd00d5cb347a (diff) | |
| download | linux-e795dd42b716ff36ebaa5384fd1be8458d6c9c34.tar.xz | |
perf vendor events powerpc: Update POWER9 events
The POWER9 hardware has dropped support for several events, added
a few new events and changed the category for a couple of events.
Update the POWER9 events in Linux to reflect these changes.
Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Michael Ellerman <mpe@ellerman.id.au>
Cc: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
Link: http://lkml.kernel.org/r/20171108201938.GA10985@us.ibm.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Diffstat (limited to 'tools/perf/pmu-events/arch/powerpc/power9/frontend.json')
| -rw-r--r-- | tools/perf/pmu-events/arch/powerpc/power9/frontend.json | 7 |
1 files changed, 1 insertions, 6 deletions
diff --git a/tools/perf/pmu-events/arch/powerpc/power9/frontend.json b/tools/perf/pmu-events/arch/powerpc/power9/frontend.json index c63a919eda98..bd8361b5fd6a 100644 --- a/tools/perf/pmu-events/arch/powerpc/power9/frontend.json +++ b/tools/perf/pmu-events/arch/powerpc/power9/frontend.json @@ -1,10 +1,5 @@ [ {, - "EventCode": "0x3E15C", - "EventName": "PM_MRK_L2_TM_ST_ABORT_SISTER", - "BriefDescription": "TM marked store abort for this thread" - }, - {, "EventCode": "0x25044", "EventName": "PM_IPTEG_FROM_L31_MOD", "BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a instruction side request" @@ -369,4 +364,4 @@ "EventName": "PM_IPTEG_FROM_L31_ECO_MOD", "BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a instruction side request" } -] +]
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