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| author | Alexander Monakov <amonakov@ispras.ru> | 2020-10-12 15:50:33 +0300 |
|---|---|---|
| committer | Rafael J. Wysocki <rafael.j.wysocki@intel.com> | 2020-10-16 18:09:14 +0300 |
| commit | 8bb2e2a887afdf8a39e68fa0dccf82a168aae655 (patch) | |
| tree | cdf363f05670b51006c1e5971702fe2f1d1178df /tools/memory-model | |
| parent | e05783346441ce03f5b422247ca571613360218d (diff) | |
| download | linux-8bb2e2a887afdf8a39e68fa0dccf82a168aae655.tar.xz | |
intel_idle: mention assumption that WBINVD is not needed
Intel SDM does not explicitly say that entering a C-state via MWAIT will
implicitly flush CPU caches as appropriate for that C-state. However,
documentation for individual Intel CPU generations does mention this
behavior.
Since intel_idle binds to any Intel CPU with MWAIT, list this assumption
of MWAIT behavior.
In passing, reword opening comment to make it clear that the driver can
load on any old and future Intel CPU with MWAIT.
Signed-off-by: Alexander Monakov <amonakov@ispras.ru>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Diffstat (limited to 'tools/memory-model')
0 files changed, 0 insertions, 0 deletions