diff options
| author | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2020-02-25 20:29:58 +0300 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2020-02-25 20:39:23 +0300 |
| commit | ff36e78fdb251b9fa65028554689806961e011eb (patch) | |
| tree | f5af925d509224e06a10936196be6c06bcbdc6ae /sound/soc/ti/davinci-mcasp.c | |
| parent | 143d9c3e7b6aa2b785abba04266ed75f2b52e94a (diff) | |
| parent | 1b245ec5b685ebf8e6e5d1e6b5bcc03b6608e8b0 (diff) | |
| download | linux-ff36e78fdb251b9fa65028554689806961e011eb.tar.xz | |
Merge drm/drm-next into drm-intel-next-queued
Some DSI and VBT pending patches from Hans will apply
cleanly and with less ugly conflicts if they are rebuilt
on top of other patches that recently landed on drm-next.
Reference: https://patchwork.freedesktop.org/series/70952/
Cc: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com
Diffstat (limited to 'sound/soc/ti/davinci-mcasp.c')
| -rw-r--r-- | sound/soc/ti/davinci-mcasp.c | 35 |
1 files changed, 28 insertions, 7 deletions
diff --git a/sound/soc/ti/davinci-mcasp.c b/sound/soc/ti/davinci-mcasp.c index 8e5371801d88..e1e937eb1dc1 100644 --- a/sound/soc/ti/davinci-mcasp.c +++ b/sound/soc/ti/davinci-mcasp.c @@ -664,18 +664,39 @@ static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id, struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); pm_runtime_get_sync(mcasp->dev); - if (dir == SND_SOC_CLOCK_OUT) { + + if (dir == SND_SOC_CLOCK_IN) { + switch (clk_id) { + case MCASP_CLK_HCLK_AHCLK: + mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, + AHCLKXE); + mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, + AHCLKRE); + clear_bit(PIN_BIT_AHCLKX, &mcasp->pdir); + break; + case MCASP_CLK_HCLK_AUXCLK: + mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, + AHCLKXE); + mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, + AHCLKRE); + set_bit(PIN_BIT_AHCLKX, &mcasp->pdir); + break; + default: + dev_err(mcasp->dev, "Invalid clk id: %d\n", clk_id); + goto out; + } + } else { + /* Select AUXCLK as HCLK */ mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE); mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE); set_bit(PIN_BIT_AHCLKX, &mcasp->pdir); - } else { - mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE); - mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE); - clear_bit(PIN_BIT_AHCLKX, &mcasp->pdir); } - + /* + * When AHCLK X/R is selected to be output it means that the HCLK is + * the same clock - coming via AUXCLK. + */ mcasp->sysclk_freq = freq; - +out: pm_runtime_put(mcasp->dev); return 0; } |