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authorShaohua Li <shaohua.li@intel.com>2011-03-16 06:37:29 +0300
committerIngo Molnar <mingo@elte.hu>2011-03-18 13:44:01 +0300
commit4981d01eada5354d81c8929d5b2836829ba3df7b (patch)
tree3f1e39b63111e06e2c213c6a0b1c5176e81a4ff9 /sound/soc/samsung/s3c24xx_simtec_hermes.c
parente8e999cf3cc733482e390b02ff25a64cecdc0b64 (diff)
downloadlinux-4981d01eada5354d81c8929d5b2836829ba3df7b.tar.xz
x86: Flush TLB if PGD entry is changed in i386 PAE mode
According to intel CPU manual, every time PGD entry is changed in i386 PAE mode, we need do a full TLB flush. Current code follows this and there is comment for this too in the code. But current code misses the multi-threaded case. A changed page table might be used by several CPUs, every such CPU should flush TLB. Usually this isn't a problem, because we prepopulate all PGD entries at process fork. But when the process does munmap and follows new mmap, this issue will be triggered. When it happens, some CPUs keep doing page faults: http://marc.info/?l=linux-kernel&m=129915020508238&w=2 Reported-by: Yasunori Goto<y-goto@jp.fujitsu.com> Tested-by: Yasunori Goto<y-goto@jp.fujitsu.com> Reviewed-by: Rik van Riel <riel@redhat.com> Signed-off-by: Shaohua Li<shaohua.li@intel.com> Cc: Mallick Asit K <asit.k.mallick@intel.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: linux-mm <linux-mm@kvack.org> Cc: stable <stable@kernel.org> LKML-Reference: <1300246649.2337.95.camel@sli10-conroe> Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'sound/soc/samsung/s3c24xx_simtec_hermes.c')
0 files changed, 0 insertions, 0 deletions