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| author | Shengjiu Wang <shengjiu.wang@nxp.com> | 2022-07-01 12:32:36 +0300 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2022-07-05 15:00:37 +0300 |
| commit | 7bad8125549cda14d9ccf97d7d76f7ef6ac9d206 (patch) | |
| tree | 611a16eb31aa6dc6a87465399dd92d05ba3f6750 /sound/soc/fsl/fsl_utils.h | |
| parent | acf981f94edca13c85fa24dd8511cdc6bd4c98ed (diff) | |
| download | linux-7bad8125549cda14d9ccf97d7d76f7ef6ac9d206.tar.xz | |
ASoC: fsl_utils: Add function to handle PLL clock source
i.MX8MQ/MN/MM/MP platforms typically have 2 AUDIO PLLs being
configured to handle 8kHz and 11kHz series audio rates.
Add common function in fsl_utils to handle these two PLL
clock source, which are needed by CPU DAI drivers
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Link: https://lore.kernel.org/r/1656667961-1799-2-git-send-email-shengjiu.wang@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/fsl/fsl_utils.h')
| -rw-r--r-- | sound/soc/fsl/fsl_utils.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/sound/soc/fsl/fsl_utils.h b/sound/soc/fsl/fsl_utils.h index c5dc2a14b492..4d5f3d93bc81 100644 --- a/sound/soc/fsl/fsl_utils.h +++ b/sound/soc/fsl/fsl_utils.h @@ -19,4 +19,11 @@ int fsl_asoc_get_dma_channel(struct device_node *ssi_np, const char *name, struct snd_soc_dai_link *dai, unsigned int *dma_channel_id, unsigned int *dma_id); + +void fsl_asoc_get_pll_clocks(struct device *dev, struct clk **pll8k_clk, + struct clk **pll11k_clk); + +void fsl_asoc_reparent_pll_clocks(struct device *dev, struct clk *clk, + struct clk *pll8k_clk, + struct clk *pll11k_clk, u64 ratio); #endif /* _FSL_UTILS_H */ |