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| author | Peter Ujfalusi <peter.ujfalusi@ti.com> | 2016-12-23 12:21:10 +0300 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2016-12-31 21:43:11 +0300 |
| commit | 63c3194b82530bd71fd49db84eb7ab656b8d404a (patch) | |
| tree | c21e4e4467dc29598477b248a2aecdb5374174e0 /sound/soc/codecs/wm_adsp.c | |
| parent | a5de5b74a50113564a1e0850e2da96c37c35e55d (diff) | |
| download | linux-63c3194b82530bd71fd49db84eb7ab656b8d404a.tar.xz | |
ASoC: tlv320aic3x: Mark the RESET register as volatile
The RESET register only have one self clearing bit and it should not be
cached. If it is cached, when we sync the registers back to the chip we
will initiate a software reset as well, which is not desirable.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Reviewed-by: Jarkko Nikula <jarkko.nikula@bitmer.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/codecs/wm_adsp.c')
0 files changed, 0 insertions, 0 deletions