diff options
| author | Christophe Branchereau <cbranchereau@gmail.com> | 2023-01-23 00:07:03 +0300 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2023-02-01 19:13:08 +0300 |
| commit | 36acae192d65195342d02595f45e404cc0f2eca0 (patch) | |
| tree | 5beb2fd12f468e0893d00fd3cac7521b1a6e7bb9 /sound/soc/codecs/jz4760.c | |
| parent | c2bc65274a307e11743d0f56a762f8e57f279b9e (diff) | |
| download | linux-36acae192d65195342d02595f45e404cc0f2eca0.tar.xz | |
ASoC: codecs/jz4760: add digital gain controls
Both the DAC and ADC have digital gain controls available
for their mixers, which go from -31 to 0db by step of 1db.
Signed-off-by: Christophe Branchereau <cbranchereau@gmail.com>
Link: https://lore.kernel.org/r/20230122210703.2552384-1-cbranchereau@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/codecs/jz4760.c')
| -rw-r--r-- | sound/soc/codecs/jz4760.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/sound/soc/codecs/jz4760.c b/sound/soc/codecs/jz4760.c index d96a4f6c9183..9df58e23d360 100644 --- a/sound/soc/codecs/jz4760.c +++ b/sound/soc/codecs/jz4760.c @@ -287,6 +287,7 @@ static const DECLARE_TLV_DB_MINMAX_MUTE(dac_tlv, -3100, 100); static const DECLARE_TLV_DB_SCALE(adc_tlv, 0, 100, 0); static const DECLARE_TLV_DB_MINMAX(out_tlv, -2500, 100); static const DECLARE_TLV_DB_SCALE(linein_tlv, -2500, 100, 0); +static const DECLARE_TLV_DB_MINMAX(mixer_tlv, -3100, 0); /* Unconditional controls. */ static const struct snd_kcontrol_new jz4760_codec_snd_controls[] = { @@ -299,6 +300,14 @@ static const struct snd_kcontrol_new jz4760_codec_snd_controls[] = { JZ4760_CODEC_REG_GCR4, JZ4760_CODEC_REG_GCR3, REG_GCR_GAIN_OFFSET, REG_GCR_GAIN_MAX, 1, linein_tlv), + SOC_SINGLE_TLV("Mixer Capture Volume", + JZ4760_CODEC_REG_MIX1, + REG_GCR_GAIN_OFFSET, REG_GCR_GAIN_MAX, 1, mixer_tlv), + + SOC_SINGLE_TLV("Mixer Playback Volume", + JZ4760_CODEC_REG_MIX2, + REG_GCR_GAIN_OFFSET, REG_GCR_GAIN_MAX, 1, mixer_tlv), + SOC_SINGLE("High-Pass Filter Capture Switch", JZ4760_CODEC_REG_CR4, REG_CR4_ADC_HPF_OFFSET, 1, 0), |