diff options
| author | Vlad.Karpovich <vkarpovi@opensource.cirrus.com> | 2023-03-15 18:47:22 +0300 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2023-03-21 15:46:42 +0300 |
| commit | 6c07be8fe92c6b0c24ee1c599601dce3506b83c7 (patch) | |
| tree | fcf50455ab68733a03d3c49201826bf7c1b8337b /sound/soc/codecs/cs35l45.h | |
| parent | 74b14e2850a34740c121cf2758d4181063d4c77c (diff) | |
| download | linux-6c07be8fe92c6b0c24ee1c599601dce3506b83c7.tar.xz | |
ASoC: cs35l45: Hibernation support
Adds support for a low-power Hibernation State.
Add support for a low-power hibernation state for the DSP. In
this state the DSP RAM contents are maintained, such that
firmware does not need to be re-downloaded, but the rest of the
chip's register state is lost.
Entry to this state is achieved via the register interface
(either by an external driver using the control port, or the
programmable DSP). Exit from this state is triggered by activity
on device GPIO pins, intended SPI transaction, or I2C
transaction with intended slave address.
Signed-off-by: Vlad Karpovich <vkarpovi@opensource.cirrus.com>
Link: https://lore.kernel.org/r/167933511185.26.10641185496218226278@mailman-core.alsa-project.org
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/codecs/cs35l45.h')
| -rw-r--r-- | sound/soc/codecs/cs35l45.h | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/sound/soc/codecs/cs35l45.h b/sound/soc/codecs/cs35l45.h index 87032619b341..0da28439f628 100644 --- a/sound/soc/codecs/cs35l45.h +++ b/sound/soc/codecs/cs35l45.h @@ -30,6 +30,9 @@ #define CS35L45_INTB_GPIO2_MCLK_REF 0x00002434 #define CS35L45_GPIO3 0x00002438 #define CS35L45_PWRMGT_CTL 0x00002900 +#define CS35L45_WAKESRC_CTL 0x00002904 +#define CS35L45_WKI2C_CTL 0x00002908 +#define CS35L45_PWRMGT_STS 0x0000290C #define CS35L45_REFCLK_INPUT 0x00002C04 #define CS35L45_GLOBAL_SAMPLE_RATE 0x00002C0C #define CS35L45_BOOST_CCM_CFG 0x00003808 @@ -348,6 +351,25 @@ #define CS35L45_POST_GLOBAL_EN_US 5000 #define CS35L45_PRE_GLOBAL_DIS_US 3000 +/* WAKESRC_CTL */ +#define CS35L45_WKSRC_SYNC_GPIO1 BIT(0) +#define CS35L45_WKSRC_INT_GPIO2 BIT(1) +#define CS35L45_WKSRC_GPIO3 BIT(2) +#define CS35L45_WKSRC_SPI BIT(3) +#define CS35L45_WKSRC_I2C BIT(4) +#define CS35L45_UPDT_WKCTL_SHIFT 15 +#define CS35L45_UPDT_WKCTL_MASK BIT(15) +#define CS35L45_WKSRC_EN_SHIFT 8 +#define CS35L45_WKSRC_EN_MASK GENMASK(12, 8) +#define CS35L45_WKSRC_POL_SHIFT 0 +#define CS35L45_WKSRC_POL_MASK GENMASK(3, 0) + +/* WAKEI2C_CTL */ +#define CS35L45_UPDT_WKI2C_SHIFT 15 +#define CS35L45_UPDT_WKI2C_MASK BIT(15) +#define CS35L45_WKI2C_ADDR_SHIFT 0 +#define CS35L45_WKI2C_ADDR_MASK GENMASK(6, 0) + #define CS35L45_SPI_MAX_FREQ 4000000 enum cs35l45_cspl_mboxstate { @@ -369,6 +391,11 @@ enum cs35l45_cspl_mboxcmd { CSPL_MBOX_CMD_INVALID_SEQUENCE = -2, }; +enum control_bus_type { + CONTROL_BUS_I2C = 0, + CONTROL_BUS_SPI = 1, +}; + #define CS35L45_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ SNDRV_PCM_FMTBIT_S24_3LE| \ SNDRV_PCM_FMTBIT_S24_LE) @@ -439,6 +466,8 @@ struct cs35l45_private { u8 slot_count; int irq_invert; int irq; + unsigned int i2c_addr; + enum control_bus_type bus_type; struct regmap_irq_chip_data *irq_data; }; |