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authorCharles Keepax <ckeepax@opensource.wolfsonmicro.com>2015-11-30 20:37:28 +0300
committerMark Brown <broonie@kernel.org>2015-12-01 18:18:44 +0300
commit800f297e8ef91901b93c280425863684dff2d9c6 (patch)
tree90ecf866ff3e24e5d8566eb174994d7ccf27f2bf /sound/soc/codecs/arizona.c
parentd190106d5a6b300b782a55ad24a1e1da71fa630b (diff)
downloadlinux-800f297e8ef91901b93c280425863684dff2d9c6.tar.xz
ASoC: arizona: Add 32uS delay after putting FLL into freerun
When switching between two clock sources using the FLL freerun to smooth the transition we should wait 32uS after putting the FLL into freerun before we proceed. In practice we appear to be getting enough delay from the surrounding code, but better to make it explicit. Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com> Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/codecs/arizona.c')
-rw-r--r--sound/soc/codecs/arizona.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/sound/soc/codecs/arizona.c b/sound/soc/codecs/arizona.c
index e76ecc7cc775..a23f7d15324a 100644
--- a/sound/soc/codecs/arizona.c
+++ b/sound/soc/codecs/arizona.c
@@ -2212,9 +2212,9 @@ static int arizona_enable_fll(struct arizona_fll *fll)
/* Facilitate smooth refclk across the transition */
regmap_update_bits_async(fll->arizona->regmap, fll->base + 0x9,
ARIZONA_FLL1_GAIN_MASK, 0);
- regmap_update_bits_async(fll->arizona->regmap, fll->base + 1,
- ARIZONA_FLL1_FREERUN,
- ARIZONA_FLL1_FREERUN);
+ regmap_update_bits(fll->arizona->regmap, fll->base + 1,
+ ARIZONA_FLL1_FREERUN, ARIZONA_FLL1_FREERUN);
+ udelay(32);
}
/*