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| author | Takashi Iwai <tiwai@suse.de> | 2014-04-29 20:38:21 +0400 |
|---|---|---|
| committer | Takashi Iwai <tiwai@suse.de> | 2014-04-29 20:41:22 +0400 |
| commit | 6ba736dd02e7b3658c344efeb2f4a096a6785d83 (patch) | |
| tree | cc8a5303afd3964ce51abbb1b311806a4fa8e36c /sound/pci/hda/hda_priv.h | |
| parent | e32dfbed8cc06aac72528e2bb53067ce02262413 (diff) | |
| download | linux-6ba736dd02e7b3658c344efeb2f4a096a6785d83.tar.xz | |
ALSA: hda - Suppress CORBRP clear on Nvidia controller chips
The recent commit (ca460f86521) changed the CORB RP reset procedure to
follow the specification with a couple of sanity checks.
Unfortunately, Nvidia controller chips seem not following this way,
and spew the warning messages like:
snd_hda_intel 0000:00:10.1: CORB reset timeout#1, CORBRP = 0
This patch adds the workaround for such chips. It just skips the new
reset procedure for the known broken chips.
Signed-off-by: Takashi Iwai <tiwai@suse.de>
Diffstat (limited to 'sound/pci/hda/hda_priv.h')
| -rw-r--r-- | sound/pci/hda/hda_priv.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/sound/pci/hda/hda_priv.h b/sound/pci/hda/hda_priv.h index ba38b819f984..4a7cb01fa912 100644 --- a/sound/pci/hda/hda_priv.h +++ b/sound/pci/hda/hda_priv.h @@ -189,6 +189,7 @@ enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 }; #define AZX_DCAPS_COUNT_LPIB_DELAY (1 << 25) /* Take LPIB as delay */ #define AZX_DCAPS_PM_RUNTIME (1 << 26) /* runtime PM support */ #define AZX_DCAPS_I915_POWERWELL (1 << 27) /* HSW i915 powerwell support */ +#define AZX_DCAPS_CORBRP_SELF_CLEAR (1 << 28) /* CORBRP clears itself after reset */ /* position fix mode */ enum { |