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| author | Vandana Kannan <vandana.kannan@intel.com> | 2016-03-31 20:45:54 +0300 |
|---|---|---|
| committer | Imre Deak <imre.deak@intel.com> | 2016-04-01 13:05:58 +0300 |
| commit | b61e79967a6f35043aa838ff36d9970658a0af3d (patch) | |
| tree | 294d5f5446f9043c945f7615c17b287a195face2 /security | |
| parent | 39ff747b2f8197de51dae540e742de4acdbd7763 (diff) | |
| download | linux-b61e79967a6f35043aa838ff36d9970658a0af3d.tar.xz | |
drm/i915: BXT DDI PHY sequence BUN
According to the BSpec update, bit 7 of PORT_CL1CM_DW0 register needs to be
checked to ensure that the register is in accessible state.
Also, based on a BSpec update, changing the timeout value to
check iphypwrgood, from 10ms to wait for up to 100us.
v2: [Ville] use wait_for_us instead of the atomic call.
v3: [Jani/Imre] read register only once
Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
Reported-by: Philippe Lecluse <Philippe.Lecluse@intel.com>
Cc: Deak, Imre <imre.deak@intel.com>
Cc: Nikula, Jani <jani.nikula@intel.com>
Acked-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1459446354-19012-1-git-send-email-vandana.kannan@intel.com
Diffstat (limited to 'security')
0 files changed, 0 insertions, 0 deletions