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authorBharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>2016-03-06 19:32:14 +0300
committerBjorn Helgaas <bhelgaas@google.com>2016-03-11 21:42:31 +0300
commitab597d35ef11d2a921e0ec507a9b7861bcb44cbd (patch)
tree03a441b7a660ce79257e1612fbb2c33b5aee9bb9 /security/min_addr.c
parent92e963f50fc74041b5e9e744c330dca48e04f08d (diff)
downloadlinux-ab597d35ef11d2a921e0ec507a9b7861bcb44cbd.tar.xz
PCI: xilinx-nwl: Add support for Xilinx NWL PCIe Host Controller
Add PCIe Root Port driver for Xilinx PCIe NWL bridge IP. [bhelgaas: wait for link like dw_pcie_wait_for_link(), simplify bitmap error path, typos, whitespace, fold in Dan Carpenter's PTR_ERR() fix] Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Rob Herring <robh@kernel.org>
Diffstat (limited to 'security/min_addr.c')
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