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authorAneesh Kumar K.V <aneesh.kumar@linux.ibm.com>2019-10-17 11:05:03 +0300
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2019-11-10 13:25:42 +0300
commitae11e9fddd4107926d0671a255f49577a1291d7d (patch)
treea0ba4c2d0768d56404216c8dbb7ae7a71ee0cb30 /scripts
parent3f5d5b30cd7284d2f8983561f753ee23aa410b58 (diff)
downloadlinux-ae11e9fddd4107926d0671a255f49577a1291d7d.tar.xz
powerpc/mm: Fixup tlbie vs mtpidr/mtlpidr ordering issue on POWER9
commit 047e6575aec71d75b765c22111820c4776cd1c43 upstream. On POWER9, under some circumstances, a broadcast TLB invalidation will fail to invalidate the ERAT cache on some threads when there are parallel mtpidr/mtlpidr happening on other threads of the same core. This can cause stores to continue to go to a page after it's unmapped. The workaround is to force an ERAT flush using PID=0 or LPID=0 tlbie flush. This additional TLB flush will cause the ERAT cache invalidation. Since we are using PID=0 or LPID=0, we don't get filtered out by the TLB snoop filtering logic. We need to still follow this up with another tlbie to take care of store vs tlbie ordering issue explained in commit: a5d4b5891c2f ("powerpc/mm: Fixup tlbie vs store ordering issue on POWER9"). The presence of ERAT cache implies we can still get new stores and they may miss store queue marking flush. Cc: stable@vger.kernel.org # v4.14 Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20190924035254.24612-3-aneesh.kumar@linux.ibm.com [sandipan: Backported to v4.14] Signed-off-by: Sandipan Das <sandipan@linux.ibm.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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