diff options
| author | Miquel Raynal <miquel.raynal@bootlin.com> | 2025-04-03 12:19:20 +0300 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2025-06-27 13:13:42 +0300 |
| commit | 91c9856dcf85f17daee2933a20b63e566e811fbd (patch) | |
| tree | 40a46f2f53401a9c5fbfba6b6eedc84dde490977 /scripts/gdb/linux/xarray.py | |
| parent | 61cad5f1f3a925718c6d2821adf732d55a3ec124 (diff) | |
| download | linux-91c9856dcf85f17daee2933a20b63e566e811fbd.tar.xz | |
mtd: spinand: Use more specific naming for the (quad output) read from cache ops
[ Upstream commit 1deae734cc1c7e976d588e7d8f46af2bb9ef5656 ]
SPI operations have been initially described through macros implicitly
implying the use of a single SPI SDR bus. Macros for supporting dual and
quad I/O transfers have been added on top, generally inspired by vendor
naming, followed by DTR operations. Soon we might see octal
and even octal DTR operations as well (including the opcode byte).
Let's clarify what the macro really mean by describing the expected bus
topology in the (quad output) read from cache macro names.
Acked-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Stable-dep-of: dba90f5a79c1 ("mtd: spinand: winbond: Prevent unsupported frequencies on dual/quad I/O variants")
Signed-off-by: Sasha Levin <sashal@kernel.org>
Diffstat (limited to 'scripts/gdb/linux/xarray.py')
0 files changed, 0 insertions, 0 deletions