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authorSebastian Siewior <bigeasy@linutronix.de>2013-04-24 12:48:25 +0400
committerDavid S. Miller <davem@davemloft.net>2013-04-25 12:13:18 +0400
commita11fbba9a7d338c4a4e4be624af0334bbf2c9a5a (patch)
treef4e73a12264bc031cad97ff1bd9411ea0ee15f55 /net/mac802154
parent6e6ceaedb5901c7ebd23e5222726dab5362938bd (diff)
downloadlinux-a11fbba9a7d338c4a4e4be624af0334bbf2c9a5a.tar.xz
net/cpsw: fix irq_disable() with threaded interrupts
During high throughput it is likely that we receive both: an RX and TX interrupt. The normal behaviour is that once we enter the ISR the interrupts are disabled in the IRQ chip and so the ISR is invoked only once and the interrupt line is disabled once. It will be re-enabled after napi completes. With threaded interrupts on the other hand the interrupt the interrupt is disabled immediately and the ISR is marked for "later". By having TX and RX interrupt marked pending we invoke them both and disable the interrupt line twice. The napi callback is still executed once and so after it completes we remain with interrupts disabled. The initial patch simply removed the cpsw_{enable|disable}_irq() calls and it worked well on my AM335X ES1.0 (beagle bone). On ES2.0 (beagle bone black) it caused an never ending interrupt (even after the mask via cpsw_intr_disable()) according to Mugunthan V N. Since I don't have the ES2.0 and no idea what is going on this patch tracks the state of the irq_disable() call and execute it only when not yet done. The book keeping is done on the first struct since with dual_emac we can have two of those and only one interrupt line. Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Acked-by: Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'net/mac802154')
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